A MOSFET device and chip

Abstract

The embodiment of the present application provides a MOSFET device and chip, which comprises an N-type substrate; an N-type epitaxial layer arranged on the other side of the N-type substrate; an N-type current spreading layer and a first P-type buried layer arranged above the N-type epitaxial layer; the N-type current spreading layer is connected with the first P-type buried layer; a first N+ region is arranged in a groove formed on the surface of the first P-type buried layer; a groove is formed above the N-type current spreading layer and the first P-type buried layer; a source polysilicon region, a gate polysilicon region and an oxide layer are arranged in the groove, and the oxide layer covers the surfaces of the source polysilicon region and the gate polysilicon region. The embodiment of the present application forms a channel diode below the source polysilicon through the N-type current spreading layer and the first P-type buried layer, and when the device is in a reverse conduction state, the channel diode is turned on earlier than a body diode, thereby avoiding the problems of large body diode freewheeling loss and bipolar degradation when the device is in a reverse freewheeling mode.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a MOSFET device and chip. Background Technology

[0002] SiC MOSFET (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor) is a high-performance power semiconductor device based on silicon carbide (SiC) material. However, when the MOSFET is in reverse freewheeling mode, i.e., when the source voltage of the MOSFET is higher than the drain voltage, the body diode (parasitic diode) of the MOSFET will conduct, forming a reverse freewheeling path. Current flows from the source to the drain through the body diode of the MOSFET. The body diode of the SiC MOSFET has a high on-state voltage drop, resulting in large conduction losses in reverse freewheeling mode. Furthermore, due to the conduction of the body diode, minority carriers (holes) accumulate inside the device, leading to a degradation in device performance. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a MOSFET device and chip that overcomes or at least partially solves the above problems.

[0004] To address the above problems, this invention discloses a MOSFET device, the device comprising:

[0005] N-type substrate;

[0006] An N-type epitaxial layer is disposed on the other side of the N-type substrate;

[0007] An N-type current spreading layer and a first P-type buried layer are disposed above the N-type epitaxial layer; the N-type current spreading layer is connected to the first P-type buried layer;

[0008] The first N+ region is located in a groove formed on the surface of the first P-type buried layer;

[0009] The trench is formed above the N-type current spreading layer and the first P-type buried layer;

[0010] A source polysilicon region, a gate polysilicon region, and an oxide layer are disposed within the trench, the oxide layer covering the surfaces of the source polysilicon region and the gate polysilicon region; the source polysilicon region is connected to the first P-type buried layer, the first N+ region, and the N-type current spreading layer through the oxide layer; the gate polysilicon region is connected to the N-type current spreading layer through the oxide layer; and the gate polysilicon region is connected to the source polysilicon region through the oxide layer.

[0011] A P-type base region is disposed above the N-type current extension layer, and the P-type base region is connected to the side of the gate polysilicon region through the oxide layer;

[0012] The P+ region and the second N+ region are disposed above the P-type base region. The second N+ region is connected to the side of the gate polysilicon region through the oxide layer. The second N+ region and the P+ region are located in the same layer.

[0013] The source electrode is formed on the surface of the oxide layer, the first P-type buried layer, the first N+ region, the P+ region, and the second N+ region; the oxide layer corresponding to the source polysilicon region is provided with contact holes so that the source electrode can contact the source polysilicon region.

[0014] Optionally, the N-type current spreading layer is L-type.

[0015] Optionally, the oxide layer extends into the second N+ region, covering a portion of the surface of the second N+ region.

[0016] Optionally, the barrier height formed by the N-type current spread layer and the first P-type buried layer is less than the barrier height formed by the N-type current spread layer and the P-type base region and the barrier height formed by the N-type epitaxial layer and the first P-type buried layer.

[0017] Optionally, the substrate of the N-type substrate and the substrate of the N-type epitaxial layer is silicon carbide.

[0018] Optionally, the device further includes a drain electrode disposed on one side of the N+ type substrate.

[0019] Optionally, the doping concentration of the N-type current spreading layer is greater than that of the N-type epitaxial layer.

[0020] Optionally, the N-type substrate is an N+ type substrate, the N-type epitaxial layer is an N- type epitaxial layer, and the doping concentration of the N-type epitaxial layer is lower than that of the N-type substrate.

[0021] Optionally, the drain electrode is the back metal layer, and the source electrode is the front metal layer.

[0022] Accordingly, embodiments of the present invention provide a chip including the MOSFET device described above.

[0023] The embodiments of the present invention have the following advantages:

[0024] The MOSFET device of this invention includes an N-type substrate; an N-type epitaxial layer disposed on the other side of the N-type substrate; an N-type current spreading layer and a first P-type buried layer disposed above the N-type epitaxial layer; the N-type current spreading layer and the first P-type buried layer being connected; a first N+ region disposed in a groove formed on the surface of the first P-type buried layer; a trench formed above the N-type current spreading layer and the first P-type buried layer; a source polysilicon region, a gate polysilicon region, and an oxide layer disposed in the trench, the oxide layer covering the surfaces of the source polysilicon region and the gate polysilicon region; the source polysilicon region being connected to the first P-type buried layer, the first N+ region, and the N-type current spreading layer through the oxide layer. The gate polysilicon region is connected to the N-type current spreading layer through an oxide layer; the gate polysilicon region is connected to the source polysilicon region through an oxide layer; the P-type base region is located above the N-type current spreading layer and is connected to the side of the gate polysilicon region through an oxide layer; the P+ region and the second N+ region are located above the P-type base region and are connected to the side of the gate polysilicon region through an oxide layer, and the second N+ region and the P+ region are located in the same layer; the source is formed on the surface of the oxide layer, the first P-type buried layer, the first N+ region, the P+ region, and the second N+ region; the oxide layer corresponding to the source polysilicon region is provided with contact holes to allow the source to contact the source polysilicon region. In this embodiment of the invention, a channel diode is formed under the source polysilicon through an N-type current extension layer and a first P-type buried layer. The channel diode is connected in parallel with the body diode. When the MOSFET device is in reverse conduction mode, the channel diode conducts before the body diode, thereby avoiding the problem of large freewheeling loss and bipolar degradation of the body diode when the MOSFET is in reverse freewheeling mode. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a MOSFET device according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of the JFET region structure of a MOSFET device according to an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of another MOSFET device according to an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of the body diode and channel diode of a MOSFET device according to an embodiment of the present invention;

[0029] Figure 5 This is an equivalent circuit diagram of a MOSFET device according to an embodiment of the present invention;

[0030] Figure 6 This is a partial structure of a MOSFET device according to an embodiment of the present invention, and a conduction band distribution diagram at the cut-off point.

[0031] Figure 7 This is a schematic diagram of another MOSFET device according to an embodiment of the present invention.

[0032] Reference numerals: N-type substrate 101, N-type epitaxial layer 102, N-type current spreading layer 103, first P-type buried layer 104, first N+ region 105, source polysilicon region 106, gate polysilicon region 107, oxide layer 108, P-type base region 109, P+ region 110, second N+ region 111, source 112, drain 113, second P-type buried layer 114, first body diode 11, second body diode 12, channel diode 13. Detailed Implementation

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] SiC MOSFETs are high-performance power semiconductor devices based on silicon carbide (SiC) material. However, when the MOSFET is in reverse freewheeling mode, i.e., when the source voltage is higher than the drain voltage, the body diode (parasitic diode) of the MOSFET will conduct, forming a reverse freewheeling path. Current flows from the source to the drain through the body diode. The body diode of SiC MOSFETs has a high on-state voltage drop, resulting in large conduction losses in reverse freewheeling mode. Furthermore, due to the conduction of the body diode, minority carriers (holes) accumulate inside the device, leading to a degradation in device performance.

[0035] One of the core concepts of this invention is that a channel diode is formed under the source polysilicon through an N-type current extension layer and a first P-type buried layer. The channel diode is connected in parallel with the body diode. When the MOSFET device is in reverse conduction mode, the channel diode conducts before the body diode, thereby avoiding the problem of large freewheeling loss and bipolar degradation of the body diode when the MOSFET is in reverse freewheeling mode.

[0036] Reference Figure 1 The diagram illustrates a structural schematic of a MOSFET device according to an embodiment of the present invention, which may specifically include the following structure:

[0037] N-type substrate 101.

[0038] N-type substrates are formed by doping with donor impurities (such as phosphorus and nitrogen), resulting in a high concentration of free electrons and a low concentration of holes. The characteristics of N-type substrates are: The high concentration of free electrons (majority carriers) due to donor impurities determines the conductivity of the N-type substrate; the relatively low concentration of holes (positively charged carriers) due to the high electron concentration results in a lower hole concentration, which contributes to the higher breakdown voltage under reverse bias; and the high conductivity due to the presence of free electrons makes N-type substrates suitable for applications requiring high conductivity. In MOSFETs, N-type substrates are used to construct the conductive channels of the device, grow epitaxial layers, and also enable rapid field cutoff, similar to the field cutoff layer in IGBTs (Insulated Gate Bipolar Transistors).

[0039] An N-type epitaxial layer 102 is disposed on one side of the N-type substrate.

[0040] N-type epitaxial layers are formed by epitaxially growing a semiconductor material doped with donor impurities (such as phosphorus and nitrogen) on a substrate, exhibiting a high free electron concentration and a low hole concentration. The characteristics of N-type epitaxial layers are: The high free electron concentration, due to the doping of donor impurities, determines the conductivity of the N-type epitaxial layer, as electrons are the majority carriers; the relatively low hole (positive charge carrier) concentration, being minority carriers, results in higher breakdown voltage under reverse bias; the resistivity of N-type epitaxial layers can be precisely controlled by the doping concentration to meet the needs of different devices. High-doped N-type epitaxial layers have lower resistivity, suitable for conductive channels, while low-doped N-type epitaxial layers have higher resistivity, suitable for breakdown voltage structures; the epitaxial growth process enables high-quality lattice matching, reducing lattice defects and improving device performance and reliability. In MOSFETs, the N-type epitaxial layer is used to construct the device's drift region, which determines the device's breakdown voltage and on-resistance, similar to the N-type drift region of IGBTs.

[0041] An N-type current extension layer 103 and a first P-type buried layer 104 are disposed above the N-type epitaxial layer 102; the N-type current extension layer 103 is connected to the first P-type buried layer 104.

[0042] An N-type current spreading layer (CSL) is used to improve the uniform distribution of current on the device surface, thereby improving device efficiency and reliability. The main function of CSL is to ensure uniform current distribution on the device surface, preventing current concentration in localized areas and thus improving overall device efficiency. Uniform current distribution reduces localized overheating and extends device lifespan. In optoelectronic devices (such as LEDs and lasers), CSL improves current diffusion, making the light-emitting area more uniform, thereby improving light output efficiency. Uniform current distribution reduces light intensity non-uniformity, improving the device's optical performance. CSL also improves current diffusion, reducing current density in localized areas, thus lowering thermal resistance. Lower thermal resistance helps improve heat dissipation and extends device lifespan. Uniform current distribution reduces stress concentration in localized areas, improving device mechanical strength and reliability. Introducing a current spreading layer increases the N-type drift region doping concentration within the JFET region. The increased N-type drift region doping concentration effectively reduces depletion within the JFET region, while also lowering the JFET region's resistance and promoting lateral current diffusion from the MOS channel to the drift region.

[0043] The P-type buried layer 104 and the N-type epitaxial layer 102 form a PN junction. Since the internal electric field distribution of the device can be adjusted under voltage, its main function is to significantly reduce the electric field strength near the corner of the gate trench and increase the reliability of the device.

[0044] P-type buried layers (P-shielding regions, PSRs) are primarily used to optimize electric field distribution and improve the breakdown voltage and reliability of devices. The functions of PSRs include: optimizing the electric field distribution of the device by introducing a P-type doped layer, reducing local electric field concentration, which improves the breakdown voltage and extends the device's lifespan; effectively dispersing the electric field and reducing the maximum electric field strength, thereby improving the device's breakdown voltage; significantly increasing the breakdown voltage of high-voltage devices, enabling them to withstand higher reverse voltages; improving the reverse characteristics of the device and reducing leakage current by reducing electric field concentration; and reducing localized electric field concentration, improving the device's mechanical strength and reliability. In high-voltage devices, PSRs reduce localized stress concentration, further enhancing the device's breakdown voltage.

[0045] The N-type current spreading layer 103 can reduce the JFET (Junction Field-Effect Transistor Effect) effect. The JFET effect refers to the phenomenon in semiconductor devices where the conductivity changes due to the electric field of the PN junction. The JFET effect commonly occurs in devices such as MOSFETs and IGBTs, especially in high-voltage devices, where the uneven electric field distribution in the drift region affects the device's conductivity. The principle of the JFET effect: The essence of the JFET effect is the influence of the PN junction's electric field on the device's conductivity. Specifically, when a PN junction exists in the device's drift region, the PN junction's electric field alters the conductivity of the drift region, leading to an increase in the device's on-resistance and affecting its efficiency and performance. In high-voltage devices, the drift region is typically composed of lightly doped N-type or P-type materials with high resistivity. When the device operates under high voltage conditions, the electric field of the PN junction acts on the drift region, causing changes in its conductivity. Due to the electric field of the PN junction, the conductivity of the drift region is limited, leading to an increase in the device's on-resistance. This increase in on-resistance results in increased conduction losses, affecting the device's efficiency. Furthermore, the electric field distribution is usually non-uniform, with higher electric field strengths in localized areas. These localized high-electric-field regions exacerbate the JFET effect, further increasing the device's on-resistance.

[0046] Reference Figure 2 This shows a schematic diagram of the JFET region structure of a MOSFET device according to an embodiment of the present invention. Figure 2 by Figure 1 The image on the left is a mirror image obtained along the axis of symmetry. The JFET region consists of two P-type doped layers and one N-type doped layer. The JFET region is composed of a P-type buried layer on the left, an N-type current spreading layer, and a P-type buried layer on the right. The resistance of the JFET region is the JFET resistance, and the magnitude of the JFET resistance is related to the length, doping, and width of the JFET region. The N-type current spreading layer 103 can reduce the JFET effect.

[0047] The first N+ region 105 is located in a groove formed on the surface of the first P-type buried layer 104.

[0048] The first N+ region 105 provides electrons when the MOSFET is reverse-biased, meaning the drain is connected to a low level and the source is connected to a high level.

[0049] The N+ region is formed through high-concentration doping with donor impurities (such as phosphorus and nitrogen), exhibiting low resistivity and high free electron concentration. As an N-type region formed by high-concentration doping (such as phosphorus and nitrogen), the doping concentration is much higher than that of ordinary N-type regions. This high doping concentration results in very high conductivity in the N+ region, making it suitable for conductive channels or termination structures. Due to the high doping concentration, the N+ region has low resistivity, effectively reducing resistance losses. This low resistivity characteristic makes the N+ region suitable for ohmic contacts or conductive channels. Furthermore, the high free electron concentration in the N+ region, with electrons being the majority carriers, contributes to its excellent conductivity.

[0050] The trench is formed above the N-type current extension layer 103 and the first P-type buried layer 104.

[0051] A source polysilicon region 106, a gate polysilicon region 107, and an oxide layer 108 are disposed within the trench. The oxide layer 108 covers the surfaces of the source polysilicon region 106 and the gate polysilicon region 107. The source polysilicon region 106 is connected to the first P-type buried layer 104, the first N+ region 105, and the N-type current spreading layer 103 through the oxide layer 108. The gate polysilicon region 107 is connected to the N-type current spreading layer 103 through the oxide layer 108. The gate polysilicon region 107 is connected to the source polysilicon region 106 through the oxide layer 108.

[0052] The source polycrystalline silicon region 106 is made of polycrystalline silicon material, and in the layout design, it is connected to the source metal.

[0053] The gate polysilicon region 107 is made of polysilicon material and is connected to the gate metal in the layout design.

[0054] The oxide layer 108 serves as a barrier and insulation layer.

[0055] A P-type base region 109 is disposed above the N-type current extension layer 103, and the P-type base region 109 is connected to the side of the gate polysilicon region 107 through the oxide layer 108.

[0056] The P-type base region (P-Body) 109, where the channel is formed, is created through P-type doping. It has a high hole concentration and a low electron concentration. The P-type base region 109 is used to construct the base region of the device and form a PN junction, thereby controlling the device's on / off state. The P-Body is the base region of the device, used to construct the PN junction and control the device's on / off state. The P-Body forms a PN junction with the N-type source region, controlling the formation and disappearance of the conductive channel. The formation and disappearance of the conductive channel are controlled by the gate voltage, thereby controlling the current flow. The gate voltage acts on the P-type base region through the gate oxide layer to form the conductive channel, thereby controlling the current flow. The P-Body forms a PN junction with the N-type source region, used to control the device's on / off state. The on / off state of the PN junction is controlled by the gate voltage.

[0057] P+ region 110 and second N+ region 111 are disposed above the P-type base region 109. The second N+ region 111 is connected to the side of the gate polysilicon region 107 through the oxide layer 108. The second N+ region 111 and the P+ region 110 are located in the same layer.

[0058] P+ regions, formed through high-concentration doping with acceptor impurities (such as aluminum), exhibit low resistivity and high hole concentration. They are commonly used to construct conductive channels, ohmic contacts, or termination structures in semiconductor devices. The characteristics of P+ regions are: they are P-type regions formed through high-concentration doping (such as aluminum), with a doping concentration far exceeding that of ordinary P-type regions. This high doping concentration results in very high conductivity, making them suitable for conductive channels or termination structures; due to the high doping concentration, P+ regions have low resistivity, effectively reducing resistance losses. This low resistivity characteristic makes P+ regions suitable for ohmic contacts or conductive channels; and they have a high hole concentration. Holes are the majority carriers, and this high hole concentration gives P+ regions excellent conductivity.

[0059] The second N+ region, 111, is formed through high-concentration donor impurities (such as phosphorus and nitrogen) doping, exhibiting low resistivity and high free electron concentration. The N+ region is an N-type region formed by high-concentration doping (such as phosphorus and nitrogen), with a doping concentration much higher than that of ordinary N-type regions. This high doping concentration results in very high conductivity in the N+ region, making it suitable for conductive channels or termination structures. Due to the high doping concentration, the N+ region has low resistivity, effectively reducing resistance loss. This low resistivity characteristic makes the N+ region suitable for ohmic contacts or conductive channels. Furthermore, the N+ region has a high free electron concentration; since electrons are the majority carriers, this high free electron concentration gives the N+ region excellent conductivity.

[0060] The second N+ region 111 provides electrons when the MOSFET is forward-biased, meaning the drain is connected to a high level and the source is connected to a low level.

[0061] The source electrode 112 is formed on the surface of the oxide layer 108, the first P-type buried layer 104, the first N+ region 105, the P+ region 110, and the second N+ region 111; the oxide layer 108 corresponding to the source polysilicon region 106 is provided with contact holes so that the source electrode 112 contacts the source polysilicon region 106.

[0062] The MOSFET device of this invention includes an N-type substrate; an N-type epitaxial layer disposed on the other side of the N-type substrate; an N-type current spreading layer and a first P-type buried layer disposed above the N-type epitaxial layer; the N-type current spreading layer being connected to the first P-type buried layer; a first N+ region disposed in a groove formed on the surface of the first P-type buried layer; a trench formed above the N-type current spreading layer and the first P-type buried layer; a source polysilicon region, a gate polysilicon region, and an oxide layer disposed within the trench, the oxide layer covering the surfaces of the source polysilicon region and the gate polysilicon region; the source polysilicon region being connected to the first P-type buried layer, the first N+ region, and the N-type current spreading layer through the oxide layer; the gate ... first P-type buried layer through the oxide layer; the first N+ region being connected to the first P-type buried layer, the first P-type buried layer, and the first P-type buried layer; the first N+ region being connected to the first P-type buried layer, the first P-type buried layer, and the first P-type buried layer; the second P-type buried layer being connected to the first P-type buried layer, the first P-type buried layer, and the first P-type buried layer; the third P-type buried layer being connected to the first P-type buried layer, the first P-type buried layer, and the first P-type buried layer; the fourth P-type buried layer being connected to the first P-type buried layer, the first P-type buried layer, and the first P-type buried layer; the fifth P-type buried layer being connected to the first P-type buried layer, the first P-type buried layer, and the first P-type buried layer; the sixth P-type buried layer being connected to the first P-type buried layer, the first P-type buried layer, and the first P-type buried The oxide layer is connected to the N-type current spreading layer; the gate polysilicon region is connected to the source polysilicon region through the oxide layer; a P-type base region is disposed above the N-type current spreading layer, and the P-type base region is connected to the side of the gate polysilicon region through the oxide layer; a P+ region and a second N+ region are disposed above the P-type base region, and the second N+ region is connected to the side of the gate polysilicon region through the oxide layer, and the second N+ region and the P+ region are located in the same layer; a source electrode is formed on the surface of the oxide layer, the first P-type buried layer, the first N+ region, the P+ region, and the second N+ region; the oxide layer corresponding to the source polysilicon region is provided with contact holes to short-circuit the source electrode with the source polysilicon region. In this embodiment of the invention, a channel diode is formed under the source polysilicon through an N-type current extension layer and a first P-type buried layer. The channel diode is connected in parallel with the body diode. When the MOSFET device is in reverse conduction mode, the channel diode conducts before the body diode, thereby avoiding the problem of large freewheeling loss and bipolar degradation of the body diode when the MOSFET is in reverse freewheeling mode.

[0063] In this embodiment of the invention, the N-type current spreading layer 103 is L-shaped. The first P-type buried layer 104 is connected to the lateral extension direction of the L-shaped N-type current spreading layer 103, and the thickness of the first P-type buried layer 104 is the same as the thickness of the L-shaped N-type current spreading layer 103 in the lateral extension direction.

[0064] In this embodiment of the invention, the oxide layer extends into the second N+ region, covering a portion of the surface of the second N+ region.

[0065] In this embodiment of the invention, the doping concentration of the N-type current extension layer 103 is greater than that of the N-type epitaxial layer 102.

[0066] In this embodiment of the invention, a drain electrode 112 is also included, disposed on one side of the N+ type substrate 101.

[0067] Reference Figure 3 The diagram shows a schematic of another MOSFET device according to an embodiment of the present invention. The MOSFET device further includes a drain 112, which is disposed on the other side of the N+ type substrate 101.

[0068] In this embodiment of the invention, the barrier height formed by the N-type current extension layer and the first P-type buried layer is less than the barrier height formed by the N-type current extension layer and the P-type base region and the barrier height formed by the N-type epitaxial layer and the first P-type buried layer.

[0069] Reference Figure 4 The diagram shows a schematic of the body diode and channel diode of a MOSFET device according to an embodiment of the present invention, including a first body diode 11, a second body diode 12, and a channel diode 13.

[0070] The body diode is a parasitic diode integrated in power devices such as MOSFETs or IGBTs, typically located between the source and drain of the device. The body diode is an unavoidable parasitic effect in the device structure, and its characteristics directly affect the device's reverse recovery performance and switching losses. The role of the body diode: During reverse recovery, the body diode generates reverse recovery charge (Qrr) and reverse recovery time (trr), leading to increased switching losses. The reverse recovery characteristics of the body diode directly affect the switching efficiency and reliability of the device. In some applications (such as motor drives and inverters), the body diode provides a freewheeling path to maintain current continuity. The forward voltage drop and reverse recovery characteristics of the body diode directly affect the efficiency and reliability of the device. The body diode is a parasitic effect in the MOSFET structure and cannot be completely eliminated, but its characteristics can be improved by optimizing the device structure. The structure of the body diode: The body diode is a PN junction formed by a P-type base region (P-Body) and an N-type source region (N+Source). The P-type base region and the N-type source region form a PN junction, thus forming the body diode.

[0071] The P-type base region 109 and the N-type current extension layer 103 are connected vertically, forming a PN junction to form the first body diode 11.

[0072] The P-type buried layer 104 and the N-type epitaxial layer 102 are connected vertically, forming a PN junction to form a second body diode 12.

[0073] The N-type current extension layer 103 is connected to the P-type buried layer 104 from left to right. The P-type buried layer 104 is located below the trench. The first N+ region 105 is disposed in a groove formed on the surface of the first P-type buried layer 104. The trench contains a gate polysilicon region 107. Figure 4 A channel diode 13 is formed within the dashed box.

[0074] When the source polysilicon region 106 is connected to the source 112, and the gate polysilicon region 107 is grounded or has a negative voltage, the drain 113 is connected to a low level, and the source 112 is connected to a high level, i.e., the device is in reverse conduction mode, a channel diode 13 is effectively integrated below the source polysilicon region 106. Figure 4 Within the dashed box. The specific working principle is as follows: After a certain voltage is applied to the split gate (i.e., the source polysilicon region 106) connected to the source 112, the P-type buried layer 104 at the bottom of the split gate will form a channel; after the channel is open, the source 112 voltage is driven by the voltage, so the current flow direction is from the drain 113 - N-type epitaxial layer 102 - N-type current extension layer 103 - P-type buried layer 104 channel - first N+ region 105 - Anode (source 112).

[0075] Reference Figure 5 The diagram shows an equivalent circuit diagram of a MOSFET device according to an embodiment of the present invention. It can be seen that the integrated channel diode 13 is connected in parallel with the first body diode 11 and the second body diode 12. A via exists between the source polysilicon region 106 and the source 112, allowing them to be connected in parallel. Drift That is, the resistance R of the N-type epitaxial layer 102. Sub That is, the resistance of the N-type substrate 101. Figure 5 This is mainly used to explain why the channel diode 13 conducts before the first body diode 11 and the second body diode 12 during reverse conduction. During reverse conduction, the Source (source 112) is at a high level, and the forward voltage of the channel diode 13 is lower than that of the first body diode 11 and the second body diode 12. Therefore, when the voltage applied to the Source (source 112) is greater than that of the channel diode 13 but less than that of the first body diode 11 and the second body diode 12, the entire SiC MOS is in the reverse conduction state.

[0076] Reference Figure 6 The diagram illustrates a partial structure of a MOSFET device according to an embodiment of the present invention, along with a conduction band distribution at the cut-off point. It can be seen that when the device is in reverse conduction mode, electrons in the N-type current extension layer 103 must overcome the potential barrier height of a diode formed by the N-type current extension layer 103 and the first P-type buried layer 104 to flow through the source 112. Figure 6In the B-B' configuration, at the interface between the first P-type buried layer 104 and the oxide layer 108, due to the downward bending of the surface energy bands, electrons only need to overcome a relatively low potential barrier to form a conductive channel and enter the source region. Figure 6 In the A-A' configuration, the surface of the first P-type buried layer 104 is in a depleted state with a very low hole density, resulting in an electron current and unipolar conduction. Therefore, the channel diode 13 conducts before the first body diode 11 and the second body diode 12. The second body diode 12 is a diode composed of the first P-type buried layer 104 and the N-type epitaxial layer 102. Since the doping of the N-type epitaxial layer 102 is lower than that of the N-type current spreading layer 103, the barrier height of the second body diode 12 is higher than that of the first body diode 11, which is composed of the N-type current spreading layer 103 and the first P-type buried layer 104. Furthermore, both the first body diode 11 and the second body diode 12 conduct bipolarly. Due to the presence of stacking faults in the silicon carbide epitaxial wafer, electrons and holes recombine in the drift region, releasing energy and activating the stacking faults, which reduces the device's conductivity and reliability.

[0077] In the depletion state, the surface band bends downwards, and electrons accumulate at the bottom of the conduction band where it bends downwards, while holes move away from that point. When the Source (source 112) is given a high level, the downward bending of the surface band increases further, and more electrons accumulate at the bend.

[0078] Bipolar conduction refers to the conductivity phenomenon in semiconductor devices where both electrons and electrons are present simultaneously in the conducting state due to the injection and accumulation of minority carriers (holes or electrons). Bipolar conduction commonly occurs in bipolar devices (such as IGBTs) and minority carrier devices (such as the body diode of a MOSFET), and its characteristics directly affect the device's conduction losses, switching speed, and reliability. The effects of bipolar conduction include: increased on-resistance, leading to increased conduction losses; decreased switching speed, affecting dynamic performance; and accumulation of minority carriers (holes or electrons), impacting reliability.

[0079] Stacking faults are defects in the silicon carbide crystal structure, typically caused by irregular atomic layer arrangement during crystal growth. Stacking faults introduce additional energy levels, affecting carrier recombination and migration. During bipolar conduction, electrons and holes recombine in the drift region, releasing energy (such as photons or heat). This energy release may activate stacking faults, leading to defect propagation and accumulation. Activation of stacking faults further disrupts the crystal structure, increasing the defect density. Increased defect density reduces device conductivity and may cause device failure. Activation of stacking faults also increases the resistance in the drift region, further reducing conductivity. This decrease in conductivity increases conduction losses, affecting device efficiency. Furthermore, increased defect density leads to decreased device reliability, potentially causing premature device failure and impacting lifespan.

[0080] For the second body diode 12, the barrier height that electrons in the N-type current extension layer 103 need to overcome to flow through the P-type base region 109 and into the source 112 is also higher than the barrier height at the interface (A-A') between the first P-type buried layer 104 and the source-dip oxide layer 108. Therefore, the channel diode 13 will also conduct before the second body diode 12.

[0081] In addition, when the gate is grounded or has a negative voltage, the drain is connected to a high level, and the source is grounded, i.e. when the device is in a forward blocking state, the first P-type buried layer 104 connected to the source 112 will cut off most of the electric field lines of the drain at that point, reducing the electric field strength at the bottom of the gate trench and improving the reliability of the device.

[0082] Forward Blocking State: When the device is in the forward blocking state, a positive voltage is applied to the drain and the source is grounded. At this time, the PN junction of the device is in a reverse bias state, and the electric field is mainly concentrated in the drift region. In the forward blocking state, the electric field lines extend from the drain to the source and concentrate at the bottom of the gate trench. The electric field strength at the bottom of the gate trench is high, which may lead to local breakdown and affect the reliability of the device. The first P-type buried layer 104 is located near the bottom of the gate trench and is connected to the source 114, forming a low-impedance path that attracts the electric field lines, causing them to be cut off at the first P-type buried layer 104. Due to the presence of the first P-type buried layer 104, the electric field lines are shielded at the first P-type buried layer 104, reducing the electric field strength at the bottom of the gate trench. The reduced electric field strength at the bottom of the gate trench reduces the risk of local breakdown, improves the device's withstand voltage capability, and extends the device's lifespan.

[0083] The split-gate SiC MOSFET structure with integrated channel diode in this embodiment of the invention has the advantage of integrating a channel diode with a turn-on voltage lower than that of the SiC MOSFET body diode, thus eliminating the bipolar degradation caused by the SiC MOSFET body diode during reverse conduction. Furthermore, since the channel diode is integrated below the trench, its P-type buried layer can adjust the internal electric field distribution during reverse breakdown, further optimizing the device's reliability.

[0084] In this embodiment of the invention, the substrate of the N-type substrate 101 and the N-type epitaxial layer 102 is silicon carbide.

[0085] In this embodiment of the invention, the N-type substrate 101 is an N+ type substrate, the N-type epitaxial layer 102 is an N- type epitaxial layer, and the doping concentration of the N-type epitaxial layer 102 is lower than that of the N-type substrate 101.

[0086] In this embodiment of the invention, the drain 113 is a back metal layer and the source 112 is a front metal layer.

[0087] In this embodiment of the invention, the device further includes:

[0088] A second P-type buried layer 114 is disposed above the N-type substrate 101. The second P-type buried layer 114 is connected to the N-type current spreading layer 103. The first P-type buried layer 104 and the second P-type buried layer 114 are respectively located on both sides of the N-type current spreading layer 103. The second P-type buried layer 114 extends to the P+ region 110 and is connected to the second N+ region 110. The extended portion is connected to the P-type base region 109.

[0089] Reference Figure 7 The device further includes a second P-type buried layer 114, which extends to and occupies the position of the P+ region 110, connects to the second N+ region 110, and the extended portion connects to the P-type base region 109. With the double P-type buried layer structure, when the device is in forward blocking mode, the double P-type buried layer attracts more electric field lines, which are then cut off, reducing the electric field strength at the bottom of the gate trench and improving device reliability.

[0090] This invention addresses the issues of high body diode freewheeling loss and bipolar degradation in SiC MOSFETs by proposing a novel SiC MOSFET structure that improves the third-quadrant characteristics. The third-quadrant characteristic refers to the operating state of a semiconductor device in reverse freewheeling mode. In this mode, the source voltage is higher than the drain voltage, and current flows from the source to the drain through the body diode. The third-quadrant characteristic directly affects the device's reverse recovery performance, switching losses, and reliability. In DC circuits, the relationship between current and voltage can be represented by four quadrants. The third quadrant indicates that both current and voltage are negative, meaning the current flows from the source to the drain, and the voltage is negative. In semiconductor devices, the third-quadrant characteristic corresponds to the reverse freewheeling mode. When the source voltage is higher than the drain voltage, current flows from the source to the drain through the body diode. The reverse freewheeling mode typically occurs after the device is turned off, where the current in the inductor freewheels through the body diode, maintaining current continuity.

[0091] This invention discloses a novel split-gate SiC MOSFET structure with an integrated channel diode. The advantage of this structure lies in its integration of a channel diode with a turn-on voltage lower than that of the SiC MOSFET body diode, eliminating the bipolar degradation caused by the SiC MOSFET body diode during reverse conduction. Furthermore, since the channel diode is integrated below the trench, its P-type buried layer can adjust the internal electric field distribution during reverse breakdown, further optimizing the device's reliability.

[0092] In this embodiment of the invention, a chip is provided, including the MOSFET device described above.

[0093] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0094] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0095] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0096] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0097] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0098] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0099] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0100] The MOSFET device and chip provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A MOSFET device, characterized in that, The device includes: N-type substrate; An N-type epitaxial layer is disposed on one side of the N-type substrate; An N-type current spreading layer and a first P-type buried layer are disposed above the N-type epitaxial layer; the N-type current spreading layer is connected to the first P-type buried layer; The first N+ region is located in a groove formed on the surface of the first P-type buried layer; The trench is formed above the N-type current spreading layer and the first P-type buried layer; A source polysilicon region, a gate polysilicon region, and an oxide layer are disposed within the trench, with the oxide layer covering the surfaces of the source polysilicon region and the gate polysilicon region. The source polysilicon region is connected to the first P-type buried layer, the first N+ region, and the N-type current spreading layer through the oxide layer, forming a channel diode below the source polysilicon region through the N-type current spreading layer and the first P-type buried layer. The gate polysilicon region is connected to the N-type current spreading layer through the oxide layer, and the gate polysilicon region is connected to the source polysilicon region through the oxide layer. A P-type base region is disposed above the N-type current spreading layer. The P-type base region is connected to the side of the gate polysilicon region through the oxide layer. The barrier height formed by the N-type current spreading layer and the first P-type buried layer is less than the barrier height formed by the N-type current spreading layer and the P-type base region and the barrier height formed by the N-type epitaxial layer and the first P-type buried layer. The P+ region and the second N+ region are disposed above the P-type base region. The second N+ region is connected to the side of the gate polysilicon region through the oxide layer. The second N+ region and the P+ region are located in the same layer. The source electrode is formed on the surface of the oxide layer, the first P-type buried layer, the first N+ region, the P+ region, and the second N+ region. The oxide layer corresponding to the source polysilicon region is provided with contact holes to allow the source electrode to contact the source polysilicon region. When the MOSFET device is in a forward blocking state, the first P-type buried layer connected to the source electrode is used to reduce the electric field strength at the bottom of the gate trench.

2. The MOSFET device according to claim 1, characterized in that, The N-type current spreading layer is L-type.

3. The MOSFET device according to claim 1, characterized in that, The oxide layer extends into the second N+ region, covering a portion of the surface of the second N+ region.

4. The MOSFET device according to claim 1, characterized in that, The substrate of the N-type substrate and the substrate of the N-type epitaxial layer are silicon carbide.

5. The MOSFET device according to claim 1, characterized in that, Also includes: A second P-type buried layer is disposed above the N-type substrate. The second P-type buried layer is connected to the N-type current spreading layer. The first P-type buried layer and the second P-type buried layer are located on both sides of the N-type current spreading layer, respectively. The second P-type buried layer extends to the P+ region and is connected to the second N+ region. The extended portion is connected to the P-type base region.

6. The MOSFET device according to claim 1, characterized in that, Also includes: The drain is located on the other side of the N+ type substrate.

7. The MOSFET device according to claim 1, characterized in that, The doping concentration of the N-type current spreading layer is greater than that of the N-type epitaxial layer.

8. The MOSFET device according to claim 1, characterized in that, The N-type substrate is an N+ type substrate, the N-type epitaxial layer is an N- type epitaxial layer, and the doping concentration of the N-type epitaxial layer is lower than that of the N-type substrate.

9. The MOSFET device according to claim 6, characterized in that, The drain electrode is the back metal layer, and the source electrode is the front metal layer.

10. A chip comprising a MOSFET device as described in any one of claims 1-9.

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