LDMOS device and preparation method thereof

Abstract

The invention relates to the technical field of MOS devices. The invention specifically relates to an LDMOS device and a preparation method thereof. The LDMOS device provided by the invention comprises a semiconductor substrate layer; the first gate structure is located on the surface of the semiconductor substrate layer; the second gate structure and the first gate structure are separately arranged; the SAB barrier layer at least covers part of the surface of the first gate structure and completely covers the second gate structure; the field plate conductive column extends from the field plate lead-out conductive layer to the SAB barrier layer and penetrates through the device dielectric layer; wherein the second gate structure at least comprises two gate sub-conductive layers which are arranged at an interval and an interval filling layer which is filled between the two gate sub-conductive layers; the projection of the field plate conductive column on the SAB barrier layer falls into the projection range of the interval filling layer on the SAB barrier layer. According to the invention, the problem of tedious processing steps of the field plate of the LDMOS device can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS devices, and in particular to an LDMOS device and a preparation method thereof. Background Art

[0002] With the continuous development of semiconductor technology, the application of power devices is becoming more and more extensive, among which LDMOS (Laterally Diffused Metal Oxide Semiconductor) is widely used in wireless communication, broadcasting and television, radar, medical and industrial fields. In LDMOS devices, the trade-off between on-resistance and breakdown voltage is the focus of device design. With the increasing application of LDMOS, higher requirements are put forward for the performance of LDMOS such as voltage resistance and output power, such as requiring it to have a higher breakdown voltage.

[0003] Field plate technology is a common technical method for improving the withstand voltage of LDMOS devices. A field plate is set above the drift region of the substrate, and an electric field is applied to the drift region to increase the breakdown voltage. One common field plate is to use semiconductor materials or metal materials to form a column structure of metal or semiconductor materials as a field plate on the side of the barrier layer at the corresponding position above the drift region of the substrate facing away from the substrate. This method usually requires that after the dielectric layer of the upper structure of the substrate is formed, the dielectric layer is punched to form a field plate. On the one hand, the column structure as a field plate needs to cover the drift region as much as possible and requires a suitable resistance value, so the diameter is large in size, resulting in a large volume occupied by the field plate part, and balancing the resistance and volume of the field plate becomes a cumbersome problem. On the other hand, there are usually more than one size of LDMOS devices in the entire semiconductor structure, and then there are also multiple sizes of field plates, and the corresponding field plate fills multiple holes. Since the same layer structure is usually prepared synchronously, it is difficult to form holes of different sizes in one step, and multiple steps are required to complete, resulting in cumbersome process steps.

[0004] Therefore, a solution is needed to solve the problem that the field plate of the LDMOS device is difficult to balance the relationship between resistance and volume, and the processing process is complicated due to the requirements of different aperture sizes. Summary of the invention

[0005] Therefore, the present invention provides an LDMOS device and a method for preparing the same, so as to solve the problem that the field plate of the LDMOS device is difficult to balance the relationship between resistance and volume, and the processing process is complicated due to the requirements of apertures of different sizes.

[0006] In one aspect of the present invention: the present invention provides an LDMOS device, comprising: a semiconductor substrate layer; a first gate structure, located on the surface of the semiconductor substrate layer; a second gate structure, separately arranged from the first gate structure; a SAB barrier layer, the SAB barrier layer at least covers a portion of the surface of the first gate structure, and extends to one side along the side of the first gate structure to the surface of the semiconductor substrate layer, and further extends on the surface of the semiconductor substrate layer and completely covers the second gate structure; a device dielectric layer, covering the first gate structure, the second gate structure and the SAB barrier layer; a field plate lead-out conductive layer, located on the surface of the device dielectric layer on the side facing away from the semiconductor substrate layer; a field plate conductive column, extending from the field plate lead-out conductive layer to the SAB barrier layer and penetrating the device dielectric layer; wherein the second gate structure comprises at least two gate sub-conductive layers spaced apart, and a spacer filling layer filling the spacer between the two gate sub-conductive layers; the projection of the field plate conductive column on the SAB barrier layer falls within the projection range of the spacer filling layer on the SAB barrier layer.

[0007] The LDMOS device provided by the present invention has a discrete second gate structure arranged on the side of the first gate structure, a SAB barrier layer covers the second gate structure, and a field plate conductive column is arranged at a position corresponding to the second gate structure. The second gate structure and the first gate structure can be formed synchronously, and the second gate structure includes two discrete gate sub-conductive layers, and the spacing filling layer therebetween can be used to retain the remaining structure when etching the sidewalls, without the need for a new mask, and the retained spacing filling layer can just support the SAB barrier layer of this part as an etching stop layer for the field plate conductive column, so that there is no need to thicken the SAB barrier layer. In addition, the field plate conductive column does not need to be adjusted for the different etching rates caused by field plate conductive columns of different sizes. Field plate conductive columns of different sizes arranged on the same wafer can also be etched at the same time.

[0008] Optionally, the LDMOS device provided by the present invention also includes: a second gate structure including second side walls spaced apart, two gate sub-conductive layers located between the second side walls and spaced apart, and a space filling layer filling the two gate sub-conductive layers; the SAB barrier layer completely covers the top of the second gate structure, extends along the second side walls toward the surface of the semiconductor substrate layer, and continues to spread and extend on the surface of the semiconductor substrate layer.

[0009] Optionally, the LDMOS device provided by the present invention also includes: the first gate structure includes a first gate conductive layer and first side walls on both sides of the first gate conductive layer; the SAB barrier layer at least covers a portion of the first gate conductive layer, extends toward one side of the second gate structure, extends along the first side wall to the surface of the semiconductor substrate layer, and forms an integrated structure with the portion covering the second gate structure.

[0010] Optionally, the LDMOS device provided by the present invention also includes: a source and a drain, the source and the drain are located in the semiconductor substrate layer, and one side surface of the source and the drain exposes the surface of the semiconductor substrate layer; a first gate structure is located between the source and the drain; a second gate structure is located between the first gate structure and the drain; a gate lead-out conductive column is located on the portion of the surface of the first gate conductive layer not covered by the SAB barrier layer, and passes through the device dielectric layer and is connected to the gate conductive metal layer on the surface of the device dielectric layer; a source lead-out conductive column is located on the surface of the source, and passes through the device dielectric layer, and is connected to the source conductive metal layer on the surface of the device dielectric layer; a drain lead-out conductive column is located on the surface of the drain, and passes through the device dielectric layer and is connected to the drain conductive metal layer on the surface of the device dielectric layer.

[0011] Optionally, in the LDMOS device, the spacing distance between the two gate sub-conductive layers is 0.05 μm to 0.2 μm; and the ratio between the lateral dimension of a single gate sub-conductive layer and the lateral dimension of the second sidewall spacer is 1:1 to 1:3.

[0012] In another aspect of the present invention, the present invention also provides a method for forming an LDMOS device, comprising the following steps: providing a semiconductor substrate layer; forming a first gate structure and a second gate structure separately arranged from the first gate structure on the surface of the semiconductor substrate layer; forming a SAB barrier layer, the SAB barrier layer at least covering a portion of the surface of the first gate structure, and extending to one side along the side of the first gate structure to the surface of the semiconductor substrate layer, and further extending on the surface of the semiconductor substrate layer and completely covering the second gate structure; forming a device dielectric layer, covering the first gate structure, the second gate structure and the SAB barrier layer; forming a field plate lead-out conductive layer on the surface of the device dielectric layer facing away from the semiconductor substrate layer; forming a field plate conductive column in the device dielectric layer, the field plate conductive column extending from the field plate lead-out conductive layer to the SAB barrier layer and penetrating the device dielectric layer; wherein: the second gate structure comprises at least two gate sub-conductive layers spaced apart, and a space filling layer filling the two gate sub-conductive layers; the projection of the field plate conductive column on the SAB barrier layer falls within the projection range of the space filling layer on the SAB barrier layer.

[0013] The method for forming an LDMOS device provided by the present invention is characterized in that a separate second gate structure is arranged on the side of the first gate structure, a SAB barrier layer covers the second gate structure, and a field plate conductive column is arranged at a position corresponding to the second gate structure. The second gate structure and the first gate structure can be formed synchronously, and the second gate structure includes two separate gate sub-conductive layers, and the spacing filling layer therebetween can be used to retain the remaining structure when etching the sidewall, without the need for a new mask, and the reserved spacing filling layer can just support the SAB barrier layer of this part as an etching stop layer for the field plate conductive column, so that there is no need to thicken the SAB barrier layer. In addition, the field plate conductive column can change its size within a certain range (1 to several hundred times) without adjusting the etching conditions of the field plate conductive column, which simplifies the process steps and saves costs.

[0014] Optionally, the steps of forming the first gate structure and the second gate structure include: forming an initial conductive layer on the surface of the semiconductor substrate layer; patterning the initial conductive layer to form a first gate conductive layer and two gate sub-conductive layers separate from the first gate conductive layer, the two gate sub-conductive layers being close to each other and spaced apart; forming an initial dielectric layer on the surface of the semiconductor substrate layer, the initial dielectric layer surrounding the first gate conductive layer and the sides of the two gate sub-conductive layers, and filling the space between the two gate sub-conductive layers; patterning and etching the initial dielectric layer to form first side walls on both sides of the first gate conductive layer and second side walls on the sides of the gate sub-conductive layers, the initial dielectric layer between the two gate sub-conductive layers being retained to form a space filling layer; the first side walls and the first gate conductive layer constitute the first gate structure; the second side walls, the two gate sub-conductive layers and the space filling layer constitute the second gate structure.

[0015] Optionally, the step of forming a field plate conductive column includes: etching through the device dielectric layer to form a through hole extending from the surface of the device dielectric layer facing away from the semiconductor substrate layer to the surface of the semiconductor substrate layer; a SAB barrier layer covering the second gate structure serves as a stop layer for the etching process; the aperture of the through hole is smaller than the minimum horizontal dimension of the spacing filling layer; and the through hole is filled with a conductive material.

[0016] Optionally, the method for forming an LDMOS device provided by the present invention also includes: forming a source and a drain, the source and the drain are located in the semiconductor substrate layer, and one side surface of the source and the drain exposes the surface of the semiconductor substrate layer; a first gate structure and a second gate structure are formed between the source and the drain, and the second gate structure is formed between the first gate structure and the drain; a field plate conductive column and a field plate lead-out conductive layer are formed in an area of ​​the device dielectric layer corresponding to the second gate structure.

[0017] Optionally, the method for forming an LDMOS device provided by the present invention also includes: forming a gate lead-out conductive column, a source lead-out conductive column and a drain lead-out conductive column; the gate lead-out conductive column is formed on a portion of the surface of the first gate conductive layer that is not covered by the SAB barrier layer, and penetrates the device dielectric layer, and is connected to the gate conductive metal layer on the surface of the device dielectric layer; the source lead-out conductive column is formed on the source surface, and penetrates the device dielectric layer, and is connected to the source conductive metal layer on the surface of the device dielectric layer; the drain lead-out conductive column is formed on the drain surface, and penetrates the device dielectric layer, and is connected to the drain conductive metal layer on the surface of the device dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the structure of an LDMOS device;

[0020] Figure 2 A schematic structural diagram of an LDMOS device according to an embodiment of the present invention;

[0021] Figure 3-Figure 10 The figure is a schematic diagram of the states of various steps in a method for forming an LDMOS device according to an embodiment of the present invention.

[0022] Description of reference numerals:

[0023] 100-semiconductor substrate layer; 210-source; 220-drain; 230-gate structure; 2301-first gate structure; 2302-second gate structure; 2310-initial conductive layer; 2320-initial dielectric layer; 2311-first gate conductive layer; 2312-gate sub-conductive layer; 2321-first side wall; 2322-second side wall; 2323-spacer filling layer; 300-SAB barrier layer; 400-device dielectric layer; 600-field plate metal column; 610-source lead conductive column; 620-drain lead conductive column; 630-gate lead conductive column; 640-field plate conductive column; 700-field plate lead conductive layer. DETAILED DESCRIPTION

[0024] refer to Figure 1, a schematic structural diagram of an LDMOS device, comprising: a semiconductor substrate layer 100; a source electrode 210 and a drain electrode 220, wherein the source electrode 210 and the drain electrode 220 are located in the semiconductor substrate layer 100, and one side surface of the source electrode 210 and the drain electrode 220 exposes the surface of the semiconductor substrate layer 100; a gate structure 230, located on the surface of the semiconductor substrate layer 100 and located between the source electrode 210 and the drain electrode 220; a SAB barrier layer 300, wherein the SAB barrier layer 300 at least covers the gate structure 2 The device dielectric layer 400 includes a gate structure 230 and a SAB barrier layer 300, and a field plate lead-out conductive layer 700 located on a surface of the device dielectric layer 400 facing away from the semiconductor substrate layer 100, and a field plate metal column 600 extending from the field plate lead-out conductive layer 700 to the SAB barrier layer 300 and penetrating the device dielectric layer 400.

[0025] In the device, a drift region D is formed in the semiconductor substrate layer 100 between the drain 220 and the gate structure 230. The breakdown voltage of this part is low, so a field plate needs to be arranged above the drift region D to provide an electric field that affects the drift region D, so as to increase the breakdown voltage of this part. Figure 1 In the LDMOS device shown, a conductive metal column is arranged above the SAB barrier layer 300 as a field plate, namely, a field plate metal column 600. This structural design can provide the field plate function and improve the breakdown voltage. However, on the one hand, the conductive metal column needs to cover the drift region as much as possible, and on the other hand, it must penetrate the device dielectric layer to connect to the conductive layer above, and a suitable resistance value is required. Therefore, the diameter is relatively large in size, resulting in a large volume occupied by the field plate part. Balancing the resistance and volume of the field plate becomes a cumbersome problem during design. On the other hand, there is usually more than one size of LDMOS device in the entire semiconductor structure, and thus there are also multiple sizes of field plates, and there are also multiple corresponding holes filled by the field plates. Since the same-layer structure is usually prepared synchronously, it is difficult to form holes of different sizes in one step, and multiple steps are required to complete, resulting in cumbersome process steps.

[0026] Based on the above problems, the present invention provides an LDMOS device to solve the problem that the field plate of the LDMOS device is difficult to balance the relationship between resistance and volume, and the processing process is complicated due to the requirements of different aperture sizes. The LDMOS device provided by the present invention includes: a semiconductor substrate layer; a first gate structure, located on the surface of the semiconductor substrate layer; a second gate structure, which is separately arranged from the first gate structure; a SAB barrier layer, the SAB barrier layer at least covers a portion of the surface of the first gate structure, and extends to one side along the side of the first gate structure to the surface of the semiconductor substrate layer, and further extends on the surface of the semiconductor substrate layer and completely covers the second gate structure; a device dielectric layer, covering the first gate structure, the second gate structure and the SAB barrier layer; a field plate lead-out conductive layer, located on the surface of the device dielectric layer facing away from the semiconductor substrate layer; a field plate conductive column, extending from the field plate lead-out conductive layer to the SAB barrier layer and penetrating the device dielectric layer; wherein the second gate structure includes at least two gate sub-conductive layers arranged at intervals, and a spacer filling layer filling the two gate sub-conductive layers; the projection of the field plate conductive column on the SAB barrier layer falls within the projection range of the spacer filling layer on the SAB barrier layer.

[0027] The present invention also provides a method for forming an LDMOS device to solve the problem that the field plate of the LDMOS device is difficult to balance the relationship between the resistance value and the volume, and the processing process has complicated steps due to the requirements of apertures of different sizes. The method for forming an LDMOS device provided by the present invention comprises the following steps: providing a semiconductor substrate layer; forming a first gate structure and a second gate structure separately arranged from the first gate structure on the surface of the semiconductor substrate layer; forming a SAB barrier layer, wherein the SAB barrier layer at least covers a part of the surface of the first gate structure, and extends to one side along the side of the first gate structure to the surface of the semiconductor substrate layer, and further extends on the surface of the semiconductor substrate layer and completely covers the second gate structure; forming a device dielectric layer, covering the first gate structure, the second gate structure and the SAB barrier layer; forming a field plate lead-out conductive layer on the surface of the device dielectric layer facing away from the semiconductor substrate layer; forming a field plate conductive column in the device dielectric layer, wherein the field plate conductive column extends from the field plate lead-out conductive layer to the SAB barrier layer and penetrates the device dielectric layer; wherein: the second gate structure comprises at least two gate sub-conductive layers spaced apart, and a space filling layer filling the two gate sub-conductive layers; and the projection of the field plate conductive column on the SAB barrier layer falls within the projection range of the space filling layer on the SAB barrier layer.

[0028] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0029] Example 1

[0030] refer to Figure 2 , this embodiment provides an LDMOS device, including:

[0031] Semiconductor substrate layer 100;

[0032] The first gate structure 2301 is located on the surface of the semiconductor substrate layer 100;

[0033] The second gate structure 2302 is separately provided from the first gate structure 2301;

[0034] A SAB barrier layer 300, the SAB barrier layer 300 covers at least a portion of the surface of the first gate structure 2301, and extends along the side of the first gate structure 2301 to the surface of the semiconductor substrate layer 100, and further extends on the surface of the semiconductor substrate layer 100 and completely covers the second gate structure 2302;

[0035] A device dielectric layer 400 covering the first gate structure 2301, the second gate structure 2302 and the SAB barrier layer 300;

[0036] The field plate lead-out conductive layer 700 is located on the surface of the device dielectric layer 400 facing away from the semiconductor substrate layer 100;

[0037] The field plate conductive pillar 640 extends from the field plate conductive layer 700 to the SAB barrier layer 300 and penetrates the device dielectric layer 400;

[0038] The second gate structure 2302 includes at least two gate sub-conductive layers 2312 spaced apart and a space filling layer filling the space between the two gate sub-conductive layers 2312 ; the projection of the field plate conductive column 640 on the SAB barrier layer 300 falls within the projection range of the space filling layer on the SAB barrier layer 300 .

[0039] The LDMOS device provided in this embodiment has a separate second gate structure 2302 disposed on the side of the first gate structure 2301, the SAB barrier layer 300 covers the second gate structure 2302, and the field plate conductive column 640 is disposed at a position corresponding to the second gate structure 2302. The second gate structure 2302 and the first gate structure 2301 can be formed simultaneously, and the second gate structure 2302 includes two separate gate sub-conductive layers 2312, and the spacing filling layer therebetween can be used to retain the remaining structure during the sidewall etching, without the need for a new mask, and the retained spacing filling layer can just support the SAB barrier layer 300 of this part as the etching stop layer of the field plate conductive column 640, so that the SAB barrier layer 300 does not need to be thickened. In addition, the field plate conductive column 640 does not need to be adjusted for the different etching rates caused by field plate conductive columns of different sizes. Field plate conductive columns of different sizes arranged on the same wafer can also be etched at the same time. The two gate sub-conductive layers 2312 disposed at intervals allow the spacer filling layer and each sidewall spacer located between the gate sub-conductive layers 2312 to be formed simultaneously without the need for additional processes.

[0040] Furthermore, in some embodiments, the second gate structure 2302 includes a second sidewall 2322 spaced apart, two gate sub-conductive layers 2312 located between the second sidewall 2322 and spaced apart, and a space filling layer 2323 filling the space between the two gate sub-conductive layers 2312; the SAB barrier layer 300 completely covers the top of the second gate structure 2302, extends along the second sidewall 2322 toward the surface of the semiconductor substrate layer 100, and continues to spread and extend on the surface of the semiconductor substrate layer 100.

[0041] Furthermore, in some embodiments, the first gate structure 2301 includes a first gate conductive layer 2311 and first side walls on both sides of the first gate conductive layer 2311; the SAB barrier layer 300 covers at least a portion of the first gate conductive layer 2311, extends toward the side of the second gate structure 2302, extends along the first side wall to the surface of the semiconductor substrate layer 100, and forms an integrated structure with the portion covering the second gate structure 2302.

[0042] Furthermore, in some embodiments, the LDMOS device provided by the present invention further includes:

[0043] The source 210 and the drain 220 are located in the semiconductor substrate layer 100, and one side surface of the source 210 and the drain 220 exposes the surface of the semiconductor substrate layer 100; the first gate structure 2301 is located between the source 210 and the drain 220; the second gate structure 2302 is located between the first gate structure 2301 and the drain 220;

[0044] The gate lead-out conductive pillar 630 is located at the portion of the surface of the first gate conductive layer 2311 not covered by the SAB barrier layer 300, penetrates the device dielectric layer 400, and is connected to the gate conductive metal layer (not shown) on the surface of the device dielectric layer 400;

[0045] The source lead-out conductive column 610 is located on the surface of the source 210 and penetrates the device dielectric layer 400 to be connected to the source conductive metal layer (not shown) on the surface of the device dielectric layer 400;

[0046] The drain lead-out conductive pillar 620 is located on the surface of the drain 220 , penetrates the device dielectric layer 400 , and is connected to the drain conductive metal layer (not shown) on the surface of the device dielectric layer 400 .

[0047] Furthermore, in some embodiments, the spacing distance between the two gate sub-conductive layers 2312 is 0.05 μm to 0.2 μm; and the ratio between the lateral dimension of a single gate sub-conductive layer 2312 and the lateral dimension of the second sidewall 2322 is 1:1 to 1:3.

[0048] The interval between the two gate sub-conductive layers 2312 should be small enough so that the interval filling layer 2323 between the two gate sub-conductive layers 2312 can still exist after etching when the gate sidewall is etched without a mask. This can be used as a barrier layer for subsequent etching of the field plate conductive column.

[0049] Example 2

[0050] refer to Figure 3-Figure 10 This embodiment provides a method for forming an LDMOS device, comprising the following steps:

[0051] Providing a semiconductor substrate layer 100;

[0052] A first gate structure 2301 and a second gate structure 2302 which is separately provided from the first gate structure 2301 are formed on the surface of the semiconductor substrate layer 100;

[0053] A SAB barrier layer 300 is formed, wherein the SAB barrier layer 300 covers at least a portion of the surface of the first gate structure 2301, and extends along a side of the first gate structure 2301 to the surface of the semiconductor substrate layer 100, and further extends on the surface of the semiconductor substrate layer 100 and completely covers the second gate structure 2302;

[0054] Forming a device dielectric layer 400 to cover the first gate structure 2301, the second gate structure 2302 and the SAB barrier layer 300;

[0055] A field plate lead-out conductive layer 700 is formed on the surface of the device dielectric layer 400 facing away from the semiconductor substrate layer 100;

[0056] A field plate conductive column 640 is formed in the device dielectric layer 400 , and the field plate conductive column extends from the field plate lead-out conductive layer 700 to the SAB barrier layer 300 and penetrates the device dielectric layer 400 ;

[0057] The second gate structure 2302 includes at least two gate sub-conductive layers 2312 spaced apart and a space filling layer 2323 filling the space between the two gate sub-conductive layers 2312 . The projection of the field plate conductive pillar 640 on the SAB barrier layer 300 falls within the projection range of the space filling layer 2323 on the SAB barrier layer 300 .

[0058] In the method for forming the LDMOS device provided in this embodiment, a separate second gate structure 2302 is arranged on the side of the first gate structure 2301, the SAB barrier layer 300 covers the second gate structure 2302, and the field plate conductive pillar 640 is arranged at a position corresponding to the second gate structure 2302. The second gate structure 2302 and the first gate structure 2301 can be formed simultaneously, and the second gate structure 2302 includes two separate gate sub-conductive layers 2312, and the spacer filling layer 2323 therebetween can be used to retain the remaining structure when etching the sidewall, without the need for a new mask, and the retained spacer filling layer 2323 can just support the SAB barrier layer 300 of this part as the etching stop layer of the field plate conductive pillar 640, so that there is no need to thicken the SAB barrier layer 300. In addition, the size of the field plate conductive pillar 640 can be changed within a certain range (1 to several hundred times) without adjusting the etching conditions of the field plate conductive pillar, which simplifies the process steps and saves costs.

[0059] Furthermore, in some embodiments, the steps of forming the first gate structure 2301 and the second gate structure 2302 include:

[0060] refer to Figure 3 , forming an initial conductive layer 2310 on the surface of the semiconductor substrate layer 100;

[0061] refer to Figure 4 , patterning the initial conductive layer 2310 to form a first gate conductive layer 2311 and two gate sub-conductive layers 2312 separated from the first gate conductive layer 2311, wherein the two gate sub-conductive layers 2312 are close to each other and spaced apart;

[0062] refer to Figure 5 , forming an initial dielectric layer 2320 on the surface of the semiconductor substrate layer 100 , the initial dielectric layer 2320 surrounds the first gate conductive layer 2311 and the sides of the two gate sub-conductive layers 2312 , and fills the interval between the two gate sub-conductive layers 2312 ;

[0063] refer to Figure 6, the initial dielectric layer 2320 is patterned and etched to simultaneously form the first sidewalls 2321 on both sides of the first gate conductive layer 2311 and the second sidewalls 2322 on the sides of the gate sub-conductive layer 2312. The initial dielectric layer between the two gate sub-conductive layers 2312 is retained to form a spacer filling layer 2323.

[0064] The first spacer 2321 and the first gate conductive layer 2311 constitute a first gate structure 2301 ; the second spacer 2322 , two gate sub-conductive layers 2312 and the spacer filling layer 2323 constitute a second gate structure 2302 .

[0065] For further reference, Fig.10 In some embodiments, the step of forming the field plate conductive pillar 640 includes:

[0066] The device dielectric layer 400 is etched through to form a through hole extending from the surface of the device dielectric layer 400 facing away from the semiconductor substrate layer 100 to the surface of the device dielectric layer 400 facing the semiconductor substrate layer 100; the SAB barrier layer 300 covering the second gate structure 2302 is used as a stop layer for the etching process; the aperture of the through hole is smaller than the minimum horizontal dimension of the spacer filling layer 2323;

[0067] A conductive material fills the through hole.

[0068] Furthermore, in some embodiments, the method for forming an LDMOS device provided by the present invention further includes:

[0069] refer to Figure 3 , forming a source electrode 210 and a drain electrode 220, wherein the source electrode 210 and the drain electrode 220 are located in the semiconductor substrate layer 100, and one side surface of the source electrode 210 and the drain electrode 220 exposes the surface of the semiconductor substrate layer 100;

[0070] The first gate structure 2301 and the second gate structure 2302 are formed between the source 210 and the drain 220 , and the second gate structure 2302 is formed between the first gate structure 2301 and the drain 220 ;

[0071] The field plate conductive pillar 640 and the field plate lead-out conductive layer 700 are formed in a region of the device dielectric layer 400 corresponding to the second gate structure 2302 .

[0072] Furthermore, in some embodiments, the method for forming an LDMOS device provided by the present invention further includes:

[0073] refer to Figure 7, forming an initial SAB barrier layer 300', the initial SAB barrier layer 300' completely covers the surface of the semiconductor substrate layer 100, the surface of the first gate structure 2301, and the surface of the second gate structure 2302, and extends to the edge of the source 210 facing the inner side of the semiconductor substrate layer 100 and the edge of the drain 220 facing the inner side of the semiconductor substrate layer 100;

[0074] refer to Figure 8 , patterning the initial SAB barrier layer 300 ′, etching and removing a portion of the initial SAB barrier layer 300 ′, wherein the removed portion includes a portion located on the surface of the first gate structure 2301 , so that a portion of the first gate conductive layer 2311 is exposed, and the remaining initial SAB barrier layer 300 ′ forms a SAB barrier layer 300 .

[0075] Furthermore, in some embodiments, the method for forming an LDMOS device provided by the present invention further includes:

[0076] refer to Fig. 9 , forming a device dielectric layer 400 , wherein the device dielectric layer 400 covers the first gate structure 2301 , the second gate structure 2302 and the SAB barrier layer 300 .

[0077] refer to Fig.10 , forming a gate lead-out conductive pillar 630, a source lead-out conductive pillar 610, and a drain lead-out conductive pillar 620; in some embodiments, the steps of forming the gate lead-out conductive pillar 630, the source lead-out conductive pillar 610, and the drain lead-out conductive pillar 620 are performed simultaneously with the step of forming the field plate conductive pillar 640. In other embodiments, the steps of forming the gate lead-out conductive pillar 630, the source lead-out conductive pillar 610, and the drain lead-out conductive pillar 620 are performed at different times from the step of forming the field plate conductive pillar 640. To simplify the process steps, a simultaneous method can be adopted.

[0078] The gate lead-out conductive pillar 630 is formed on the surface of the first gate conductive layer 2311 which is not covered by the SAB barrier layer 300, and penetrates the device dielectric layer 400, and is connected to the gate conductive metal layer (not shown) on the surface of the device dielectric layer 400;

[0079] The source lead-out conductive column 610 is formed on the surface of the source 210, penetrates the device dielectric layer 400, and is connected to the source conductive metal layer (not shown) on the surface of the device dielectric layer 400;

[0080] The drain lead-out conductive pillar 620 is formed on the surface of the drain 220 , penetrates the device dielectric layer 400 , and is connected to the drain conductive metal layer (not shown) on the surface of the device dielectric layer 400 .

[0081] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. An LDMOS device, characterized in that: include: Semiconductor substrate layer; A first gate structure, located on the surface of the semiconductor substrate layer; A second gate structure is disposed separately from the first gate structure; A SAB barrier layer, the SAB barrier layer at least covers a portion of the surface of the first gate structure, extends along a side of the first gate structure to a surface of the semiconductor substrate layer, and further extends on the surface of the semiconductor substrate layer to completely cover the second gate structure; A device dielectric layer, covering the first gate structure, the second gate structure and the SAB barrier layer; A field plate lead-out conductive layer is located on a surface of the device dielectric layer on a side facing away from the semiconductor substrate layer; A field plate conductive column, extending from the field plate conductive layer to the SAB barrier layer and penetrating the device dielectric layer; The second gate structure comprises at least two gate sub-conductive layers spaced apart and a spacer filling layer filling the spacer between the two gate sub-conductive layers; the projection of the field plate conductive column on the SAB barrier layer falls within the projection range of the spacer filling layer on the SAB barrier layer.

2. The LDMOS device according to claim 1, characterized in that: Also includes: The second gate structure includes a second spacer spaced apart, two gate sub-conductive layers located between the second spacer spacers and spaced apart, and the spacer filling layer filled between the two gate sub-conductive layers; the SAB barrier layer completely covers the top of the second gate structure, extends along the second spacer spacer toward the surface of the semiconductor substrate layer, and continues to spread and extend on the surface of the semiconductor substrate layer.

3. The LDMOS device according to claim 1, characterized in that: Also includes: The first gate structure includes a first gate conductive layer and first spacers on both sides of the first gate conductive layer; The SAB barrier layer at least covers a portion of the first gate conductive layer, extends toward one side of the second gate structure, extends along the first sidewall to the surface of the semiconductor substrate layer, and forms an integral structure with the portion covering the second gate structure.

4. The LDMOS device according to claim 1, characterized in that: Also includes: A source electrode and a drain electrode, wherein the source electrode and the drain electrode are located in the semiconductor substrate layer, and one side surface of the source electrode and the drain electrode exposes the surface of the semiconductor substrate layer; The first gate structure is located between the source and the drain; the second gate structure is located between the first gate structure and the drain; A gate lead-out conductive column is located at a portion of the surface of the first gate conductive layer that is not covered by the SAB barrier layer, penetrates the device dielectric layer, and is connected to the gate conductive metal layer on the surface of the device dielectric layer; A source lead-out conductive column is located on the surface of the source electrode, penetrates the device dielectric layer, and is connected to the source conductive metal layer on the surface of the device dielectric layer; The drain lead-out conductive column is located on the surface of the drain, penetrates the device dielectric layer, and is connected to the drain conductive metal layer on the surface of the device dielectric layer.

5. The LDMOS device according to claim 2, characterized in that: The spacing distance between the two gate sub-conductive layers is 0.05 μm to 0.2 μm; The ratio between the lateral dimension of a single gate sub-conductive layer and the lateral dimension of the second sidewall spacer is 1:1 to 1:

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6. A method for forming an LDMOS device, characterized in that: The following steps are involved: providing a semiconductor substrate layer; forming a first gate structure and a second gate structure separately provided from the first gate structure on the surface of the semiconductor substrate layer; forming a SAB barrier layer, wherein the SAB barrier layer at least covers a portion of the surface of the first gate structure, extends along a side of the first gate structure to a surface of the semiconductor substrate layer, and further extends on the surface of the semiconductor substrate layer and completely covers the second gate structure; forming a device dielectric layer, covering the first gate structure, the second gate structure and the SAB barrier layer; Forming a field plate lead-out conductive layer on a surface of the device dielectric layer facing away from the semiconductor substrate layer; Forming a field plate conductive column in the device dielectric layer, wherein the field plate conductive column extends from the field plate lead-out conductive layer to the SAB barrier layer and penetrates the device dielectric layer; Wherein: the second gate structure comprises at least two gate sub-conductive layers spaced apart and a spacer filling layer filling the spacer between the two gate sub-conductive layers; the projection of the field plate conductive column on the SAB barrier layer falls within the projection range of the spacer filling layer on the SAB barrier layer.

7. The method for forming an LDMOS device according to claim 6, characterized in that: The steps of forming the first gate structure and the second gate structure include: Forming an initial conductive layer on the surface of the semiconductor substrate layer; patterning the initial conductive layer to form a first gate conductive layer and two gate sub-conductive layers separated from the first gate conductive layer, wherein the two gate sub-conductive layers are close to each other and spaced apart; An initial dielectric layer is formed on the surface of the semiconductor substrate layer, the initial dielectric layer surrounds the first gate conductive layer and the sides of the two gate sub-conductive layers, and fills the gap between the two gate sub-conductive layers; the initial dielectric layer is patterned and etched to form first side walls on both sides of the first gate conductive layer and second side walls on the sides of the gate sub-conductive layers, and the initial dielectric layer between the two gate sub-conductive layers is retained to form a gap filling layer; the first side walls and the first gate conductive layer constitute the first gate structure; the second side walls, the two gate sub-conductive layers and the gap filling layer constitute the second gate structure.

8. The method for forming an LDMOS device according to claim 7, characterized in that: The step of forming the field plate conductive column comprises: Etching through the device dielectric layer to form a through hole extending from the surface of the device dielectric layer facing away from the semiconductor substrate layer to the surface of the semiconductor substrate layer; the SAB barrier layer covering the second gate structure serves as a stop layer for the etching process; the aperture of the through hole is smaller than the minimum horizontal dimension of the spacer filling layer; A conductive material fills the through hole.

9. The method for forming an LDMOS device according to claim 7, characterized in that: Also includes: forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located in the semiconductor substrate layer, and one side surface of the source electrode and the drain electrode exposes the surface of the semiconductor substrate layer; The first gate structure and the second gate structure are formed between the source and the drain, and the second gate structure is formed between the first gate structure and the drain; The field plate conductive column and the field plate lead-out conductive layer are formed in a region of the device dielectric layer corresponding to the second gate structure.

10. The method for forming an LDMOS device according to claim 9, characterized in that: Also includes: forming a gate lead-out conductive column, a source lead-out conductive column and a drain lead-out conductive column; The gate lead-out conductive column is formed on a portion of the surface of the first gate conductive layer that is not covered by the SAB barrier layer, penetrates the device dielectric layer, and is connected to the gate conductive metal layer on the surface of the device dielectric layer; A source lead-out conductive column is formed on the surface of the source electrode, penetrates the device dielectric layer, and is connected to the source conductive metal layer on the surface of the device dielectric layer; The drain lead-out conductive column is formed on the surface of the drain, penetrates the device dielectric layer, and is connected to the drain conductive metal layer on the surface of the device dielectric layer.

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