Power semiconductor device

Abstract

This application relates to a power semiconductor device. The power semiconductor device includes: a cell region and a non-cell region, the non-cell region being adjacent to the cell region; the cell region includes a junction field effect transistor region; the power semiconductor device further includes a gate layer, the gate layer includes a first rectangular region, the first rectangular region is located above the junction field effect transistor region or in the non-cell region; the first rectangular region includes a hollowed-out region. The technical solution provided by this application can reduce the input capacitance of the device and the gate internal resistance of the device, and at the same time can reduce the charge and discharge amount of the drive and save the drive power, reduce the cost of the drive board, and make the drive board more miniaturized.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a power semiconductor device. Background Art

[0002] In the related art, a polysilicon gate layer is an essential component of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET for short). Its main function is to transmit the gate signal to each cell, so that the normal turn-on and turn-off of the cell can be controlled by the gate signal. The structure of the polysilicon gate layer has a very significant impact on the electrical performance of the MOSFET device. However, the structure of the polysilicon gate layer in the MOSFET device in the related art is rough and there is room for further improvement. Summary of the Invention

[0003] The purpose of this application is to provide a power semiconductor device, which can reduce the input capacitance of the device and the gate internal resistance of the device, and at the same time can reduce the charge and discharge amount of the drive and save the drive power, reduce the cost of the drive board, and make the drive board more miniaturized.

[0004] According to the first aspect of the embodiment of this application, a power semiconductor device is provided, including: a cell region and a non-cell region, the non-cell region is adjacent to the cell region; the cell region includes a junction field effect transistor region;

[0005] The power semiconductor device further includes: a gate layer, the gate layer includes a first rectangular region, the first rectangular region is located above the junction field effect transistor region; the first rectangular region includes a hollow region.

[0006] In an embodiment, the power semiconductor device further includes:

[0007] A substrate of a first conductivity type, the substrate includes an epitaxial layer of a first conductivity type;

[0008] A first well region and a second well region of a second conductivity type, located in the epitaxial layer;

[0009] A first source region, located in the first well region;

[0010] A second source region, located in the second well region; the edge of the first source region close to the second source region and the edge of the first well region close to the second well region form a first effective channel, and the edge of the second source region close to the first source region and the edge of the second well region close to the first well region form a second effective channel; the junction field effect transistor region is located between the first effective channel and the second effective channel;

[0011] When the first rectangular region is located above the junction field effect transistor region, the first rectangular region further includes a first gate bar and a second gate bar, and the hollow region is located between the first gate bar and the second gate bar;

[0012] The first gate bar is located above the first effective channel, and the projection of the first effective channel on the substrate is located within the projection of the first gate bar on the substrate;

[0013] The second gate bar is located above the second effective channel, and the projection of the second effective channel on the substrate is located within the projection of the second gate bar on the substrate.

[0014] In one embodiment, the distance between the edge of the first gate bar close to the second gate bar and the edge of the first well region close to the second well region is greater than or equal to the process margin;

[0015] The distance between the edge of the second gate bar close to the first gate bar and the edge of the second well region close to the first well region is greater than or equal to the process margin.

[0016] In one embodiment, the power semiconductor device further includes a gate oxide layer, and the gate oxide layer is located between the epitaxial layer and the gate layer;

[0017] The surface of the junction field effect transistor region is provided with a first microgroove, and the first microgroove is located below the hollow region.

[0018] In one embodiment, the power semiconductor device further includes a non-cell region, the non-cell region is adjacent to the cell region, the non-cell region is provided with a fifth rectangular region, and the fifth rectangular region includes a hollow region.

[0019] In one embodiment, the non-cell region is a gate pad region;

[0020] The hollow region is rectangular, and the fifth rectangular region further includes a first annular region, and the first annular region surrounds the hollow region;

[0021] The power semiconductor device further includes an insulating layer and a gate contact hole, the insulating layer is located above the first annular region, the gate contact hole penetrates through the insulating layer and contacts the first annular region, and the width of the first annular region is greater than or equal to the minimum allowable line width and greater than or equal to the minimum size of the gate contact hole.

[0022] In one embodiment, the non-cell region is a gate pad region;

[0023] The hollowed-out area is annular. The fifth rectangular area further includes a second annular area and the second rectangular area. The hollowed-out area surrounds the second rectangular area, and the second annular area surrounds the hollowed-out area;

[0024] The second rectangular area is floating.

[0025] In one embodiment, the non-cell area is a gate trace area;

[0026] The fifth rectangular area further includes a third rectangular area and a plurality of third gate bars. The first side of the third rectangular area is provided with the hollowed-out area and the third gate bars arranged alternately in sequence. The third gate bars are connected to the third rectangular area. The second side of the third rectangular area is provided with the hollowed-out area and the third gate bars arranged alternately in sequence. The first side and the second side are opposite in position;

[0027] The power semiconductor device further includes an insulating layer and a gate contact hole. The insulating layer is located above the third rectangular area. The gate contact hole penetrates through the insulating layer and contacts the third rectangular area. The width of the third rectangular area is less than the width of the fifth rectangular area. The width of the third rectangular area is greater than or equal to the minimum allowable line width and greater than or equal to the minimum size of the gate contact hole.

[0028] In one embodiment, the non-cell area is a terminal area;

[0029] The fifth rectangular area further includes a fourth rectangular area and a plurality of fourth gate bars. The hollowed-out area includes a plurality of first hollowed-out parts and second hollowed-out parts. The fourth gate bars and the first hollowed-out parts are located on one side of the fourth rectangular area close to the cell area and are arranged alternately. The fourth gate bars are connected to the fourth rectangular area. The second hollowed-out parts are located on the side of the fourth rectangular area far from the cell area. The fourth gate bars and the first hollowed-out parts extend along the width direction of the fourth rectangular area, and the second hollowed-out parts extend along the length direction of the fourth rectangular area;

[0030] The power semiconductor device further includes an insulating layer and a gate contact hole. The insulating layer is located above the fourth rectangular area. The gate contact hole penetrates through the insulating layer and contacts the fourth rectangular area. The width of the fourth rectangular area is greater than or equal to the minimum allowable line width and greater than or equal to the minimum size of the gate contact hole.

[0031] In one embodiment, the material of the gate layer is polysilicon.

[0032] In one embodiment, the materials of the substrate and the epitaxial layer are silicon carbide.

[0033] Compared with the prior art, the beneficial effects of the present application are as follows: Since the gate layer includes a first rectangular region located above the junction field effect transistor region, and the first rectangular region includes a hollowed-out region, the area of the gate layer can be reduced. As a result, the input capacitance of the device and the gate internal resistance of the device can be decreased. Meanwhile, the charge and discharge amount of the drive can be reduced, the drive power can be saved, the cost of the drive board can be decreased, and the drive board can be made more miniaturized.

[0034] Since the width of the gate layer or the area of the hollowed-out region can be greatly adjusted according to requirements, the parasitic parameters such as the input capacitance and the gate internal resistance can be adjusted within a large range. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic cross-sectional view of a cell region of a MOSFET chip shown according to the related art.

[0036] Figure 2 is a top view of a polysilicon gate layer in a cell region of a MOSFET chip shown according to the related art.

[0037] Figure 3 is a top view of a polysilicon gate layer in a gate pad region of a MOSFET chip shown according to the related art.

[0038] Figure 4 is a top view of a polysilicon gate layer in a gate trace region of a MOSFET chip shown according to the related art.

[0039] Figure 5 is a top view of a polysilicon gate layer in a terminal region of a MOSFET chip shown according to the related art.

[0040] Figure 6 is a schematic cross-sectional view of a cell region of a power semiconductor device shown according to an exemplary embodiment.

[0041] Figure 7 is Figure 6 a top view of the gate layer in

[0042] Figure 8 is a schematic cross-sectional view of a cell region of a power semiconductor device shown according to another exemplary embodiment.

[0043] Figure 9 is a top view of a gate layer in a gate pad region of a power semiconductor device shown according to another exemplary embodiment.

[0044] Figure 10 is a top view of a gate layer in a gate pad region of a power semiconductor device shown according to still another exemplary embodiment.

[0045] Figure 11 is a top view of a gate layer in a gate trace region of a power semiconductor device shown according to another exemplary embodiment.

[0046] Figure 12 is a top view of a gate layer in a terminal region of a power semiconductor device shown according to another exemplary embodiment. Detailed implementation manners

[0047] Unless otherwise defined, technical terms or scientific terms used in this specification and claims should have the ordinary meanings understood by those of ordinary skill in the technical field to which this application belongs. The following will describe the detailed implementation manners of this application with reference to the drawings. It should be noted that in the specific description of these implementation manners, for the sake of concise description, this specification may not describe all features of the actual implementation manners in detail. Without departing from the spirit and scope of this application, those skilled in the art can modify and replace the implementation manners of this application, and the obtained implementation manners are also within the protection scope of this application.

[0048] In the related art, the polysilicon gate layer of the MOSFET chip is mainly distributed in four regions of the chip, and these four regions are the cell region, the gate pad region, the terminal region, and the gate trace region (other gate buses are located in this region). In the related art, the existing structure of the polysilicon gate layer is relatively rough, and the potential of this structure has not been fully explored. The existing structures of the polysilicon gate layer in each region will be introduced separately below.

[0049] As Figures 1 to 2 shown, the polysilicon gate layer 17 includes a fifth gate bar 171, and the fifth gate bar 171 is located in the cell region and straddles two P-type wells 12 and the JFET (Junction Field-Effect Transistor) region 111 between the two P-type wells 12. Among them, Figure 1 is a cross-sectional schematic diagram of the cell region of the MOSFET chip, Figure 2 is a top view of the polysilicon gate layer in the cell region.

[0050] As Figure 1 shown, the MOSFET chip includes an N-type substrate 11, two P-type wells 12, an N+-type source region 13, an N+-type source region 14, two P+-doped regions 15, a gate oxide layer 16, a polysilicon gate layer 17, a first interlayer dielectric layer 18, two conductive parts 19, and a first metal layer 110. The N-type substrate 11 includes an N-type epitaxial layer, and the two P-type wells 12 are located in the N-type epitaxial layer, and the JFET region 111 is between the two P-type wells 12.

[0051] As Figure 2As shown, the first region 1711 of the fifth gate bar 171 above the JFET region 111 is a gate bar with a relatively large width and a relatively rugged structure.

[0052] As Figure 3 shown, the second region 172 of the gate layer 17 in the gate pad region is a gate bar with a relatively large width and a relatively rugged structure. The second region 172 is connected to the fifth gate bar 171 in the cell region.

[0053] As Figure 4 shown, the third region 173 of the gate layer 17 in the gate trace region is a gate bar with a relatively large width and a relatively rugged structure. Among them, the width of the third region 173 is larger than the width D1 of the first protrusion 161 in the gate oxide layer 16. The third region 173 is connected to the fifth gate bar 171 in the cell region.

[0054] As Figure 5 shown, the fourth region 174 of the gate layer 17 in the terminal region is a gate bar with a relatively large width and a relatively rugged structure. Among them, the fourth region 174 is connected to the fifth gate bar 171 in the cell region. The first boundary E1 of the fourth region 174 close to the cell region is farther from the terminal region than the second boundary E2 of the second protrusion 162 in the gate oxide layer 16 close to the cell region.

[0055] To solve the above technical problems, the present application proposes a power semiconductor device, which can reduce the input capacitance of the device and the gate internal resistance of the device, and at the same time can reduce the charge and discharge amount of the drive and save the drive power, reduce the cost of the drive board, and make the drive board more miniaturized.

[0056] An embodiment of the present application provides a power semiconductor device. The power semiconductor device can be a MOSFET with a planar gate and a silicon carbide substrate, but is not limited thereto. The power semiconductor device may include a cell region and a non-cell region, and the non-cell region is adjacent to the cell region.

[0057] In one embodiment, the non-cell region may include a cell region, a gate pad region, a terminal region, and a gate trace region.

[0058] In one embodiment, as Figure 6 shown, the structure of the power semiconductor device in the cell region includes: a substrate 61 of the first conductivity type, a first well region 62 and a second well region 63 of the second conductivity type, a first source region 64 of the first conductivity type, a second source region 65 of the first conductivity type, a first doping region 66 and a second doping region 67 of the second conductivity type, a JFET region 111, a gate oxide layer 16, a gate layer 68, a source 69, a drain 610, an interlayer dielectric layer 18, and a second metal layer 611.

[0059] In one embodiment, the first conduction type may be N-type, and the second conduction type may be P-type, but is not limited thereto. The first source region 64 is an N+-type source region, and the second source region 65 is an N+-type source region. The first doped region 66 and the second doped region 67 are P+-type doped regions.

[0060] In one embodiment, the substrate 61 may include an epitaxial layer of the first conduction type. As Figure 6 shown, the first well region 62 and the second well region 63 are located in the epitaxial layer. The first source region 64 is located in the first well region 62, and the second source region 65 is located in the second well region 63. The first effective channel C1 is between the edge of the first source region 64 close to the second source region 65 and the edge of the first well region 62 close to the second well region 63. The second effective channel C2 is between the edge of the second source region 65 close to the first source region 64 and the edge of the second well region 63 close to the first well region 62. The junction field effect transistor region 111 is located between the first effective channel C1 and the second effective channel C2.

[0061] In one embodiment, as Figure 6 shown, the first doped region 66 penetrates through the first source region 64 and extends into the first well region 62, and the second doped region 67 penetrates through the second source region 65 and extends into the second well region 63.

[0062] In one embodiment, as Figure 6 shown, the gate oxide layer 16 is located on the epitaxial layer. The material of the gate oxide layer 16 may be silicon oxide.

[0063] In one embodiment, as Figure 6 shown, the gate electrode layer 68 is located on the gate oxide layer 16. The first via hole 612 and the second via hole 613 are provided on the gate oxide layer 16 and the gate electrode layer 68. The first via hole 612 penetrates through the gate oxide layer 16 and the gate electrode layer 68 for exposing a part of the first source region 64. The second via hole 613 penetrates through the gate oxide layer 16 and the gate electrode layer 68 for exposing a part of the second source region 65.

[0064] In one embodiment, as Figure 6 shown, the interlayer dielectric layer 18 covers the gate electrode layer 68. The source electrode contact hole 615 and the drain electrode contact hole 616 are provided on the interlayer dielectric layer 18. The source electrode contact hole 615 penetrates through the interlayer dielectric layer 18 for exposing the first doped region 66. The drain electrode contact hole 616 penetrates through the interlayer dielectric layer 18 for exposing the second doped region 67.

[0065] In one embodiment, as Figure 6 shown, the source electrode 69 is located in the source electrode contact hole 615 and is in contact with the first doped region 66. The drain electrode 610 is located in the drain electrode contact hole 616 and is in contact with the second doped region 67.

[0066] In one embodiment, as Figure 6As shown, the source electrode 69 and the drain electrode 610 are electrically connected to the second metal layer 611.

[0067] In one embodiment, the material of the gate layer 68 is polysilicon.

[0068] In one embodiment, the materials of the substrate 61 and the epitaxial layer are both silicon carbide.

[0069] In one embodiment, as Figure 6 and Figure 7 shown, the gate layer 68 includes a first rectangular region 681. The first rectangular region 681 is located above the junction field effect transistor region 111. The first rectangular region 681 includes a hollow region 6811, a first gate bar 6812, and a second gate bar 6813. The hollow region 6811 is located between the first gate bar 6812 and the second gate bar 6813. The projection of the hollow region 6811 on the substrate 61 is located within the projection of the junction field effect transistor region 111 on the substrate 61.

[0070] In one embodiment, as Figure 6 shown, the first gate bar 6812 is located above the first effective channel C1. The projection of the first effective channel C1 on the substrate 61 is located within the projection of the first gate bar 6812 on the substrate 61. The second gate bar 6813 is located above the second effective channel C2. The projection of the second effective channel C2 on the substrate 61 is located within the projection of the second gate bar 6813 on the substrate 61.

[0071] In one embodiment, the distance between the edge of the first gate bar 6812 close to the second gate bar 6813 and the edge of the first well region 62 close to the second well region 63 can be greater than the process margin or equal to the process margin.

[0072] In one embodiment, the distance between the edge of the second gate bar 6813 close to the first gate bar 6812 and the edge of the second well region 63 close to the first well region 62 can be greater than the process margin or equal to the process margin.

[0073] In one embodiment, the gate layer 68 can be implemented by a high-precision lithography machine, layout, and etching machine.

[0074] In the embodiment of the present application, since the gate layer 68 includes the first rectangular region 681, the first rectangular region 681 is located above the junction field effect transistor region 111, and the first rectangular region 681 includes the hollow region 6811, the area of the gate layer 68 can be reduced. Furthermore, the input capacitance of the device and the gate internal resistance of the device can be reduced. At the same time, the charge and discharge amount of the drive can be reduced, the drive power can be saved, the cost of the drive board can be reduced, and the drive board can be made more miniaturized.

[0075] Another embodiment of the present application provides a power semiconductor device. AsFigure 8 As shown, in this embodiment, a first micro-groove 614 is provided on the surface of the junction field effect transistor region 111, and the first micro-groove 614 is located below the hollowed-out region 6811.

[0076] In this embodiment, since the first micro-groove 614 is provided on the surface of the junction field effect transistor region 111, the surface width of the junction field effect transistor region 111 is reduced, the parasitic capacitance of the device can be reduced, and the gate oxide layer 16 can be protected.

[0077] In one embodiment, the first through-hole 612, the second through-hole 613 and the hollowed-out region 6811 can be prepared by the same etching process. While forming the first micro-groove 614 on the surface of the junction field effect transistor region 111, the first through-hole 612 extends to the first source region 64, and the second through-hole 613 extends to the second source region 65, resulting in over-etching. However, over-etching at the positions of the first through-hole 612 and the second through-hole 613 has no impact on the subsequent processes.

[0078] Another exemplary embodiment of the present application further provides a power semiconductor device. In this embodiment, the non-cell region is a gate pad region.

[0079] In this embodiment, as Figure 9 shown, in the gate layer 68 of the gate pad region, a fifth rectangular region 680 including a first annular region 6814 and a hollowed-out region 6811 is provided.

[0080] As Figure 9 shown, the hollowed-out region 6811 is rectangular, the first annular region 6814 surrounds the hollowed-out region 6811, and the width of the first annular region 6814 is greater than or equal to the minimum allowable line width, and the minimum allowable line width is 0.2 micrometers. For example, the width of the first annular region 6814 can be 0.2 micrometers or 3 micrometers.

[0081] The power semiconductor device further includes an insulating layer and a gate contact hole. The insulating layer is located above the first annular region 6814, and the gate contact hole penetrates the insulating layer and contacts the first annular region 6814. The width of the first annular region 6814 is greater than or equal to the minimum size of the gate contact hole.

[0082] In one embodiment, the material of the insulating layer is silicon oxide.

[0083] In this embodiment, as Figure 9 shown, the gate layer 68 includes a sixth gate bar 682. The sixth gate bar 682 is located in the cell region, and the sixth gate bar 682 is connected to the fifth rectangular region 680.

[0084] Since the gate layer 68 in the gate pad region includes a fifth rectangular region 680, and the fifth rectangular region 680 includes a hollowed-out region 6811, the area of the gate layer 68 can be reduced. As a result, the input capacitance of the device can be decreased, the gate internal resistance of the device can be reduced, the charge and discharge amount of the drive can be decreased, the drive power can be saved, the cost of the drive board can be reduced, and the drive board can be made more miniaturized.

[0085] It should be noted that the embodiment shown as Figure 9 and the embodiment shown as Figure 6 can be implemented independently or simultaneously. The embodiment shown as Figure 9 and the embodiment shown as Figure 8 can be implemented independently or simultaneously.

[0086] Another exemplary embodiment of the present application further provides a power semiconductor device. In this embodiment, the non-cell region is the gate pad region.

[0087] In this embodiment, as shown in Figure 10 , in the gate layer 68 of the gate pad region, the fifth rectangular region 680 includes a hollowed-out region 6811, a second annular region 6815, and a second rectangular region 6816.

[0088] As shown in Figure 10 , the hollowed-out region 6811 is annular, the hollowed-out region 6811 surrounds the second rectangular region 6816, and the second annular region 6815 surrounds the hollowed-out region 6811.

[0089] In one embodiment, the second rectangular region 6816 is floating and not connected to an electrical signal.

[0090] In one embodiment, as shown in Figure 10 , the gate layer 68 includes a sixth gate bar 682, the sixth gate bar 682 is located in the cell region, and the sixth gate bar 682 is connected to the fifth rectangular region 680.

[0091] Since the gate layer 68 in the gate pad region includes a fifth rectangular region 680, and the fifth rectangular region 680 includes a hollowed-out region 6811, the area of the gate layer 68 can be reduced. As a result, the input capacitance of the device can be decreased, the gate internal resistance of the device can be reduced, the charge and discharge amount of the drive can be decreased, the drive power can be saved, the cost of the drive board can be reduced, and the drive board can be made more miniaturized.

[0092] It should be noted that the embodiment shown as Figure 10 , the embodiment shown as Figure 9 and the embodiment shown as Figure 6 can be implemented independently or simultaneously. The embodiment shown as Figure 10 , the embodiment shown as Figure 9 and the embodiment shown as Figure 8The illustrated embodiments can be implemented independently or simultaneously.

[0093] Another exemplary embodiment of the present application further provides a power semiconductor device. In this embodiment, the non-cell region is a gate trace region.

[0094] In this embodiment, as Figure 11 shown, in the gate layer 68 of the gate trace region, the fifth rectangular region 680 includes a plurality of hollow regions 6811, a third rectangular region 6817, and a plurality of third gate bars 6818.

[0095] As Figure 11 shown, on the first side of the third rectangular region 6817, the hollow regions 6811 and the third gate bars 6818 are arranged alternately in sequence. The third gate bars 6818 are connected to the third rectangular region 6817. On the second side of the third rectangular region 6817, the hollow regions 6811 and the third gate bars 6818 are arranged alternately in sequence. The first side and the second side are opposite to each other.

[0096] In one embodiment, the power semiconductor device further includes an insulating layer and a gate contact hole. The insulating layer is located above the third rectangular region. The gate contact hole penetrates through the insulating layer and contacts the third rectangular region 6817. The width D2 of the third rectangular region 6817 is smaller than the width D3 of the fifth rectangular region 680. The width D3 of the third rectangular region 6817 can be greater than or equal to the minimum allowable line width and greater than or equal to the minimum size of the gate contact hole. The minimum allowable line width is 0.2 micrometers. The minimum size of the gate contact hole is 0.2 micrometers. The width D3 of the third rectangular region 6817 can be 0.2 micrometers or 3 micrometers.

[0097] In one embodiment, as Figure 11 shown, the width D2 of the third rectangular region 6817 can also be smaller than the width D1 of the first protrusion 161 in the gate oxide layer 16.

[0098] In one embodiment, as Figure 11 shown, the gate layer 68 includes a sixth gate bar 682. The sixth gate bar 682 is located in the cell region. The sixth gate bar 682 is connected to the third gate bars 6818.

[0099] Since the gate layer 68 in the gate trace region includes the fifth rectangular region 680, and the fifth rectangular region 680 includes the hollow regions 6811, the area of the gate layer 68 can be reduced. Furthermore, the input capacitance of the device and the gate internal resistance of the device can be reduced. At the same time, the charge and discharge amount of the drive can be reduced, the drive power can be saved, the cost of the drive board can be reduced, and the drive board can be made more miniaturized.

[0100] It should be noted that, as Figure 11 shown in the embodiment, as Figure 10 shown in the embodiment, asFigure 9 The illustrated embodiments can be implemented independently or simultaneously with the embodiments as Figure 6 shown. The embodiments as Figure 11 shown, the embodiments as Figure 10 shown, the embodiments as Figure 9 shown and the embodiments as Figure 8 shown can be implemented independently or simultaneously.

[0101] Another exemplary embodiment of the present application further provides a power semiconductor device. In this embodiment, the non-cell region is a terminal region.

[0102] In this embodiment, as Figure 12 shown, in the gate layer 68 of the terminal region, the fifth rectangular region 680 includes a hollow region 6811, a fourth rectangular region 6819 and a plurality of fourth gate bars 6810.

[0103] As Figure 12 shown, the hollow region 6811 includes a plurality of first hollow portions 8111 and a second hollow portion 8112. The fourth gate bars 6810 and the first hollow portions 8111 are located on one side of the fourth rectangular region 6819 close to the cell region and are arranged alternately. The fourth gate bars 6810 are connected to the fourth rectangular region 6819. The second hollow portion 8112 is located on the side of the fourth rectangular region 6819 away from the cell region. The fourth gate bars 6810 and the first hollow portions 8111 extend along the width direction of the fourth rectangular region 6819, and the second hollow portion 8112 extends along the length direction of the fourth rectangular region 6819.

[0104] In one embodiment, the power semiconductor device further includes an insulating layer and a gate contact hole. The insulating layer is located above the fourth rectangular region. The gate contact hole penetrates the insulating layer and contacts the fourth rectangular region 6819. The width of the fourth rectangular region 6819 is greater than or equal to the minimum allowable line width and greater than or equal to the minimum size of the gate contact hole. The width D3 of the fourth rectangular region 6819 can be 0.2 micrometers or 3 micrometers.

[0105] As Figure 12 shown, the third boundary E3 of the fourth rectangular region 6819 close to the cell region is closer to the terminal region than the second boundary E2 of the second protrusion 162 in the gate oxide layer 16 close to the cell region.

[0106] In one embodiment, as Figure 12 shown, the gate layer 68 includes a sixth gate bar 682. The sixth gate bar 682 is located in the cell region and the sixth gate bar 682 is connected to the fourth gate bars 6810.

[0107] Since the gate layer 68 in the terminal region includes a fifth rectangular region 680, and the fifth rectangular region 680 includes a hollow region 6811, the area of the gate layer 68 can be reduced. As a result, the input capacitance of the device can be decreased, the gate internal resistance of the device can be reduced, the charge and discharge amount of driving can be decreased, the driving power can be saved, the cost of the driving board can be reduced, and the driving board can be made more miniaturized.

[0108] It should be noted that the embodiments shown as Figure 12 such, the embodiments shown as Figure 11 such, the embodiments shown as Figure 10 such, the embodiments shown as Figure 9 such and the embodiments shown as Figure 6 such can be implemented independently or simultaneously. The embodiments shown as Figure 12 such, the embodiments shown as Figure 11 such, the embodiments shown as Figure 10 such, the embodiments shown as Figure 9 such and the embodiments shown as Figure 8 such can be implemented independently or simultaneously.

[0109] The above-mentioned various embodiments can be combined and matched without conflict. Moreover, the width of the gate layer 68 or the area of the hollow region 6811 can be adjusted significantly according to requirements, so as to achieve the purpose of adjusting parasitic parameters such as input capacitance and gate internal resistance within a large range.

[0110] The above description of the embodiments is for the convenience of those of ordinary skill in the art to understand and apply this application. Those skilled in the art can obviously make various modifications to these embodiments easily and apply the general principles described here to other embodiments without creative efforts. Therefore, this application is not limited to the embodiments here. The improvements and modifications made by those skilled in the art according to the content disclosed in this application are within the scope of this application without departing from the scope and spirit of this application.

Claims

1. A power semiconductor device, characterized in that: include: A cell region, the cell region including a junction field effect transistor region; The power semiconductor device further comprises: A gate layer, the gate layer comprising a first rectangular area, the first rectangular area is located above the junction field effect transistor area; the first rectangular area comprises a hollow area; A substrate of a first conductivity type, the substrate comprising an epitaxial layer of the first conductivity type; A first well region and a second well region of a second conductivity type are located in the epitaxial layer; A first source region, located in the first well region; a second source region, located in the second well region; a first effective channel is formed between an edge of the first source region close to the second source region and an edge of the first well region close to the second well region, and a second effective channel is formed between an edge of the second source region close to the first source region and an edge of the second well region close to the first well region; the junction field effect transistor region is located between the first effective channel and the second effective channel; the first rectangular region further includes a first gate bar and a second gate bar, and the hollow region is located between the first gate bar and the second gate bar; the first gate bar is located above the first effective channel, and a projection of the first effective channel on the substrate is located within a projection of the first gate bar on the substrate; the second gate bar is located above the second effective channel, and a projection of the second effective channel on the substrate is located within a projection of the second gate bar on the substrate; A gate oxide layer, the gate oxide layer is located between the epitaxial layer and the gate layer; a first micro groove is provided on the surface of the junction field effect transistor region, the first micro groove is located below the hollow region; the gate oxide layer includes a third through hole, the hollow region, the third through hole and the first micro groove are connected in sequence; A first interlayer dielectric layer, covering the hollow area, the third through hole and the first micro groove; The power semiconductor device further includes a non-cellular region, the non-cellular region is adjacent to the cellular region, the non-cellular region is provided with a fifth rectangular region, and the fifth rectangular region includes a hollow region; The non-cell region is a gate pad region; The hollow area is rectangular, and the fifth rectangular area further includes a first annular area, which surrounds the hollow area; The power semiconductor device further comprises an insulating layer and a gate contact hole, wherein the insulating layer is located above the first annular region, the gate contact hole penetrates the insulating layer and contacts the first annular region, and the width of the first annular region is greater than or equal to the minimum allowed line width and greater than or equal to the minimum size of the gate contact hole; Alternatively, the non-cell region is a gate pad region; The hollow area is annular, the fifth rectangular area further includes a second annular area and a second rectangular area, the hollow area surrounds the second rectangular area, and the second annular area surrounds the hollow area; The second rectangular area is floating; Alternatively, the non-cell region is a gate wiring region; The fifth rectangular area further includes a third rectangular area and a plurality of third grid bars, the first side of the third rectangular area is provided with the hollow areas and the third grid bars arranged alternately in sequence, the third grid bars are connected to the third rectangular area, the second side of the third rectangular area is provided with the hollow areas and the third grid bars arranged alternately in sequence, and the first side is opposite to the second side; The power semiconductor device further comprises an insulating layer and a gate contact hole, wherein the insulating layer is located above the third rectangular area, the gate contact hole penetrates the insulating layer and contacts the third rectangular area, the width of the third rectangular area is smaller than the width of the fifth rectangular area, the width of the third rectangular area is greater than or equal to the minimum allowed line width, and greater than or equal to the minimum size of the gate contact hole; Alternatively, the non-cellular region is a terminal region; The fifth rectangular area also includes a fourth rectangular area and a plurality of fourth grid bars, the hollow area includes a plurality of first hollow portions and a second hollow portion; the fourth grid bars and the first hollow portions are located on a side of the fourth rectangular area close to the cell area and are arranged alternately, and the fourth grid bars are connected to the fourth rectangular area; the second hollow portion is located on a side of the fourth rectangular area away from the cell area, the fourth grid bars and the first hollow portions extend along the width direction of the fourth rectangular area, and the second hollow portion extends along the length direction of the fourth rectangular area; The power semiconductor device also includes an insulating layer and a gate contact hole, the insulating layer is located above the fourth rectangular area, the gate contact hole penetrates the insulating layer and contacts the fourth rectangular area, and the width of the fourth rectangular area is greater than or equal to the minimum allowable line width and greater than or equal to the minimum size of the gate contact hole.

2. The power semiconductor device according to claim 1, characterized in that: The distance between the edge of the first gate strip close to the second gate strip and the edge of the first well region close to the second well region is greater than or equal to the process margin; A distance between an edge of the second gate strip close to the first gate strip and an edge of the second well region close to the first well region is greater than or equal to a process margin.

3. The power semiconductor device according to claim 1, characterized in that: The material of the gate layer is polysilicon.

4. The power semiconductor device according to claim 1, characterized in that: The substrate and the epitaxial layer are made of silicon carbide.

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