Display device

Abstract

A display device is provided. The display device includes a substrate, a first conductive layer over the substrate, an active layer over the first conductive layer, a second conductive layer over the active layer and including a transparent conductive oxide and not including indium (In), a third conductive layer over the second conductive layer, a transistor including a gate electrode at the second conductive layer and a drain electrode and a source electrode at the active layer, and a light emitting element including a first electrode at the third conductive layer and connected to the source electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0146643 filed in the Korean Intellectual Property Office on October 30, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] As multimedia develops, display devices are becoming more and more important. Therefore, various display devices such as liquid crystal display devices (LCD) and organic light emitting diode display devices (OLED) are being developed.

[0005] In a display device, a self-luminous display device includes a self-luminous element such as an organic light emitting diode. The self-luminous element may include two electrodes facing each other and a light emitting layer interposed between the two electrodes. If the self-luminous element is an organic light emitting diode, electrons and holes provided from the two electrodes may be recombined in the light emitting layer to generate excitons. When the generated excitons change from an excited state to a ground state, light may be emitted.

[0006] Because self-luminous display devices do not require a light source such as a backlight unit, they have low power consumption, can be made lightweight and thin, and have a wide viewing angle, high brightness and contrast, and a fast response speed. Due to these high-quality characteristics, self-luminous display devices have attracted much attention as next-generation display devices.

[0007] The self-luminous display device may include various circuit layers for driving the light-emitting layer. These circuit layers may be formed by multiple patterning processes using masks. As the number of masks and the number of layers constituting the circuit layers decreases, the process efficiency may be improved. Therefore, the height difference between the light-emitting layer and the transistor for driving the light-emitting layer may be reduced. Summary of the invention

[0008] Aspects of the present disclosure provide a display device including a conductive layer having low reflectivity.

[0009] Aspects of the present disclosure also provide display devices with reduced or minimized light-induced degradation.

[0010] Aspects of the present disclosure also provide a display device having improved reliability.

[0011] Aspects of the present disclosure also provide a display device with improved process efficiency.

[0012] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0013] According to aspects of the present disclosure, a display device is provided, which includes a substrate, a first conductive layer above the substrate, an active layer above the first conductive layer, a second conductive layer above the active layer and including a transparent conductive oxide but not including indium (In), a third conductive layer above the second conductive layer, a transistor including a gate electrode at the second conductive layer and a drain electrode and a source electrode at the active layer, and a light-emitting element including a first electrode at the third conductive layer and connected to the source electrode.

[0014] The second conductive layer may include aluminum zinc tin oxide (AZTO).

[0015] The second conductive layer may include a first gate conductive layer and a second gate conductive layer, the second gate conductive layer being above the first gate conductive layer and having a higher light transmittance than the first gate conductive layer.

[0016] The second gate conductive layer may include aluminum zinc tin oxide (AZTO).

[0017] The second gate conductive layer may include about 1 at % to about 10 at % of aluminum based on atoms excluding oxygen atoms.

[0018] The second gate conductive layer may include about 60 at % to about 90 at % of zinc based on atoms excluding oxygen atoms.

[0019] The second gate conductive layer may include about 10 at % to about 30 at % of tin based on atoms excluding oxygen atoms.

[0020] The second gate conductive layer may include about 0.5 at % to about 5 at % of aluminum based on total atoms.

[0021] The second gate conductive layer may include about 20 at % to about 40 at % of zinc based on total atoms.

[0022] The second gate conductive layer may include about 7 at % to about 15 at % of tin based on total atoms.

[0023] The second gate conductive layer may include about 50 at % to about 60 at % of oxygen based on total atoms.

[0024] The first gate conductive layer may have a lower reflectivity than the second gate conductive layer.

[0025] The first gate conductive layer may include titanium (Ti).

[0026] The thickness of the second gate conductive layer may be greater than the thickness of the first gate conductive layer.

[0027] The thickness of the second gate conductive layer may be about 2 times to about 30 times the thickness of the first gate conductive layer.

[0028] The thickness of the second gate conductive layer may be about to about

[0029] The thickness of the first gate conductive layer may be about to about

[0030] The third conductive layer may include a transparent conductive oxide different from that of the second conductive layer.

[0031] The second conductive layer may have a lower reflectivity than the first conductive layer or the third conductive layer.

[0032] According to aspects of the present disclosure, a display device is provided, which includes: a substrate; a first conductive layer, which is above the substrate; an active layer, which is above the first conductive layer; a second conductive layer, which is above the active layer and includes a first gate conductive layer, a second gate conductive layer, a third gate conductive layer and a fourth gate conductive layer, the first gate conductive layer including a first material including a metal, the second gate conductive layer is above the first gate conductive layer and includes a second material including a metal, the third gate conductive layer is above the second gate conductive layer and includes a third material including a metal, and the fourth gate conductive layer is above the third gate conductive layer and includes aluminum zinc tin oxide (AZTO); a transistor is above the first conductive layer; and a light-emitting element is above the second conductive layer and connected to the transistor.

[0033] The first material, the second material, and the third material may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof.

[0034] The first material may include titanium (Ti).

[0035] The second material may include copper (Cu).

[0036] The third material may include titanium (Ti).

[0037] The thickness of the fourth gate conductive layer may be greater than the thickness of the third gate conductive layer.

[0038] The thickness of the second gate conductive layer may be greater than the thickness of the fourth gate conductive layer.

[0039] According to aspects of the present disclosure, a display device is provided, which includes: a substrate including a display area and a pad area at one side of the display area; a first conductive layer above the substrate; an active layer above the first conductive layer; a second conductive layer above the active layer in the display area and including a transparent conductive oxide but not including indium (In); a transistor above the first conductive layer in the display area; a light-emitting element above the second conductive layer in the display area and connected to the transistor; and a wiring pad above the substrate in the pad area and including a first pad electrode at the first conductive layer and a second pad electrode at the second conductive layer.

[0040] The second pad electrode may not include a transparent conductive oxide.

[0041] The display device may further include a driving component connected to the wiring pad, wherein the second pad electrode includes a sub-pad including a metal directly contacting the driving component.

[0042] The display device according to one or more embodiments of the present disclosure may include a conductive layer having low reflectivity.

[0043] The display device according to one or more embodiments of the present disclosure may reduce or minimize light-induced degradation.

[0044] A display device according to one or more embodiments of the present disclosure may have improved reliability.

[0045] The display device according to one or more embodiments of the present disclosure may have improved process efficiency.

[0046] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] These and / or other aspects will become apparent and more easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0048] Figure 1 is a perspective view of a display device according to one or more embodiments;

[0049] Figure 2 It is along Figure 1 A cross-sectional view taken along the line X1-X1';

[0050] Figure 3 is a cross-sectional view of a display device according to one or more embodiments;

[0051] Figure 4is a plan view showing a state in which a connection film is attached to a wiring pad of a display device according to one or more embodiments;

[0052] Figure 5 is a plan view showing a state in which a connection film is not attached to a wiring pad of a display device according to one or more embodiments;

[0053] Figure 6 shows pixels and lines of a display device according to one or more embodiments;

[0054] Figure 7 is a schematic plan view of a portion of a display area of ​​a display substrate according to one or more embodiments;

[0055] Figure 8 is a schematic plan view of a portion of a display area of ​​a display substrate according to one or more embodiments;

[0056] Fig. 9 It is along Figure 7 A cross-sectional view taken along line X2-X2';

[0057] Fig.10 is an equivalent circuit diagram of a pixel according to one or more embodiments;

[0058] Fig.11 is a cross-sectional view of an example of a first transistor of a circuit layer according to one or more embodiments;

[0059] Fig.12 is a cross-sectional view of an example of a second transistor and a third transistor of a circuit layer according to one or more embodiments;

[0060] Fig.13 is a cross-sectional view showing an example of a portion of a display region and a portion of a pad region of a display device according to one or more embodiments;

[0061] Fig.14 is a cross-sectional view of an example of a bottom conductive layer according to one or more embodiments;

[0062] Fig.15 is a cross-sectional view of an example of a gate conductive layer according to one or more embodiments;

[0063] Fig.16 is a cross-sectional view of an example of an anode conductive layer according to one or more embodiments;

[0064] Fig.17 is a cross-sectional view of an example of a conventional gate conductive layer;

[0065] Fig.18is a photograph showing precipitated particles formed on a cross section of a conventional gate conductive layer;

[0066] Fig.19 is a cross-sectional view showing an example of a portion of a display region and a portion of a pad region of a display device according to one or more embodiments;

[0067] Fig. 20 is a cross-sectional view showing a wiring pad and a connection film of a display device according to one or more embodiments;

[0068] Fig.21 , Fig. 22 and Fig.23 is a schematic perspective view of a device including a display device according to one or more embodiments; and

[0069] Fig.24 and Fig.25 is a schematic perspective view of a transparent display device including the display device according to one or more embodiments. DETAILED DESCRIPTION

[0070] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for realizing them. The embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0071] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. When describing the embodiments, the use of "can", "may", or "may not" corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents, and substitutions within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in its entirety, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0072] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading is often provided in the drawings to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements, unless otherwise indicated.

[0073] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. Thus, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances are anticipated. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but rather include deviations in shapes due to, for example, manufacturing.

[0074] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0075] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper", "upper side" etc. may be used herein to describe the relationship between an element or feature and another (multiple) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as being "below", "below" or "below" other elements or features will then be oriented to be "above" other elements or features. Therefore, the exemplary terms "below" and "below" may include both the orientations of above and below. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being arranged "on" a second portion, this means that the first portion is arranged at the upper or lower side of the second portion, without being limited to its upper side based on the direction of gravity.

[0076] In addition, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The term "overlap" or "overlapping" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. In addition, the term "overlap" may include stacking, facing (face) or facing (facing), extending throughout ..., covering or partially covering or any other suitable term as will be understood and appreciated by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "separated from ..." or "set side by side with ..." or "offset with ..." and any other suitable equivalents that will be understood and appreciated by a person of ordinary skill in the art. The terms "facing (face)" and "facing (facing)" may mean that the first object may be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0077] It will be understood that when an element, layer, region, or component is referred to as being "formed" "on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may refer collectively to direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, capacitors, etc. In describing the embodiments, unless explicitly described as directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or on another component without intermediate components.

[0078] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the situation that the part is "directly" "below" another part, but also includes the situation that there is another other part between the part and the other part. At the same time, other expressions such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to..." that describe the relationship between components can be interpreted similarly. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0079] For the purposes of this disclosure, expressions such as "at least one of..." or "any one of..." or "one or more of...", when following a list of elements, modify the entire list of elements, rather than modifying individual elements in the list. For example, "at least one of X, Y, and Z," and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of...", "a plurality of," "one of...", and other prepositional phrases, when following a list of elements, modify the entire list of elements, rather than modifying individual elements in the list.

[0080] It will be understood that, although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or sections in this article, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, the first element, first component, first area, first layer or first section described below can be referred to as the second element, second component, second area, second layer or second section, without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish elements of different categories or different groups in this article. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0081] In the example, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0082] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, and the plural forms are also intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprise", "including", "have", "having", "including" and "including" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0083] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of ±5% of the corresponding value. In view of the measurement discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the value and mean within the acceptable deviation range of the particular value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" relates to "one or more embodiments of the present disclosure".

[0084] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such in this article.

[0085] Figure 1 is a perspective view of a display device 10 according to one or more embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken along line X1-X1'. Figure 3 is a cross-sectional view of a display device 10_1 according to one or more embodiments.

[0086] refer to Figure 1 , Figure 2 and Figure 3 The display device 10 can be applied to various electronic devices, including small and medium-sized electronic devices such as tablet personal computers (PCs), smart phones, car navigation units, cameras, central information displays (CIDs) provided in vehicles, watch-type electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), and game consoles, as well as medium and large electronic devices such as televisions, outdoor billboards, monitors, PCs, and notebook computers. These are presented only as examples, and the display device 10 can also be used for other electronic devices as long as it does not deviate from the spirit of the present disclosure.

[0087] In one or more embodiments, the display device 10 may be rectangular in a plan view. The display device 10 may include two long sides extending in a first direction DR1, and two short sides extending in a second direction DR2 intersecting the first direction DR1. Each corner where the long side and the short side of the display device 10 intersect may be a right angle. However, the present disclosure is not limited thereto, and each corner may also form a curved surface. In one or more embodiments, the long side may extend in the second direction DR2, and the short side may extend in the first direction DR1. The planar shape of the display device 10 is not limited to the above examples, and may also be a circular shape or other shapes.

[0088] In the drawings, the first direction DR1 and the second direction DR2 are horizontal directions that intersect each other. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. In addition, the third direction DR3 may intersect the first direction DR1 and the second direction DR2. For example, the third direction DR3 may be a vertical direction orthogonal to the first direction DR1 and the second direction DR2. Unless otherwise specified, in this specification, the direction indicated by the arrow of each of the first direction DR1, the second direction DR2 and the third direction DR3 may be referred to as one side, and the opposite direction may be referred to as the other side. In addition, in this specification, "upper", "upper side", "above", "top" and "upper surface" refer to the direction to which the arrow of the third direction DR3 in the drawings points, and "below", "lower side", "below", "bottom" and "lower surface" refer to the direction opposite to the direction to which the arrow of the third direction DR3 in the drawings points.

[0089] The display device 10 may include a display area DA displaying an image and a non-display area NDA not displaying an image. In one or more embodiments, the non-display area NDA may be located around the display area DA and may surround the display area DA.

[0090] In one or more embodiments, reference Figure 2 , the display device 10 may include a display substrate 100 and a color conversion substrate 200 facing the display substrate 100 , and may further include a sealing portion 400 combining the display substrate 100 and the color conversion substrate 200 together and a filler 300 filling a space between the display substrate 100 and the color conversion substrate 200 .

[0091] The display substrate 100 may include elements and circuits for displaying images, such as pixel circuits such as switching elements, pixel defining layers that define emission areas and non-emission areas in the display area DA to be described later, and self-luminous elements. In one or more embodiments, each of the self-luminous elements may include at least one of an organic light-emitting diode, a quantum dot light-emitting diode, a micron light-emitting diode based on an inorganic material (e.g., a micron LED), and a nano light-emitting diode based on an inorganic material (e.g., a nano LED). For ease of description, the case where the self-luminous element is an organic light-emitting diode will be described below as an example.

[0092] The color conversion substrate 200 may be located on the display substrate 100 (as used herein, "on" may mean "above"), and may face the display substrate 100. In one or more embodiments, the color conversion substrate 200 may include a color conversion pattern that converts the color of incident light. In one or more embodiments, the color conversion pattern may include at least any one of a color filter and a wavelength conversion pattern.

[0093] The sealing portion 400 may be located between the display substrate 100 and the color conversion substrate 200 in the non-display area NDA. The sealing portion 400 may be located along the edges of the display substrate 100 and the color conversion substrate 200 in the non-display area NDA to surround the display area DA in a plan view. The display substrate 100 and the color conversion substrate 200 may be bonded to each other through the sealing portion 400.

[0094] In one or more embodiments, the sealing portion 400 may be made of an organic material. For example, the sealing portion 400 may be made of, but is not limited to, epoxy-based resin.

[0095] The filler 300 may be located between the display substrate 100 and the color conversion substrate 200 in a space surrounded by the sealing portion 400. The filler 300 may fill the space between the display substrate 100 and the color conversion substrate 200.

[0096] In one or more embodiments, the filler 300 may be made of a material capable of transmitting light. In one or more embodiments, the filler 300 may be made of an organic material. For example, the filler 300 may be made of, but not limited to, a silicon-based organic material or an epoxy-based organic material. In one or more embodiments, the filler 300 may also be omitted.

[0097] In one or more embodiments, reference Figure 3, the display device 10_1 may not include the sealing portion 400. For example, the color conversion substrate 200_1 of the display device 10_1 may be an encapsulation substrate. The color conversion substrate 200_1 may include a protruding portion positioned along the periphery of the color conversion substrate 200_1 and protruding toward the display substrate 100 in the third direction DR3, and a concave portion surrounded by the protruding portion. The internal space may be sealed by the display substrate 100 and the color conversion substrate 200_1. The filler 300 may fill the concave portion.

[0098] Figure 4 FIG. 1 is a diagram showing a wiring pad WPD (see FIG. 10 ) in which a connection film 510 is attached to a display device 10 according to one or more embodiments. Figure 5 ) state plan. Figure 5 is a plan view illustrating a state in which a connection film 510 is not attached to the wiring pad WPD of the display device 10 according to one or more embodiments.

[0099] refer to Figure 4 and Figure 5 , the display device 10 may include a display substrate 100 , a connection film 510 , a display driver 520 , a circuit board 530 , a timing controller 540 , a power supply 550 , and a gate driver 560 .

[0100] The display substrate 100 may be rectangular in a plan view. For example, the display substrate 100 may be shaped as a rectangular plane having a long side in a first direction DR1 and a short side in a second direction DR2. Each corner where the long side extending in the first direction DR1 and the short side extending in the second direction DR2 intersect may be a right angle, or may be rounded with a certain curvature (e.g., a predetermined curvature). The planar shape of the display substrate 100 is not limited to a rectangular shape, and may also be other polygonal shapes, a circular shape, or an elliptical shape. For example, the display substrate 100 may be formed to be flat, but the present disclosure is not limited thereto. For another example, the display substrate 100 may be formed to be curved with a certain curvature (e.g., a predetermined curvature).

[0101] The display substrate 100 may include a display area DA and a non-display area NDA.

[0102] The display area DA may be an area for displaying an image, and may be defined as a central area of ​​the display substrate 100. In one or more embodiments, the display area DA may include pixels SP, gate lines GL, data lines DL, initialization voltage lines VIL, first voltage lines VDL, horizontal voltage lines HVDL, vertical voltage lines VVSL, and second voltage lines VSL.

[0103] The pixels SP may be formed in pixel regions intersecting the data lines DL and the gate lines GL, respectively. In one or more embodiments, the pixels SP may include a first pixel SP1, a second pixel SP2, and a third pixel SP3. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be connected to the gate line GL and the data line DL. Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be defined as a minimum unit region for outputting light.

[0104] Each of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may include an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, a micro light emitting diode, or an inorganic light emitting diode including an inorganic semiconductor.

[0105] The first pixel SP1 may emit light of a first color or red light, the second pixel SP2 may emit light of a second color or green light, and the third pixel SP3 may emit light of a third color or blue light. The pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be sequentially arranged in a direction opposite to the second direction DR2, but the order of the pixel circuits is not limited thereto.

[0106] The gate lines GL may include a first gate line GL1 and a second gate line GL2. The first gate lines GL1 may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2. The first gate lines GL1 may receive a first gate signal from a gate driver 560 and may provide the first gate signal to the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0107] The second gate lines GL2 may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The second gate lines GL2 may receive a second gate signal from the gate driver 560 and may provide the second gate signal to the first, second, and third pixels SP1, SP2, and SP3.

[0108] The data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3. The first data line DL1, the second data line DL2, and the third data line DL3 may provide data voltages to the first pixel SP1, the second pixel SP2, and the third pixel SP3, respectively.

[0109] The initialization voltage lines VIL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The initialization voltage lines VIL may provide an initialization voltage received from the display driver 520 to the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The initialization voltage lines VIL may receive a sensing signal from the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3 and may provide the sensing signal to the display driver 520.

[0110] The first voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The first voltage lines VDL may provide a driving voltage or a high potential voltage received from a power source 550 to the first, second, and third pixels SP1, SP2, and SP3.

[0111] The horizontal voltage lines HVDL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The horizontal voltage lines HVDL may be connected to the first voltage lines VDL. The horizontal voltage lines HVDL may receive a driving voltage or a high potential voltage from the first voltage lines VDL.

[0112] The vertical voltage lines VVSL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The vertical voltage lines VVSL may be connected to the second voltage line VSL. The vertical voltage lines VVSL may provide a low potential voltage received from the power supply 550 to the second voltage line VSL.

[0113] The second voltage lines VSL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2 The second voltage line VSL may provide a low potential voltage to the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0114] The connection relationship between the pixels SP, the gate lines GL, the data lines DL, the initialization voltage lines VIL, the first voltage lines VDL, the horizontal voltage lines HVDL, the vertical voltage lines VVSL and the second voltage lines VSL may be variously designed and changed according to the number and arrangement of the pixels SP.

[0115] The non-display area NDA may be defined as an area other than the display area DA in the display substrate 100. For example, the non-display area NDA may include a fan-out line connecting the data line DL, the initialization voltage line VIL, the first voltage line VDL, and the vertical voltage line VVSL to the display driver 520, and may include a gate driver 560 and a wiring pad WPD connected to the connection film 510.

[0116] refer to Figure 5, the non-display area NDA may include a pad area PDA in which the wiring pad WPD is located. The pad area PDA may be positioned adjacent to one side of the display device 10. For example, the pad area PDA may be positioned adjacent to the lower side of the display device 10. In one or more embodiments, the pad area PDA may extend along the first direction DR1.

[0117] The connection film 510 may be connected to the wiring pads WPD located on the lower side of the non-display area NDA and to the board pads BPD located on the upper side of the circuit board 530. The input terminals (e.g., protrusions 512, see FIG. 5 ) located on one side and the other side of the connection film 510 may be connected to the wiring pads WPD located on the lower side of the non-display area NDA and to the board pads BPD located on the upper side of the circuit board 530. Fig. 20 ) can be attached to the wiring pad WPD and the board pad BPD by a film attachment process. For example, each of the connection films 510 can be flexible, such as a tape carrier package or a chip on film. The connection film 510 can be bent toward the bottom of the display substrate 100 to reduce the frame area of ​​the display device 10.

[0118] The display driver 520 may be mounted on the connection film 510. For example, the display driver 520 may be implemented as an integrated circuit (IC). The display driver 520 may receive digital video data and a data control signal from the timing controller 540, may convert the digital video data into an analog data voltage according to the data control signal, and may provide the analog data voltage to the data line DL through a fan-out line.

[0119] The circuit board 530 may support the timing controller 540 and the power supply 550, and may provide signals and power to the display driver 520. For example, the circuit board 530 may provide a signal provided from the timing controller 540, and may provide a power supply voltage provided from the power supply 550 to the connection film 510 and the display driver 520 through the board pad BPD to display an image in each pixel SP. To this end, a signal line and a power line may be provided on the circuit board 530.

[0120] The timing controller 540 may be mounted on the circuit board 530, and may receive image data and a timing synchronization signal from a display driving system or from a graphics device through a user connector provided on the circuit board 530. The timing controller 540 may generate digital video data by arranging the image data according to the pixel arrangement structure based on the timing synchronization signal, and may provide the generated digital video data to the display driver 520. The timing controller 540 may generate a data control signal and a gate control signal based on the timing synchronization signal. The timing controller 540 may control the data voltage supply timing of the display driver 520 based on the data control signal, and may control the gate signal supply timing of the gate driver 560 based on the gate control signal.

[0121] The power supply 550 may be located on the circuit board 530 to provide a power supply voltage to the connection film 510 and the display driver 520. For example, the power supply 550 may generate a driving voltage or a high potential voltage and may provide the driving voltage or the high potential voltage to the first voltage line VDL, may generate a low potential voltage and may provide the low potential voltage to the vertical voltage line VVSL, and may generate an initialization voltage and may provide the initialization voltage to the initialization voltage line VIL.

[0122] The gate driver 560 may be located on at least either of the left and right sides of the non-display area NDA. The gate driver 560 may generate a gate signal based on a gate control signal provided from the timing controller 540. The gate control signal may include, but is not limited to, a start signal, a clock signal, and a power supply voltage. The gate driver 560 may provide the gate signal to the gate line GL according to a set sequence.

[0123] Figure 6 Pixels and lines of a display device 10 according to one or more embodiments are shown.

[0124] Apart from Figure 4 and Figure 5 In addition, reference Figure 6 The pixel SP may include a first pixel SP1, a second pixel SP2, and a third pixel SP3. The pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be sequentially arranged in a direction opposite to the second direction DR2, but the order of the pixel circuits is not limited thereto.

[0125] Each of the first pixel SP1 , the second pixel SP2 , and the third pixel SP3 may be connected to a first voltage line VDL, an initialization voltage line VIL, a gate line GL, and a data line DL.

[0126] The first voltage line VDL may extend in the second direction DR2. The first voltage line VDL may be located on the left side of the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The first voltage line VDL may provide a driving voltage or a high potential voltage to the transistors of the first pixel SP1, the second pixel SP2, and the third pixel SP3.

[0127] The horizontal voltage line HVDL may extend in the first direction DR1. The horizontal voltage line HVDL may be located at a position located in the kth row ROW. k (where k is a positive integer). The horizontal voltage line HVDL may be connected to the first voltage line VDL. The horizontal voltage line HVDL may receive a driving voltage or a high potential voltage from the first voltage line VDL.

[0128] The initialization voltage line VIL may extend in the second direction DR2. The initialization voltage line VIL may be located on the left side of the vertical auxiliary line branched from each second gate line GL2 in the second direction DR2. The initialization voltage line VIL may be located between the vertical auxiliary line branched from each second gate line GL2 in the second direction DR2 and the vertical voltage line VVSL. The initialization voltage line VIL may provide an initialization voltage to a pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3. The initialization voltage line VIL may receive a sensing signal from a pixel circuit of each of the first pixel SP1, the second pixel SP2, and the third pixel SP3, and may provide the sensing signal to the display driver 520.

[0129] The vertical voltage line VVSL may extend in the second direction DR2. The vertical voltage lines VVSL may be located on the left side of the initialization voltage line VIL, respectively. The vertical voltage line VVSL may be connected between the power supply 550 and the second voltage line VSL. The vertical voltage line VVSL may provide the second voltage line VSL with a low potential voltage received from the power supply 550.

[0130] The second voltage line VSL may extend in the first direction DR1. The second voltage line VSL may be located at a (k+1)th row ROW. k+1 The second voltage line VSL may provide the low potential voltage received from the vertical voltage line VVSL to the light emitting element layers EML (see Fig. 9 ).

[0131] The first gate lines GL1 may extend in the first direction DR1. The first gate lines GL1 may be respectively located above the pixel circuits of the first pixels SP1. At least a portion of each of the first gate lines GL1 may extend in a direction opposite to the second direction DR2. For example, each of the first gate lines GL1 may include a vertical auxiliary line branching on the right side of the first pixel SP1, the second pixel SP2, and the third pixel SP3 and extending in a direction opposite to the second direction DR2. The vertical auxiliary line of each of the first gate lines GL1 may be respectively located on the right side of the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3. Each of the first gate lines GL1 may provide the first gate signal received from the gate driver 560 to the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3 through the vertical auxiliary line extending in the direction opposite to the second direction DR2.

[0132] The second gate lines GL2 may extend in the first direction DR1. The second gate lines GL2 may be respectively located under the pixel circuits of the third pixels SP3. At least a portion of each of the second gate lines GL2 may extend in the second direction DR2. For example, each of the second gate lines GL2 may include a vertical auxiliary line branching on the left side of the first voltage line VDL and extending in the second direction DR2. The vertical auxiliary line of each of the second gate lines GL2 may be respectively located on the left side of the first voltage line VDL. Each of the second gate lines GL2 may provide the second gate signal received from the gate driver 560 to the pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3 through the vertical auxiliary line extending in the second direction DR2.

[0133] The data lines DL may extend in the second direction DR2. The data lines DL may provide data voltages to the pixels SP. The data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3.

[0134] The second data line DL2 may extend in the second direction DR2. The second data line DL2 may be located on the right side of the vertical auxiliary line of each first gate line GL1, respectively. The second data line DL2 may provide a data voltage received from the display driver 520 to the pixel circuit of the second pixel SP2.

[0135] The third data lines DL3 may extend in the second direction DR2. The third data lines DL3 may be located on the right sides of the second data lines DL2, respectively. The third data lines DL3 may provide a data voltage received from the display driver 520 to a pixel circuit of the third pixel SP3.

[0136] The first data lines DL1 may extend in the second direction DR2. The first data lines DL1 may be located on the right side of the third data lines DL3, respectively. The first data lines DL1 may provide a data voltage received from the display driver 520 to a pixel circuit of the first pixel SP1.

[0137] In the drawings, the second data line DL2, the third data line DL3 and the first data line DL1 are sequentially arranged in the first direction DR1. However, the present disclosure is not limited thereto. The order in which the first data line DL1, the second data line DL2 and the third data line DL3 are arranged in the first direction DR1 may be variously changed.

[0138] Figure 7 is a schematic plan view of a portion of a display area DA of a display substrate 100 according to one or more embodiments. Figure 8 is a schematic plan view of a portion of a display area DA of a display substrate 100 according to one or more embodiments.

[0139] Apart from Figure 1 , Figure 2 and Figure 3 In addition, reference Figure 7 and Figure 8 , a plurality of emission areas LA and non-emission areas NLA may be defined in the display area DA of the display substrate 100. The emission area LA may be an area where light generated by the light emitting element of the display substrate 100 is emitted to the outside of the display substrate 100, and the non-emission area NLA may be an area where light generated by the light emitting element of the display substrate 100 is not emitted to the outside of the display substrate 100. In some embodiments, the emission area LA may include a first emission area LA1, a second emission area LA2, and a third emission area LA3.

[0140] In some embodiments, the emission area LA and the non-emission area NLA may be defined by a pixel defining layer PDL (see Fig. 9 ). For example, the emission area LA may be a layer that is aligned with the pixel definition layer PDL (see Fig. 9 ), and the non-emission area NLA may be an area that does not overlap with the opening of the pixel defining layer PDL (see Fig. 9 )’s openings overlap.

[0141] In one or more embodiments, the light emitted from the emission area LA of the display substrate 100 to the color conversion substrate 200 may be light of a third color. For example, the light of the third color may be blue light and may have a peak wavelength in the range of about 440 nm to about 480 nm. The peak wavelength may refer to a wavelength having a maximum intensity in a wavelength region. However, the present disclosure is not limited thereto, and the light emitted from the emission area LA of the display substrate 100 to the color conversion substrate 200 may also be light in an ultraviolet region.

[0142] If the first to third emission areas LA1 , LA2 , and LA3 emit light of the same color, the first to third pixels SP1 , SP2 , and SP3 may represent various colors by the color conversion pattern included in the color conversion substrate 200 .

[0143] In one or more embodiments, the first emission area LA1, the second emission area LA2, and the third emission area LA3 may emit light of different corresponding colors. For example, the light emitted from the first emission area LA1 may be red light, the light emitted from the second emission area LA2 may be green light, and the light emitted from the third emission area LA3 may be blue light.

[0144] The first emission area LA1, the second emission area LA2, and the third emission area LA3 may constitute a first pixel SP1, a second pixel SP2, and a third pixel SP3, respectively. The first emission area LA1, the second emission area LA2, and the third emission area LA3 may be repeatedly positioned throughout the entire display area DA along the first direction DR1 and the second direction DR2. The first emission area LA1, the second emission area LA2, and the third emission area LA3 may constitute a unit color pixel.

[0145] In one or more embodiments, reference Figure 7 , the first emission area LA1, the second emission area LA2, and the third emission area LA3 may be arranged in a diagonal direction defined by a direction opposite to the first direction DR1 and a second direction DR2. For example, in one unit color pixel, the first emission area LA1 is approximately located at the upper left corner in a plan view, the second emission area LA2 is approximately located at the center in a plan view, and the third emission area LA3 is approximately located at the lower right corner in a plan view. However, the arrangement order of the first emission area LA1, the second emission area LA2, and the third emission area LA3 is not limited thereto.

[0146] In one or more embodiments, reference Figure 8 , the first emission area LA1, the second emission area LA2, and the third emission area LA3 may be arranged along the first direction DR1. For example, in one unit color pixel, the first emission area LA1 is approximately located on the left side in a plan view, the second emission area LA2 is approximately located in the center in a plan view, and the third emission area LA3 is approximately located on the right side in a plan view. However, the arrangement order of the first emission area LA1, the second emission area LA2, and the third emission area LA3 is not limited thereto.

[0147] In one or more embodiments, reference Figure 7 , the first emission area LA1 may have a polygonal shape extending in the first direction DR1 and the second direction DR2. In the drawings, a pentagon (e.g., an irregular pentagon) is shown as an example of the shape of the first emission area LA1. The second emission area LA2 may have a polygonal shape extending approximately in a diagonal direction defined by the first direction DR1 and the second direction DR2. In the drawings, a polygon with steps at both ends is shown as an example of the shape of the second emission area LA2. The third emission area LA3 may have a polygonal shape extending approximately in the first direction DR1 and the second direction DR2. In the drawings, a polygon including a portion protruding in a direction opposite to the first direction DR1 and in the second direction DR2 is shown as an example of the shape of the third emission area LA3.

[0148] In one or more embodiments, reference Figure 8 , the first emission area LA1, the second emission area LA2, and the third emission area LA3 may have a polygonal shape extending in the second direction DR2. In the drawings, a quadrilateral is shown as an example of the shape of each of the first emission area LA1, the second emission area LA2, and the third emission area LA3. However, the shapes of the first emission area LA1, the second emission area LA2, and the third emission area LA3 are not limited thereto.

[0149] In one or more embodiments, reference Figure 7 , the widths and shapes of the first emission area LA1, the second emission area LA2, and the third emission area LA3 may be different from each other. For example, the first emission area LA1 may have a similar width in the first direction DR1 and the second direction DR2. The second emission area LA2 may have a relatively wide width in the diagonal direction defined by the first direction DR1 and the second direction DR2, and may have a relatively narrow width in the diagonal direction defined by the direction opposite to the first direction DR1 and the second direction DR2. Therefore, the second emission area LA2 may be shaped as a polygon extending substantially in the diagonal direction defined by the first direction DR1 and the second direction DR2. The third emission area LA3 may have a similar width in the first direction DR1 and the second direction DR2.

[0150] In one or more embodiments, reference Figure 8 , the widths and shapes of the first emission area LA1, the second emission area LA2, and the third emission area LA3 may be the same. For example, the widths of the first emission area LA1, the second emission area LA2, and the third emission area LA3 in the first direction DR1 may be the same, and the widths of the first emission area LA1, the second emission area LA2, and the third emission area LA3 in the second direction DR2 may be the same.

[0151] The non-emission area NLA may be located around the emission area LA of the display substrate 100 in the display area DA (e.g., in a plan view). The non-emission area NLA may be located not only around the emission area LA but also between the first emission area LA1 and the second emission area LA2, between the second emission area LA2 and the third emission area LA3, and between the third emission area LA3 and the first emission area LA1.

[0152] Light emitted from the emission area LA of the display substrate 100 may pass through the light-transmitting area of ​​the color conversion substrate 200 and may then be provided to the outside of the display device 10 .

[0153] Fig. 9 It is along Figure 7 A cross-sectional view taken along line X2-X2'.

[0154] Apart from Figure 7 and Figure 8 In addition, reference Fig. 9 , the display device 10 may include a display substrate 100 , a color conversion substrate 200 facing the display substrate 100 , and a filler 300 combining the display substrate 100 and the color conversion substrate 200 together.

[0155] The display substrate 100 may include a first substrate 110 , a circuit layer CCL, a light emitting element layer EML, and an encapsulation structure 170 .

[0156] The first substrate 110 may include a transparent material. For example, the first substrate 110 may include a transparent insulating material such as glass or quartz. The first substrate 110 may be a rigid substrate. However, the first substrate 110 is not limited thereto. The first substrate 110 may also include a plastic such as polyimide, or may have a flexible property such that it may be bent, curved, folded, or curled.

[0157] The circuit layer CCL (eg, a thin film transistor layer) may be located on the first substrate 110. Fig.11 etc. to describe the circuit layer CCL.

[0158] The light emitting element layer EML may be located on the circuit layer CCL. The light emitting element layer EML may include a pixel electrode PXE, a pixel defining layer PDL, a light emitting layer LEL, and a common electrode CME.

[0159] The pixel electrode PXE may be a first electrode (e.g., an anode) of a light-emitting diode. The pixel electrode PXE may have a stacked structure of a reflective material layer and a material layer having a high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ), the reflective material layer is such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. The material layer with a high work function may be located on the reflective material layer so that it is positioned close to the light emitting layer LEL. The pixel electrode PXE may have, but is not limited to, ITO / Mg, ITO / MgF 2 , ITO / Ag or ITO / Ag / ITO multilayer structure.

[0160] The pixel electrode PXE may include a first pixel electrode PXR, a second pixel electrode PXG, and a third pixel electrode PXB. The first pixel electrode PXR may overlap the first emission area LA1. The second pixel electrode PXG may overlap the second emission area LA2. The third pixel electrode PXB may overlap the third emission area LA3.

[0161] The pixel defining layer PDL may be located on the surface of the first substrate 110 along the boundary of the pixel SP. The pixel defining layer PDL may be located on the pixel electrode PXE and may include / define an opening exposing the pixel electrode PXE. The emission area LA and the non-emission area NLA may be defined by the pixel defining layer PDL and its opening.

[0162] The pixel defining layer PDL may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The pixel defining layer PDL may also include an inorganic material.

[0163] The light-emitting layer LEL may be located on the pixel electrode PXE exposed by the pixel defining layer PDL. The light-emitting layer LEL may contact not only the pixel electrode PXE but also the side surface and the upper surface of the pixel defining layer PDL. The light-emitting layer LEL may be connected without distinguishing between the emission areas LA and between the pixels SP. The light-emitting layer LEL may be positioned over the entire surface without distinguishing between the emission areas LA and between the pixels SP. Therefore, the light-emitting layers LEL of the emission areas LA1, LA2, and LA3 may emit light having the same wavelength. For example, the light-emitting layers LEL of the emission areas LA1, LA2, and LA3 may emit blue light or ultraviolet light, and the wavelength conversion layer WCL included in the color conversion substrate 200 to be described later may enable each pixel SP to display a corresponding color.

[0164] In one or more embodiments, the light emitting layers LEL may be respectively located in the emission areas LA1, LA2, and LA3 separated by the pixel defining layer PDL. In this case, the light emitting layers LEL of the emission areas LA1, LA2, and LA3 may emit light having the same wavelength.

[0165] In one or more embodiments in which the display device 10 is an organic light-emitting display device, the light-emitting layer LEL may include an organic layer including an organic material. The organic layer may include an organic light-emitting layer. In some cases, the organic layer may also include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer as an auxiliary layer for assisting light emission. In one or more embodiments, if the display device 10 is a micro-LED display device or a nano-LED display device, the light-emitting layer LEL may include an inorganic material such as an inorganic semiconductor.

[0166] In some embodiments, the light emitting layer LEL may have a series structure including a plurality of organic light emitting layers overlapping each other in a thickness direction and a charge generating layer located therebetween. The organic light emitting layers overlapping each other may emit light of the same wavelength or may emit light of different wavelengths. At least some of the light emitting layers LEL of each pixel SP may be separated from at least some of the light emitting layers LEL of adjacent pixels SP by a pixel defining layer PDL, or may be connected to at least some of the light emitting layers LEL of adjacent pixels SP.

[0167] The common electrode CME may be located on the light emitting layer LEL. The common electrode CME may be connected without distinguishing between the emission areas LA and between the pixels SP. The common electrode CME may be a full-surface electrode positioned throughout the entire surface without distinguishing between the emission areas LA and between the pixels SP. The common electrode CME may be a second electrode (e.g., a cathode) of a light emitting diode. The common electrode CME may include a material layer having a small work function, such as Li, Ca, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al. The common electrode CME may also include a transparent metal oxide layer located on the material layer having a small work function.

[0168] The pixel electrode PXE, the light emitting layer LEL, and the common electrode CME may constitute a light emitting element (eg, an organic light emitting diode). Light L emitted from the light emitting layer LEL may be output upward through the common electrode CME.

[0169] The encapsulation structure 170 may be located on the common electrode CME. The encapsulation structure 170 may include at least one thin film encapsulation layer. For example, the encapsulation structure 170 may include a first encapsulation inorganic layer 171 , an encapsulation organic layer 172 , and a second encapsulation inorganic layer 173 .

[0170] The first encapsulation inorganic layer 171 may be located on the light emitting element layer EML. The first encapsulation inorganic layer 171 may include silicon nitride (SiN x ), silicon oxide (SiOx ) or silicon oxynitride (SiO x N y ).

[0171] Encapsulating organic layer 172 may be on first encapsulating inorganic layer 171. Encapsulating organic layer 172 may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0172] The second encapsulation inorganic layer 173 may be located on the encapsulation organic layer 172. The second encapsulation inorganic layer 173 may include the same material as the first encapsulation inorganic layer 171 described above. For example, the second encapsulation inorganic layer 173 may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0173] In some embodiments, some layers of the encapsulation structure 170 or the entire encapsulation structure 170 may be omitted. If the encapsulation structure 170 is omitted, the filler 300, the sealing portion 400, and the color conversion substrate 200 may be directly located on the light emitting element layer EML and may perform an encapsulation function.

[0174] The color conversion substrate 200 may be located on the encapsulation structure 170 to face the display substrate 100. The color conversion substrate 200 may include a second substrate 210, a light blocking member BM, a color filter layer CFL, a first capping layer 220, a partition wall PTL, a wavelength conversion layer WCL, a light transmitting layer TPL, and a second capping layer 230.

[0175] The second substrate 210 may include a transparent material. The second substrate 210 may include a transparent insulating material such as glass or quartz. The second substrate 210 may be a rigid substrate. However, the second substrate 210 is not limited thereto. The second substrate 210 may also include a plastic such as polyimide, or may have a flexible property such that it may be bent, curved, folded, or curled.

[0176] The second substrate 210 may be the same substrate as the first substrate 110, but may have a different material, thickness, and transmittance from the first substrate 110. For example, the second substrate 210 may have a higher transmittance than the first substrate 110. The second substrate 210 may be thicker or thinner than the first substrate 110.

[0177] The light blocking member BM may be located on a surface of the second substrate 210 facing the first substrate 110 along the boundary of the pixel SP. The light blocking member BM may overlap the pixel defining layer PDL of the display substrate 100 and may be located in the non-emission area NLA. The light blocking member BM may include / define an opening exposing a surface of the second substrate 210 overlapping the emission area LA. The light blocking member BM may be formed in a grid shape in a plan view.

[0178] The light blocking member BM may include an organic material. The light blocking member BM may reduce color distortion due to reflection of external light by absorbing external light. In addition, the light blocking member BM may reduce or prevent light emitted from the light emitting layer LEL from intruding into adjacent pixels SP.

[0179] In one or more embodiments, the light blocking member BM may absorb all visible light wavelengths. The light blocking member BM may include a light absorbing material. For example, the light blocking member BM may be made of a material used as a black matrix of the display device 10.

[0180] In one or more embodiments, the light blocking member BM may absorb light of a corresponding wavelength among the visible light wavelengths, and may transmit light of another corresponding wavelength. For example, the light blocking member BM may include the same material as the color filter layer CFL. For example, the light blocking member BM may be made of the same material as the blue color filter layer. In some embodiments, the light blocking member BM may be formed integrally with the blue color filter layer. The light blocking member BM may also be omitted.

[0181] The color filter layer CFL may be located on the surface of the second substrate 210 on which the light blocking member BM is located. The color filter layer CFL may be located on the surface of the second substrate 210 exposed by the opening of the light blocking member BM. In addition, each of the color filter layers CFL may be located on a portion of an adjacent light blocking member BM.

[0182] The color filter layer CFL may include a first color filter layer CFL1 located in the first pixel SP1, a second color filter layer CFL2 located in the second pixel SP2, and a third color filter layer CFL3 located in the third pixel SP3. Each color filter layer CFL may include a colorant such as a dye or a pigment that absorbs wavelengths other than the corresponding color wavelength. The first color filter layer CFL1 may be a red color filter layer, the second color filter layer CFL2 may be a green color filter layer, and the third color filter layer CFL3 may be a blue color filter layer. Although adjacent color filter layers CFL are spaced apart from each other on the light blocking member BM in the drawings, they may also at least partially overlap each other on the light blocking member BM.

[0183] The first capping layer 220 may be positioned on the color filter layer CFL. The first capping layer 220 may reduce or prevent damage or contamination to the color filter layer CFL by reducing or preventing impurities such as moisture or air from penetrating into the color filter layer CFL from the outside.

[0184] The first capping layer 220 may directly contact the surface of the color filter layer CFL ( Fig. 9 The first capping layer 220 may be made of an inorganic material. For example, the first capping layer 220 may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, or silicon oxynitride.

[0185] The partition wall PTL may be located on the first capping layer 220. The partition wall PTL may be located in the non-emission area NLA. The partition wall PTL may overlap with the light blocking member BM. The partition wall PTL may include / define an opening exposing the first capping layer 220. The partition wall PTL may include, but is not limited to, a photosensitive organic material. The partition wall PTL may also include a light blocking material.

[0186] The wavelength conversion layer WCL and / or the light-transmitting layer TPL may be located in a space exposed by the opening of the partition wall PTL. The wavelength conversion layer WCL and the light-transmitting layer TPL may be formed by an inkjet process using the partition wall PTL as a bank, but the present disclosure is not limited thereto.

[0187] In one or more embodiments in which the light emitting layer LEL of each pixel SP emits light of a third color, the wavelength conversion layer WCL may include a first wavelength conversion pattern WCL1 in the first pixel SP1 and a second wavelength conversion pattern WCL2 in the second pixel SP2. The light transmitting layer TPL may be in the third pixel SP3.

[0188] The first wavelength conversion pattern WCL1 may include a first base resin BRS1 and a first wavelength conversion material WCP1 in the first base resin BRS1. The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and a second wavelength conversion material WCP2 in the second base resin BRS2. The light transmitting layer TPL may include a third base resin BRS3 and a scatterer SCP in the third base resin BRS3.

[0189] The first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may include a light-transmitting organic material. For example, the first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first base resin BRS1, the second base resin BRS2, ​​and the third base resin BRS3 may all be made of the same material, but the present disclosure is not limited thereto.

[0190] The scatterers SCP may be metal oxide particles or organic particles. The metal oxide may be, for example, titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 ), zinc oxide (ZnO x , which may be ZnO and / or ZnO 2 ) or tin oxide (SnO 2 ), and the organic particulate material may be, for example, an acrylic resin or a polyurethane resin.

[0191] The first wavelength conversion material WCP1 may convert the third color into the first color, and the second wavelength conversion material WCP2 may convert the third color into the second color. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 may be quantum dots, quantum rods, or phosphors. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI compound nanocrystals, or a combination thereof. The first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 may further include a scatterer SCP to improve wavelength conversion efficiency.

[0192] The light-transmitting layer TPL located in the third pixel SP3 may transmit the light of the third color emitted from the light-emitting layer LEL while maintaining the wavelength of the light. The scatterer SCP of the light-transmitting layer TPL may control the emission path of the light emitted through the light-transmitting layer TPL. The light-transmitting layer TPL may not include a wavelength conversion material.

[0193] The second capping layer 230 may be located on the wavelength conversion layer WCL, the light-transmitting layer TPL, and the partition wall PTL. The second capping layer 230 may be made of an inorganic material. The second capping layer 230 may include a material selected from the materials listed as the materials of the first capping layer 220. The second capping layer 230 and the first capping layer 220 may be made of the same material, but the present disclosure is not limited thereto.

[0194] The filler 300 may be located between the display substrate 100 and the color conversion substrate 200. The filler 300 may fill the space between the display substrate 100 and the color conversion substrate 200, and may bond and couple them to each other. The filler 300 may be located between the encapsulation structure 170 of the display substrate 100 and the second capping layer 230 of the color conversion substrate 200. The filler 300 may be made of, but is not limited to, a Si-based organic material or an epoxy-based organic material.

[0195] Fig.10 is an equivalent circuit diagram of a pixel SP according to one or more embodiments.

[0196] refer to Fig.10 , each pixel SP may be connected to a first voltage line VDL, a data line DL, an initialization voltage line VIL, a first gate line GL1 , a second gate line GL2 , and a vertical voltage line VVSL.

[0197] Each pixel SP may include a pixel circuit and a light emitting element ED. In one or more embodiments, as shown in the accompanying drawings, the pixel circuit of each pixel SP may have a 3T1C structure including three transistors and one capacitor. For example, the pixel circuit of each pixel SP may include a first transistor ST1, a second transistor ST2, and a third transistor ST3 and a capacitor C1. However, the present disclosure is not limited thereto, and the number of transistors and capacitors in each pixel circuit may be changed differently. Although a 3T1C structure is described below as an example for ease of description, the present disclosure is not limited thereto, and various other modified structures such as a 2T1C structure, a 7T1C structure, a 6T1C structure, and a 17T3C structure are also applicable.

[0198] The first transistor ST1 may include a gate electrode, a drain electrode, and a source electrode. The first transistor ST1 may have a gate electrode connected to the first node N1, a drain electrode connected to the first voltage line VDL, and a source electrode connected to the second node N2. The first transistor ST1 may control a drain-source current (or a drive current) based on a data voltage applied to the gate electrode. The first transistor ST1 may be a driving transistor for driving the light emitting element ED.

[0199] The light emitting element ED may emit light in response to the received driving current. The amount of light emitted from the light emitting element ED or the brightness of the light emitting element ED may be proportional to the magnitude of the driving current. The light emitting element ED may be an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, a micro light emitting diode, or an inorganic light emitting diode including an inorganic semiconductor.

[0200] A first electrode (e.g., a pixel electrode) of the light emitting element ED may be connected to the second node N2, and a second electrode of the light emitting element ED may be connected to the vertical voltage line VVSL. The first electrode of the light emitting element ED may be connected to the source electrode of the first transistor ST1, the drain electrode of the third transistor ST3, and the first capacitor electrode of the capacitor C1 through the second node N2.

[0201] The second transistor ST2 may be turned on by the first gate signal of the first gate line GL1 to electrically connect the data line DL and the first node N1 as the gate electrode of the first transistor ST1. The second transistor ST2 may be turned on based on the first gate signal to provide a data voltage to the first node N1. The second transistor ST2 may have a gate electrode connected to the first gate line GL1, a drain electrode connected to the data line DL, and a source electrode connected to the first node N1. The source electrode of the second transistor ST2 may be connected to the gate electrode of the first transistor ST1 and the second capacitor electrode of the capacitor C1 through the first node N1. The second transistor ST2 may be a switching transistor that controls a current flowing through the first transistor ST1 and the light emitting element ED.

[0202] The third transistor ST3 may be turned on by the second gate signal of the second gate line GL2 to electrically connect the initialization voltage line VIL and the second node N2 as the source electrode of the first transistor ST1. The third transistor ST3 may be turned on based on the second gate signal to provide the initialization voltage to the second node N2. The third transistor ST3 may be turned on based on the second gate signal to provide the sensing signal to the initialization voltage line VIL. The third transistor ST3 may have a gate electrode connected to the second gate line GL2, a drain electrode connected to the second node N2, and a source electrode connected to the initialization voltage line VIL. The drain electrode of the third transistor ST3 may be connected to the source electrode of the first transistor ST1, the first capacitor electrode of the capacitor C1, and the first electrode of the light emitting element ED through the second node N2. The third transistor ST3 may be a switching transistor that controls the current flowing through the first transistor ST1 and the light emitting element ED.

[0203] Fig.11 is a cross-sectional view of an example of a first transistor ST1 of a circuit layer CCL according to one or more embodiments. Fig.12 is a cross-sectional view of an example of a second transistor ST2 and a third transistor ST3 of a circuit layer CCL according to one or more embodiments.

[0204] Apart from Fig.10 In addition, reference Fig.11 and Fig.12 , the display substrate 100 may include a first substrate 110 , a circuit layer CCL, and a light emitting element layer EML.

[0205] Because the above reference Fig. 9 The first substrate 110 is described, so a description thereof will be omitted.

[0206] The circuit layer CCL may be located on (e.g., above) the first substrate 110. The circuit layer CCL (e.g., thin film transistor layer) may include a bottom conductive layer BML, a buffer layer BF, an active layer ACTL, a gate insulating layer GI, a gate conductive layer GML, a passivation layer PV, and a via layer VIA. The circuit layer CCL may include a first transistor ST1, a second transistor ST2, and a third transistor ST3, and a capacitor C1.

[0207] The bottom conductive layer BML may be located on the first substrate 110. The bottom conductive layer BML may include a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0208] In one or more embodiments, the bottom conductive layer BML may include an initialization voltage line VIL, a data line DL, a first voltage line VDL, a vertical voltage line VVSL, and a first capacitor electrode CPE1 of the capacitor C1.

[0209] The buffer layer BF may be located on the bottom conductive layer BML. The buffer layer BF may include an inorganic material such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Alternatively, the buffer layer BF may include a multilayer in which a plurality of layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0210] The active layer ACTL may be located on the buffer layer BF. The active layer ACTL may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor material.

[0211] In one or more embodiments, the active layer ACTL may include a first active region ACT1, a first drain electrode DE1 and a first source electrode SE1 of the first transistor ST1, a second active region ACT2, a second drain electrode DE2 and a second source electrode SE2 of the second transistor ST2, a third active region ACT3, a third drain electrode DE3 and a third source electrode SE3 of the third transistor ST3, and a second capacitor electrode CPE2 of the capacitor C1.

[0212] The gate insulating layer GI may be on the active layer ACTL. The gate insulating layer GI may include an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0213] The gate conductive layer GML may be located on the gate insulating layer GI. The gate conductive layer GML may include a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0214] In one or more embodiments, the gate conductive layer GML may include a first gate line GL1, a second gate line GL2, a first gate electrode GE1 of the first transistor ST1, a second gate electrode GE2 of the second transistor ST2, a third gate electrode GE3 of the third transistor ST3, and connection electrodes CE1, CE2, CE3, and CE4.

[0215] In the display device 10, the gate conductive layer GML may have a lower reflectivity than at least one of the bottom conductive layer BML and the anode conductive layer AML. The gate conductive layer GML may further include a material for reducing reflectivity. For example, the gate conductive layer GML may include aluminum zinc tin oxide (AZTO).

[0216] The first light L1 (such as light from the outside or light emitted from the adjacent pixel SP) may be reflected from the upper surface of the gate conductive layer GML. The second light L2 reflected from the upper surface of the gate conductive layer GML may be reflected again from the lower surface of the anode conductive layer AML to enter the active layer ACTL. Therefore, light-induced degradation may occur. Light-induced degradation refers to a phenomenon in which a characteristic curve between a drain-source current and a gate voltage of a transistor is shifted due to external light incident on the transistor, thereby changing the magnitude of a threshold voltage.

[0217] In the display device 10 , the gate conductive layer GML further including a material for reducing reflectivity may reduce reflected light, such as the second light L2 . Therefore, light-induced degradation may be reduced or minimized, thereby improving the reliability of the display device 10 .

[0218] The passivation layer PV may be located on the gate conductive layer GML. The passivation layer PV may include an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0219] The via layer VIA may be located on the passivation layer PV. The via layer VIA may include an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0220] The circuit layer CCL may include first, second, and third transistors ST1 , ST2 , and ST3 , and a capacitor C1 .

[0221] The first transistor ST1 may include a first active region ACT1 , a first gate electrode GE1 , a first drain electrode DE1 , and a first source electrode SE1 .

[0222] The first active region ACT1 may be located in the active layer ACTL. The first active region ACT1 may overlap the first gate electrode GE1 in the third direction DR3. The first active region ACT1 may be a region of the active layer ACTL that is not conductive in a region overlapping the first gate electrode GE1.

[0223] The first gate electrode GE1 may be located in the gate conductive layer GML. Fig.10 , the first gate electrode GE1 may be connected to the second source electrode SE2 of the second transistor ST2 and the second capacitor electrode CPE2 of the capacitor C1 through the first node N1.

[0224] In the drawings, the first transistor ST1 is shown as having a top gate structure in which the first gate electrode GE1 is located above the first active region ACT1. However, the present disclosure is not limited thereto. For example, the first transistor ST1 may also have a bottom gate structure in which the first gate electrode GE1 is located below the first active region ACT1. For another example, the first transistor ST1 may have a dual gate structure in which the first gate electrode GE1 is located both above and below the first active region ACT1.

[0225] The first drain electrode DE1 and the first source electrode SE1 may be formed by thermally treating the active layer ACTL to make it conductive. The first drain electrode DE1 and the first source electrode SE1 may be, but are not limited to, a P-type semiconductor or an N-type semiconductor.

[0226] refer to Fig.10 , the first drain electrode DE1 may be electrically connected to the first voltage line VDL. Fig.11 , the first drain electrode DE1 may be connected to the first voltage line VDL through the first connection electrode CE1. Therefore, the first drain electrode DE1 may receive a driving voltage from the first voltage line VDL.

[0227] refer to Fig.10 , the first source electrode SE1 may be connected to the light emitting element ED through the second node N2. Fig.11 , the first source electrode SE1 may be connected to the pixel electrode PXE through the second connection electrode CE2. Therefore, the first source electrode SE1 may provide a driving current to the light emitting element ED.

[0228] refer to Fig.10 , the first source electrode SE1 may be connected to the capacitor C1 through the second node N2. Fig.11 , the first source electrode SE1 may be connected to the first capacitor electrode CPE1 of the capacitor C1 through the second connection electrode CE2.

[0229] The second transistor ST2 may include a second active region ACT2 , a second gate electrode GE2 , a second drain electrode DE2 , and a second source electrode SE2 .

[0230] The second active region ACT2 may be located in the active layer ACTL. The second active region ACT2 may overlap the second gate electrode GE2 in the third direction DR3. The second active region ACT2 may be a region of the active layer ACTL that is non-conductive in a region overlapping the second gate electrode GE2.

[0231] The second gate electrode GE2 may be located in the gate conductive layer GML. Fig.10 , the second gate electrode GE2 may be connected to the first gate line GL1. Therefore, the second gate electrode GE2 may receive the first gate signal from the first gate line GL1.

[0232] In the drawings, the second transistor ST2 is shown as having a top gate structure in which the second gate electrode GE2 is located above the second active region ACT2. However, the present disclosure is not limited thereto. For example, the second transistor ST2 may also have a bottom gate structure in which the second gate electrode GE2 is located below the second active region ACT2. For another example, the second transistor ST2 may have a dual gate structure in which the second gate electrode GE2 is located both above and below the second active region ACT2.

[0233] The second drain electrode DE2 and the second source electrode SE2 may be formed by thermally treating the active layer ACTL to make it conductive. The second drain electrode DE2 and the second source electrode SE2 may be, but are not limited to, a P-type semiconductor or an N-type semiconductor.

[0234] refer to Fig.10 , the second drain electrode DE2 may be electrically connected to the data line DL. Fig.12 , the second drain electrode DE2 may be connected to the data line DL through the third connection electrode CE3. Therefore, the second drain electrode DE2 may receive the data voltage from the data line DL.

[0235] refer to Fig.10 , the second source electrode SE2 may be connected to the first gate electrode GE1 of the first transistor ST1 through the first node N1. Therefore, the second source electrode SE2 may provide a data voltage to the first gate electrode GE1 of the first transistor ST1 through the first node N1. The first transistor ST1 may control a driving current based on the data voltage received from the second source electrode SE2.

[0236] refer to Fig.10, the second source electrode SE2 may be connected to the capacitor C1 through the first node N1. For example, in one or more embodiments, the second source electrode SE2 may be connected to the second capacitor electrode CPE2 of the capacitor C1 through a separate connection electrode located in the gate conductive layer GML.

[0237] The third transistor ST3 may include a third active region ACT3 , a third gate electrode GE3 , a third drain electrode DE3 , and a third source electrode SE3 .

[0238] The third active region ACT3 may be located in the active layer ACTL. The third active region ACT3 may overlap the third gate electrode GE3 in the third direction DR3. The third active region ACT3 may be a region of the active layer ACTL that is non-conductive in a region overlapping the third gate electrode GE3.

[0239] The third gate electrode GE3 may be located in the gate conductive layer GML. Fig.10 , the third gate electrode GE3 may be connected to the second gate line GL2. Therefore, the third gate electrode GE3 may receive the second gate signal from the second gate line GL2.

[0240] In the drawings, the third transistor ST3 is shown as having a top gate structure in which the third gate electrode GE3 is located above the third active region ACT3. However, the present disclosure is not limited thereto. For example, the third transistor ST3 may also have a bottom gate structure in which the third gate electrode GE3 is located below the third active region ACT3. For another example, the third transistor ST3 may have a dual gate structure in which the third gate electrode GE3 is located both above and below the third active region ACT3.

[0241] The third drain electrode DE3 and the third source electrode SE3 may be formed by thermally treating the active layer ACTL to make it conductive. The third drain electrode DE3 and the third source electrode SE3 may be, but are not limited to, a P-type semiconductor or an N-type semiconductor.

[0242] refer to Fig.10 , the third drain electrode DE3 may be electrically connected to the first source electrode SE1 of the first transistor ST1. For example, in one or more embodiments, the third drain electrode DE3 may be connected to the first source electrode SE1 of the first transistor ST1 through a separate connection electrode in the gate conductive layer GML.

[0243] refer to Fig.10 , the third drain electrode DE3 may be connected to the capacitor C1. For example, in one or more embodiments, the third drain electrode DE3 may be connected to the first capacitor electrode CPE1 of the capacitor C1 through a separate connection electrode located in the gate conductive layer GML.

[0244] refer to Fig.10 , the third source electrode SE3 may be connected to the initialization voltage line VIL. Fig.12 , the third source electrode SE3 may be connected to the initialization voltage line VIL through the fourth connection electrode CE4. Therefore, the third source electrode SE3 may receive the initialization voltage from the initialization voltage line VIL and may provide a sensing signal to the initialization voltage line VIL.

[0245] The capacitor C1 may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2 .

[0246] The first capacitor electrode CPE1 may be located in the bottom conductive layer BML. The first capacitor electrode CPE1 may be connected to the first source electrode SE1 of the first transistor ST1 through the second connection electrode CE2. The first capacitor electrode CPE1 may be connected to the third drain electrode DE3 of the third transistor ST3 through a separate connection electrode located in the gate conductive layer GML.

[0247] The second capacitor electrode CPE2 may be located in the active layer ACTL. The second capacitor electrode CPE2 may be connected to the first gate electrode GE1 of the first transistor ST1 through a separate connection electrode located in the gate conductive layer GML. The second capacitor electrode CPE2 may be connected to the second source electrode SE2 of the second transistor ST2 through a separate connection electrode located in the gate conductive layer GML.

[0248] The light emitting element layer EML may include an anode conductive layer AML and a pixel defining layer PDL.

[0249] Because the above reference Fig. 9 The pixel defining layer PDL is described, so a description thereof will be omitted.

[0250] The anode conductive layer AML may be located on the circuit layer CCL. For example, the anode conductive layer AML may be located on the via layer VIA. In one or more embodiments, the anode conductive layer AML may include a pixel electrode PXE.

[0251] The anode conductive layer AML may have a stacked structure of a reflective material layer and a material layer having a high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium oxide (In 2 O 3), the reflective material layer is such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. The material layer with a high work function may be located on the reflective material layer so that it is positioned close to the light emitting layer LEL. The pixel electrode PXE may have, but is not limited to, a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag or ITO / Ag / ITO.

[0252] In the display device 10, the number of layers included in the circuit layer CCL is reduced or minimized to reduce the number of masks suitable for patterning each layer. Therefore, process efficiency can be improved.

[0253] For example, lines such as data lines DL, initialization voltage lines VIL, first voltage lines VDL, and vertical voltage lines VVSL are placed in the bottom conductive layer BML, and lines such as gate lines GL, horizontal voltage lines HVDL, and second voltage lines VSL are placed in the gate conductive layer GML. Therefore, since a layer for placing lines is not added, the number of layers can be reduced or minimized.

[0254] For another example, the first capacitor electrode CPE1 is placed in the bottom conductive layer BML, and the second capacitor electrode CPE2 is placed in the active layer ACTL. Therefore, since a layer for placing the capacitor C1 is not added, the number of layers can be reduced or minimized.

[0255] For another example, a connection electrode for connecting the bottom conductive layer BML, the active layer ACTL, and the gate conductive layer GML is placed in the gate conductive layer GML. Therefore, since a layer for placing a connection electrode is not added, the number of layers can be reduced or minimized.

[0256] In the display device 10, since the number of layers included in the circuit layer CCL is reduced or minimized, the distance between the light emitting element layer EML and the active layer ACTL in the third direction DR3 can be reduced. Therefore, light from the outside or light emitted from the adjacent pixel SP can properly enter the active layer ACTL. In order to reduce or minimize the resulting light-induced degradation, the gate conductive layer GML of the display device 10 may include a reflectivity reduction structure.

[0257] Now refer to Fig.13 etc. to describe the reflectivity reducing structure of the gate conductive layer GML.

[0258] Fig.13 is a cross-sectional view illustrating an example of a portion of a display area DA and a portion of a pad area PDA of the display device 10 according to one or more embodiments. Fig.14is a cross-sectional view of an example of a bottom conductive layer BML according to one or more embodiments. Fig.15 is a cross-sectional view of an example of a gate conductive layer GML according to one or more embodiments. Fig.16 is a cross-sectional view of an example of an anode conductive layer AML according to one or more embodiments.

[0259] Fig.13 An exemplary cross section of the first transistor ST1 and the capacitor C1 in the display area DA is shown, and an exemplary cross section of the wiring pad WPD in the pad area PDA is shown.

[0260] refer to Figures 13 to 16 , the display device 10 may include a display area DA and a pad area PDA. The display area DA is an area where an image is displayed, and may be approximately a central area of ​​the display substrate 100. The pad area PDA may be an area where the wiring pad WPD is located. As has been referred to above Figure 5 The display area DA and the pad area PDA are described, so description thereof will be omitted.

[0261] refer to Fig.13 and Fig.14 , the bottom conductive layer BML may include a first bottom conductive layer BML1 and a second bottom conductive layer BML2.

[0262] The first bottom conductive layer BML1 may be located on the first substrate 110 (as used herein, "on" may mean "above"). The first bottom conductive layer BML1 may be a layer for improving adhesion between the first substrate 110 and the bottom conductive layer BML. For example, the first bottom conductive layer BML1 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. For example, the first bottom conductive layer BML1 may include, but is not limited to, titanium (Ti).

[0263] The second bottom conductive layer BML2 may be located on the first bottom conductive layer BML1. The second bottom conductive layer BML2 may include a material having excellent electrical conductivity. For example, the second bottom conductive layer BML2 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or an alloy thereof. For example, the second bottom conductive layer BML2 may include, but is not limited to, copper (Cu).

[0264] refer to Fig.13 and Fig.15 The gate conductive layer GML may include a first gate conductive layer GML1, a second gate conductive layer GML2, a third gate conductive layer GML3, and a fourth gate conductive layer GML4.

[0265] The first gate conductive layer GML1 may be located on the gate insulating layer GI. The first gate conductive layer GML1 may be a layer for improving adhesion between the gate insulating layer GI and the gate conductive layer GML. For example, the first gate conductive layer GML1 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or an alloy thereof. For example, the first gate conductive layer GML1 may include, but is not limited to, titanium (Ti). In one or more embodiments, the thickness TH1 of the first gate conductive layer GML1 may be, but is not limited to, about to about

[0266] The second gate conductive layer GML2 may be located on the first gate conductive layer GML1. The second gate conductive layer GML2 may include a material having excellent electrical conductivity. For example, the second gate conductive layer GML2 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. For example, the second gate conductive layer GML2 may include, but is not limited to, copper (Cu). In one or more embodiments, the thickness TH2 of the second gate conductive layer GML2 may be, but is not limited to, about to about

[0267]

[0268] The third gate conductive layer GML3 may be located on the second gate conductive layer GML2. The third gate conductive layer GML3 may include a material having a high extinction coefficient and a low reflectivity. For example, the third gate conductive layer GML3 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or an alloy thereof. For example, the third gate conductive layer GML3 may include, but is not limited to, titanium (Ti). In one or more embodiments, the thickness TH3 of the third gate conductive layer GML3 may be, but is not limited to, about to about

[0269] The fourth gate conductive layer GML4 may be located on the third gate conductive layer GML3. The fourth gate conductive layer GML4 may include a material having high light transmittance. The fourth gate conductive layer GML4 may include a transparent conductive oxide (TCO). For example, the fourth gate conductive layer GML4 may include aluminum zinc tin oxide (AZTO).

[0270] In some embodiments, the fourth gate conductive layer GML4 may include about 1 at % to about 10 at % aluminum based on atoms other than oxygen atoms. The fourth gate conductive layer GML4 may include about 60 at % to about 90 at % zinc based on atoms other than oxygen atoms. The fourth gate conductive layer GML4 may include about 10 at % to about 30 at % tin based on atoms other than oxygen atoms. Here, the respective ratios of aluminum, zinc, and tin included in the fourth gate conductive layer GML4 refer to the ratios of the number of respective particles of aluminum, zinc, and tin atoms to the total number of particles of aluminum, zinc, and tin atoms as atoms other than oxygen atoms.

[0271] In some embodiments, the fourth gate conductive layer GML4 may include about 0.5at% to about 5at% aluminum based on the total atoms including oxygen atoms. The fourth gate conductive layer GML4 may include about 20at% to about 40at% zinc based on the total atoms including oxygen atoms. The fourth gate conductive layer GML4 may include about 7at% to about 15at% tin based on the total atoms including oxygen atoms. The fourth gate conductive layer GML4 may include about 50at% to about 60at% oxygen based on the total atoms including oxygen atoms. Here, the corresponding ratios of aluminum, zinc, tin, and oxygen included in the fourth gate conductive layer GML4 refer to the ratios of the number of corresponding particles of aluminum, zinc, tin, and oxygen atoms to the total number of particles of aluminum, zinc, tin, and oxygen atoms.

[0272] In some embodiments, the reflectivity of the third gate conductive layer GML3 may be lower than the reflectivity of the fourth gate conductive layer GML4. The transmittance of the fourth gate conductive layer GML4 may be higher than the transmittance of the third gate conductive layer GML3.

[0273] In the display device 10 , the reflectivity of the gate conductive layer GML may be reduced by adjusting the thickness TH3 of the third gate conductive layer GML3 and the thickness TH4 of the fourth gate conductive layer GML4 .

[0274] For example, refer to Fig.15 , the third light L3 incident on the gate conductive layer GML may pass through the fourth gate conductive layer GML4 and may be partially absorbed by the third gate conductive layer GML3. The portion of the third light L3 not absorbed by the third gate conductive layer GML3 may be reflected by the third gate conductive layer GML3 to destructively interfere with the fourth light L4 incident later. The result may be the fifth light L5 whose energy is reduced or disappears. Therefore, the reflectivity of the gate conductive layer GML may be reduced.

[0275] In some embodiments, the thickness TH4 of the fourth gate conductive layer GML4 may be greater than the thickness TH3 of the third gate conductive layer GML3. For example, the thickness TH4 of the fourth gate conductive layer GML4 may be about 2 to about 30 times the thickness TH3 of the third gate conductive layer GML3.

[0276] In some embodiments, the thickness TH4 of the fourth gate conductive layer GML4 may be about 1000 Å. to about If the thickness TH4 of the fourth gate conductive layer GML4 is less than about If the thickness TH4 of the fourth gate conductive layer GML4 exceeds about Then, the process efficiency may be reduced, and the reliability of the conductive layer may be reduced due to the heat applied during the process of forming the conductive layer. For example, the thickness TH4 of the fourth gate conductive layer GML4 may be about to about

[0277] refer to Fig.13 and Fig.16 The anode conductive layer AML may include a first anode conductive layer AML1, a second anode conductive layer AML2, and a third anode conductive layer AML3.

[0278] The first anode conductive layer AML1 may be located on the via layer VIA. The second anode conductive layer AML2 may be located on the first anode conductive layer AML1. The third anode conductive layer AML3 may be located on the second anode conductive layer AML2.

[0279] The first anode conductive layer AML1 and the third anode conductive layer AML3 may include a material having a high work function and a high light transmittance. For example, the first anode conductive layer AML1 and the third anode conductive layer AML3 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In 2 O 3 ). For example, the first anode conductive layer AML1 and the third anode conductive layer AML3 may include, but are not limited to, indium tin oxide (ITO).

[0280] The second anode conductive layer AML2 may include a material having a high reflectivity. For example, the second anode conductive layer AML2 may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. For example, the second anode conductive layer AML2 may include, but is not limited to, silver (Ag).

[0281] In the display device 10, because the third gate conductive layer GML3 includes a material having low reflectivity, and because the fourth gate conductive layer GML4 includes a material having high transmittance, the gate conductive layer GML may have a lower reflectivity than the bottom conductive layer BML and the anode conductive layer AML. Therefore, light incident from the outside or light incident from the adjacent pixel SP may be reduced or prevented from being reflected from the gate conductive layer GML and the anode conductive layer AML into the active layer ACTL. Therefore, light-induced degradation may be reduced or minimized.

[0282] The display device 10 may include a wiring pad WPD in the pad area PDA. In some embodiments, the wiring pad WPD may include a first pad electrode PDE1 and a second pad electrode PDE2.

[0283] The first pad electrode PDE1 may be located in the bottom conductive layer BML. The first pad electrode PDE1 may include the same material as the bottom conductive layer BML of the display area DA. For example, the first pad electrode PDE1 may include a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0284] In some embodiments, the first pad electrode PDE1 may include a first sub pad SPD1 and a second sub pad SPD2.

[0285] The first sub pad SPD1 may be located in the first bottom conductive layer BML1. The first sub pad SPD1 may include the same material as the first bottom conductive layer BML1 of the display area DA. For example, the first sub pad SPD1 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. For example, the first sub pad SPD1 may include, but is not limited to, titanium (Ti).

[0286] The second sub-pad SPD2 may be located in the second bottom conductive layer BML2. The second sub-pad SPD2 may include the same material as the second bottom conductive layer BML2 of the display area DA. For example, the second sub-pad SPD2 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or an alloy thereof. For example, the second sub-pad SPD2 may include, but is not limited to, copper (Cu).

[0287] The second pad electrode PDE2 may be located in the gate conductive layer GML. The second pad electrode PDE2 may include the same material as the gate conductive layer GML of the display area DA. For example, the second pad electrode PDE2 may include a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. In some embodiments, the second pad electrode PDE2 may include aluminum zinc tin oxide (AZTO).

[0288] In some embodiments, the second pad electrode PDE2 may include a third sub-pad SPD3, a fourth sub-pad SPD4, a fifth sub-pad SPD5, and a sixth sub-pad SPD6.

[0289] The third sub-pad SPD3 may be located in the first gate conductive layer GML1. The third sub-pad SPD3 may include the same material as the first gate conductive layer GML1 of the display area DA. For example, the third sub-pad SPD3 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or an alloy thereof. For example, the third sub-pad SPD3 may include, but is not limited to, titanium (Ti).

[0290] The fourth sub-pad SPD4 may be located in the second gate conductive layer GML2. The fourth sub-pad SPD4 may include the same material as the second gate conductive layer GML2 of the display area DA. For example, the fourth sub-pad SPD4 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or an alloy thereof. For example, the fourth sub-pad SPD4 may include, but is not limited to, copper (Cu).

[0291] The fifth sub-pad SPD5 may be located in the third gate conductive layer GML3. The fifth sub-pad SPD5 may include the same material as the third gate conductive layer GML3 of the display area DA. For example, the fifth sub-pad SPD5 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or an alloy thereof. For example, the fifth sub-pad SPD5 may include, but is not limited to, titanium (Ti).

[0292] The sixth sub-pad SPD6 may be located in the fourth gate conductive layer GML4. The sixth sub-pad SPD6 may include the same material as the fourth gate conductive layer GML4 of the display area DA. For example, the sixth sub-pad SPD6 may include a transparent conductive oxide (TCO). For example, the sixth sub-pad SPD6 may include aluminum zinc tin oxide (AZTO).

[0293] Fig.17 is a cross-sectional view of an example of a conventional gate conductive layer GML. Fig.18 is a photograph showing precipitated particles PRC formed on a cross section of a conventional gate conductive layer GML.

[0294] Apart from Figures 13 to 16 In addition, reference Fig.17 and Fig.18 , the gate conductive layer GML may not include indium. The conventional gate conductive layer GML may include indium. For example, the fourth gate conductive layer GML4 of the conventional gate conductive layer GML may include indium tin oxide (ITO). The first gate conductive layer GML1, the second gate conductive layer GML2, and the third gate conductive layer GML3 of the conventional gate conductive layer GML may respectively include the same material as that of the gate conductive layer GML.

[0295] refer to Fig.17 and Fig.18 , in the conventional gate conductive layer GML, since the fourth gate conductive layer GML4 includes indium, precipitated particles PRC may be formed.

[0296] For example, if the third gate conductive layer GML3 includes titanium, the indium atoms of the fourth gate conductive layer GML4 may precipitate in the form of particles due to the difference in binding energy (e.g., Gibbs free energy) between titanium oxide and indium oxide. Because titanium oxide has a lower Gibbs free energy than indium oxide, it may have a higher binding energy than indium oxide. Therefore, the oxygen atoms of the indium tin oxide of the conventional fourth gate conductive layer GML4 move toward the titanium oxide due to the high temperature generated in the process of forming the passivation layer PV or the via layer VIA on the gate conductive layer GML. Therefore, precipitated particles PRC may be formed in the fourth gate conductive layer GML4.

[0297] refer to Fig.18 In the conventional display device 10, if the second gate conductive layer GML2 includes copper, if indium atoms are precipitated, the indium atoms and the copper atoms may be combined to generate an indium-copper alloy as precipitated particles PRC.

[0298] Since the gate conductive layer GML does not include indium, the formation of precipitated particles PRC including indium metal or indium copper alloy may be avoided. Therefore, the reliability of the gate conductive layer GML may be improved.

[0299] Hereinafter, the first and second comparative examples and the first example will be compared and described with reference to the following Table 1. The first and second comparative examples may be the above-described conventional gate conductive layer GML, and the first example may be the above-described gate conductive layer GML.

[0300] Table 1

[0301]

[0302]

[0303] Referring to Table 1, the gate conductive layer GML according to the first comparative example may include a stacked structure of Ti / Cu / ITO, the gate conductive layer GML according to the second comparative example may include a stacked structure of Ti / Cu / Ti / ITO, and the gate conductive layer GML according to the first example may include a stacked structure of Ti / Cu / Ti / AZTO. In the stacked structure of Ti / Cu / ITO, the stacked structure of Ti / Cu / Ti / ITO, and the stacked structure of Ti / Cu / Ti / AZTO, the order from left to right represents the order from the bottom layer to the top layer of the gate conductive layer GML.

[0304] Since the upper layer of the gate conductive layer GML according to the first comparative example does not include the Ti layer, a reduction in reflectivity may hardly occur regardless of the wavelength of light.

[0305] Because the upper layer of the gate conductive layer GML according to the second comparative example includes a Ti layer, the reflectivity of the gate conductive layer GML according to the second comparative example for light having wavelengths of 450nm and 650nm may be lower than the reflectivity of the gate conductive layer GML according to the first comparative example for light having wavelengths of 450nm and 650nm. However, the reflectivity of the gate conductive layer GML according to the second comparative example for light having a wavelength of 550nm may be higher than the reflectivity of the gate conductive layer GML according to the first comparative example for light having a wavelength of 550nm. In addition, because the upper layer of the gate conductive layer GML according to the second comparative example includes both a Ti layer and an ITO layer, precipitated particles PRC may be formed as described above.

[0306] On the other hand, the reflectivity of the gate conductive layer GML according to the first example to light of all wavelengths may be lower than that of the gate conductive layer GML according to the first comparative example and the second comparative example. Since the upper layer of the gate conductive layer GML according to the first example includes a Ti layer and an AZTO layer, the reflectivity of the gate conductive layer GML may be reduced. In addition, since the gate conductive layer GML according to the first example does not include indium atoms, precipitated particles PRC may not be formed, thereby improving the reliability of the gate conductive layer GML.

[0307] Hereinafter, other embodiments of the display device 10 will be described. In the following embodiments, the same elements as those of the above-described embodiments are denoted by the same reference numerals, and any redundant description thereof will be omitted or briefly given, and differences will be mainly described.

[0308] Fig.19is a cross-sectional view illustrating an example of a portion of a display area DA and a portion of a pad area PDA of the display device 10 according to one or more embodiments. Fig. 20 is a cross-sectional view illustrating a wiring pad WPD and a connection film 510 of a display device 10 according to one or more embodiments.

[0309] refer to Fig.19 and Fig. 20 , the display device 10 and the reference Fig.13 The display device 10 described above is different in that it does not include the sixth sub pad SPD6.

[0310] For example, in the display substrate 100_1 of the display device 10, the second pad electrode PDE2_1 of the wiring pad WPD may not include the sixth sub pad SPD6 (see Fig.13 ). For example, the uppermost layer of the second pad electrode PDE2_1 of the wiring pad WPD may be the fifth sub-pad SPD5.

[0311] The passivation layer PV positioned on the wiring pad WPD may include a through hole for exposing the wiring pad WPD. The fifth sub pad SPD5 may be exposed through the through hole of the passivation layer PV.

[0312] In some embodiments, the connection film 510 may include a base film 511 and a protrusion 512. The base film 511 may be a flexible circuit film such as a display driver 520 (see Figure 4 ) components may be mounted on the flexible circuit film. The protrusion 512 may be a conductive protrusion protruding from the base film 511 toward the wiring pad WPD. In the display device 10, the protrusion 512 of the connection film 510 may directly contact the fifth sub pad SPD5.

[0313] refer to Fig.13 The sixth sub-pad SPD6 of the display device 10 described in Fig.13 ) may include metal oxide. On the other hand, the fifth sub-pad SPD5 of the display device 10 may include metal. Therefore, the wiring pad WPD of the display device 10 may have a larger Fig.13 The display device 10 described in the above embodiments has good electrical characteristics. Therefore, the loss of signals and voltages received from or provided to the connection film 510 by the display substrate 100_1 can be reduced or minimized.

[0314] In the drawings, a case where the connection film 510 is connected to the wiring pad WPD is shown as an example. However, the present disclosure is not limited thereto. For example, even if reference is made to Figure 4 and Figure 5 The display driver 520 described in Figure 4 ) and / or circuit board 530 (see Figure 4) is connected to the wiring pad WPD, and the same technical spirit can also be applied. Figure 4 ) and circuit board 530 (see Figure 4 ) can be called a driving component.

[0315] Figure 21 to Figure 23 is a schematic perspective view of a device including a display device according to one or more embodiments.

[0316] Fig.21 A virtual reality (VR) device 1 to which a display device 10 according to one or more embodiments has been applied is shown. Fig. 22 A smart watch 2 to which the display device 10 according to one or more embodiments has been applied is shown. Fig.23 A display unit of a vehicle to which the display devices 10 — a to 10 — e according to one or more embodiments have been applied is shown.

[0317] refer to Fig.21 According to one or more embodiments, the VR device 1 may be a device in the form of glasses. The VR device 1 may include a display device 10, a left lens 10a, a right lens 10b, a support frame 20, glasses frame legs 30a and 30b, a reflective member 40, and a display device housing 50.

[0318] In the drawings, a VR device 1 including glasses frame legs 30a and 30b is shown as an example. However, the VR device 1 may also be applied to a head mounted display including a head mounted band that can be worn on the head instead of the glasses frame legs 30a and 30b. The VR device 1 is not limited to the structure shown, and may be applied to various other electronic devices in various forms.

[0319] The display device housing 50 may include a display device 10 and a reflective member 40. The image displayed on the display device 10 may be reflected by the reflective member 40 and may be provided to the right eye of the user through the right lens 10b. Therefore, the user may view the VR image displayed on the display device 10 through the right eye.

[0320] The display device housing 50 may be located at the right end of the support frame 20. However, the present disclosure is not limited thereto. For example, the display device housing 50 may also be located at the left end of the support frame 20. In this case, the image displayed on the display device 10 may be reflected by the reflective member 40 and may be provided to the user's left eye through the left lens 10a. Therefore, the user may view the VR image displayed on the display device 10 through the left eye. Alternatively, the display device housing 50 may be located at both the right end and the left end of the support frame 20. In this case, the user may view the VR image displayed on the display device 10 through both the left eye and the right eye.

[0321] refer to Fig. 22 The display device 10 according to one or more embodiments may be applied to a smart watch 2 which is one of smart devices.

[0322] refer to Fig.23 The display devices 10_a, 10_b, and 10_c according to one or more embodiments may be applied to a dashboard of a vehicle, a central dashboard of a vehicle, or a central information display (CID) located on a dashboard of a vehicle. In addition, the display devices 10_d and 10_e according to one or more embodiments may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0323] Fig.24 and Fig.25 is a schematic perspective view of a transparent display device including the display device 10 according to one or more embodiments.

[0324] refer to Fig.24 and Fig.25 , the display device 10 can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM. A user located in front of the transparent display device can not only view the image IM displayed on the display device 10, but also view an object RS or a background located behind the transparent display device.

[0325] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the aspects of the present disclosure. Therefore, the disclosed embodiments are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A display device, comprising: substrate; a first conductive layer over the substrate; an active layer, above the first conductive layer; a second conductive layer, over the active layer, and comprising a transparent conductive oxide but not indium; a third conductive layer, above the second conductive layer; a transistor including a gate electrode at the second conductive layer and a drain electrode and a source electrode at the active layer; as well as A light emitting element includes a first electrode at the third conductive layer and connected to the source electrode.

2. The display device according to claim 1, wherein: The second conductive layer includes aluminum zinc tin oxide.

3. The display device according to claim 1, wherein: The second conductive layer includes a first gate conductive layer and a second gate conductive layer, the second gate conductive layer being above the first gate conductive layer and having a higher light transmittance than the first gate conductive layer.

4. The display device according to claim 3, wherein: The second gate conductive layer includes aluminum zinc tin oxide.

5. The display device according to claim 4, wherein: The second gate conductive layer includes 1 at % to 10 at % of aluminum based on atoms excluding oxygen atoms.

6. The display device according to claim 4, wherein: The second gate conductive layer includes 60 at % to 90 at % of zinc based on atoms excluding oxygen atoms.

7. The display device according to claim 4, wherein: The second gate conductive layer includes 10 at % to 30 at % of tin based on atoms excluding oxygen atoms.

8. The display device according to claim 4, wherein: The second gate conductive layer includes 0.5 at % to 5 at % of aluminum based on total atoms.

9. The display device according to claim 4, wherein: The second gate conductive layer includes 20 at % to 40 at % of zinc based on total atoms.

10. The display device according to claim 4, wherein: The second gate conductive layer includes 7 at % to 15 at % of tin based on total atoms.

11. The display device according to claim 4, wherein: The second gate conductive layer includes 50 at % to 60 at % of oxygen based on total atoms.

12. The display device according to claim 3, wherein: The first gate conductive layer has a lower reflectivity than the second gate conductive layer.

13. The display device according to claim 12, wherein: The first gate conductive layer includes titanium.

14. The display device according to claim 3, wherein: The thickness of the second gate conductive layer is greater than the thickness of the first gate conductive layer.

15. The display device according to claim 14, wherein: The thickness of the second gate conductive layer is 2 to 30 times the thickness of the first gate conductive layer.

16. The display device according to claim 15, wherein: The thickness of the second gate conductive layer is to 17. The display device according to claim 15, wherein: The thickness of the first gate conductive layer is to 18. The display device according to claim 1, wherein: The third conductive layer includes a transparent conductive oxide different from the transparent conductive oxide of the second conductive layer.

19. The display device according to claim 1, wherein: The second conductive layer has a lower reflectivity than the first conductive layer or the third conductive layer.

20. A display device, comprising: substrate; a first conductive layer over the substrate; an active layer, above the first conductive layer; A second conductive layer, above the active layer, and comprising: A first gate conductive layer including a first material including a metal; a second gate conductive layer, over the first gate conductive layer, and comprising a second material including a metal; a third gate conductive layer over the second gate conductive layer and including a third material including metal; and a fourth gate conductive layer, above the third gate conductive layer, and comprising aluminum zinc tin oxide; a transistor, over the first conductive layer; and A light emitting element is above the second conductive layer and connected to the transistor.

21. The display device according to claim 20, wherein: The first material, the second material and the third material include molybdenum, aluminum, chromium, gold, titanium, nickel, neodymium, copper or alloys thereof.

22. The display device according to claim 21, wherein: The first material includes titanium.

23. The display device according to claim 21, wherein: The second material includes copper.

24. The display device according to claim 21, wherein: The third material includes titanium.

25. The display device according to claim 20, wherein: The thickness of the fourth gate conductive layer is greater than the thickness of the third gate conductive layer.

26. The display device according to claim 20, wherein: The thickness of the second gate conductive layer is greater than the thickness of the fourth gate conductive layer.

27. A display device comprising: A substrate comprising a display area and a pad area at one side of the display area; a first conductive layer over the substrate; an active layer, above the first conductive layer; a second conductive layer, located above the active layer in the display region and including a transparent conductive oxide but not including indium; a transistor in the display region over the first conductive layer; a light emitting element, above the second conductive layer in the display region and connected to the transistor; as well as A wiring pad is over the substrate in the pad region and includes a first pad electrode at the first conductive layer and a second pad electrode at the second conductive layer.

28. The display device according to claim 27, wherein: The second pad electrode does not include a transparent conductive oxide.

29. The display device according to claim 27, further comprising a driving component connected to the wiring pad, in, The second pad electrode includes a sub-pad including metal that directly contacts the driving component.

Images