Array substrate, display panel and display device

Abstract

The invention relates to an array substrate, a display panel and a display device, and the array substrate comprises a substrate, and an active layer, an insulating layer and a grid layer which are sequentially stacked on the substrate, and is used for forming a thin film transistor in a pixel circuit of the display panel. An active layer comprises a channel region and a shielding structure, the channel region and the shielding structure are arranged at an interval, the orthographic projection of the channel region on a substrate falls into the orthographic projection of a gate layer on the substrate, at least part of the orthographic projection of the shielding structure on the substrate falls into the orthographic projection of the gate layer on the substrate, and the shielding structure is used for shielding the polarization effect of the gate layer on the substrate. Under the combined action of the channel region and the shielding structure, the polarization effect of the gate layer on the substrate located below the gate layer is basically completely shielded, so that the substrate located below the gate layer cannot be polarized by the gate layer, and the substrate located below the gate layer cannot influence the current flowing through the thin film transistor; therefore, the ghosting problem in the working process of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display devices have the advantages of self-luminescence, low power consumption, wide viewing angle, and fast response speed, and are regarded as potential display devices with broad application prospects in various fields.

[0003] However, in the related art, the display device may have an afterimage problem during actual operation. Summary of the invention

[0004] Based on this, it is necessary to provide an array substrate, a display panel and a display device that can improve the afterimage in order to solve the above technical problems.

[0005] In a first aspect, the present application provides an array substrate, comprising:

[0006] substrate;

[0007] An active layer, located on one side of the substrate; wherein the active layer includes a channel region and a shielding structure, and the channel region and the shielding structure are spaced apart;

[0008] An insulating layer, located on a side of the active layer away from the substrate;

[0009] A gate layer is located on a side of the insulating layer away from the active layer; wherein the orthographic projection of the channel region on the substrate falls within the orthographic projection of the gate layer on the substrate, the orthographic projection of the shielding structure on the substrate at least partially falls within the orthographic projection of the gate layer on the substrate, and the shielding structure is used to shield the polarization effect of the gate layer on the substrate.

[0010] In one embodiment, the material of the shielding structure includes a conductor material or a semiconductor material.

[0011] In one embodiment, the material of the shielding structure is the same as the material of the channel region.

[0012] In one embodiment, the material of the shielding structure includes low temperature polysilicon or indium gallium zinc oxide.

[0013] In one of the embodiments, an area of ​​an orthographic projection of the shielding structure on the substrate is smaller than an area of ​​an orthographic projection of the channel region on the substrate.

[0014] In one of the embodiments, the channel region is U-shaped, and the shielding structure is at least partially located inside an opening of the U-shape.

[0015] In one embodiment, the shape of the channel region is S-shaped or Z-shaped, and the shielding structure is at least partially located in a bending area of ​​the S-shape or the Z-shape.

[0016] In one of the embodiments, along a direction parallel to the plane where the substrate is located, a distance between the shielding structure and the channel region is greater than or equal to 1 um.

[0017] In one of the embodiments, the shielding structure has an orthographic projection on the substrate in the shape of a circle, an ellipse or a polygon.

[0018] In one embodiment, the substrate is a flexible substrate.

[0019] In one embodiment, the substrate includes a polyimide film layer, an organic film layer and an inorganic film layer which are stacked.

[0020] In a second aspect, the present application further provides a display panel, comprising an array substrate as provided in any of the above embodiments.

[0021] In a third aspect, the present application further provides a display device, comprising a display panel as provided in the above embodiment.

[0022] The array substrate, display panel and display device described above, wherein the array substrate includes a substrate and an active layer, an insulating layer and a gate layer stacked in sequence on the substrate, and the active layer, the insulating layer and the gate layer can be used to form a thin film transistor (TFT) in a pixel circuit of the display panel. The active layer includes a channel region and a shielding structure, the channel region and the shielding structure are arranged at intervals, the orthographic projection of the channel region on the substrate falls within the orthographic projection of the gate layer on the substrate, the orthographic projection of the shielding structure on the substrate at least partially falls within the orthographic projection of the gate layer on the substrate, and the shielding structure is used to shield the polarization effect of the gate layer on the substrate, so that under the joint action of the channel region and the shielding structure, the polarization effect of the gate layer on the substrate below the gate layer is basically completely shielded, so that the substrate below the gate layer will not be polarized by the gate layer, and therefore the substrate below the gate layer will not affect the current flowing through the thin film transistor. If the thin film transistor is a driving thin film transistor in a pixel circuit of a display panel, the substrate located below the gate layer of the driving thin film transistor will not affect the driving current flowing through the driving thin film transistor, thereby improving the afterimage problem during operation of the display panel, and further improving the afterimage problem during operation of the display device including the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 is a cross-sectional schematic diagram of a thin film transistor in one embodiment;

[0025] Figure 2 is a schematic diagram of an active layer of each thin film transistor in a pixel circuit on a substrate in one embodiment;

[0026] Figure 3 for Figure 2 A partial enlarged view of

[0027] Figure 4A is a schematic top view of a shielding structure in one embodiment;

[0028] Figure 4B is one of the top view schematic diagrams of the positional relationship between the shielding structure and the channel region in one embodiment;

[0029] Figure 4C FIG2 is a second schematic top view of the positional relationship between the shielding structure and the channel region in one embodiment;

[0030] Figure 5 One of the schematic diagrams of the shape of the shielding structure in one embodiment;

[0031] Figure 6 The second schematic diagram of the shape of the shielding structure in one embodiment;

[0032] Figure 7 The third schematic diagram of the shape of the shielding structure in one embodiment;

[0033] Figure 8 FIG. 4 is a schematic cross-sectional view of a substrate in one embodiment.

[0034] Explanation of the reference numerals: substrate 110, active layer 120, insulating layer 130, gate layer 140; source region 121, drain region 122, channel region 123, shielding structure 124; polyimide film layer (PI1) 111, inorganic film layer (BL1) 112, organic film layer (A-si) 113, polyimide film layer (PI2) 114, inorganic film layer (BL2) 115, inorganic film layer (SiN) 116 and inorganic film layer (SiO) 117. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] Typically, an OLED display device includes an OLED display panel, the OLED display panel includes a pixel light-emitting unit and an array substrate, the array substrate includes a substrate and a pixel circuit disposed on the substrate, and the pixel circuit is used to control the pixel light-emitting unit. The pixel circuit includes a plurality of thin film transistors, and the thin film transistor includes an active layer, a gate layer, a source layer, and a drain layer; wherein the active layer includes a source region and a drain region, the source region and the drain region are respectively used to be electrically connected to the source layer and the drain layer, and in the process of establishing a current in the thin film transistor, the active layer also includes a channel region located below the gate layer and between the source region and the drain region. In addition, the thin film transistors in the pixel circuit can be divided into: a switching thin film transistor that acts as a switch and a driving thin film transistor for driving the pixel light-emitting unit according to their functions; wherein the driving thin film transistor provides a driving current for the pixel light-emitting unit to drive the pixel light-emitting unit to emit light.

[0037] As mentioned in the background technology, the display device will have a residual image problem during the actual operation process. The inventor has found that the reason is that as the display device works for a long time, the thin film transistor in the array substrate of the display device, the substrate corresponding to the area outside the channel area and below the gate layer (hereinafter referred to as the non-channel area) will be polarized by the gate layer, and the polarized substrate will self-build an electric field inside. The self-built electric field will affect the current flowing through the thin film transistor, such as increasing or decreasing the current, thereby affecting the display effect of the display device, such as causing the display device to have a residual image problem; furthermore, under normal circumstances, the size of the driving thin film transistor in the pixel circuit will be larger than the size of the switching thin film transistor, so the polarization of the gate layer in the driving thin film transistor to the substrate corresponding to the non-channel area will be more obvious in the pixel circuit, and the current provided by the driving thin film transistor in the pixel circuit is also the driving current, and the driving current will be significantly affected, causing the display device to have a significant residual image problem. It should be noted that the polarization of the substrate by the gate layer is essentially that the voltage applied to the gate layer will affect the substrate, that is, the substrate will be polarized.

[0038] To address this, an embodiment of the present application provides an array substrate to improve the image sticking problem of an OLED display device.

[0039] In an exemplary embodiment, referring to Figure 1 , an array substrate is provided, which includes a substrate 110, an active layer 120, an insulating layer 130 and a gate layer 140.

[0040] The substrate 110 can provide support for the film layers and devices such as the active layer 120, the insulating layer 130 and the gate layer 140 that are subsequently arranged. The substrate 110 can be a single-layer structure or a multi-layer structure. The substrate 110 can be a hard substrate, and the material of the hard substrate can be glass, quartz, etc. The substrate 110 can be a flexible substrate, and the material of the flexible substrate can include an organic polymer material, and the organic polymer material includes at least one of polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate and polyethersulfone.

[0041] The active layer 120 is located on one side of the substrate 110, and the active layer 120 includes a channel region 123 and a shielding structure 124. The channel region 123 is the channel region 123 of the thin film transistor. The shielding structure 124 is spaced apart from the channel region 123 so that the channel region 123 is insulated from the shielding structure 124, and the space between the shielding structure 124 and the channel region 123 may be filled with an insulating material, such as silicon oxide. In addition, the active layer 120 may also include a source region and a drain region located on both sides of the channel region 123, and the source region and the drain region are respectively used to be electrically connected to the source layer and the drain layer. The materials of the channel region 123, the source region, and the drain region may all be semiconductors.

[0042] The insulating layer 130 is located on a side of the active layer 120 away from the substrate 110 . The material of the insulating layer 130 may be, but is not limited to, silicon oxide (SiO).

[0043] The gate layer 140 is located on a side of the insulating layer 130 away from the active layer 120. The gate layer 140 is the gate layer 140 of a thin film transistor, and the material of the gate layer 140 may be a metal material. The orthographic projection of the channel region 123 on the substrate 110 falls within the orthographic projection of the gate layer 140 on the substrate 110. The orthographic projection of the shielding structure 124 on the substrate 110 at least partially falls within the orthographic projection of the gate layer 140 on the substrate 110, that is, at least part of the shielding structure 124 is located in the non-channel area, and the shielding structure 124 is used to shield the polarization effect of the gate layer 140 on the substrate 110.

[0044] Figure 2 FIG. 1 schematically shows the active layer of each thin film transistor in a pixel circuit on a substrate. Figure 3 yes Figure 2 A local enlarged view of the driving thin film transistor is used as an example to illustrate the Figure 2 and Figure 3 , the mark M indicates the area where the driving thin film transistor is located, the mark G indicates the positive projection area of ​​the gate layer 140 of the driving thin film transistor on the substrate 110, and the marks 121 and 122 respectively indicate the source region and the drain region of the driving thin film transistor.

[0045] The orthographic projection of the channel region 123 of the driving thin film transistor on the substrate 110 falls within the orthographic projection of the gate layer 140 on the substrate 110, and the orthographic projection of the shielding structure 124 corresponding to the driving thin film transistor on the substrate 110 at least partially falls within the orthographic projection of the gate layer 140 on the substrate 110. In this way, since the material of the channel region 123 is a semiconductor, the polarization effect of the gate layer 140 on the substrate 110 located below the gate layer 140 and covered by the channel region 123 is shielded by the channel region 123, and due to the existence of the shielding structure 124, the polarization effect of the gate layer 140 on the substrate 110 corresponding to the non-channel region is shielded by the shielding structure 124 (the non-channel region is the region outside the channel region 123 and located below the gate layer 140, refer to Figure 3 , that is, the area within region G excluding the channel region 123), that is, under the joint action of the channel region 123 and the shielding structure 124, the polarization effect of the gate layer 140 on the substrate 110 located below the gate layer 140 is basically completely shielded, so that the substrate 110 located below the gate layer 140 will not be polarized by the gate layer 140, and therefore the substrate 110 located below the gate layer 140 will not affect the driving current provided by the driving thin film transistor, thereby improving the afterimage problem during the operation of the display panel, and further improving the afterimage problem of the display device including the display panel during the operation.

[0046] In this application embodiment, refer to Figure 3 A shielding structure 124 can be set in any area within the entire non-channel region of the thin film transistor to ensure that the shielding structure 124 is insulated from the channel region 123. The shielding structure 124 can even extend from the non-channel region to the area located outside the non-channel region to ensure that the shielding structure 124 can shield the polarization effect of the voltage applied to the gate layer 140 on the substrate 110.

[0047] In an exemplary embodiment, when the active layer 120 includes multiple sub-membrane layers, the channel region 123 and the shielding structure 124 can be located in different sub-membrane layers or in the same sub-membrane layer. When the active layer 120 is a single-layer structure, the channel region 123 and the shielding structure 124 are located in the same film layer. This embodiment does not specifically limit this.

[0048] In an exemplary embodiment, the material of the shielding structure 124 includes a conductor material or a semiconductor material, so that the polarization effect of the voltage applied to the gate layer 140 on the substrate 110 can be shielded.

[0049] In an exemplary embodiment, the material of the shielding structure 124 is the same as that of the channel region 123 , so as to simplify the manufacturing process of the array substrate and reduce the cost of the array substrate.

[0050] In an exemplary embodiment, the material of the shielding structure 124 includes Low Temperature Poly Silicon (LTPS) or Indium Gallium Zinc Oxide (IGZO).

[0051] In an exemplary embodiment, referring to Figure 4A , the area of ​​the orthographic projection of the shielding structure 124 on the substrate 110 is smaller than the area of ​​the orthographic projection of the channel region 123 on the substrate 110. It can be understood that, considering that most of the substrate 110 below the gate layer 140 has been covered by the channel region 123, and the polarization effect of the gate layer 140 on the substrate 110 located below the gate layer 140 and covered by the channel region 123 is shielded by the channel region 123, the shielding structure 124 only needs to shield the polarization effect of the gate layer 140 on the substrate 110 corresponding to the non-channel region. At this time, the shielding structure 124 is only located in the non-channel region to achieve the effect. In this way, the area of ​​the orthographic projection of the shielding structure 124 on the substrate 110 is smaller than the area of ​​the orthographic projection of the channel region 123 on the substrate 110. Not only can the shielding structure 124 shield the polarization effect of the gate layer 140 on the substrate 110 corresponding to the non-channel region, but the shielding structure 124 is relatively small and consumes less material, saving costs.

[0052] In an exemplary embodiment, continue to refer to Figure 4A The channel region 123 is U-shaped, and the shielding structure 124 is at least partially located inside the U-shaped opening. In this way, the shielding structure 124 is not only sufficient to shield the polarization effect of the gate layer 140 on the substrate 110 corresponding to the non-channel region, but also the shielding structure 124 is located as much as possible in the area where the thin film transistor is located, thereby saving the layout area.

[0053] In an exemplary embodiment, the shape of the channel region 123 may also be S-shaped (see Figure 4B ) or Z-shaped (refer to Figure 4C ), the shielding structure 124 is at least partially located in the bending area of ​​the S-shape or the Z-shape, so that the shielding structure 124 is not only sufficient to shield the polarization effect of the gate layer 140 on the substrate 110 corresponding to the non-channel area, but also the shielding structure 124 is located as much as possible in the area where the thin film transistor is located, thereby saving the layout area.

[0054] In an exemplary embodiment, along a direction parallel to the plane of the substrate 110 , the spacing between the shielding structure 124 and the channel region 123 is greater than or equal to 1 um, which helps to ensure the insulation between the shielding structure 124 and the channel region 123 and avoid the setting of the shielding structure 124 bringing adverse effects on the channel region 123.

[0055] In the embodiment of the present application, the shape, thickness, etc. of the shielding structure 124 are arbitrary and can be adaptively set according to the actual layout structure of the thin film transistor and the required shielding capability, and no specific restrictions are imposed on this.

[0056] In an exemplary embodiment, referring to Figure 5 The shape of the orthographic projection of the shielding structure 124 on the substrate 110 is circular, thus simplifying the shape of the shielding structure 124 and making the shielding structure 124 easy to manufacture.

[0057] In an exemplary embodiment, referring to Figure 6 The shape of the orthographic projection of the shielding structure 124 on the substrate 110 is an ellipse, which not only makes the shielding structure 124 easy to manufacture, but also helps to ensure that the shielding structure 124 has a sufficient size to have the required shielding capability.

[0058] In an exemplary embodiment, referring to Figure 7 The shape of the orthographic projection of the shielding structure 124 on the substrate 110 is a polygon, which helps to ensure that the shielding capability of the shielding structure 124 matches actual requirements.

[0059] In an exemplary embodiment, referring to Figure 8 , the substrate 110 includes stacked polyimide film layers 111 and 114, an organic film layer 113, and inorganic film layers 112, 115, 116, and 117. Among them, the polyimide film layer (PI1) 111, the inorganic film layer (BL1) 112, the organic film layer (A-si) 113, the polyimide film layer (PI2) 114, the inorganic film layer (BL2) 115, the inorganic film layer 116, and the inorganic film layer 117 are stacked in sequence; the materials of BL1 and BL2 can be silicon oxide (SiO); the materials of the inorganic film layer 116 and the inorganic film layer 117 can be silicon nitride (SiN) and silicon oxide (SiO), respectively.

[0060] It can be understood that, when the substrate 110 is a flexible substrate 110, since the material of the flexible substrate 110 includes an organic polymer material, the polarization of the flexible substrate 110 is more obvious than the polarization of the rigid substrate 110. In view of this, by adopting the technical solution of the embodiment of the present application and setting the shielding structure 124, the polarization problem of the gate layer 140 to the flexible substrate 110 below the gate layer 140 can be significantly improved, thereby achieving the effect of eliminating the afterimage of the display panel.

[0061] In an exemplary embodiment, a display panel is provided, and the display panel includes the array substrate provided by any of the above embodiments.

[0062] The display panel and array substrate provided in this embodiment belong to the same inventive concept, can solve the same technical problem, and thus achieve the same technical effect, and the repeated contents will not be repeated here.

[0063] In an exemplary embodiment, a display device is provided. The display device includes the display panel provided in the above embodiment.

[0064] The display device and the display panel provided in this embodiment belong to the same inventive concept, can solve the same technical problem, and thus achieve the same technical effect, and the repeated contents will not be repeated here.

[0065] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0066] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. An array substrate, characterized in that: include: substrate; An active layer, located on one side of the substrate; wherein the active layer includes a channel region and a shielding structure, and the channel region and the shielding structure are spaced apart; an insulating layer, located on a side of the active layer away from the substrate; The gate layer is located on a side of the insulating layer away from the active layer; wherein the orthographic projection of the channel region on the substrate falls within the orthographic projection of the gate layer on the substrate, and the orthographic projection of the shielding structure on the substrate at least partially falls within the orthographic projection of the gate layer on the substrate.

2. The array substrate according to claim 1, characterized in that: The material of the shielding structure includes a conductor material or a semiconductor material.

3. The array substrate according to claim 2, characterized in that: The material of the shielding structure is the same as the material of the channel region; Optionally, the material of the shielding structure includes low temperature polysilicon or indium gallium zinc oxide.

4. The array substrate according to claim 1, characterized in that: An area of ​​an orthographic projection of the shielding structure on the substrate is smaller than an area of ​​an orthographic projection of the channel region on the substrate.

5. The array substrate according to claim 4, characterized in that: The channel region is in a U-shape, and the shielding structure is at least partially located inside an opening of the U-shape; Alternatively, the channel region is in an S-shape or a Z-shape, and the shielding structure is at least partially located in a bending region of the S-shape or the Z-shape.

6. The array substrate according to any one of claims 1 to 5, characterized in that: Along a direction parallel to the plane where the substrate is located, a distance between the shielding structure and the channel region is greater than or equal to 1 um.

7. The array substrate according to any one of claims 1 to 5, characterized in that: The shielding structure has an orthographic projection on the substrate in the shape of a circle, an ellipse or a polygon.

8. The array substrate according to any one of claims 1 to 5, characterized in that: The substrate is a flexible substrate; Optionally, the substrate includes a polyimide film layer, an organic film layer and an inorganic film layer which are stacked.

9. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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