Four-terminal all-silicon-based multi-junction solar cell and preparation method thereof
By designing a four-end all-silicon-based multi-junction structure in solar cells and setting all electrodes on the back, the light-shading damage and stability problems caused by electrode distribution in existing stacked batteries are solved, and higher battery performance and yield rates are achieved.
Patent Information
- Application Number
- CN202510386670.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2045-03-31
AI Technical Summary
Due to the limitations of structural design of existing stacked solar cells, the electrodes are distributed on the front and back, resulting in light shading damage and poor battery stability, affecting performance improvement and yield.
It adopts a four-end all-silicon-based multi-junction solar cell design, and all electrodes are located on the back of the battery, avoiding frontal shading damage and improving the stability of the battery through a full-silicon-based structure.
It effectively reduces the damage to the front of the battery, improves the battery performance and yield rate, and at the same time, due to the perovskite-free battery, the overall stability of the battery is better.
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Figure CN119922989A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of solar cells, and in particular to a four-terminal all-silicon-based multi-junction solar cell and a preparation method thereof. Background Art
[0002] Tandem cells are a type of multi-junction solar cell newly developed in recent years. At present, this type of cell is composed of a stack of perovskite cells and crystalline silicon cells. For example, patent CN118414005A discloses a perovskite-crystalline silicon tandem cell. It has a perovskite cell on the top and a crystalline silicon cell on the bottom. Compared with other solar cells, tandem cells have higher conversion efficiency, so they have become more popular in recent years. However, tandem cells composed of perovskite cells and crystalline silicon cells also have some disadvantages.
[0003] First, due to the limitations of structural design, current stacked cells usually have electrodes on both the front and back of the cell. On the one hand, having a negative electrode on the front will not only reduce light shading damage, but also limit the further improvement of battery performance; on the other hand, when individual cells are assembled in series into a battery module, they must be connected in a Z-shaped series connection that alternates up and down. In this connection method, the connecting wires will be interspersed between adjacent silicon wafers. The connection wires and the edges of the silicon wafers will alternate up and down, which will cause greater stress on the silicon wafers, making them prone to damage and resulting in a low yield rate.
[0004] Secondly, compared with crystalline silicon cells, perovskite cells have poor stability, which makes the overall reliability of the battery face huge challenges. Summary of the invention
[0005] In order to solve the above technical problems, the present invention provides a four-terminal all-silicon-based multi-junction solar cell and a preparation method. First, in the four-terminal all-silicon-based multi-junction solar cell of the present invention, all electrodes are located on the back, which can not only effectively reduce shading damage, but also help improve battery performance. After a single battery is connected in series as a battery assembly, it can avoid damage caused by connecting wires passing through the gaps between adjacent batteries, thereby improving the yield rate. Secondly, the multi-junction solar cell of the present invention is an all-silicon-based battery and does not contain a perovskite battery, so the overall stability of the battery is better.
[0006] The specific technical scheme of the present invention is: In a first aspect, the present invention provides a four-terminal all-silicon-based multi-junction solar cell, comprising: An N-type silicon substrate, a pyramid velvet surface and a passivation film sequentially arranged on the front side of the N-type silicon substrate, and a positive electrode region A, a negative electrode region A, a positive electrode region B and a negative electrode region B arranged alternately on the back side of the N-type silicon substrate; The positive electrode region A comprises an inner boron diffusion layer, a phosphorus diffusion layer, an outer boron diffusion layer and a passivation film which are sequentially arranged on the back of the N-type silicon substrate, and a positive electrode which is arranged on the surface of the outer boron diffusion layer and penetrates the passivation film; The negative electrode region A is adjacent to the positive electrode region A, and includes an inner boron diffusion layer, a phosphorus diffusion layer and a passivation film sequentially arranged on the back of the N-type silicon substrate, and a negative electrode arranged on the surface of the phosphorus diffusion layer and penetrating the passivation film; The positive electrode region B is adjacent to the negative electrode region A, and includes an inner boron diffusion layer and a passivation film sequentially arranged on the back of the N-type silicon substrate, and an anode arranged on the surface of the inner boron diffusion layer and penetrating the passivation film; The cathode region B is adjacent to the anode region B, and includes a passivation film disposed on the back of the N-type silicon substrate, and a cathode disposed on the back of the N-type silicon substrate and penetrating the passivation film.
[0007] The above-mentioned four-terminal all-silicon-based multi-junction solar cell of the present invention is characterized in that: (1) Through structural optimization, all electrodes are placed on the back of the battery. This design can effectively reduce the damage caused by shading on the front of the battery, which is beneficial to improving battery performance. On the other hand, when connecting single batteries in series to form a battery module, it can avoid damage caused by connecting wires passing through the gaps between adjacent batteries, thereby improving the yield rate.
[0008] (2) The multi-junction solar cell of the present invention is a fully silicon-based cell and does not contain a perovskite cell, thus avoiding the problem of poor overall cell stability caused by the perovskite cell.
[0009] (3) Due to the presence of two positive and negative electrodes, the four-terminal stacked battery has more efficient internal carrier transport and extraction than the two-terminal type, and can eliminate the current matching problem of each part, and the corresponding battery process window is wider.
[0010] Preferably, in terms of thickness, the positive electrode region B>the negative electrode region A>the positive electrode region A.
[0011] The present invention limits the thickness relationship of the above-mentioned regions to the above-mentioned order, which is conducive to further improving the battery performance: since the boron diffusion layer is a hole (positive charge), compared with the phosphorus diffusion layer, which is an electron (negative charge), the conductivity of holes is not as good as that of electrons, and in the subsequent slurry sintering process, the phosphorus diffusion layer is more likely to react with the slurry (more likely to gain or lose electrons) to form an Ag-Si alloy ohmic contact. In addition, the doping concentration of the inner boron diffusion layer (positive electrode region B) is less than the doping concentration of the phosphorus diffusion layer (negative electrode region A) and the doping concentration of the outer boron diffusion layer (positive electrode region A). The diffusion layer with a higher doping concentration has more free mobile carriers inside, making it more conductive. In order to balance the carrier transport and extraction performance between different diffusion layers, the thickness of the inner boron diffusion layer (positive electrode region B) needs to be larger, while the thickness of the phosphorus diffusion layer (negative electrode region A) needs to be smaller. In addition, since the outer boron diffusion layer is located at the outermost surface of the battery, its carrier transmission distance is shorter than the carrier transmission distance from the inner boron diffusion layer and the phosphorus diffusion layer to the electrode. Therefore, the thickness of the outer boron diffusion layer (positive electrode region A) can be the thinnest, so that the thickness of each layer is positive electrode region B>negative electrode region A>positive electrode region A.
[0012] Preferably, in terms of width, the negative electrode region B>the positive electrode region B>the negative electrode region A>the positive electrode region A.
[0013] Regarding the width of each layer, since the doping concentration of the N-type silicon substrate (negative electrode region B) is less than the doping concentration of the inner boron diffusion layer (positive electrode region B) and less than the doping concentration of the phosphorus diffusion layer (negative electrode region A) and less than the doping concentration of the outer boron diffusion layer (positive electrode region A), the number of free mobile carriers in each layer actually also shows the above-mentioned difference. In order to match the current collection performance of each doping layer (in the subsequent screen printing process), the initial width is negative electrode region B>positive electrode region B>negative electrode region A>positive electrode region A.
[0014] Preferably, the boron concentration in the inner boron diffusion layer is lower than the phosphorus concentration in the phosphorus diffusion layer, and the phosphorus concentration in the phosphorus diffusion layer is lower than the boron concentration in the outer boron diffusion layer.
[0015] In a second aspect, the present invention provides a method for preparing the above-mentioned four-terminal all-silicon-based multi-junction solar cell, which comprises the following steps: S1, N-type silicon substrate double-sided polishing.
[0016] S2. Perform a first boron diffusion on the back side to sequentially form an inner boron diffusion layer and a BSG layer on the back side of the N-type silicon substrate.
[0017] After the first boron diffusion, the back surface of the silicon substrate is transformed from N-type to P-type inner boron diffusion layer. Since the present invention needs to further perform phosphorus doping (S5 phosphorus diffusion) and secondary boron doping (S8 secondary boron diffusion) on the inner boron diffusion layer in subsequent steps, a part of the surface layer of the inner boron diffusion layer is transformed into a phosphorus diffusion layer and an outer boron diffusion layer with a higher concentration; therefore, the surface boron atom doping concentration during the S2 first boron diffusion needs to be relatively low (but higher than the phosphorus atom doping amount of the N-type silicon substrate itself, 1E15~1E16cm -3 ), and the doping depth needs to be deeper.
[0018] S3. Remove the BSG layer of the negative electrode region A and the positive electrode region A on the back side.
[0019] After S3 treatment, there is a BSG layer on the surface of the negative electrode region B and the positive electrode region B on the back of the N-type silicon substrate, which can block the diffusion of atoms into the inner boron diffusion layer during subsequent diffusion. After the BSG layer on the surface of the positive electrode region A and the negative electrode region A is removed, it is conducive to the subsequent diffusion process. The diffusion of atoms into the inner boron diffusion layer.
[0020] S4, alkaline cleaning: Alkaline cleaning can further remove the BSG layer that has not been completely removed from the surface of the positive electrode region A and the negative electrode region A in S3.
[0021] S5. Back side phosphorus diffusion to convert the surface layer of the exposed inner boron diffusion layer into a phosphorus diffusion layer and a PSG layer.
[0022] In this phosphorus diffusion process, the phosphorus atom doping concentration is controlled to be higher than the boron atom concentration of the first boron diffusion, and the doping depth is shallower than the first boron diffusion, so that the surface layer of the inner boron diffusion layer can be transformed into a phosphorus diffusion layer. In addition, after the first boron diffusion of S2, a wrap-around layer (boron diffusion layer and BSG layer) will be formed on the front of the N-type silicon substrate, which can prevent the diffused atoms from penetrating into the front of the N-type silicon substrate during this phosphorus diffusion.
[0023] S6. Remove the PSG layer in the positive electrode region A.
[0024] After S6 treatment, a PSG layer exists on the surface of the negative electrode region A on the back of the N-type silicon substrate, which can block the penetration of boron atoms into the phosphorus diffusion layer during the subsequent secondary boron diffusion. After the PSG layer on the surface of the positive electrode region A is removed, it is beneficial for the penetration of boron atoms into the inner phosphorus diffusion layer during the subsequent secondary boron diffusion process.
[0025] S7, alkaline cleaning: Alkaline cleaning can further remove the PSG layer that has not been completely removed from the surface of the positive electrode region A in S6.
[0026] S8. Secondary boron diffusion converts the surface layer of the exposed phosphorus diffusion layer into an outer boron diffusion layer and a BSG layer.
[0027] In this secondary boron diffusion process, the boron atom doping concentration is controlled to be higher than the phosphorus atom concentration of the phosphorus diffusion, and the doping depth is shallower than the primary boron diffusion, so that the surface layer of the exposed phosphorus diffusion layer can be transformed into an outer boron diffusion layer, thereby forming a layered alternating NPNP (double junction) structure (N-type silicon substrate-P-type inner boron diffusion layer-N-type phosphorus diffusion layer-P-type outer boron diffusion layer) on the back of the entire silicon wafer.
[0028] S9. Remove the BSG layer of the back negative electrode region B to expose the inner boron diffusion layer at the bottom.
[0029] S10, chain-removing the BSG layer plated on the front side.
[0030] S11, cleaning and texturing, to remove the inner boron diffusion layer on the surface of the negative electrode area B of the N-type silicon substrate to expose the back of the bottom N-type silicon substrate, and at the same time form a pyramid velvet surface on the front of the N-type silicon substrate. On the surface of the positive electrode area B, the negative electrode area A and the positive electrode area A on the back of the N-type silicon substrate, since there is still a PSG layer or BSG layer on the surface, the bottom deposition layers of this area can be protected from being damaged during the wet texturing process. The acid cleaning tank that comes with the tank body can then remove the PSG layer and BSG layer remaining on the back.
[0031] S12, double-sided coating, forming a passivation film on the front and back sides.
[0032] S13, screen printing, sintering, light injection, forming positive electrodes and negative electrodes in each positive electrode region and negative electrode region respectively.
[0033] Preferably, the phosphorus atom concentration of the N-type silicon substrate is less than the boron atom concentration of the first boron diffusion, less than the phosphorus atom concentration of the phosphorus diffusion, and less than the boron atom concentration of the second boron diffusion; and the first boron diffusion depth is greater than the phosphorus diffusion depth, and the second boron diffusion depth. Preferably, in S2, the conditions for the first boron diffusion are: diffusion temperature 900-930°C, time 10-60 min, BCl3 flow rate 20-80 sccm, O2 flow rate 300-900 sccm; oxidation advancement temperature 1000-1050°C, O2 flow rate 1000-8000 sccm, time 50-100 min; surface boron doping concentration 1E17-3E18 cm -3 , the doping depth is 2~4 μm; the obtained BSG layer thickness is 20~60 nm.
[0034] In order to transform a part of the surface layer of the inner boron diffusion layer into a phosphorus diffusion layer during the subsequent phosphorus diffusion, it is necessary to control the surface boron atom doping concentration to be low (but higher than the phosphorus atom doping amount of the N-type silicon substrate itself, 1E15~1E16cm -3 ), and the doping depth needs to be deeper. Therefore, the conditions for the primary boron diffusion need to be precisely controlled. Finally, the present invention found that the above purpose can be achieved under the above conditions (the main characteristics of the primary boron diffusion process compared with the conventional boron diffusion process are: relatively less source flow; longer oxidation advancement time).
[0035] Preferably, in S5, the phosphorus diffusion conditions are: diffusion temperature 750-850°C, time 10-50 min, POCl3 flow rate 100-300 sccm, O2 flow rate 200-1000 sccm; oxidation advancement temperature 850-950°C, O2 flow rate 500-2000 sccm, time 50-100 min; surface phosphorus doping concentration 5E18-9E18 cm -3 , doping depth 1.2~2 μm; the obtained PSG layer thickness is 20~60 nm.
[0036] In order to convert the surface of the inner boron diffusion layer into an N-type phosphorus diffusion layer, the phosphorus atom doping concentration of the phosphorus diffusion needs to be higher than the boron atom concentration of the first boron diffusion, and the doping depth is shallower than the first boron diffusion. Similarly, the phosphorus diffusion conditions need to be precisely controlled. Ultimately, the above purpose can be achieved under the above phosphorus diffusion conditions (the main feature of this phosphorus diffusion process compared to the conventional phosphorus diffusion process is that the oxidation advancement time is longer).
[0037] Preferably, in S8, the conditions for the secondary boron diffusion are: diffusion temperature 900-950°C, time 10-80 min, BCl3 flow rate 200-1000 sccm, O2 flow rate 2000-10000 sccm; oxidation advancement temperature 1000-1050°C, O2 flow rate 5000-80000 sccm, time 10-30 min; surface boron doping concentration 1E19-3E19 cm -3 , the doping depth is 0.3~0.8 μm; the obtained BSG layer thickness is 10~50 nm.
[0038] In order to transform the surface of the phosphorus diffusion layer into a high-concentration outer boron diffusion layer, the surface boron atom doping concentration of the secondary boron diffusion must be higher than the phosphorus atom doping concentration of the phosphorus diffusion layer; and the doping depth must be less than the phosphorus doping depth. In the secondary boron diffusion, the flow rate of the boron source is relatively large, so that the surface boron atom doping concentration is high; at the same time, the oxidation advancement time is relatively short, so that the doping depth can be accurately controlled.
[0039] Preferably, in S3, S6 and S9, the BSG layer or the PSG layer is removed by laser patterning and grooving.
[0040] Laser patterning is used to remove the BSG layer or PSG layer. Due to the difference in the laser patterning processing areas, through multiple laser processing + alkaline cleaning + diffusion, a relatively obvious height difference can be accurately formed on the back of the N-type silicon substrate, that is, in terms of thickness, the positive electrode area B> the negative electrode area A> the positive electrode area A.
[0041] Preferably, the conditions for the laser patterning grooving are: laser wavelength 400-600 nm, frequency 500-700 KHz, marking speed 40000-50000 mm / s, power 10-50 W, and processing time 1-5 s.
[0042] Compared with the prior art, the beneficial effects of the present invention are: (1) The present invention achieves that all electrodes are arranged on the back of the battery through structural optimization. This design can effectively reduce the damage caused by shading on the front of the battery, which is beneficial to improving battery performance; on the other hand, when connecting single batteries in series to form a battery module, it can avoid damage caused by connecting wires passing through the gaps between adjacent batteries, thereby improving the yield rate.
[0043] (2) The multi-junction solar cell of the present invention is a fully silicon-based cell and does not contain a perovskite cell, thus avoiding the problem of poor overall cell stability caused by the perovskite cell.
[0044] (3) The present invention has developed a method for preparing the above-mentioned four-terminal all-silicon-based multi-junction solar cell structure through ingenious step design.
[0045] (4) The present invention also provides a method for connecting the ends of a four-terminal multi-junction battery module. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] Figure 1 Schematic diagram of the structure after double-sided polishing of the N-type silicon substrate.
[0047] Figure 2 Schematic diagram of the structure of an N-type silicon substrate after one boron diffusion.
[0048] Figure 3 Schematic diagram of the structure after phosphorus diffusion on an N-type silicon substrate.
[0049] Figure 4 Schematic diagram of the structure after secondary boron diffusion of N-type silicon substrate.
[0050] Figure 5 This is a schematic diagram of the structure of the N-type silicon substrate after cleaning and texturing.
[0051] Figure 6 It is a schematic structural diagram of a four-terminal all-silicon-based multi-junction solar cell of the present invention.
[0052] Figure 7 It is a schematic diagram of the structure of a unit cell B in the solar cell assembly of the present invention.
[0053] Figure 8 It is a schematic diagram of the connection method of the solar cell assembly of the present invention.
[0054] The figures are marked as follows: N-type silicon substrate 1, inner boron diffusion layer 2, BSG layer 3, phosphorus diffusion layer 4, PSG layer 5, outer boron diffusion layer 6, pyramid velvet 7, passivation film 8, positive electrode 9, negative electrode 10, P-type silicon substrate 11, welding strip 12, inner phosphorus diffusion layer 13, boron diffusion layer 14, outer phosphorus diffusion layer 15. DETAILED DESCRIPTION
[0055] The present invention will be further described below in conjunction with the embodiments.
[0056] (1) A four-terminal all-silicon-based multi-junction solar cell, comprising: An N-type silicon substrate, a pyramid velvet surface and a passivation film sequentially arranged on the front side of the N-type silicon substrate, and a positive electrode region A, a negative electrode region A, a positive electrode region B and a negative electrode region B arranged alternately on the back side of the N-type silicon substrate; The positive electrode region A comprises an inner boron diffusion layer, a phosphorus diffusion layer, an outer boron diffusion layer and a passivation film which are sequentially arranged on the back of the N-type silicon substrate, and a positive electrode which is arranged on the surface of the outer boron diffusion layer and penetrates the passivation film; The negative electrode region A is adjacent to the positive electrode region A, and includes an inner boron diffusion layer, a phosphorus diffusion layer and a passivation film sequentially arranged on the back of the N-type silicon substrate, and a negative electrode arranged on the surface of the phosphorus diffusion layer and penetrating the passivation film; The positive electrode region B is adjacent to the negative electrode region A, and includes an inner boron diffusion layer and a passivation film sequentially arranged on the back of the N-type silicon substrate, and an anode arranged on the surface of the inner boron diffusion layer and penetrating the passivation film; The cathode region B is adjacent to the anode region B, and includes a passivation film disposed on the back of the N-type silicon substrate, and a cathode disposed on the back of the N-type silicon substrate and penetrating the passivation film.
[0057] In some preferred implementation cases, in terms of thickness, the positive electrode region B>the negative electrode region A>the positive electrode region A.
[0058] In some preferred implementation cases, in terms of width, the negative electrode region B>the positive electrode region B>the negative electrode region A>the positive electrode region A.
[0059] In some preferred implementation cases, the boron concentration in the inner boron diffusion layer is lower than the phosphorus concentration in the phosphorus diffusion layer, and the phosphorus concentration in the phosphorus diffusion layer is lower than the boron concentration in the outer boron diffusion layer.
[0060] (2) A method for preparing the above-mentioned four-terminal all-silicon-based multi-junction solar cell, comprising the following steps: S1, N-type silicon substrate double-sided polishing.
[0061] In some preferred implementation cases, an N-type silicon substrate cut by diamond wire is selected and placed in an alkaline polishing tank. The temperature is maintained at 75-85° C. for 6-8 min for double-sided polishing. The polishing thickness is 3-7 μm and the thinning amount is 0.35-0.45 g.
[0062] S2. Perform a first boron diffusion on the back side to sequentially form an inner boron diffusion layer and a BSG layer on the back side of the N-type silicon substrate.
[0063] In some preferred implementation cases, the conditions for the primary boron diffusion are: diffusion temperature 900-930°C, time 10-60 min, BCl3 flow rate 20-80 sccm, O2 flow rate 300-900 sccm; oxidation advancement temperature 1000-1050°C, O2 flow rate 1000-8000 sccm, time 50-100 min; surface boron doping concentration 1E17-3E18 cm -3 , the doping depth is 2~4μm; the resulting BSG layer thickness is 20~60 nm.
[0064] S3. Remove the BSG layer of the negative electrode region A and the positive electrode region A on the back side.
[0065] In some preferred implementation cases, in S3, the BSG layer is removed by laser patterning and grooving.
[0066] In some more preferred implementation cases, the conditions for the laser patterning grooving are: laser wavelength 400~600nm, frequency 500~700KHz, marking speed 40000~50000 mm / s, power 10~50W, and processing time 1~5s.
[0067] S4, alkaline cleaning. Alkaline cleaning can further remove the BSG layer that has not been completely removed from the surface of the positive electrode area A and the negative electrode area A in S3. During the alkaline cleaning process, the BSG layer on the surface can be accurately removed by auxiliary equipment such as ellipsoid offset and scanning electron microscope, so as not to corrode the bottom inner boron diffusion layer too much.
[0068] In some preferred implementation cases, in S4, the alkaline cleaning conditions are: the concentration of the KOH solution is 1.7-2.2 wt %, and the temperature is 75-85° C.
[0069] S5. Back side phosphorus diffusion to convert the surface layer of the exposed inner boron diffusion layer into a phosphorus diffusion layer and a PSG layer.
[0070] In some preferred implementation cases, in S5, the phosphorus diffusion conditions are: diffusion temperature 750-850°C, time 10-50 min, POCl3 flow rate 100-300 sccm, O2 flow rate 200-1000 sccm; oxidation advancement temperature 850-950°C, O2 flow rate 500-2000 sccm, time 50-100 min; surface phosphorus doping concentration 5E18-9E18 cm -3 , doping depth 1.2~2μm; the obtained PSG layer thickness is 20~60 nm.
[0071] S6. Remove the PSG layer in the positive electrode region A.
[0072] In some preferred implementation cases, in S6, the PSG layer is removed by laser patterning and grooving.
[0073] In some more preferred implementation cases, the conditions for the laser patterning grooving are: laser wavelength 400~600nm, frequency 500~700KHz, marking speed 40000~50000 mm / s, power 10~50W, and processing time 1~5s.
[0074] S7, alkaline cleaning. Alkaline cleaning can further remove the PSG layer that has not been completely removed from the surface of the positive electrode region A in S6. During the alkaline cleaning process, auxiliary equipment such as ellipsoidal displacement and scanning electron microscope can be used to accurately remove the PSG layer on the surface, so as not to corrode the bottom phosphorus diffusion layer too much.
[0075] In some preferred implementation cases, the alkaline cleaning conditions are: the concentration of the KOH solution is 1.7-2.2 wt %, and the temperature is 75-85° C.
[0076] S8, secondary boron diffusion, so that the surface of the exposed phosphorus diffusion layer is transformed into an outer boron diffusion layer and a BSG layer. In this secondary boron diffusion process, the boron atom doping concentration is controlled to be higher than the phosphorus atom concentration of the phosphorus diffusion, and the doping depth is shallower than the primary boron diffusion, so that the surface of the exposed phosphorus diffusion layer can be transformed into an outer boron diffusion layer, thereby forming a layered alternating NPNP (double junction) structure (N-type silicon substrate-P-type inner boron diffusion layer-N-type phosphorus diffusion layer-P-type outer boron diffusion layer) on the back of the entire silicon wafer.
[0077] In some preferred implementation cases, in S8, the conditions for the secondary boron diffusion are: diffusion temperature 900-950°C, time 10-80 min, BCl3 flow rate 200-1000 sccm, O2 flow rate 2000-10000 sccm; oxidation advancement temperature 1000-1050°C, O2 flow rate 5000-80000 sccm, time 10-30 min; surface boron doping concentration 1E19-3E19 cm -3 , the doping depth is 0.3~0.8 μm; the obtained BSG layer thickness is 10~50 nm.
[0078] S9. Remove the BSG layer of the back negative electrode region B to expose the inner boron diffusion layer at the bottom.
[0079] In some preferred implementation cases, in S9, the BSG layer is removed by laser patterning and grooving.
[0080] In some more preferred implementation cases, the conditions for the laser patterning grooving are: laser wavelength 400~600nm, frequency 500~700KHz, marking speed 40000~50000 mm / s, power 10~50W, and processing time 1~5s.
[0081] S10, chain-removing the BSG layer plated on the front side.
[0082] In some preferred implementation cases, in S10, the concentration of the HF solution in the chain conveyor is 20-80 wt %, and the belt speed is 0.5-5 m / min.
[0083] S11, cleaning and texturing, to remove the inner boron diffusion layer on the surface of the negative electrode area B of the N-type silicon substrate to expose the back of the bottom N-type silicon substrate, and at the same time form a pyramid velvet surface on the front of the N-type silicon substrate. On the surface of the positive electrode area B, the negative electrode area A and the positive electrode area A on the back of the N-type silicon substrate, since there is still a PSG layer or BSG layer on the surface, the bottom deposition layers of this area can be protected from being damaged during the wet texturing process. The acid cleaning tank that comes with the tank body can then remove the PSG layer and BSG layer remaining on the back.
[0084] In some preferred implementation cases, in S11, the cleaning and texturing conditions are: 1.7-2.2 wt% KOH, temperature 70-85°C, time 6-10 min.
[0085] S12, double-sided coating, forming a passivation film on the front and back sides.
[0086] In some preferred implementation cases, in S12, an AlOx film is deposited on the front and back sides of the treated N-type silicon substrate by ALD deposition, which is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of 8-10 nm, and the process temperature is controlled at 220-280°C. Then, SiN is deposited on the front and back sides by a tubular PECVD device. x Films, including SiN x The thickness of the film is 80~120 nm, and the refractive index is 1.9~2.1; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1500~1700 mTorr, the power is 10000~15000W, the temperature is 400~600℃, the SiH4 gas flow rate is 900~2000 sccm, the NH3 gas flow rate is 7000~12000 sccm, and the deposition time is 5~20 min.
[0087] S13, screen printing, sintering, light injection, forming positive electrodes and negative electrodes in each positive electrode region and negative electrode region respectively.
[0088] In some preferred implementation cases, in S12, the coated battery is subjected to a screen printing process, and electrodes (negative electrodes) are printed on corresponding areas on the back of the battery to form a final four-terminal (two positive electrodes, two negative electrodes) battery structure, which is then sintered at 700-800°C to form Ag-Si ohmic contacts, and finally light injection repair is performed to obtain the final finished battery.
[0089] Specific examples and comparative examples.
[0090] Example 1 A method for preparing the above-mentioned four-terminal all-silicon-based multi-junction solar cell comprises the following steps: S1, N-type silicon substrate double-sided polishing: select the N-type silicon substrate 1 cut by diamond wire, put it into the alkaline polishing tank, maintain the temperature at 75℃, and perform double-sided polishing for 6 min. The polishing thickness is about 4 μm, and the thinning amount is about 0.42 g. Figure 1 shown.
[0091] S2, a boron diffusion on the back side, forming an inner boron diffusion layer 2 and a BSG layer 3 on the back side of the N-type silicon substrate in sequence, such as Figure 2The conditions for the first boron diffusion are as follows: diffusion temperature 920°C, time 15 min, BCl3 flow rate 40 sccm, O2 flow rate 350 sccm; oxidation advancement temperature 1045°C, O2 flow rate 2000 sccm, time 70 min; surface boron doping concentration is about 7E17cm -3 , the doping depth is about 3.5 μm; the thickness of the obtained BSG layer is about 50 nm.
[0092] S3, removing the BSG layer of the back negative electrode region A and the positive electrode region A by laser patterning grooving. The conditions of the laser patterning grooving are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 50 W, and processing time 3 s.
[0093] S4, alkaline cleaning: Alkaline cleaning further removes the BSG layer that has not been completely removed from the surface of the positive electrode region A and the negative electrode region A in S3. During the alkaline cleaning process, the BSG layer on the surface is accurately removed by elliptical displacement and scanning electron microscope auxiliary equipment, so as not to corrode the bottom inner boron diffusion layer too much. The alkaline cleaning conditions are: KOH solution concentration is 2.0 wt%, and temperature is 75°C.
[0094] S5, back side phosphorus diffusion, so that the surface layer of the exposed inner boron diffusion layer is converted into phosphorus diffusion layer 4, PSG layer 5, such as Figure 3 The phosphorus diffusion conditions are as follows: diffusion temperature 780°C, time 30 min, POCl3 flow rate 150 sccm, O2 flow rate 500 sccm; oxidation advancement temperature 880°C, O2 flow rate 800 sccm, time 70 min; surface phosphorus doping concentration 6E18 cm -3 , the doping depth is about 1.3 μm; the thickness of the obtained PSG layer is about 48 nm.
[0095] S6. Remove the PSG layer of the positive electrode region A by laser patterning and grooving. The conditions of the laser patterning and grooving are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, and processing time 2.7 s.
[0096] S7, alkaline cleaning: Alkaline cleaning further removes the PSG layer that has not been completely removed from the surface of the positive electrode region A in S6. During the alkaline cleaning process, the PSG layer on the surface can be accurately removed by elliptical displacement and scanning electron microscope auxiliary equipment, so as not to corrode the bottom phosphorus diffusion layer too much. The alkaline cleaning conditions are: KOH solution concentration is 2.0 wt%, and the temperature is 75°C.
[0097] S8, secondary boron diffusion, so that the surface of the exposed phosphorus diffusion layer is converted into an outer boron diffusion layer 6 and a BSG layer 3, such as Figure 4The conditions for secondary boron diffusion are as follows: diffusion temperature 930°C, time 50 min, BCl3 flow rate 500 sccm, O2 flow rate 7000 sccm; oxidation advancement temperature 1050°C, O2 flow rate 30000 sccm, time 12 min; surface boron doping concentration 2E19 cm -3 , the doping depth is about 0.5 μm; the thickness of the obtained BSG layer is about 15 nm.
[0098] In this secondary boron diffusion process, the boron atom doping concentration is controlled to be higher than the phosphorus atom concentration of the phosphorus diffusion, and the doping depth is shallower than the primary boron diffusion, so that the surface layer of the exposed phosphorus diffusion layer can be transformed into an outer boron diffusion layer, thereby forming a layered alternating NPNP (double junction) structure (N-type silicon substrate-P-type inner boron diffusion layer-N-type phosphorus diffusion layer-P-type outer boron diffusion layer) on the back of the entire silicon wafer.
[0099] S9, removing the BSG layer of the back negative electrode region B by laser patterning and grooving, so as to expose the inner boron diffusion layer at the bottom thereof. The conditions of the laser patterning and grooving are as follows: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 50 W, and processing time 3 s.
[0100] S10, chain removal of the BSG layer plated on the front side: the concentration of the HF solution in the chain machine is 40 wt%, and the belt speed is 3 m / min.
[0101] S11, cleaning and texturing, so as to remove the inner boron diffusion layer on the surface of the negative electrode region B of the N-type silicon substrate to expose the back side of the bottom N-type silicon substrate, and at the same time form a pyramid velvet surface 7 on the front side of the N-type silicon substrate, such as Figure 5 As shown. On the surface of the positive region B, negative region A and positive region A on the back of the N-type silicon substrate, since there is still a PSG layer or BSG layer on the surface, the deposited layers at the bottom of this area can be protected from being damaged during the wet texturing process. The acid cleaning tank that comes with the tank body can then remove the PSG layer and BSG layer remaining on the back. Among them, the cleaning and texturing conditions are: 1.7 wt% KOH, temperature 80°C, time 8 min.
[0102] S12, double-sided coating, forming a passivation film 8 on the front and back: ALD deposition method is used to deposit AlOx thin film on the front and back of the treated N-type silicon substrate, which is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm, and the process temperature is controlled at 250℃. Then, SiN is deposited on the front and back using a tubular PECVD device. x Films, including SiN xThe thickness of the film is about 90 nm and the refractive index is 2.0; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 450℃, the SiH4 gas flow rate is 1100 sccm, the NH3 gas flow rate is 9000 sccm, and the deposition time is 12 min.
[0103] S13. The coated battery is subjected to a screen printing process, and electrodes (negative electrodes) are printed on the corresponding areas on the back of the battery to form a final four-terminal (two positive electrodes, two negative electrodes) battery structure. It is then sintered at 770°C to form Ag-Si ohmic contacts, and finally repaired by light injection to obtain the final finished battery.
[0104] like Figure 6 As shown, the four-terminal all-silicon-based multi-junction solar cell finally obtained in this embodiment includes: An N-type silicon substrate 1, a pyramid velvet surface 7 and a passivation film 8 are sequentially arranged on the front side of the N-type silicon substrate, and a positive electrode region A, a negative electrode region A, a positive electrode region B and a negative electrode region B are arranged alternately on the back side of the N-type silicon substrate.
[0105] The positive electrode region A comprises an inner boron diffusion layer 2, a phosphorus diffusion layer 4, an outer boron diffusion layer 5 and a passivation film 8 which are sequentially arranged on the back of the N-type silicon substrate, and an anode 9 which is arranged on the surface of the outer boron diffusion layer and penetrates the passivation film; The negative electrode region A is adjacent to the positive electrode region A, and includes an inner boron diffusion layer 2, a phosphorus diffusion layer 4 and a passivation film 8 sequentially arranged on the back of the N-type silicon substrate, and a negative electrode 10 arranged on the surface of the phosphorus diffusion layer and penetrating the passivation film; The positive electrode region B is adjacent to the negative electrode region A, and includes an inner boron diffusion layer 2 and a passivation film 8 sequentially arranged on the back of the N-type silicon substrate, and an anode 9 arranged on the surface of the inner boron diffusion layer and penetrating the passivation film; The cathode region B is adjacent to the anode region B, and includes a passivation film 8 disposed on the back side of the N-type silicon substrate, and a cathode 10 disposed on the back side of the N-type silicon substrate and penetrating the passivation film.
[0106] In terms of thickness, the positive electrode region B>the negative electrode region A>the positive electrode region A. In terms of width, the negative electrode region B>the positive electrode region B>the negative electrode region A>the positive electrode region A.
[0107] Comparative Example 1 Compared with Example 1, the only difference is that the phosphorus diffusion degree is insufficient: S5, back phosphorus diffusion, phosphorus diffusion conditions are: phosphorus diffusion temperature 760℃, diffusion time 5 min, POCl3 carried by nitrogen with a flow rate of 80 sccm, O2 flow rate 150 sccm; oxidation push temperature 860℃, O2 flow rate 400 sccm, push time 30 min; the thickness of the obtained PSG layer is about 15 nm, and the surface phosphorus atom doping concentration is about 1.2E18 cm-3 , the doping depth is about 0.35μm.
[0108] Comparative Example 2 Compared with Example 1, the only difference is that phosphorus diffuses excessively: S5, back phosphorus diffusion, phosphorus diffusion conditions are: phosphorus diffusion temperature 820℃, diffusion time 60 min, POCl3 carried by nitrogen with a flow rate of 800 sccm, O2 flow rate 3000 sccm; oxidation push temperature 900℃, O2 flow rate 6000 sccm, push time 120 min; the thickness of the obtained PSG layer is about 65 nm, and the surface phosphorus atom doping concentration is about 1.5E19 cm -3 , the doping depth is about 6.0 μm.
[0109] Comparative Example 3 Compared with Example 1, the only difference is that the secondary boron diffusion is not enough: S8, back secondary boron diffusion, secondary boron diffusion conditions: boron diffusion temperature 890 ° C, diffusion time 8 min, BCl3 flow rate 150 sccm, O2 flow rate 1200 sccm; oxidation push temperature 1020 ° C, O2 flow rate 4500 sccm, push time 8 min, the resulting BSG layer thickness is about 12 nm, the surface doping concentration is about 1.7E18 cm -3 , the doping depth is about 0.15 μm.
[0110] Comparative Example 4 Compared with Example 1, the only difference is that the secondary boron diffusion is excessive: S8, back side secondary boron diffusion, secondary boron diffusion conditions: boron diffusion temperature 950℃, diffusion time 90 min, BCl3 flow rate 1500 sccm, O2 flow rate 12000 sccm; oxidation push temperature 1050℃, O2 flow rate 70000 sccm, push time 110 min, the obtained BSG layer thickness is about 78 nm, the surface doping concentration is about 1.9E20 cm -3 , the doping depth is about 6.2 μm.
[0111] Comparative Example 5 A conventional single-junction back-contact cell preparation method comprising: S1. Select N-type single crystal silicon wafers cut by diamond wire, put the cut silicon wafers into alkaline polishing tank, maintain the temperature at 75℃, and perform double-sided polishing for 6 min. The polishing thickness is about 4 μm and the thinning amount is about 0.42 g.
[0112] S2. Then, high-temperature boron diffusion is used to transform the back of the silicon wafer into a boron diffusion layer and a BSG layer. The boron diffusion temperature is 850°C, the diffusion time is 10 min, the BCl3 gas flow rate is 200 sccm, the O2 gas flow rate is 1200 sccm, the oxidation advancement temperature is 950°C, the O2 flow rate is 7000 sccm, the advancement time is 30 min, and the BSG layer thickness is about 45 nm. In this process, a boron diffusion layer and a BSG layer will be formed on the front and side of the silicon wafer.
[0113] S3. Use laser patterning to groove the BSG layer on the back of the silicon wafer so that the grooved position will serve as the subsequent negative electrode area. The laser wavelength used is 532 nm, the frequency is 600 KHZ, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3 s.
[0114] S4. Use a chain acid cleaning machine to remove the BSG layer on the front and side surfaces of the silicon wafer, wherein the concentration of the HF solution in the chain machine is 40 wt% and the belt speed is 3 m / min.
[0115] S5. Then put the silicon wafer into an alkaline texturing tank for wet cleaning of the laser grooved area on the back and integrated texturing of the front. The KOH solution concentration in the texturing tank is 1.7 wt%, the temperature is maintained at 82°C, and the time is 7 min. Since the BSG layer on the front of the silicon wafer has been removed, an effective light-trapping texture surface can be formed during the texturing process; and in the laser patterning area on the back, the alkaline solution can effectively remove the boron diffusion layer until the N-type silicon substrate is exposed. In addition, since the BSG layer on the side of the silicon wafer is also removed, the corresponding side-expanded boron diffusion layer is also further cleaned and removed, preventing the occurrence of edge leakage. The subsequent acid (HF / HCl) cleaning tank of the texturing tank can further remove the residual BSG layer on the silicon wafer.
[0116] S6, double-sided coating, forming a passivation film on the front and back sides: ALD deposition method is used to deposit AlO on the front and back sides of the treated silicon substrate x The film is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm and a process temperature of 250°C. Then, SiN is deposited on the front and back sides using a tubular PECVD device. x Films, including SiN x The thickness of the film is about 85 nm and the refractive index is about 2.0; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440℃, the SiH4 gas flow rate is 1200 sccm, the NH3 gas flow rate is 9000 sccm, and the deposition time is 12 min.
[0117] S7. The coated film is screen-printed on the back to form a metal contact (the positive electrode is printed on the back boron diffusion layer, and the negative electrode is printed on the N-type silicon substrate), and then sintered at 770°C to form an Ag-Si ohmic contact. Finally, it is repaired by light injection to obtain the final conventional single-junction back-contact finished battery.
[0118] Performance Testing The electrical properties of the solar cells obtained in the embodiments and comparative examples were tested, and the results are shown in Table 1.
[0119] Table 1
[0120] First, for Example 1, since the battery adopts a four-terminal all-silicon-based double-junction back contact structure, due to the double-junction series superposition effect, its V oc The value is relatively high; and the battery has two positive and negative electrodes, the internal carrier transmission and extraction of the battery is more effective than the two-terminal type, which can eliminate the current matching problem of each part, and the corresponding battery process window is wider; in addition, the back contact grid line structure can further reduce the shading loss of the front grid line of the battery, and the corresponding battery J sc The value is also high. Therefore, the overall battery performance is the highest.
[0121] For Comparative Example 1, since the degree of phosphorus diffusion is not enough during the phosphorus diffusion process (the phosphorus doping amount is low), the surface layer of the inner boron diffusion layer cannot be fully transformed into the phosphorus diffusion layer, thereby failing to form the so-called "layered" double junction structure on the back side, resulting in insufficient current (electrons) flowing out of the surface electrode of the negative electrode region A. On the one hand, the battery has only a single pn junction structure, and on the other hand, it has only a simple two-terminal electrode contact, resulting in lower performance parameters of the battery end than those of Example 1; but since the conventional structure of the back contact battery is basically met, the battery performance is not significantly reduced.
[0122] For Comparative Example 2, due to the excessive phosphorus diffusion during the phosphorus diffusion process (high phosphorus doping amount and deep doping depth), the inner boron diffusion layer is excessively transformed into a phosphorus diffusion layer. After the secondary boron diffusion, the battery end cannot form the so-called back "layered" double junction structure and four-terminal electrode contact, but it also basically meets the conventional structure of the back contact battery, so the battery performance is not greatly reduced. Due to the large amount of doping during the phosphorus diffusion process, the carrier recombination between the diffusion layers is large, and the corresponding battery V oc The value is low, and the overall electrical performance is lower than that of Example 1 and Comparative Example 1.
[0123] For Comparative Example 3, since the degree of boron diffusion is insufficient during the secondary boron diffusion process, the outer layer of the phosphorus diffusion layer cannot be fully transformed into the outer boron diffusion layer. On the one hand, the "layered" double junction structure on the back side cannot be formed. On the other hand, the positive electrode area A originally set as the silicon wafer will become the negative electrode area, making the battery a three-terminal electrode contact, which will not only affect the battery performance test, but also there will be major problems in the corresponding component end connection, resulting in the lowest overall battery performance.
[0124] For Comparative Example 4, due to the large degree of boron diffusion during the secondary boron diffusion process, the phosphorus diffusion layer is excessively transformed into a boron diffusion layer, and the so-called four-terminal electrode contact cannot be formed. In addition, due to the large amount of surface boron doping, the surface recombination rate is even greater. However, since the conventional structure of the back contact battery is also met, the battery performance is higher than that of Comparative Example 3, but lower than that of the other groups.
[0125] For Comparative Example 5, since the back of the battery only adopts a two-terminal single junction back contact structure, the battery V oc The value is lower than that of the four-terminal multi-junction back contact structure, and the overall electrical performance is also lower than that of Example 1.
[0126] Example 2 A four-terminal all-silicon-based multi-junction solar cell assembly comprises unit cells A and unit cells B which are staggered in series. The unit cell A is the four-terminal all-silicon-based multi-junction solar cell prepared in Example 1.
[0127] The difference between unit cell B and unit cell A is that the polarity is opposite. The specific structure of unit cell B is as follows: Figure 7 As shown, it includes: a P-type silicon substrate 11, a pyramid velvet surface and a passivation film sequentially arranged on the front side of the P-type silicon substrate, and a cathode region A, an anode region A, a cathode region B and an anode region B arranged alternately on the back side of the P-type silicon substrate. Specifically: The cathode region A includes an inner phosphorus diffusion layer 13, a boron diffusion layer 14, an outer phosphorus diffusion layer 15 and a passivation film sequentially arranged on the back of the P-type silicon substrate, and a cathode 10 arranged on the surface of the outer phosphorus diffusion layer and penetrating the passivation film; The positive electrode region A is adjacent to the negative electrode region A, and includes an inner phosphorus diffusion layer 13, a boron diffusion layer 14 and a passivation film sequentially arranged on the back of the P-type silicon substrate, and a positive electrode 9 arranged on the surface of the boron diffusion layer and penetrating the passivation film; The cathode region B is adjacent to the anode region A, and includes an inner phosphorus diffusion layer 13 and a passivation film sequentially disposed on the back of the P-type silicon substrate, and a cathode 10 disposed on the surface of the inner phosphorus diffusion layer and penetrating the passivation film; The positive electrode region B is adjacent to the negative electrode region B, and includes a passivation film disposed on the back of the P-type silicon substrate, and an anode 9 disposed on the back of the P-type silicon substrate and penetrating the passivation film. The concentration of phosphorus atoms in the inner phosphorus diffusion layer is lower than the concentration of boron atoms in the boron diffusion layer, and the concentration of boron atoms in the boron diffusion layer is lower than the concentration of phosphorus atoms in the outer phosphorus diffusion layer.
[0128] The positive and negative electrodes of unit cell A and unit cell B are in opposite positions, such as Figure 8 As shown, their connection method is: the negative electrode of the negative electrode area B of the unit cell A is connected to the positive electrode of the positive electrode area B of its subsequent adjacent unit cell B through the welding strip 12, and the positive electrode of the positive electrode area B of the unit cell A is connected to the negative electrode of the negative electrode area B of its previous adjacent unit cell B through the welding strip.
[0129] The negative electrode of the negative electrode region A of unit cell A is connected to the positive electrode of the positive electrode region A of its subsequent adjacent unit cell B through a welding strip 12, and the positive electrode of the positive electrode region A of unit cell A is connected to the negative electrode of the negative electrode region A of its preceding adjacent unit cell B through a welding strip.
[0130] The raw materials and equipment used in the present invention, unless otherwise specified, are all commonly used raw materials and equipment in the art; the methods used in the present invention, unless otherwise specified, are all conventional methods in the art.
[0131] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent transformation made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.
Claims
1. A four-terminal all-silicon-based multi-junction solar cell, characterized in that include: An N-type silicon substrate, a pyramid velvet surface and a passivation film sequentially arranged on the front side of the N-type silicon substrate, and a positive electrode region A, a negative electrode region A, a positive electrode region B and a negative electrode region B arranged alternately on the back side of the N-type silicon substrate; The positive electrode region A comprises an inner boron diffusion layer, a phosphorus diffusion layer, an outer boron diffusion layer and a passivation film which are sequentially arranged on the back of the N-type silicon substrate, and a positive electrode arranged on the outer boron diffusion layer; The cathode region A includes an inner boron diffusion layer, a phosphorus diffusion layer and a passivation film, and a cathode disposed on the phosphorus diffusion layer; The positive electrode region B includes an inner boron diffusion layer and a passivation film, and a positive electrode disposed on the inner boron diffusion layer; The cathode region B includes a passivation film and a cathode disposed on an N-type silicon substrate.
2. The four-terminal all-silicon-based multi-junction solar cell according to claim 1, characterized in that: In terms of thickness, positive electrode region B>negative electrode region A>positive electrode region A; In terms of width, the negative electrode region B>the positive electrode region B>the negative electrode region A>the positive electrode region A.
3. The four-terminal all-silicon-based multi-junction solar cell according to claim 1 or 2, characterized in that: The boron concentration in the inner boron diffusion layer is lower than the phosphorus concentration in the phosphorus diffusion layer, and the phosphorus concentration in the phosphorus diffusion layer is lower than the boron concentration in the outer boron diffusion layer.
4. A method for preparing a four-terminal all-silicon-based multi-junction solar cell according to any one of claims 1 to 3, characterized in that include: S1, N-type silicon substrate double-sided polishing; S2, primary boron diffusion; S3, removing the BSG layer of the negative electrode area A and the positive electrode area A on the back side; S4, alkali cleaning; S5, phosphorus diffusion; S6, removing the PSG layer of the positive electrode region A; S7, alkali cleaning; S8, secondary boron diffusion; S9, removing the BSG layer of the back negative electrode region B; S10, removing the front BSG layer; S11, cleaning and velveting; S12, double-sided coating; S13, screen printing, sintering, light injection.
5. The preparation method according to claim 4, characterized in that: The phosphorus atomic concentration of the N-type silicon substrate is less than the boron atomic concentration of the first boron diffusion, less than the phosphorus atomic concentration of the phosphorus diffusion, less than the boron atomic concentration of the second boron diffusion; and The primary boron diffusion depth is greater than the phosphorus diffusion depth and greater than the secondary boron diffusion depth.
6. The preparation method according to claim 4, characterized in that: In S2, the conditions for the primary boron diffusion are: diffusion temperature 900-930°C, time 10-60 min, BCl3 flow rate 20-80 sccm, O2 flow rate 300-900 sccm; oxidation advancement temperature 1000-1050°C, O2 flow rate 1000-8000 sccm, time 50-100 min; surface boron doping concentration 1E17-3E18cm -3 , the doping depth is 2.0~4.0 μm; the obtained BSG layer thickness is 20~60 nm.
7. The preparation method according to claim 4, characterized in that: In S5, the phosphorus diffusion conditions are: diffusion temperature 750-850°C, time 10-50 min, POCl3 flow rate 100-300 sccm, O2 flow rate 200-1000 sccm; oxidation advancement temperature 850-950°C, O2 flow rate 500-2000 sccm, time 50-100 min; surface phosphorus doping concentration 5E18-9E18 cm -3 , doping depth 1.2~2.0 μm; the obtained PSG layer thickness is 20~60 nm.
8. The preparation method according to claim 4, characterized in that: In S8, the conditions for the secondary boron diffusion are: diffusion temperature 900-950°C, time 10-80 min, BCl3 flow rate 200-1000 sccm, O2 flow rate 2000-10000 sccm; oxidation advancement temperature 1000-1050°C, O2 flow rate 5000-80000 sccm, time 10-30 min; surface boron doping concentration 1E19-3E19 cm -3 , the doping depth is 0.3~0.8 μm; the obtained BSG layer thickness is 10~50 nm.
9. The preparation method according to claim 4, characterized in that: In S3, S6 and S9, the BSG layer or the PSG layer is removed by laser patterning and grooving.
10. The preparation method according to claim 9, characterized in that: The conditions for the laser patterning grooving are: laser wavelength 400-600 nm, frequency 500-700 KHz, marking speed 40000-50000 mm / s, power 10-50 W, and processing time 1-5 s.
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