Image sensor integrated chip structure and forming method thereof

Abstract

The invention relates to a multi-dimensional image sensor integrated chip (IC) structure. A multi-dimensional image sensor IC structure includes a plurality of image sensing elements disposed within a plurality of pixel regions in a pixel array arranged in a first integrated chip (IC) level. The plurality of pixel regions includes a plurality of active pixel regions and one or more dummy pixel regions. A plurality of pixel support devices are disposed on the second substrate within a second IC level bonded to the first IC level. A plurality of logic devices are disposed within a third IC level bonded to the second IC level. A through substrate via (TSV) extends vertically through the second substrate located laterally outward of the plurality of pixel support devices and located directly below the pixel array. The embodiment of the invention also relates to an image sensor integrated chip structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a multi-dimensional image sensor integrated chip structure, an image sensor integrated chip structure and a method for forming the same. Background Art

[0002] Integrated circuits (ICs) with image sensors are used in a variety of modern electronic devices, such as cameras and mobile phones. In recent years, complementary metal oxide semiconductor (CMOS) image sensors have begun to be widely used, largely replacing charge coupled device (CCD) image sensors. Compared with CCD image sensors, CMOS image sensors are becoming more and more popular due to their low power consumption, small size, fast data processing speed, direct data output, and low manufacturing cost. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a multi-dimensional image sensor integrated chip (IC) structure is provided, including: a plurality of image sensing elements, arranged in a plurality of pixel regions in a pixel array arranged in a first integrated chip (IC) level, wherein the plurality of pixel regions include a plurality of active pixel regions and one or more dummy pixel regions; a plurality of pixel support devices, arranged on a second substrate in a second IC level bonded to the first IC level; a plurality of logic devices, arranged in a third IC level bonded to the second IC level; and a through substrate via (TSV) extending vertically through the second substrate laterally outside the plurality of pixel support devices and directly below the pixel array.

[0004] According to another aspect of an embodiment of the present application, an image sensor integrated chip (IC) structure is provided, including: a pixel array, including a plurality of image sensing elements arranged in a plurality of pixel regions of a first substrate, wherein the plurality of pixel regions include a plurality of active pixel regions laterally surrounding one or more dummy pixel regions; a plurality of pixel support devices, arranged in a second substrate stacked on the first substrate and coupled to a second interconnect structure on the second substrate, wherein the plurality of active pixel regions respectively include one or more of the plurality of image sensing elements electrically coupled to the plurality of pixel support devices; a plurality of logic devices, arranged on a third substrate stacked on the second substrate and coupled to a third interconnect structure on the third substrate; and a through substrate via (TSV) extending vertically through the second substrate directly below the pixel array and laterally outside the plurality of pixel support devices.

[0005] According to another aspect of an embodiment of the present application, a method for forming an image sensor integrated chip (IC) structure is provided, comprising: forming a first integrated chip (IC) level including a plurality of image sensing elements within a pixel array in a first substrate, the pixel array including a plurality of active pixel regions surrounding one or more dummy pixel regions; forming a second IC level including a plurality of pixel support devices on a second substrate; bonding the first IC level to the second IC level so that one or more regions of the second substrate are laterally located outside the plurality of pixel support devices and vertically located directly below the pixel array; forming through substrate vias (TSVs) to extend through one or more regions of the second substrate; forming a third IC level including a plurality of logic devices on a third substrate; and bonding the third IC level to the second IC level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of a multi-dimensional image sensor integrated chip (IC) structure including a through substrate via (TSV) located below a pixel array including a dummy pixel region are shown.

[0008] Figure 2 A top view of some embodiments of the disclosed multi-dimensional image sensor IC structure including TSVs located below a pixel array including a dummy pixel region is shown.

[0009] Figure 3 Cross-sectional views of some additional embodiments of the disclosed multi-dimensional image sensor IC structures including TSVs located below dummy pixel regions within a pixel array are shown.

[0010] Figure 4A-4B Some additional embodiments of the disclosed multi-dimensional image sensor IC structures including TSVs located below dummy pixel regions within a pixel array are shown.

[0011] Figure 5A-Figure 5B Some additional embodiments of the disclosed multi-dimensional image sensor IC structures including multiple TSVs located below a dummy pixel region within a pixel array are shown.

[0012] Figure 6A-6B Some additional embodiments of the disclosed multi-dimensional image sensor IC structures including TSVs located below dummy pixel regions within a pixel array are shown.

[0013] Figure 7-Figure 8Top views of some additional embodiments of the disclosed multi-dimensional image sensor IC structures including TSVs located below dummy pixel regions within a pixel array are shown.

[0014] Fig. 9 Cross-sectional views of some additional embodiments of the disclosed multi-dimensional image sensor IC structures including TSVs located below a pixel array including a dummy pixel region are shown.

[0015] Figure 10-Figure 30 Cross-sectional views of some embodiments of methods of forming a multi-dimensional image sensor IC structure including TSVs located below a pixel array including a dummy pixel region are shown.

[0016] Fig.31 A flow chart illustrating some embodiments of a method of forming a multi-dimensional image sensor IC structure including TSVs located below a pixel array including dummy pixel regions.

[0017] Figure 32-Figure 51 Cross-sectional views of some additional embodiments of methods of forming a multi-dimensional image sensor IC structure including TSVs located below a pixel array including dummy pixel regions are shown.

[0018] Fig.52 Flowcharts illustrating some additional embodiments of methods of forming a multi-dimensional image sensor IC structure including TSVs located below a pixel array including dummy pixel regions. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0021] An image sensor integrated chip structure (e.g., a complementary metal oxide semiconductor sensor (CIS)) typically includes a plurality of photodiodes arranged in pixel regions in rows and columns of a pixel array. In order to improve the performance (e.g., resolution) of the image sensor integrated chip structure, the semiconductor industry has increased the size of the pixel array. In some embodiments, a multi-dimensional image sensor integrated chip structure may include image sensing elements (e.g., photodiodes) disposed on a separate integrated chip layer different from the logic circuit to provide a larger size for the pixel array. For example, a multi-dimensional image sensor integrated chip structure may include a pixel array located on a first integrated chip level, a pixel support device located below the pixel array at a second integrated chip level, and an image signal processing circuit located on a third integrated chip level.

[0022] In this multi-dimensional image sensor integrated chip structure, the electrical connection between the image signal processing circuit and the pixel array and / or pixel support device can be achieved by using a through substrate via (TSV) that runs through the substrate within one of the integrated chip levels. In order to avoid damage to the pixel support device, the TSV is usually located at the periphery of the pixel array. However, due to the long electrical connection path between the image signal processing circuit and the pixel array and / or pixel support device, positioning the TSV along the periphery of the pixel array will result in a relatively low transmission speed of the multi-dimensional image sensor integrated chip structure. In addition, as the size of the pixel array increases, the length of the electrical connection path will also increase, thereby increasing the parasitic resistance and reducing the performance of the multi-dimensional image sensor integrated chip structure.

[0023] The present invention relates to a multi-dimensional image sensor integrated chip (IC) structure, which has one or more through-substrate vias (TSVs) arranged directly below a pixel array, and the pixel array includes one or more dummy pixel areas. In some embodiments, the disclosed multi-dimensional image sensor IC structure may include a first substrate, a second substrate, and a third substrate. A pixel array including a plurality of pixel areas is arranged in a first substrate, a plurality of pixel support devices are arranged on and / or in a second substrate, and a plurality of logic devices are arranged on and / or in a third substrate. The pixel array includes a plurality of active pixel areas that laterally surround one or more dummy pixel areas. The plurality of active pixel areas respectively include image sensing elements. A through-substrate via (TSV) extends vertically through the second substrate at a position laterally outside the plurality of pixel support devices so as to provide electrical connection between the plurality of pixel support devices and the plurality of logic devices. Because the dummy pixel area does not have an associated pixel support device, the dummy pixel area provides an area in the second substrate without a pixel support device and directly below the pixel array. The TSV may extend through the second substrate in the area, thereby allowing the TSV to provide a shorter electrical connection path length between the plurality of pixel support devices and the plurality of logic devices. Shorter electrical connection path lengths provide lower resistance, thereby improving the performance of the multi-dimensional image sensor IC structure.

[0024] Figure 1 A cross-sectional view of some embodiments of the disclosed multi-dimensional image sensor IC structure 100 is shown, which includes a through substrate via (TSV) located below a pixel array including a dummy pixel region.

[0025] The multi-dimensional image sensor IC structure 100 includes a plurality of integrated chip (IC) levels 102a-102c stacked on each other. In some embodiments, the multi-dimensional image sensor IC structure 100 may include a three-dimensional integrated chip (3DIC) structure. In some embodiments, the plurality of IC levels 102a-102c include a first IC level 102a, a second IC level 102b, and a third IC level 102c.

[0026] The first IC level 102a includes a plurality of image sensing elements 106 disposed within a first substrate 104a. The plurality of image sensing elements 106 are disposed within a pixel array 108 including a plurality of pixel regions 108a and 108d. A plurality of transmission gates 110 are disposed on and / or within the first substrate 104a. A first interconnect structure 112a is also disposed on the first substrate 104a. The first interconnect structure 112a includes a first plurality of interconnects 114a disposed within a first interlayer dielectric (ILD) structure 113a. One or more of the first plurality of interconnects 114a are electrically coupled to the plurality of transmission gates 110.

[0027] The second IC level 102b includes a plurality of pixel support devices 116 disposed on and / or within the second substrate 104b. In some embodiments, the plurality of pixel support devices 116 may include reset transistors, source follower transistors, row select transistors, and the like (e.g., transistors configured to function as analog-to-digital converters, amplifiers, multiplexers, and the like). The plurality of pixel support devices 116 are connected to a second interconnect structure 112b, which includes a second plurality of interconnects 114b disposed within a second ILD structure 113b. In various embodiments, the plurality of pixel support devices 116 may include planar FETs, FinFETs, gate-all-around (GAA) transistors, nanosheet transistors, and the like. In some embodiments, the first interconnect structure 112a is bonded to the second interconnect structure 112b along a bonding interface including one or more conductive interfaces and one or more dielectric interfaces.

[0028] The third IC level 102c includes a plurality of logic devices 118 disposed on and / or within the third substrate 104c. In some embodiments, the plurality of logic devices 118 may be configured to operate as an image processing circuit. In various embodiments, the plurality of logic devices 118 may include planar FETs, FinFETs, surround gate FETs (e.g., nanosheets), etc. The third interconnect structure 112c is disposed on the third substrate 104c. The third interconnect structure 112c includes a third plurality of interconnects 114c disposed within the third ILD structure 113c. The third plurality of interconnects 114c are electrically coupled to the plurality of logic devices 118.

[0029] The multiple pixel regions 108a and 108d include multiple active pixel regions 108a and one or more dummy pixel regions 108d. Along the cross-sectional view, the one or more dummy pixel regions 108d are laterally surrounded by the multiple active pixel regions 108a. The multiple active pixel regions 108a respectively include one or more of the multiple image sensing elements 106, which are configured to generate a current provided to the multiple pixel support devices 116 in response to incident radiation. The one or more dummy pixel regions 108d do not include an image sensing element configured to generate a current provided to the multiple pixel support devices 116 in response to incident radiation, so that the one or more dummy pixel regions do not have a photosensitive function. For example, in some embodiments, the one or more dummy pixel regions 108d may respectively include one or more dummy image sensing elements of the multiple image sensing elements 106, which are not electrically coupled to the multiple pixel support devices 116.

[0030] A plurality of pixel support devices 116 are disposed on and / or within the second substrate 104b directly below the pixel array 108 and / or within the second substrate 104a. In some embodiments, a plurality of pixel support devices 116 are disposed on and / or within the second substrate 104b directly below the plurality of active pixel regions 108a and outside the one or more dummy pixel regions 108d. In such an embodiment, the second substrate 104b may not have a pixel support device directly below the one or more dummy pixel regions 108d. In other embodiments, a plurality of pixel support devices 116 are disposed on and / or within the second substrate 104b, directly below the one or more dummy pixel regions 108d and outside one of the plurality of active pixel regions 108a. Because the one or more dummy pixel regions 108d do not have an associated pixel support device, the one or more dummy pixel regions 108d provide one or more regions within the second substrate 104b that are laterally outside the pixel support device 116 and directly below the pixel array 108.

[0031] Through substrate vias (TSVs) 120 extend through the second substrate 104b directly below the pixel array 108 and are located in one or more regions laterally outside the plurality of pixel support devices 116. The TSVs 120 electrically connect the second plurality of interconnects 114b to the third plurality of interconnects 114c. In some embodiments, the TSVs 120 may extend through the second substrate 104b directly below the one or more dummy pixel regions 108d. Because the one or more regions are located below the pixel array 108, the TSVs 120 are able to provide relatively short electrical connections between the plurality of logic devices 118 and the plurality of image sensing elements 106 and / or the plurality of pixel support devices 116. The relatively short electrical connections reduce the parasitic resistance of the multi-dimensional image sensor IC structure 100 and improve the multi-dimensional image sensing IC structure 100.

[0032] Figure 2 A top view 200 of some embodiments of the disclosed multi-dimensional image sensor IC structure is shown, which includes TSVs located below a pixel array including a dummy pixel region.

[0033] As shown in the top view 200, the plurality of pixel regions 108a and 108d are arranged in a pixel array 108 having rows 202 and columns 204. The rows 202 extend along a first direction 206, and the columns 204 extend along a second direction 208 perpendicular to the first direction 206. The plurality of pixel regions 108a and 108d include a plurality of active pixel regions 108a and one or more dummy pixel regions 108d. The one or more dummy pixel regions 108d are laterally surrounded by the plurality of active pixel regions 108a in the first direction 206 and / or the second direction 208.

[0034] During operation, the image sensing elements within the plurality of active pixel regions 108a are configured to generate electrical signals in response to incident radiation. The electrical signals are provided to pixel support devices and / or logic devices within a substrate disposed below the pixel array 108. The electrical signals may be provided by TSVs 120 located directly below the pixel array 108 (e.g., laterally bounded by the periphery of the pixel array 108) between the pixel support devices and the logic devices. In some embodiments, the TSVs 120 may be arranged directly below one or more dummy pixel regions 108d within the pixel array 108. Because the TSVs 120 are located directly below the pixel array 108, the TSVs 120 are able to provide relatively short electrical connections between the plurality of logic devices and the plurality of pixel support devices.

[0035] Figure 3 Some additional embodiments of the disclosed multi-dimensional image sensor IC structure 300 are shown that include TSVs located below dummy pixel regions within a pixel array.

[0036] The multi-dimensional image sensor IC structure 300 includes a plurality of IC levels 102a-102c stacked on each other. In some embodiments, the plurality of IC levels 102a-102c include a first IC level 102a, a second IC level 102b, and a third IC level 102c. The first IC level 102a includes a plurality of image sensing elements 106 (e.g., photodetectors) disposed within a first substrate 104a. The plurality of image sensing elements 106 are disposed within a pixel array 108, and the pixel array 108 includes a plurality of active pixel regions 108a and one or more dummy pixel regions 108d. The plurality of active pixel regions 108a respectively include one or more of a plurality of transfer gates 110 disposed on the first substrate 104a. The plurality of transfer gates 110 are configured to selectively provide charge from the plurality of image sensing elements 106 to a floating diffusion region 302 disposed within the first substrate 104a. The floating diffusion region 302 is electrically coupled to one or more of a first plurality of interconnects 114a within a first interconnect structure 112a on the first substrate 104a. In some embodiments, one or more dummy pixel regions 108d lack a transfer gate such that image sensing elements (eg, dummy image sensing elements) within the one or more dummy pixel regions 108d are not electrically coupled to interconnects within the first interconnect structure 112a.

[0037] In some embodiments, the isolation structure 308 is arranged in the first substrate 104a along the opposite sides of the plurality of active pixel regions 108a and the one or more dummy pixel regions 108d. The isolation structure 308 may include one or more dielectric materials disposed in one or more trenches formed by the sidewalls of the first substrate 104a. In some embodiments, the isolation structure 308 may include a backside deep trench isolation (BS-DTI) structure including one or more dielectric materials disposed in one or more trenches extending to the back side of the first substrate 104a. In some embodiments, the isolation structure 308 may extend completely through the first substrate 104a.

[0038] The second IC level 102b includes a plurality of pixel support devices 116 disposed on and / or within the front side 105a of the second substrate 104b. In some embodiments, the plurality of pixel support devices 116 include a reset transistor, a source follower transistor, and a row select transistor. The reset transistor includes a source coupled to the floating diffusion region 302. The source follower transistor includes a gate coupled to the floating diffusion region 302. The row select transistor is coupled to the drain of the source follower transistor. In some embodiments, the second IC level 102b may also include one or more in-pixel devices (e.g., including column amplifiers and / or capacitors, column decoders, analog-to-digital converters, conversion gain transistors, voltage domain global shutter transistors, polysilicon capacitors, etc.) coupled to the plurality of pixel support devices 116. The plurality of pixel support devices 116 are coupled to one or more of the second plurality of interconnects 114b within the second interconnect structure 112b on the second substrate 104b. In some embodiments, the first interconnect structure 112 a may include a first conductive bonding structure 304 a bonded to a second conductive bonding structure 304 b within the second interconnect structure 112 b along an interface.

[0039] The third IC level 102c includes a plurality of logic devices 118 disposed on and / or within the front side of the third substrate 104c and coupled to a third plurality of interconnects 114c within the third interconnect structure 112c. In some embodiments, one or more of the logic devices 118 may be configured to perform operations such as image processing, analog data processing (e.g., noise reduction, data sampling, etc.). In some embodiments, the third interconnect structure 112c may include a third conductive bonding structure 304c disposed above and along the top of the third plurality of interconnects 114c.

[0040] The TSV 120 extends vertically through the second substrate 104b at a location directly below one of the one or more dummy pixel regions 108d. The TSV 120 electrically couples the one or more pixel support devices 116 to the one or more logic devices 118. In some embodiments, the TSV 120 may extend from one of the second plurality of interconnects 114b to the back side 105b of the second substrate 104b.

[0041] In some embodiments, the one or more dummy pixel regions 108d include one or more dummy image sensing elements of the plurality of image sensing elements 106. The one or more dummy image sensing elements are electrically isolated from the plurality of pixel support devices 116. During the formation of the plurality of image sensing elements 106, the one or more dummy image sensing elements may improve process parameters (e.g., photolithography parameters), thereby improving the performance of the multi-dimensional image sensor IC structure 300. In some embodiments, the TSV 120 extends vertically through the second substrate 104b at a location directly below the one or more dummy image sensing elements.

[0042] In some embodiments, the TSV 120 may include a backside through substrate via (BTSV) having a tapered sidewall, which causes the width of the TSV 120 to decrease between the back side 105b and the front side 105a of the second substrate 104b. In some embodiments, the TSV 120 may physically contact an additional conductive bonding structure 304d disposed within an additional dielectric structure 306 arranged along the back side 105b of the second substrate 104b. In some embodiments, the third conductive bonding structure 304c contacts the additional conductive bonding structure 304 along an interface.

[0043] During operation, electromagnetic radiation (e.g., photons) striking the plurality of image sensing elements 106 generates charge carriers that are collected in the plurality of image sensing elements 106. When the plurality of transfer gates 110 are turned on, the charge carriers in the plurality of image sensing elements 106 within the plurality of active pixel regions 108a are transferred to the floating diffusion region 402 due to the potential difference existing between the plurality of image sensing elements 106 and the floating diffusion region 302. The charge is converted into a voltage signal by the source follower transistor, and the row select transistor is used for addressing. Prior to the charge transfer, the floating diffusion region 302 can be set to a predetermined low charge state by turning on the reset transistor, which causes the electrons in the floating diffusion region 302 to flow into the voltage source (VDD).

[0044] In some embodiments, to implement an autofocus function, the plurality of pixel regions 108a and 108d may include two image sensor regions 312a-312b, respectively, each including an image sensing element (e.g., a photodiode) arranged in a dual image sensing element configuration. During operation, a convex module lens (not shown) may be configured to focus incident radiation to the multi-dimensional image sensor IC structure 300. If the incident radiation is focused, the radiation will be evenly distributed between the image sensing elements within the two image sensor regions 312a-312b. However, if the incident radiation is out of focus, one of the image sensing elements will receive more radiation than the other. Thus, the amount of charge may be read independently of the image sensing element and used to change the focus (e.g., position) of the convex module lens.

[0045] In some embodiments, one or more additional isolation regions 310 may be disposed within the first substrate 104a above the floating diffusion region 302. In some such embodiments, the plurality of image sensor regions 312a-312b are separated from one another by the one or more additional isolation regions 310. The one or more additional isolation regions 310 extend partially through the first substrate 104a to provide electrical isolation between adjacent regions of the plurality of image sensor regions 312a-312b while still allowing the floating diffusion region 302 to be shared between adjacent regions of the plurality of image sensor regions 312a-312b.

[0046] In some embodiments, a plurality of color filters 314 are disposed on the back side of the first substrate 104a, and a plurality of micro lenses 316 are arranged on the plurality of color filters 314. The plurality of micro lenses 316 directly cover the image sensing element 106 in one of the plurality of pixel regions 108a and 108d, respectively.

[0047] Figure 4A Cross-sectional views of some additional embodiments of the disclosed multi-dimensional image sensor IC structure 400 are shown, which includes TSVs located below dummy pixel regions within a pixel array.

[0048] The multi-dimensional image sensor IC structure 400 includes a plurality of IC levels 102a-102c stacked on each other. In some embodiments, the plurality of IC levels 102a-102c include a first IC level 102a, a second IC level 102b, and a third IC level 102c. The first IC level 102a includes a plurality of image sensing elements 106 (e.g., photodetectors) disposed within a first substrate 104a. The second IC level 102b includes a plurality of pixel support devices 116 disposed on and / or within the second substrate 104b. The third IC level 102c includes a plurality of logic devices 118 disposed on and / or within the third substrate 104c.

[0049] A plurality of image sensing elements 106 are disposed within a pixel array 108, and the pixel array 108 includes a plurality of active pixel regions 108a and one or more dummy pixel regions 108d. In some embodiments, the plurality of active pixel regions 108a may have a first width 402, and the one or more dummy pixel regions 108d may have a second width 404 that is different from the first width 402. In some embodiments, the first width 402 may be greater than the second width 404. In some embodiments, the first substrate 104a may not have an image sensing element (e.g., a photodiode) within the dummy pixel region 108d.

[0050] Figure 4B Shown with Figure 4A 4. A top view 406 of some embodiments corresponding to the multi-dimensional image sensor IC structure 400 of FIG. 4 is shown in the top view 406. As shown in the top view 406, a plurality of active pixel regions 108a and one or more dummy pixel regions 108d are arranged in the pixel array 108 in rows 202 and columns 204. In some embodiments, one or more of the plurality of active pixel regions 108a have a different shape than one or more dummy pixel regions 108d. For example, one or more of the plurality of active pixel regions 108a have a square shape, while one or more dummy pixel regions 108d have a rectangular shape.

[0051] In some embodiments, at least one of the plurality of active pixel regions 108a has a first width 402 along the first direction 206 and along the second direction 208. In various embodiments, one or more dummy pixel regions 108d may have a second width 404 along the first direction 206 and / or along the second direction 208. For example, in some embodiments, one or more dummy pixel regions 108d may have a second width 404 along the first direction 206 and the second direction 208. In other embodiments, one or more dummy pixel regions 108d may have a first width 402 along the first direction 206 and a second width 404 along the second direction 208, or a second width 404 along the first direction 206 and a first width 402 along the second direction 208.

[0052] Figure 5A Cross-sectional views of some additional embodiments of the disclosed multi-dimensional image sensor IC structure 500 are shown, which includes TSVs located below dummy pixel regions within a pixel array.

[0053] The multi-dimensional image sensor IC structure 500 includes a first IC level 102a, a second IC level 102b stacked on the first IC level 102a, and a third IC level 102c stacked on the second IC level 102b. The first IC level 102a includes a pixel array 108, and the pixel array 108 includes a plurality of active pixel regions 108a and one or more dummy pixel regions 108d. The plurality of active pixel regions 108a respectively include one or more of a plurality of transmission gates 110 arranged on a first substrate 104a.

[0054] The first IC level 102a also includes a first interconnect structure 112a disposed on the first substrate 104a. In some embodiments, the first interconnect structure 112a has no interconnects below the one or more dummy pixel regions 108d. The second IC level 102b includes a second interconnect structure 112b disposed on the second substrate 104b. The third IC level 102c includes a third interconnect structure 112c disposed on the third substrate 104c.

[0055] The TSV 120 extends through the second substrate 104b directly below the one or more dummy pixel regions 108d. One or more additional TSVs 502 also extend through the second substrate 104b directly below the one or more dummy pixel regions 108d. The TSV 120 is laterally separated from the one or more additional TSVs 502 by the second substrate 104b. The TSV 120 and the one or more additional TSVs 502 are arranged between adjacent active pixel regions in the plurality of active pixel regions 108a along the cross-sectional view.

[0056] Figure 5B Shown with Figure 5A 504 of some embodiments corresponding to the multi-dimensional image sensor IC structure 500. As shown in the top view 504, the TSV 120 and one or more additional TSVs 502 are arranged in the same dummy pixel region of the one or more dummy pixel regions 108d, and are separated from each other along the first direction 206 and / or the second direction 208. In some embodiments, the TSV 120 and one or more additional TSVs 502 are arranged in the same dummy pixel region in the TSV array 510. In some embodiments, the TSV array 510 may include a 2x2 array, a 3x3 array, etc.

[0057] In some embodiments, TSV 120 and one or more additional TSVs 502 may each have a width 506 and a pitch 508. In some embodiments, width 506 may be in a range between about 1.5 micrometers (μm) and about 0.2 μm, between about 0.5 μm and about 0.2 μm, between about 0.3 μm, or other similar values. In some embodiments, pitch 508 may be in a range between about 0.5 micrometers (μm) and about 2.5 μm, between about 0.8 μm and about 1.2 μm, about 1 μm, or other similar values.

[0058] Figure 6A-6B Some additional embodiments of the disclosed multi-dimensional image sensor IC structure are shown that include TSVs located below dummy pixel regions within a pixel array.

[0059] The multi-dimensional image sensor IC structure 600 includes a first IC level 102a, a second IC level 102b stacked on the first IC level 102a, and a third IC level 102c stacked on the second IC level 102b. The first IC level 102a includes a plurality of image sensing elements 106 (e.g., photodetectors) disposed within a first substrate 104a. The plurality of image sensing elements 106 are disposed within a pixel array 108, and the pixel array 108 includes a plurality of active pixel regions 108a and one or more dummy pixel regions 108d. The plurality of active pixel regions 108a respectively include one or more of a plurality of transmission gates 110 disposed on the first substrate 104a.

[0060] The peripheral region 602 surrounds the pixel array 108. One or more peripheral TSVs 604 are arranged in the peripheral region 602 and laterally outside the pixel array 108. The one or more peripheral TSVs 604 extend vertically through the second substrate 104b to provide additional electrical connections between the second IC level 102b and the third IC level 102c (e.g., between the plurality of pixel support devices 116 and the plurality of logic devices 118). Figure 6B As shown in top view 606 of , peripheral region 602 extends around the periphery of pixel array 108 .

[0061] By having TSV 120 and one or more peripheral TSVs 604 provide electrical connections between second IC level 102 b and third IC level 102 c, shorter electrical connections may be achieved between multiple logic devices 118 and multiple image sensing elements 106 and / or multiple pixel support devices 116. Shorter electrical connections provide lower resistance, thereby improving the performance of multi-dimensional image sensor IC structure 600.

[0062] Figure 7Top views of some additional embodiments of the disclosed multi-dimensional image sensor IC structure 700 are shown, which includes TSVs located below dummy pixel regions within a pixel array.

[0063] The multi-dimensional image sensor IC structure 700 includes a pixel array 108 having a plurality of active pixel regions 108a and one or more dummy pixel regions 108d. In some embodiments, the one or more dummy pixel regions 108d may include at least two dummy pixel regions. The at least two dummy pixel regions may be arranged in different rows 202 and / or different columns 204. In some embodiments, the at least two dummy pixel regions may be separated along the first direction 206 and along the second direction 208. In some embodiments, the at least two dummy pixel regions may be arranged in a periodic pattern within the pixel array 108. In some embodiments, the at least two dummy pixel regions within the pixel array 108 may include between about 6 dummy pixel regions and about 600 dummy pixel regions.

[0064] Figure 8 Top views of some additional embodiments of the disclosed multi-dimensional image sensor IC structure 800 are shown, which includes TSVs located below dummy pixel regions within a pixel array.

[0065] The multi-dimensional image sensor IC structure 800 includes a pixel array 108 having a plurality of active pixel regions 108a and one or more dummy pixel regions 108d. In some embodiments, the one or more dummy pixel regions 108d may include at least two dummy pixel regions. The at least two dummy pixel regions may be arranged in different rows 202 and / or different columns 204. In some embodiments, the at least two dummy pixel regions may be separated along the first direction 206 and along the second direction 208. In some embodiments, the at least two dummy pixel regions may include TSV arrays 510, respectively, so that the plurality of TSV arrays are arranged below the pixel array 108. In some additional embodiments, the at least two dummy pixel regions may include TSV 120, respectively. In other embodiments, at least one dummy pixel region may include TSV 120, and at least one dummy pixel region may include TSV array 510.

[0066] Fig. 9 Cross-sectional views of some additional embodiments of the disclosed multi-dimensional image sensor IC structure 900 including TSVs beneath a pixel array including a dummy pixel region are shown.

[0067] The multi-dimensional image sensor IC structure 900 includes a plurality of IC levels 102a-102c stacked on each other. In some embodiments, the plurality of IC levels 102a-102c include a first IC level 102a, a second IC level 102b, and a third IC level 102c. The first IC level 102a includes a plurality of image sensing elements 106 (e.g., photodetectors) disposed within a first substrate 104a. A first interconnect structure 112a is disposed on the front side of the first substrate 104a. The second IC level 102b includes a plurality of pixel support devices 116. The second interconnect structure 112b is disposed on the front side 105a of the second substrate 104b, and an additional conductive bonding structure 304d is disposed within an additional dielectric structure 306 on the back side 105b of the third substrate 104b. The third IC level 102c includes a plurality of logic devices 118 disposed on the front side and / or within the front side of the third substrate 104c. The third interconnect structure 112c is disposed on the front side of the third substrate 104c. The front side of the first substrate 104a is bonded to the back side 105b of the second substrate 104b. The front side 105a of the second substrate 104b is bonded to the front side of the third substrate 104c.

[0068] A plurality of image sensing elements 106 are disposed within a pixel array 108, and the pixel array 108 includes a plurality of active pixel regions 108a and one or more dummy pixel regions 108d. The plurality of active pixel regions 108a respectively include one or more of the plurality of image sensing elements 106, which are configured to generate a current provided to the plurality of pixel support devices 116 in response to incident radiation. The one or more dummy pixel regions 108d do not include an image sensing element configured to generate a current provided to the plurality of pixel support devices in response to incident radiation, so that the one or more dummy pixel regions do not have a photosensitive function.

[0069] A plurality of pixel support devices 116 are arranged within the second substrate 104b directly below the dummy pixel region 108d. The plurality of image sensing elements 106 within the plurality of active pixel regions 108a are electrically coupled to the plurality of pixel support devices 116 via TSVs 120, which extend through the second substrate 104b laterally outside the pixel support devices 116. For example, in some embodiments, the TSVs 120 extend through the second substrate 104b directly below one of the plurality of active pixel regions 108a to connect to a second plurality of interconnects 114b, which are electrically coupled to the plurality of pixel support devices 116. In some additional embodiments, the TSV array 510 may extend through the second substrate 104b laterally outside the plurality of pixel support devices 116. For example, in some embodiments, the TSV array 510 may extend through the second substrate 104b directly below one of the plurality of active pixel regions 108a to connect to a second plurality of interconnects 114b.

[0070] Figure 10-Figure 30 A cross-sectional view of some embodiments of a method of forming a multi-dimensional image sensor IC structure including TSVs located below a pixel array including a dummy pixel region is shown. Figure 10-Figure 30 It is described with respect to a method, but it should be understood that the structure disclosed in the method is not limited to the method, but can exist independently as a structure independent of the method.

[0071] like Fig.10 As shown in the cross-sectional view 1000 of , a first substrate 104a is provided. In various embodiments, the first substrate 104a can be any type of semiconductor body (e.g., silicon, SiGe, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or epitaxial layer associated therewith.

[0072] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , multiple image sensing elements 106 are formed in multiple pixel regions 108a and 108d in the pixel array 108 in the first substrate 104a. In some embodiments, the multiple pixel regions 108a and 108d may include multiple active pixel regions 108a and one or more dummy pixel regions 108d.

[0073] In some embodiments, the plurality of image sensing elements 106 may include photodiodes formed by implanting one or more dopants into the front side of the first substrate 104a. For example, the plurality of image sensing elements 106 may be formed by selectively performing a first implantation process (e.g., according to a first mask layer) to form a first region having a first doping type (e.g., n-type), followed by performing a second implantation process to form a second region adjacent to the first region and having a second doping type (e.g., p-type) different from the first doping type. In some embodiments, the floating diffusion region 302 may also be formed within the first substrate 104a. The floating diffusion region 302 may be formed by selectively implanting one or more dopants into the first substrate 104a according to a mask layer. In some embodiments, the floating diffusion region 302 may be formed using one of the first or second implantation processes.

[0074] like Fig.12As shown in the cross-sectional view 1200 of FIG. 1 , a plurality of transmission gates 110 are formed in a plurality of active pixel regions 108a along the front side of the first substrate 104a. In some embodiments, the plurality of transmission gates 110 may be formed by depositing a gate dielectric film and a gate electrode film on the front side of the first substrate 104a, and then patterning the gate dielectric film and the gate electrode film to form a gate dielectric layer and a gate electrode. Sidewall spacers may be formed on the outer sidewalls of the gate electrode. In some embodiments, the sidewall spacers may be formed by depositing a spacer layer (e.g., nitride, oxide, etc.) on the front side of the first substrate 104a and selectively etching the spacer layer to form a sidewall spacer.

[0075] The first interconnect structure 112a is formed on the front side of the first substrate 104a. The first interconnect structure 112a includes a first plurality of interconnects 114a formed in a first ILD structure 113a including one or more ILD layers. The first plurality of interconnects 114a include conductive contacts, interconnect lines and / or interconnect vias. In some embodiments, the first interconnect structure 112a may be formed using a damascene process (e.g., a single damascene process and / or a dual damascene process). For example, a damascene process may be performed by forming an ILD layer on the front side of the first substrate 104a, etching the ILD layer to form vias and / or trenches, filling the vias and / or trenches with a conductive material, and performing a planarization process (e.g., a chemical mechanical planarization process) to remove excess conductive material from the ILD layer. In some embodiments, the ILD layer may be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.), and the conductive material may be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the conductive material may include tungsten, copper, aluminum, copper, etc.

[0076] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 13 , a second substrate 104 b is provided. In various embodiments, the second substrate 104 b may be any type of semiconductor body (e.g., silicon, SiGe, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or epitaxial layer associated therewith.

[0077] like Fig.14As shown in the cross-sectional view 1400 of FIG. 14 , a plurality of pixel support devices 116 are formed on and / or within the front side 105a of the second substrate 104b. In some embodiments, the plurality of pixel support devices 116 may include a reset transistor, a source follower transistor, a row select transistor, etc. In some embodiments, the plurality of pixel support devices 116 may be formed by depositing a gate dielectric film and a gate electrode film on the second substrate 104b, and then patterning the gate dielectric film and the gate electrode film to form a gate dielectric layer and a gate electrode. The second substrate 104b may then be implanted to form a source / drain region within the second substrate 104a and on the opposite side of the gate electrode.

[0078] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 15, a second interconnect structure 112b is formed on the front side 105a of the second substrate 104b. The second interconnect structure 112b includes a second plurality of interconnects 114b formed within a second ILD structure 113b including one or more ILD layers. In some embodiments, the second interconnect structure 112b may be formed using a damascene process (e.g., a single damascene process and / or a dual damascene process).

[0079] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , the second substrate 104b is bonded to the first substrate 104a such that one or more regions of the second substrate 104a are laterally located outside the pixel support device 116 and vertically located below the pixel array 108. In various embodiments, the second substrate 104b may be bonded to the first substrate 104a by a bonding process that forms a bonding interface including a dielectric interface and a metal interface. In some embodiments, the first substrate 104a may be bonded to the second substrate 104b along a bonding interface including a first conductive bonding structure 304a and a second conductive bonding structure 304b.

[0080] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 1 , the thickness of the second substrate 104b is reduced. In some embodiments, the thickness of the second substrate 104a can be reduced by performing a first grinding process on the second substrate 104b to reduce the thickness of the second substrate 104b from the first thickness 1702 to a second thickness 1704 that is less than the first thickness 1702. In some embodiments, the first thickness 1702 can be within a first range of about 595 μm and about 950 μm, about 700 μm and 800 μm, or other suitable values. In some embodiments, the second thickness 1704 can be within a second range of about 0.5 μm and about 10 μm, about 1 μm and about 8 μm, or other similar values.

[0081] like Fig.18As shown in the cross-sectional view 1800 of FIG. 18 , a through substrate via (TSV) 120 is formed to extend through the second substrate 104b in one or more regions laterally outside the pixel support device 116. The TSV 120 is formed by performing an etching process to selectively etch through the second substrate 104b and / or the second interconnect structure 112b to form a TSV opening. In some embodiments, the etching process may expose the back side 105b of the second substrate 104b to an etchant. A conductive material is then formed within the TSV opening, followed by a planarization process (e.g., a CMP process).

[0082] like Fig.19 As shown in the cross-sectional view 1900 , an additional conductive bonding structure 304 d is formed within the additional dielectric structure 306 formed on the back side 105 b of the second substrate 104 b .

[0083] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 1 , a first edge trimming cut is performed on the first substrate 104a and the second substrate 104b. The first edge trimming cut removes the peripheral portion 2004 of the first substrate 104a and the second substrate 104b surrounding the central portion 2006 of the first substrate 104a. In some embodiments, the first edge trimming cut forms a recessed upper surface 2008 in the first substrate 104a. In some embodiments, the first edge trimming cut can be performed by contacting the first blade 2002 with the second substrate 104b along a closed loop. The first blade 2002 has a grinding element (e.g., diamond particles) joined to a core having a circular cross-section. When the grinding element contacts the second substrate 104b, the core is configured to rotate around a first axis.

[0084] like Fig.21 As shown in the cross-sectional view 2100 of , a third substrate 104c is provided. In various embodiments, the third substrate 104c can be any type of semiconductor body (e.g., silicon, SiGe, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or epitaxial layer associated therewith.

[0085] like Fig. 22 As shown in the cross-sectional view 2200 of FIG. 22, a plurality of logic devices 118 are formed on and / or within the third substrate 104c. In some embodiments, the plurality of logic devices 118 may include transistors formed by depositing a gate dielectric film and a gate electrode film on the third substrate 104c and then patterning the gate dielectric film and the gate electrode film to form a gate dielectric layer and a gate electrode. The third substrate 104c may then be implanted to form source / drain regions within the third substrate 104a and on opposite sides of the gate electrode.

[0086] like Fig.23As shown in the cross-sectional view 2300 of FIG. 23, the third interconnect structure 112c is formed on the front side of the third substrate 104c. The third interconnect structure 112c includes a third plurality of interconnects 114c formed within a third ILD structure 113c including one or more ILD layers. In some embodiments, the third interconnect structure 112c can be formed using a damascene process (e.g., a single damascene process and / or a dual damascene process).

[0087] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 24, the second substrate 104b is bonded to the third substrate 104c to form a semiconductor structure. In various embodiments, the second substrate 104b may be bonded to the third substrate 104c by a bonding process that forms a bonding interface including a dielectric interface and a metal interface. In some embodiments, the second substrate 104b is bonded to the third substrate 104c along a bonding interface including a third conductive bonding structure 304c and an additional conductive bonding structure 304d.

[0088] like Fig.25 As shown in the cross-sectional view 2500 of FIG. 1 , the thickness of the first substrate 104a is reduced. In some embodiments, the thickness of the first substrate 104a can be reduced by performing a second grinding process on the first substrate 104a to reduce the first substrate 104a from a first thickness 2502 to a second thickness 2504 that is less than the first thickness 2502. Thinning the first substrate 104a allows radiation to be more easily transferred to the plurality of image sensing elements 106. In various embodiments, the first substrate 104a can be thinned by etching and / or mechanically grinding the back side of the first substrate 104a.

[0089] like Fig.26 As shown in the cross-sectional view 2600 of FIG. 1 , one or more grooves 2602 are formed on the back side of the first substrate 104a. One or more grooves 2602 extend vertically from the back side of the first substrate 104a into the first substrate 104a along the opposite sides of the plurality of pixel regions 108a and 108d. In some embodiments, the one or more grooves 2602 may be formed by selectively etching the back side of the first substrate 104a with a first etching process. In some embodiments, the back side of the first substrate 104a may be selectively etched by exposing the back side of the first substrate 104a to one or more etchants according to a first mask layer. In some embodiments, the mask layer may include a photoresist, a hard mask, etc. In some embodiments, the one or more etchants may include a dry etchant. In some embodiments, the dry etchant may have an etching chemistry including one or more of oxygen (O2), nitrogen (N2), hydrogen (H2), argon (Ar), and / or fluorine substances (e.g., CF4, CHF3, C4F8, etc.).

[0090] In some additional embodiments, one or more additional trenches 2604 may be formed by selectively etching the back side of the first substrate 104a with a second etching process. In some embodiments, the first substrate 104a may be selectively etched by exposing the back side of the first substrate 104a to one or more etchants according to the second mask layer. The one or more additional trenches 2604 may extend into the first substrate 104a to a lesser depth than the one or more trenches 2602. In other additional embodiments (not shown), an isolation implant process may be performed to form an isolation implant region within the first substrate 104a.

[0091] like Fig. 27 As shown in the cross-sectional view 2700 of , one or more dielectric materials are formed in one or more trenches 2602 to form an isolation structure 308 on opposite sides of the plurality of pixel regions 108a and 108d. In some embodiments, one or more dielectric materials may be formed to arrange the inner surface of the first substrate 104a forming the one or more trenches 2602, and further cover the back side of the first substrate 104a. In some such embodiments, after forming the one or more dielectric materials, a planarization process (e.g., a chemical mechanical planarization (CMP) process) may be performed to remove the one or more dielectric materials from the back side of the first substrate 104a. In some embodiments, the one or more dielectric materials may be formed by a vapor deposition process (e.g., a chemical vapor deposition (CVD) process, a plasma enhanced CVD process, etc.). In other embodiments, the one or more dielectric materials may be formed by an atomic layer deposition (ALD) process. One or more dielectric materials may also be formed in one or more additional trenches 2604 to form one or more additional isolation regions 310.

[0092] like Fig.28 As shown in the cross-sectional view 2800 of FIG. 28 , the semiconductor structure is singulated to form one or more integrated chip dies 2802. In some embodiments, the semiconductor structure can be separated by a dicing process by mounting the semiconductor structure on an adhesive surface of a dicing tape 2804. Then, a wafer saw cuts the wafer along scribe lines 2806 to separate the wafer into one or more integrated chip dies 2802.

[0093] like Fig.29 As shown in the cross-sectional view 2900, from the cutting belt ( Fig.28 2804) to remove one or more integrated chip dies 2802.

[0094] like Fig.30As shown in the cross-sectional view 3000 of , a plurality of color filters 314 are formed on the first substrate 104a. In some embodiments, the plurality of color filters 314 are formed by depositing (e.g., by CVD, PVD, ALD, sputtering, spin coating process, etc.) a filter material on the first substrate 104a. The filter material is a material that allows the transmission of radiation (e.g., light) having a specific wavelength range while blocking light of wavelengths outside the specified range. Subsequently, in some embodiments, a planarization process (e.g., CMP) may be performed on the plurality of color filters 314 to planarize the upper surfaces of the plurality of color filters 314.

[0095] A plurality of microlenses 316 are formed on the plurality of color filters 314. In some embodiments, the plurality of microlenses 316 may be formed by depositing a microlens material on the plurality of color filters 314 (e.g., by CVD, PVD, ALD, sputtering, spin coating processes, etc.). A microlens template (not shown) having a curved upper surface is patterned over the microlens material. In some embodiments, the microlens template may include a photoresist material exposed using a distributed exposure light dose (e.g., for a negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed, and baked to form a circular shape. Then, the plurality of microlenses 316 are formed by selectively etching the microlens material according to the microlens template.

[0096] Fig.31 A flow chart illustrating some embodiments of a method 3100 of forming an image sensor integrated chip structure including TSVs located below a pixel array including a dummy pixel region.

[0097] Although the disclosed methods (e.g., methods 3100 and 5200) are shown and described herein as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be interpreted as limiting. For example, some actions may occur in a different order and / or concurrently with other actions or events than those shown and / or described herein. In addition, not all of the actions shown are required to implement one or more aspects or embodiments described herein. In addition, one or more of the actions described herein may be performed in one or more separate actions and / or stages.

[0098] At act 3102, a first IC level is formed to include a plurality of image sensing elements within a pixel array within a first substrate. The pixel array includes a plurality of active pixel regions surrounding one or more dummy pixel regions. In some embodiments, the first IC level can be formed according to acts 3104-3108.

[0099] At act 3104, a plurality of image sensing elements are formed in a first substrate within a pixel array having a plurality of active pixel regions surrounding one or more dummy pixel regions. Fig.11A cross-sectional view 1100 of some embodiments corresponding to act 3104 is shown.

[0100] At act 3106, a transfer gate is formed on the front side of the first substrate. Fig.12 A cross-sectional view 1200 of some embodiments corresponding to act 3106 is shown.

[0101] At act 3108, a first interconnect structure is formed on the front side of the first substrate. Fig.12 A cross-sectional view 1200 of some embodiments corresponding to act 3108 is shown.

[0102] At act 3110, a second IC level is formed to include a plurality of pixel support devices on a second substrate. In some embodiments, the second IC level may be formed according to acts 3112-3114.

[0103] At act 3112, a plurality of pixel support devices are formed on a second substrate. Fig.14 A cross-sectional view 1400 of some embodiments corresponding to act 3112 is shown.

[0104] At act 3114, a second interconnect structure is formed on the front side of the second substrate. Fig.15 A cross-sectional view 1500 of some embodiments corresponding to act 3114 is shown.

[0105] At act 3116, the first substrate is bonded to the second substrate such that one or more regions of the second substrate are laterally outward of the pixel support device and vertically below the pixel array. Fig.16 A cross-sectional view 1600 of some embodiments corresponding to act 3116 is shown.

[0106] At act 3118, through substrate vias (TSVs) are formed to extend through one or more regions of the second substrate. Fig.18 A cross-sectional view 1800 of some embodiments corresponding to act 3118 is shown.

[0107] At act 3120, a third IC level is formed to include a plurality of logic devices on a third substrate. In some embodiments, the third IC level can be formed according to acts 3122-3124.

[0108] At act 3122, a plurality of logic devices are formed on a third substrate. Fig. 22 A cross-sectional view 2200 of some embodiments corresponding to act 3122 is shown.

[0109] At act 3124, a third interconnect structure is formed on the front side of the third substrate. Fig.23A cross-sectional view 2300 of some embodiments corresponding to act 3124 is shown.

[0110] At act 3126, a third substrate is bonded to the second substrate. Fig.24 A cross-sectional view 2400 of some embodiments corresponding to act 3126 is shown.

[0111] At act 3128, a plurality of color filters are formed on the back side of the first substrate. Fig.30 A cross-sectional view 3000 of some embodiments corresponding to act 3128 is shown.

[0112] At act 3130, a plurality of microlenses are formed on the plurality of color filters. Fig.30 A cross-sectional view 3000 of some embodiments corresponding to act 3130 is shown.

[0113] Figure 32-Figure 51 Cross-sectional views of some additional embodiments of methods of forming a multi-dimensional image sensor integrated chip structure including TSVs located below a pixel array including a dummy pixel region are shown. Figure 32-Figure 51 It is described with respect to a method, but it should be understood that the structure disclosed in the method is not limited to the method, but can exist independently as a structure independent of the method.

[0114] like Fig.32 As shown in the cross-sectional view 3200, a first substrate 104a is provided.

[0115] like Fig.33 As shown in the cross-sectional view 3300 of , a plurality of image sensing elements 106 are formed in a plurality of pixel regions 108a and 108d in the pixel array 108 in the first substrate 104a. In some embodiments, the plurality of pixel regions 108a and 108d may include a plurality of active pixel regions 108a and one or more dummy pixel regions 108d. In some embodiments, a floating diffusion region 302 may also be formed in the first substrate 104a.

[0116] like Fig.34 As shown in the cross-sectional view 3400 of FIG. 34 , a plurality of transmission gates 110 are formed in a plurality of active pixel regions 108a along the front side of the first substrate 104a. A first interconnect structure 112a is formed on the front side of the first substrate 104a. The first interconnect structure 112a includes a first plurality of interconnects 114a formed in a first ILD structure 113a including one or more ILD layers.

[0117] like Fig.35 As shown in the cross-sectional view 3500, a second substrate 104b is provided.

[0118] like Fig.36As shown in the cross-sectional view 3600 of FIG. 36 , a plurality of pixel support devices 116 are formed on and / or within the second substrate 104 b. In some embodiments, the plurality of pixel support devices 116 may include a reset transistor, a source follower transistor, a row selection transistor, and the like.

[0119] like Fig.37 As shown in the cross-sectional view 3700 of FIG. 37 , the second interconnect structure 112b is formed on the front side 105a of the second substrate 104b. The second interconnect structure 112b includes a second plurality of interconnects 114b formed within a second ILD structure 113b including one or more ILD layers.

[0120] like Fig.38 As shown in the cross-sectional view 3800 of FIG. 38 , a third substrate 104c is provided. In various embodiments, the third substrate 104c may be any type of semiconductor body (e.g., silicon, SiGe, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or epitaxial layer associated therewith.

[0121] like Fig.39 As shown in the cross-sectional view 3900 , a plurality of logic devices 118 are formed on and / or within the third substrate 104 c .

[0122] like Fig.40 As shown in the cross-sectional view 4000 of FIG. 4000 , the third interconnect structure 112c is formed on the front side of the third substrate 104c. The third interconnect structure 112c includes a third plurality of interconnects 114c formed within a third ILD structure 113c including one or more ILD layers.

[0123] like Fig.41 As shown in the cross-sectional view 4100 of FIG. 41 , the second substrate 104b is bonded to the third substrate 104c. In various embodiments, the second substrate 104b may be bonded to the third substrate 104c by a bonding process that forms a bonding interface including a dielectric interface and a metal interface.

[0124] like Fig.42 As shown in the cross-sectional view 4200 of FIG. 4201 , the thickness of the second substrate 104b is reduced. In some embodiments, the thickness of the second substrate 104b can be reduced from the first thickness 4202 to a second thickness 4204 that is smaller than the first thickness 4202.

[0125] like Fig.43As shown in the cross-sectional view 4300 of FIG. 43, TSV 120 is formed to extend through second substrate 104b in one or more regions laterally outside pixel support device 116. TSV 120 is formed by performing an etching process to selectively etch through second substrate 104b and / or second interconnect structure 112b to form a TSV opening exposing one of the second plurality of interconnects 114b. In some embodiments, the etching process may expose the back side 105b of second substrate 104b to an etchant. A conductive material is then formed within the TSV opening, followed by a planarization process (e.g., a CMP process).

[0126] like Fig.44 As shown in the cross-sectional view 4400 , an additional conductive bonding structure 304 d is formed within the additional dielectric structure 306 formed on the back side 105 b of the second substrate 104 b.

[0127] like Fig.45 As shown in the cross-sectional view 4500 of FIG. 45, a first edge trimming cut is performed on the third substrate 104c and the second substrate 104b. The first edge trimming cut removes the peripheral portion 4504 of the third substrate 104c and the second substrate 104b surrounding the central portion 4506 of the third substrate 104c and the second substrate 104b. In some embodiments, the first edge trimming cut forms a recessed upper surface 4508 in the third substrate 104c. In some embodiments, the first edge trimming cut can be performed by contacting the first blade 4502 with the second substrate 104b along a closed loop.

[0128] like Fig.46 As shown in the cross-sectional view 4600 of FIG. 46A , the first substrate 104a is bonded to the additional dielectric structure 306 to form a semiconductor structure having TSVs 120 in one or more regions laterally outside the pixel support device 116 and directly below the pixel array 108. In some embodiments, the TSVs 120 may be directly below the dummy pixel region 108d. In various embodiments, the first substrate 104a may be bonded to the additional dielectric structure 306 by a bonding process that forms a bonding interface including a dielectric interface and a metal interface.

[0129] like Fig.47 As shown in the cross-sectional view 4700 of , the thickness of the first substrate 104a is reduced. In some embodiments, the thickness of the first substrate 104a can be reduced by performing a second grinding process on the first substrate 104a to reduce the first substrate 104a from a first thickness 4702 to a second thickness 4704 that is less than the first thickness 4702.

[0130] like Fig.48As shown in the cross-sectional view 4800 of FIG. 48, a second edge trimming cut is performed in a peripheral portion 4804 of the first substrate 104a around a central portion 4806. The second edge trimming cut removes the peripheral portion 4804 of the first substrate 104a. In some embodiments, the second edge trimming cut can be performed by contacting the second blade 4802 with the first substrate 104a along a closed loop.

[0131] like Fig.49 As shown in the cross-sectional view 4900 of FIG. 49A , the isolation structure 308 is formed in the back side of the first substrate 104a along the opposite sides of the plurality of pixel regions 108a and 108d. In some embodiments, the isolation structure 308 can be formed by forming one or more dielectric materials in one or more trenches 2602 etched along the back side of the first substrate 104a. In some embodiments, one or more additional isolation regions 310 can be formed in the back side of the first substrate 104a above the floating diffusion region 302.

[0132] like Fig.50 As shown in the cross-sectional view 5000 of FIG. 2 , the semiconductor structure is singulated to form one or more integrated chip dies 2802. In some embodiments, the semiconductor structure can be singulated by a dicing process by mounting the semiconductor structure on an adhesive surface of a dicing tape 2804. Then, a wafer saw dices the wafer along scribe lines 2806 to separate the wafer into one or more integrated chip dies 2802.

[0133] like Fig.51 As shown in the cross-sectional view 5100 of FIG. 51 , a plurality of color filters 314 are formed on the first substrate 104 a . A plurality of micro lenses 316 are formed on the plurality of color filters 314 .

[0134] Fig.52 A flow chart illustrating some additional embodiments of a method 5200 of forming an image sensor integrated chip structure including TSVs located below a pixel array including a dummy pixel region.

[0135] At act 5202, a first IC level is formed to include a plurality of image sensing elements within a pixel array within a first substrate. The pixel array includes a plurality of active pixel regions surrounding one or more dummy pixel regions. In some embodiments, the first IC level can be formed according to acts 5204-5208.

[0136] At act 5204, a plurality of image sensing elements are formed in a first substrate within a pixel array having a plurality of active pixel regions surrounding one or more dummy pixel regions. Fig.33 A cross-sectional view 3300 of some embodiments corresponding to action 5204 is shown.

[0137] At act 5206, a transfer gate is formed on the front side of the first substrate. Fig.34 A cross-sectional view 3400 of some embodiments corresponding to action 5206 is shown.

[0138] At act 5208, a first interconnect structure is formed on the front side of the first substrate. Fig.34 A cross-sectional view 3400 of some embodiments corresponding to action 5208 is shown.

[0139] At act 5210, a second IC level is formed to include a plurality of pixel support devices on a second substrate. In some embodiments, the second IC level can be formed according to acts 5212-5214.

[0140] At action 5212, a plurality of pixel support devices are formed on the front side of the second substrate. Fig.36 A cross-sectional view 3600 of some embodiments corresponding to act 5212 is shown.

[0141] At act 5214, a second interconnect structure is formed on the front side of the second substrate. Fig.37 A cross-sectional view 3700 of some embodiments corresponding to action 5214 is shown.

[0142] At act 5216, a third IC level is formed to include a plurality of logic devices on a third substrate. In some embodiments, the third IC level can be formed according to acts 5218-5220.

[0143] At act 5218, a plurality of logic devices are formed on the third substrate. Fig.39 A cross-sectional view 3900 of some embodiments corresponding to action 5218 is shown.

[0144] At act 5220, a third interconnect structure is formed on the front side of the third substrate. Fig.40 A cross-sectional view 4000 of some embodiments corresponding to act 5220 is shown.

[0145] At act 5222, the front side of the third substrate is bonded to the front side of the second substrate. Fig.41 A cross-sectional view 4100 of some embodiments corresponding to action 5222 is shown.

[0146] At act 5224, through substrate vias (TSVs) are formed to extend through one or more regions of the second substrate laterally outward from the one or more pixel support devices. Fig.43 A cross-sectional view 4300 of some embodiments corresponding to action 5224 is shown.

[0147] At act 5226, the front side of the first substrate is bonded to the back side of the second substrate such that the TSVs are located within the one or more regions and directly below the pixel array. Fig.46 A cross-sectional view 4600 of some embodiments corresponding to action 5226 is shown.

[0148] At act 5228, a plurality of color filters are formed on the back side of the first substrate. Fig.51 Cross-sectional view 5100 of some embodiments corresponding to action 5228 is shown.

[0149] At act 5230, a plurality of microlenses are formed on the plurality of color filters. Fig.51 Cross-sectional view 5100 of some embodiments corresponding to action 5230 is shown.

[0150] Therefore, the present invention is directed to a multi-dimensional image sensor integrated chip (IC) structure having one or more through substrate vias (TSVs) disposed directly below a pixel array having one or more dummy pixel regions.

[0151] In some embodiments, the present disclosure relates to a multi-dimensional image sensor integrated chip (IC) structure. The multi-dimensional image sensor IC structure includes: a plurality of image sensing elements, arranged in a plurality of pixel regions in a pixel array arranged in a first integrated chip (IC) level, wherein the plurality of pixel regions include a plurality of active pixel regions and one or more dummy pixel regions; a plurality of pixel support devices, arranged on a second substrate in a second IC level bonded to the first IC level; a plurality of logic devices, arranged in a third IC level bonded to the second IC level; and a through-substrate via (TSV), extending vertically through a second substrate located laterally outside the plurality of pixel support devices and directly below the pixel array. In some embodiments, the multi-dimensional image sensor IC structure further includes: a plurality of transmission gates, arranged on a first substrate of the first IC level, and respectively arranged in one of the plurality of active pixel regions, wherein, in a cross-sectional perspective, the TSV is laterally located between a first transmission gate and a second transmission gate in the plurality of transmission gates. In some embodiments, the multi-dimensional image sensor IC structure further includes: one or more dummy image sensing elements, arranged in one or more dummy pixel regions, wherein the one or more dummy image sensing elements are electrically isolated from the plurality of pixel support devices. In some embodiments, the first IC level includes a first interconnect structure disposed on a first substrate, the first interconnect structure having no interconnect directly below one or more dummy pixel regions. In some embodiments, in a top-down perspective of the pixel array, one or more dummy pixel regions are laterally surrounded by multiple active pixel regions along a first direction and along a second direction perpendicular to the first direction. In some embodiments, the multidimensional image sensor IC structure further includes: one or more peripheral TSVs extending vertically through the second substrate at one or more positions laterally outside the pixel array. In some embodiments, the multiple active pixel regions have a first width, and the one or more dummy pixel regions have a second width, the first width being different from the second width, as measured along a cross section. In some embodiments, the multidimensional image sensor IC structure further includes: one or more additional through-substrate vias (TSVs) extending vertically through a second substrate laterally outside a plurality of pixel support devices and directly below the pixel array, wherein the TSVs and the one or more additional TSVs are arranged along a cross section between adjacent active pixel regions in a plurality of active pixel regions. In some embodiments, the TSVs extend vertically through the second substrate directly below the one or more dummy pixel regions. In some embodiments, the multi-dimensional image sensor IC structure further includes: one or more transfer gates arranged on a first substrate of a first IC level and located in corresponding active pixel regions among a plurality of active pixel regions, wherein the first substrate has no transfer gates in one or more dummy pixel regions.

[0152] In other embodiments, the present invention relates to an image sensor IC structure. The image sensor IC structure includes: a pixel array, including a plurality of image sensing elements arranged in a plurality of pixel regions of a first substrate, wherein the plurality of pixel regions include a plurality of active pixel regions laterally surrounding one or more dummy pixel regions; a plurality of pixel support devices, arranged in a second substrate stacked on the first substrate and coupled to a second interconnect structure on the second substrate, wherein the plurality of active pixel regions respectively include one or more of the plurality of image sensing elements electrically coupled to the plurality of pixel support devices; a plurality of logic devices, arranged on a third substrate stacked on the second substrate and coupled to a third interconnect structure on the third substrate; and a through substrate via (TSV), extending vertically through the second substrate directly below the pixel array and laterally outside the plurality of pixel support devices. In some embodiments, the plurality of pixel support devices are arranged directly below the plurality of active pixel regions, and the TSV is arranged directly below the one or more dummy pixel regions. In some embodiments, the plurality of pixel support devices are arranged directly below the one or more dummy pixel regions, and the TSV is arranged directly below the plurality of active pixel regions. In some embodiments, the TSV is part of a TSV array arranged between the sides of the plurality of active pixel regions facing each other. In some embodiments, the one or more dummy pixel regions include one or more dummy image sensing elements of the plurality of image sensing elements, the one or more dummy image sensing elements being electrically isolated from the plurality of pixel support devices. In some embodiments, the TSV electrically connects the second interconnect structure to the third interconnect structure.

[0153] In other embodiments, the present invention relates to a method for forming an image sensor IC structure. The method includes: forming a first integrated chip (IC) level including a plurality of image sensing elements within a pixel array in a first substrate, the pixel array including a plurality of active pixel areas surrounding one or more dummy pixel areas; forming a second IC level including a plurality of pixel support devices on a second substrate; bonding the first IC level to the second IC level so that one or more regions of the second substrate are laterally located outside the plurality of pixel support devices and vertically located directly below the pixel array; forming through substrate vias (TSVs) to extend through one or more regions of the second substrate; forming a third IC level including a plurality of logic devices on a third substrate; and bonding the third IC level to the second IC level. In some embodiments, the method also includes: bonding the front side of the first substrate to the front side of the second substrate; and bonding the front side of the third substrate to the back side of the second substrate. In some embodiments, the method also includes: etching the back side of the second substrate to form a TSV opening extending through the second substrate; and forming a TSV within the TSV opening. In some embodiments, the plurality of image sensing elements include one or more dummy image sensing elements located within the one or more dummy pixel regions, wherein the TSV is located directly below the one or more dummy image sensing elements after bonding the first substrate to the second substrate.

[0154] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A multi-dimensional image sensor integrated chip structure, comprising: a plurality of image sensing elements disposed in a plurality of pixel regions in a pixel array arranged at a first integrated chip level, wherein the plurality of pixel regions include a plurality of active pixel regions and one or more dummy pixel regions; a plurality of pixel support devices disposed on a second substrate within a second integrated chip level bonded to the first integrated chip level; a plurality of logic devices disposed in a third integrated chip level coupled to the second integrated chip level; and The substrate through hole vertically extends through the second substrate located laterally outside the plurality of pixel support devices and directly below the pixel array.

2. The multi-dimensional image sensor integrated chip structure according to claim 1, further comprising: A plurality of transmission gates are arranged on the first substrate of the first integrated chip level and are respectively set in one active pixel area among the plurality of active pixel areas, wherein, from a cross-sectional perspective, the substrate through hole is laterally located between a first transmission gate and a second transmission gate among the plurality of transmission gates.

3. The multi-dimensional image sensor integrated chip structure according to claim 1, further comprising: One or more dummy image sensing elements are disposed in the one or more dummy pixel regions, wherein the one or more dummy image sensing elements are electrically isolated from the plurality of pixel support devices.

4. The multi-dimensional image sensor integrated chip structure according to claim 1, further comprising: One or more peripheral substrate through-holes extend vertically through the second substrate at one or more locations laterally outside the pixel array.

5. The multi-dimensional image sensor integrated chip structure according to claim 1, wherein: The plurality of active pixel regions have a first width measured along a cross section, and the one or more dummy pixel regions have a second width, the first width being different from the second width.

6. The multi-dimensional image sensor integrated chip structure according to claim 1, further comprising: One or more additional substrate through holes extend vertically through the second substrate laterally located outside the multiple pixel support devices and directly below the pixel array, wherein the substrate through holes and the one or more additional substrate through holes are arranged along the cross section between adjacent active pixel areas among the multiple active pixel areas.

7. The multi-dimensional image sensor integrated chip structure according to claim 1, wherein: The through-substrate via vertically extends through the second substrate directly below the one or more dummy pixel regions.

8. An image sensor integrated chip structure, comprising: A pixel array comprising a plurality of image sensing elements disposed within a plurality of pixel regions of a first substrate, wherein the plurality of pixel regions include a plurality of active pixel regions laterally surrounding one or more dummy pixel regions; a plurality of pixel support devices disposed in a second substrate stacked on the first substrate and coupled to a second interconnect structure on the second substrate, wherein the plurality of active pixel regions respectively include one or more of the plurality of image sensing elements electrically coupled to the plurality of pixel support devices; a plurality of logic devices disposed on a third substrate stacked on the second substrate and coupled to a third interconnect structure on the third substrate; and The substrate through hole vertically extends through the second substrate located directly below the pixel array and laterally outside the plurality of pixel support devices.

9. A method for forming an image sensor integrated chip structure, comprising: forming a first integrated chip level including a plurality of image sensing elements within a pixel array in a first substrate, the pixel array including a plurality of active pixel regions surrounding one or more dummy pixel regions; forming a second integrated chip level including a plurality of pixel support devices on a second substrate; bonding the first integrated chip level to the second integrated chip level such that one or more regions of the second substrate are laterally located outside of the plurality of pixel support devices and vertically located directly below the pixel array; forming a through substrate via to extend through the one or more regions of the second substrate; forming a third integrated chip level including a plurality of logic devices on a third substrate; as well as The third integrated chip level is bonded to the second integrated chip level.

10. The method according to claim 9, further comprising: bonding the front side of the first substrate to the front side of the second substrate; as well as The front side of the third substrate is bonded to the back side of the second substrate.

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