Back contact battery and preparation method thereof

Abstract

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell and a preparation method thereof.The preparation method comprises the following specific isolation groove grooving post-texturing process that a laminated conductive film layer is deposited on the back face, the laminated conductive film layer comprises a non-acid-resistant transparent conductive film and an acid-resistant laser absorbing metal layer which are formed in sequence, the thickness ratio of the non-acid-resistant transparent conductive film to the laser absorption metal layer is 1: (0.20-0.70), and the corrosion time of the laser absorption metal layer in an HCl solution with the temperature being 20 DEG C and the mass concentration being 15 wt% is 5-7 times that of the non-acid-resistant transparent conductive film under the same condition. According to the invention, precise laser grooving is realized, the isolation groove with a good insulation effect is formed, the leakage current of the battery is reduced, and the reliability and conversion efficiency of the battery are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a back contact battery and a preparation method thereof. Background Art

[0002] At present, the process flow of back-contact batteries is generally as follows: the first semiconductor layer is plated on the back of the silicon wafer; the first mask layer is plated after removing PSG and backwashing; an opening is made on the back of the silicon wafer by laser or etching, and the first mask layer and part of the first semiconductor layer are removed to form a second semiconductor opening area; the silicon wafer is textured and cleaned to form a pyramid texture surface on the front of the silicon wafer, and at the same time, the remaining first semiconductor layer in the second semiconductor opening area is removed from the back of the silicon wafer, and then the remaining first mask layer is removed; a passivation layer and an anti-reflection layer are deposited on the front of the silicon wafer, and a second semiconductor layer is deposited on the back; an opening is etched on the back of the silicon wafer to form a first semiconductor opening area alternately arranged with the second semiconductor opening area; a transparent conductive film is deposited on the back of the silicon wafer; an isolation groove is formed between the first semiconductor opening area and the second semiconductor opening area in the corresponding area at the junction of the textured surface and the polished surface by etching; a silver paste gate line electrode is formed on the corresponding area of ​​the first semiconductor opening area and the second semiconductor opening area of ​​the silicon wafer.

[0003] In the post-texturing process of the prior art, when an isolation groove is formed in the corresponding area at the junction of the textured surface and the polished surface after the transparent conductive film is deposited, the isolation groove is set between the first semiconductor opening area and the second semiconductor opening area, that is, between the textured surface and the polished surface to ensure the insulation effect. Acid etching is generally used, which is better than laser grooving. This is because laser grooving will damage the semiconductor functional layer, especially the second semiconductor opening area (textured surface). Because of the presence of pyramids on the textured surface, when the laser hits it, light scattering in different directions is easy to occur. This process is uncontrollable. The isolation groove formed by laser grooving has the defect that the second semiconductor layer is easily damaged, which will be directly reflected in the decrease of Voc in the battery performance and the poor reliability of the battery. Therefore, it is difficult to achieve simple laser grooving on the textured surface. However, the acid etching method has the disadvantage of high etching alignment accuracy.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects in the prior art that the isolation grooves in the back-texturing method of the back-contact battery cannot be laser-grooved and the battery reliability and battery conversion efficiency cannot be taken into account. A method for preparing a back-contact battery is provided, which realizes precise laser grooving to form isolation grooves with good insulation effect, which is beneficial to reduce battery leakage current while taking into account improving battery reliability and battery conversion efficiency.

[0006] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a method for preparing a back contact battery, comprising the following specific isolation groove post-texturing process: S00, forming a first semiconductor layer on the back side of the silicon wafer, and then forming a second semiconductor opening area; then performing texturing and cleaning, forming a texturing surface on the front side of the silicon wafer and the second semiconductor opening area, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polishing surface; then depositing a second semiconductor layer on the back side, and then forming a first semiconductor opening area on a portion of the second semiconductor layer, which is spaced apart from the second semiconductor opening area; S07, then depositing a laminated conductive film layer on the back side, the laminated conductive film layer comprising an acid-resistant transparent conductive film and an acid-resistant laser absorption metal layer formed in sequence, wherein the thickness ratio of the acid-resistant transparent conductive film to the laser absorption metal layer is 1:0.20-0.70, the corrosion time of the acid-resistant transparent conductive film in a 15wt% HCl solution at a temperature of 20°C is 15-30s, the corrosion time of the laser absorption metal layer in a 15wt% HCl solution at a temperature of 20°C is 5-7 times the corrosion time of the acid-resistant transparent conductive film under the same conditions, and the absorptivity ratio of the acid-resistant transparent conductive film to the laser absorption metal layer at a wavelength of 320-1100nm is 1:250-500; S08, performing a third groove on a portion of the laminated conductive film layer in the target area between the first semiconductor opening area and the second semiconductor opening area, forming an isolation groove in a corresponding area at the junction of the textured surface and the polished surface, the third groove process comprising: firstly etching the laser absorption metal layer in the target area with a laser, and then etching away the acid-resistant transparent conductive film in the target area with hydrochloric acid; S10, forming metal fine gate electrodes on the outer surfaces of the corresponding stacked conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0007] In some preferred embodiments of the present invention, the acid-intolerant transparent conductive film has a thickness of 40-80 nm.

[0008] In some preferred embodiments of the present invention, the corrosion time of the laser absorbing metal layer in a 15 wt % HCl solution at a temperature of 20° C. is 100-200 s.

[0009] In some preferred embodiments of the present invention, the acid-intolerant transparent conductive film is selected from an indium tin oxide film and / or a tungsten-doped indium oxide film.

[0010] In some preferred embodiments of the present invention, the laser absorbing metal layer includes at least one of a nickel metal layer, a nickel-copper alloy layer, a titanium metal layer, and a nickel-titanium alloy layer.

[0011] In some preferred embodiments of the present invention, the thickness of the laser absorbing metal layer is 10-30 nm.

[0012] In some preferred embodiments of the present invention, the mass concentration of hydrochloric acid in S08 is 20%-30%.

[0013] In some preferred embodiments of the present invention, the conditions for hydrochloric acid corrosion in S08 include: hydrochloric acid temperature is 20-40° C., and corrosion time is 15-30 s.

[0014] In some preferred embodiments of the present invention, the laser used for the laser etching in S08 is a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser.

[0015] In some preferred embodiments of the present invention, the conditions for laser etching include: the power of the laser is 20-60 kW, the frequency is 200-500 kHz, and the spot size is 30-150 μm.

[0016] In some preferred embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, and the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer.

[0017] In some preferred embodiments of the present invention, the width W1 of the second semiconductor opening region is 300-700 μm, the width W2 of the first semiconductor opening region is 150-350 μm, and the width WgL of the isolation trench is 30-150 μm.

[0018] In some preferred embodiments of the present invention, the process of S00 specifically includes: S01. Provide double-sided polished silicon wafers; S02, sequentially forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; S03, performing a first opening on the back surface obtained in S02 to form a second semiconductor opening region; S04, forming a textured surface on the front side of the silicon wafer and the second semiconductor opening area through texturing and cleaning, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polished surface, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs; S05, depositing a second semiconductor layer on the back surface obtained in S04; S06. Perform a second opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region.

[0019] In some preferred embodiments of the present invention, the method for preparing the back-contact cell further comprises: before or after depositing the second semiconductor layer, sequentially depositing a passivation layer and an anti-reflection layer on the front side of the silicon wafer.

[0020] In some preferred embodiments of the present invention, the method for preparing a back-contact battery further includes: S11, forming an insulating ink layer arranged at intervals on the outer surface of the metal fine gate electrode on the back side of the silicon wafer, and then forming a metal main gate electrode on the outer surface of the back side.

[0021] In a first aspect, the present invention provides a back-contact battery, which is prepared by the method for preparing a back-contact battery described in the first aspect.

[0022] Beneficial effects: The present invention adopts the above-mentioned technical scheme, and in the post-texturing method, adopts a laminated conductive film layer including a specific acid-resistant transparent conductive film and an acid-resistant laser absorbing metal layer. By utilizing the different acid resistances and laser absorption rates of the acid-resistant transparent conductive film and the acid-resistant laser absorbing metal layer, and a suitable thickness ratio, when forming the isolation groove at the junction of the texturing area and the polishing area, laser grooving can be first performed to etch away the laser absorbing metal layer of the target area, and then hydrochloric acid can be used to corrode the acid-resistant transparent conductive film of the target area, while retaining the laser absorbing metal layer of other areas, thereby achieving the effect of insulating grooving without damaging the corresponding passivation layer of the second semiconductor layer by laser grooving, without causing side etching problems, with good insulation effect, and beneficial to reducing battery leakage current; and the acid-resistant transparent conductive film used in the back contact battery structure obtained by the present invention is covered with a laser absorbing metal layer, which can effectively protect the acid-resistant transparent conductive film, help improve battery reliability, and thus improve battery conversion efficiency.

[0023] Among them, the acid-resistant transparent conductive film and the acid-resistant laser absorbing metal layer with different corrosion rates in hydrochloric acid are specially used, and the subsequent hydrochloric acid corrosion is combined to complete the purpose of local precise corrosion and grooving without damaging other film layers and causing side corrosion problems, which is beneficial to improving the insulation effect of the isolation groove and effectively reducing the battery leakage current. Under the same conditions, if hydrochloric acid is replaced by hydrofluoric acid, the acidity of hydrofluoric acid is relatively strong, and it is easy to corrode the acid-resistant transparent conductive film and the laser absorbing metal layer at the same time during the wet corrosion stage, which is not conducive to the retention of the laser absorbing metal layer and the reliability of the battery.

[0024] In the preferred embodiment of the present invention, a combined passivation structure is adopted, which is combined with a specific isolation groove cutting method to further reduce the battery leakage current. DETAILED DESCRIPTION

[0025] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0026] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0027] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0028] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0029] In a first aspect, the present invention provides a method for preparing a back contact battery, comprising the following specific isolation groove post-texturing process: S00, forming a first semiconductor layer on the back side of the silicon wafer, and then forming a second semiconductor opening area; then performing texturing and cleaning, forming a texturing surface on the front side of the silicon wafer and the second semiconductor opening area, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polishing surface; then depositing a second semiconductor layer on the back side, and then forming a first semiconductor opening area on a portion of the second semiconductor layer, which is spaced apart from the second semiconductor opening area; S07, then depositing a laminated conductive film layer on the back side, the laminated conductive film layer comprises an acid-resistant transparent conductive film and an acid-resistant laser absorbing metal layer formed in sequence, wherein the thickness ratio of the acid-resistant transparent conductive film to the laser absorbing metal layer is 1:0.20-0.70, preferably 1:0.30-0.70, the corrosion time of the acid-resistant transparent conductive film in a 15wt% HCl solution at a temperature of 20°C is 15-30s, the corrosion time of the laser absorbing metal layer in a 15wt% HCl solution at a temperature of 20°C is 5-7 times, preferably 6-7 times, the corrosion time of the acid-resistant transparent conductive film under the same conditions, and the absorptivity ratio of the acid-resistant transparent conductive film to the laser absorbing metal layer at a wavelength of 320-1100nm is 1:250-500, preferably 1:310-450; S08, performing a third groove on a portion of the laminated conductive film layer in the target area between the first semiconductor opening area and the second semiconductor opening area, forming an isolation groove in a corresponding area at the junction of the textured surface and the polished surface, the third groove process comprising: firstly etching the laser absorption metal layer in the target area with a laser, and then etching away the acid-resistant transparent conductive film in the target area with hydrochloric acid; S10, forming metal fine gate electrodes on the outer surfaces of the corresponding stacked conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0030] In some preferred embodiments of the present invention, the acid-intolerant transparent conductive film has a thickness of 40-80 nm.

[0031] In the present invention, the test method for the absorbance is: using a spectrum analyzer to measure the transmittance curve and reflectance curve of the target film layer in the full band, and converting the absorbance curve according to the principle of transmittance + reflectance + absorbance = 1. The unit of absorbance is %.

[0032] In the present invention, "corrosion time in a 15 wt% HCl solution at a temperature of 20°C" refers to the time it takes for a film layer of a certain thickness in a target area to be completely corroded under the specific conditions. It is understandable that different thicknesses will result in different corrosion times.

[0033] Preferably, the laser absorbing metal layer is etched for 100-200 seconds in a 15wt% HCl solution at a temperature of 20°C. The laser absorbing metal layer of this preferred solution is more conducive to protecting the transparent conductive film in the non-grooved area.

[0034] In some preferred embodiments of the present invention, the acid-intolerant transparent conductive film is selected from indium tin oxide film (ITO) and / or tungsten-doped indium oxide (IWO). Conventional IZO / AZO transparent conductive films are easily corroded in acid solution and are prone to side corrosion in subsequent treatments.

[0035] In some preferred embodiments of the present invention, the laser absorbing metal layer includes at least one of a nickel metal layer, a nickel-copper alloy layer, a titanium metal layer, and a nickel-titanium alloy layer, and more preferably at least one of a nickel metal layer, a nickel-copper alloy layer, and a nickel-titanium alloy layer.

[0036] In some preferred embodiments of the present invention, the thickness of the laser absorbing metal layer is 10-30 nm. The use of the laser absorbing metal layer with this preferred thickness is more conducive to protecting the transparent conductive film in the non-grooved area during the corrosion process.

[0037] In some preferred embodiments of the present invention, the mass concentration of hydrochloric acid in S08 is 20%-30%. Using this appropriate concentration of hydrochloric acid is more conducive to improving the slotting insulation effect while ensuring that the laser absorbing metal layer can effectively protect the non-slotting area.

[0038] In some preferred embodiments of the present invention, the hydrochloric acid etching conditions in S08 include: the hydrochloric acid temperature is 20-40° C., and the etching time is 15-30 seconds. This preferred solution is more conducive to completely etching the transparent conductive film in the grooved area.

[0039] In some preferred embodiments of the present invention, the laser used for laser etching in S08 is a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser, more preferably a flat-top picosecond green laser. The use of the preferred laser is more conducive to the absorption of the laser by the metal layer, thereby achieving the purpose of grooving.

[0040] In some preferred embodiments of the present invention, the laser etching conditions include: the laser power is 20-60 kW, the frequency is 200-500 kHz, and the spot size is 30-150 μm. The preferred laser etching conditions are more conducive to fully opening the isolation groove.

[0041] In some preferred embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, and the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer. The first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon or microcrystalline silicon. The second doped silicon layer can be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer.

[0042] Further preferably, the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer arranged in sequence, and the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon layer arranged in sequence. One of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type. The use of a combined passivation structure in conjunction with a specific isolation trench opening method is more conducive to improving the passivation effect, reducing current leakage current, and further improving the battery conversion efficiency.

[0043] The thickness of the tunnel oxide layer, the intrinsic amorphous silicon layer, the first doped polysilicon layer and the second doped silicon layer and the corresponding doping concentration of the tunnel oxide layer, the intrinsic amorphous silicon layer and the first doped polysilicon layer and the second doped silicon layer of the present invention can refer to the range of the prior art, and can be used in the present invention. For example, the thickness of the tunnel oxide layer is 1-2nm, the thickness of the first doped polysilicon layer is 80-200nm, and the effective doping concentration is greater than 5e18cm -3 The thickness of the intrinsic amorphous silicon layer is 5-15nm, the thickness of the second doped silicon layer is 10-15nm, and the effective doping concentration is 2e18cm -3 -3e20cm -3 .

[0044] In some preferred embodiments of the present invention, the width W1 of the second semiconductor opening region is 300-700 μm, the width W2 of the first semiconductor opening region is 150-350 μm, and the width WgL of the isolation trench is 30-150 μm.

[0045] In some preferred embodiments of the present invention, the process of S00 specifically includes: S01. Provide double-sided polished silicon wafers; S02, sequentially forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; S03, performing a first opening on the back surface obtained in S02 to form a second semiconductor opening region; S04, forming a textured surface on the front side of the silicon wafer and the second semiconductor opening area through texturing and cleaning, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polished surface, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs; S05, depositing a second semiconductor layer on the back surface obtained in S04; S06. Perform a second opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region.

[0046] The present invention may also include other conventional steps, for example, S02 also includes: after forming the first semiconductor layer, removing PSG on the surface, backwashing, and then plating a mask layer on the back side.

[0047] In some preferred embodiments of the present invention, the method for preparing the back-contact cell further comprises: before or after depositing the second semiconductor layer, sequentially depositing a passivation layer and an anti-reflection layer on the front side of the silicon wafer.

[0048] In some preferred embodiments of the present invention, the method for preparing a back-contact battery further includes: S11, forming an insulating ink layer arranged at intervals on the outer surface of the metal fine gate electrode on the back of the silicon wafer, and then forming a metal main gate electrode on the outer surface of the back. The connection structure of the metal fine gate electrode, the insulating ink layer and the metal main gate electrode can refer to the prior art and will not be described in detail here.

[0049] In a first aspect, the present invention provides a back-contact battery, which is prepared by the method for preparing a back-contact battery described in the first aspect.

[0050] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0051] Example 1 A back contact battery is prepared by the following method: S01, double-sided polishing of silicon wafer; S02, a first semiconductor layer is plated on the back of the silicon wafer, wherein the first semiconductor layer is a tunneling oxide layer with a thickness of 1.5 nm and an N-type doped polysilicon layer, wherein the thickness of the N-type doped polysilicon layer is 100 nm and the effective doping concentration is 2e20 cm -3 ; After PSG and backwashing, the back side is plated with a mask layer, which is silicon nitride; S03, opening an opening on the back side of the silicon wafer, removing the mask layer and part of the first semiconductor layer, and forming a second semiconductor opening region, wherein the width W1 of the second semiconductor opening region is 500 μm; S04, texturing and cleaning the silicon wafer, forming a pyramid texturing surface in the second semiconductor opening area and the front side of the silicon wafer, and removing the first semiconductor layer in the second semiconductor opening area on the back side of the silicon wafer, and then removing all mask layers; S05, depositing a passivation layer and an anti-reflection layer on the front side of the silicon wafer, and depositing a second semiconductor layer on the back side, wherein the second semiconductor layer is an intrinsic amorphous silicon layer with a thickness of 10 nm and a 12.5 nm thick silicon layer with an effective doping concentration of 2e19 cm -3 The P-type doped amorphous silicon layer is deposited by PECVD. S06, opening the back of the silicon wafer by laser to form a first semiconductor opening region arranged alternately with the second semiconductor opening region, wherein the width W2 of the first semiconductor opening region is 250 μm; cleaning the silicon wafer to remove the oxide layer in the first semiconductor opening region; S07, depositing a stacked conductive film layer on the back side of the silicon wafer; The laminated conductive film layer is composed of a sequentially formed acid-resistant transparent conductive film (i.e., ITO) superimposed on a laser absorbing metal layer. The laser absorbing metal layer is Ni, wherein the ITO thickness is 60nm, and its corrosion time in a HCl solution with a temperature of 20°C and a mass concentration of 15wt% is 24s. The laser absorbing metal layer is 20nm thick, and its corrosion time in a HCl solution with a temperature of 20°C and a mass concentration of 15wt% is 150s. The ratio of the absorptivity of the acid-resistant transparent conductive film and the laser absorbing metal layer at a wavelength of 320-1100nm is 1:333.

[0052] S08, forming an isolation groove between the first semiconductor opening area and the second semiconductor opening area at a corresponding area at the junction of the textured surface and the polished surface, the width WgL of the isolation groove is 100 μm, and the isolation groove is formed at the junction of the textured area and the polished area; The isolation groove is formed by first using a flat-top picosecond green laser with a power of 30 kW, a frequency of 400 kHz, and a spot size of 100 μm.

[0053] Laser etching of the laser absorbing metal layer on ITO, but due to poor absorption of ITO in the 512nm band, it cannot be etched away, so after the laser, acid (mass concentration of 20% HCl) is used to etch away the ITO, so as to achieve the effect of slot insulation. The conditions for hydrochloric acid etching include: hydrochloric acid temperature of 30°C, etching time of 20s.

[0054] S09, forming an insulating ink layer arranged at intervals on the conductive mask layer on the back side of the silicon wafer, wherein the insulating ink is formed by printing or spraying; S10, forming a silver paste fine gate electrode on the first semiconductor opening region and the second semiconductor opening region of the silicon wafer; S11. An insulating ink layer arranged in intervals is formed on the outer surface of the metal fine gate electrode on the back side of the silicon wafer, and then a metal main gate electrode is formed on the outer surface of the back side.

[0055] Example 2 The method of Example 1 is referred to, except that the acid-resistant transparent conductive film is replaced by tungsten-doped indium oxide, and the etching time in a 15wt% HCl solution at a temperature of 20°C is 30 seconds. The ratio of the absorptivity of the tungsten-doped indium oxide to the laser absorbing metal layer at a wavelength of 320-1100nm is 1:294.

[0056] Example 3 The method of Example 1 is referred to, except that the thickness of the laser absorbing metal layer is 15 nm, and the etching time in the HCl solution with a temperature of 20°C and a mass concentration of 15 wt% is 110 s. The ratio of the absorption rate of ITO and the laser absorbing metal layer at a wavelength of 320-1100 nm is 1:300.

[0057] Example 4 The method of Example 1 is referred to, except that the laser absorbing metal layer is replaced by a nickel-copper alloy layer with the same thickness, and the corrosion time in a 15wt% HCl solution at a temperature of 20°C is 130s. The ratio of the absorption rate of ITO and the laser absorbing metal layer at a wavelength of 320-1100nm is 1:366.

[0058] Example 5 The method of Example 1 is used, except that the corrosion time of hydrochloric acid corrosion is 30 seconds.

[0059] Example 6 The method of Example 1 is referred to, except that the structure of the first semiconductor layer is different, and the passivation structure is a heterojunction. Specifically, the first semiconductor layer is an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer. The thickness of the intrinsic amorphous silicon layer is 10 nm, the thickness of the N-type doped amorphous silicon layer is 60 nm, and the effective doping concentration is 1e19 cm -3 .

[0060] Comparative Example 1 The method of Example 1 is referred to, except that the laminated conductive film layer is replaced by an ITO single film layer (with unchanged thickness), and no laser absorbing metal layer is provided; and the third groove in S08 is formed by laser etching the ITO single film layer.

[0061] Comparative Example 2 The method of Example 1 is referred to, except that the thickness of the laser absorbing metal layer is adjusted so that the thickness ratio of the acid-intolerant transparent conductive film to the laser absorbing metal layer is 1:0.16.

[0062] Comparative Example 3 The method of Example 1 is followed, except that after forming an isolation groove in the corresponding area at the junction of the velvet surface and the polished surface, all remaining laser absorbing metal layers are etched away by laser, and then a metal fine gate electrode is formed on the outer surface of the acid-non-resistant transparent conductive film; that is, the laser absorbing metal layer is not retained in the final structure.

[0063] Comparative Example 4 The method of Example 1 is referred to, except that the ITO layer in the laminated conductive film layer is replaced by a zinc-doped indium oxide IZO film, whose thickness remains unchanged, and the etching time in a 15wt% HCl solution at a temperature of 20°C is 10s. The ratio of the absorptivity of the IZO film and the laser absorption metal layer at a wavelength of 320-1100nm is 1:454.

[0064] Comparative Example 5 The method of Example 1 is followed, except that the hydrochloric acid in S08 is replaced by a hydrofluoric acid solution of the same mass concentration.

[0065] Test Case The back contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. The cell reliability is characterized by cell light induced degradation, and the test method is as follows: by comparing the cell before and after light induced degradation under standard test conditions (1000W / m 2 , 25℃, AM1.5), calculate the photo-induced decay rate of the battery, photo-induced decay rate = (maximum output power before photo-induced decay - maximum output power after photo-induced decay) / maximum output power before photo-induced decay. Dark current yield refers to the proportion of qualified products in the same batch of battery production that meet the condition of IRev2<2A under the condition of reverse voltage of 15V.

[0066] Table 1

[0067] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention achieves laser precision grooving to form an isolation groove with good insulation effect, which is beneficial to reducing battery leakage current while improving battery reliability and battery conversion efficiency.

[0068] Furthermore, according to Example 1 and Examples 2-6, it can be seen that the adoption of the preferred solution of the present invention is more conducive to reducing battery leakage current, while further improving battery reliability and battery conversion efficiency.

[0069] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A method for preparing a back contact battery, characterized in that: The post-texturing process of specific isolation groove opening is as follows: S00, forming a first semiconductor layer on the back side of the silicon wafer, and then forming a second semiconductor opening area; then performing texturing and cleaning, forming a texturing surface on the front side of the silicon wafer and the second semiconductor opening area, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polishing surface; then depositing a second semiconductor layer on the back side, and then forming a first semiconductor opening area on a portion of the second semiconductor layer, which is spaced apart from the second semiconductor opening area; S07, then depositing a laminated conductive film layer on the back side, the laminated conductive film layer comprising an acid-resistant transparent conductive film and an acid-resistant laser absorption metal layer formed in sequence, wherein the thickness ratio of the acid-resistant transparent conductive film to the laser absorption metal layer is 1:0.20-0.70, the corrosion time of the acid-resistant transparent conductive film in a 15wt% HCl solution at a temperature of 20°C is 15-30s, the corrosion time of the laser absorption metal layer in a 15wt% HCl solution at a temperature of 20°C is 5-7 times the corrosion time of the acid-resistant transparent conductive film under the same conditions, and the absorptivity ratio of the acid-resistant transparent conductive film to the laser absorption metal layer at a wavelength of 320-1100nm is 1:250-500; S08, performing a third groove on a portion of the laminated conductive film layer in the target area between the first semiconductor opening area and the second semiconductor opening area, forming an isolation groove in a corresponding area at the junction of the textured surface and the polished surface, the third groove process comprising: firstly etching the laser absorption metal layer in the target area with a laser, and then etching away the acid-resistant transparent conductive film in the target area with hydrochloric acid; S10, forming metal fine gate electrodes on the outer surfaces of the corresponding stacked conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

2. The method for preparing a back contact battery according to claim 1, characterized in that: The thickness of the acid-resistant transparent conductive film is 40-80 nm; and / or, The corrosion time of the laser absorbing metal layer in a 15wt% HCl solution at a temperature of 20°C is 100-200s.

3. The method for preparing a back contact battery according to claim 1 or 2, characterized in that: The acid-inresistant transparent conductive film is selected from indium tin oxide film and / or tungsten-doped indium oxide; the laser absorption metal layer includes at least one of a nickel metal layer, a nickel-copper alloy layer, a titanium metal layer, and a nickel-titanium alloy layer.

4. The method for preparing a back contact battery according to claim 1, characterized in that: The thickness of the laser absorbing metal layer is 10-30 nm.

5. The method for preparing a back contact battery according to claim 1, characterized in that: The mass concentration of hydrochloric acid in S08 is 20%-30%, and / or, The conditions for hydrochloric acid corrosion in S08 include: hydrochloric acid temperature is 20-40°C, and corrosion time is 15-30s.

6. The method for preparing a back contact battery according to claim 1, characterized in that: The laser used for laser etching in S08 is a flat-top picosecond green laser or a flat-top picosecond ultraviolet laser; and / or, The conditions for laser etching include: the power of the laser is 20-60 kW, the frequency is 200-500 kHz, and the spot size is 30-150 μm.

7. The method for preparing a back contact battery according to claim 1, characterized in that: The first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer; and / or, The width W1 of the second semiconductor opening region is 300-700 μm, the width W2 of the first semiconductor opening region is 150-350 μm, and the width WgL of the isolation groove is 30-150 μm.

8. The method for preparing a back contact battery according to claim 1, characterized in that: The S00 process specifically includes: S01. Provide double-sided polished silicon wafers; S02, sequentially forming a first semiconductor layer and a mask layer on the back side of the silicon wafer; S03, performing a first opening on the back surface obtained in S02 to form a second semiconductor opening region; S04, forming a textured surface on the front side of the silicon wafer and the second semiconductor opening area through texturing and cleaning, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polished surface, and then selecting whether to perform a step of removing the mask layer outside the second semiconductor opening area on the back side of the silicon wafer through cleaning according to needs; S05, depositing a second semiconductor layer on the back surface obtained in S04; S06. Perform a second opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region.

9. The method for preparing a back contact battery according to claim 1 or 8, characterized in that: The method for preparing the back contact battery also includes: Before or after depositing the second semiconductor layer, a passivation layer and an anti-reflection layer are sequentially deposited on the front side of the silicon wafer; S11. An insulating ink layer arranged in intervals is formed on the outer surface of the metal fine gate electrode on the back side of the silicon wafer, and then a metal main gate electrode is formed on the outer surface of the back side.

10. A back contact battery, characterized in that: The back contact battery is prepared by the method for preparing a back contact battery as claimed in any one of claims 1 to 9.

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