Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention discloses a solar cell, a preparation method thereof and a photovoltaic module, the solar cell comprises a silicon substrate, the silicon substrate comprises a first surface and a second surface which are oppositely arranged, the second surface comprises a first area and a second area which are distributed at an interval, and the first area and the second area are arranged on the silicon substrate. A tunneling passivation contact structure and a second electrode are arranged in a partial area of the second surface, and the projection of the tunneling passivation contact structure on the second surface of the silicon substrate is located in the first area. The tunneling passivation contact structure comprises a tunneling layer which is in direct contact with the silicon substrate, a second doping layer which is laminated on the tunneling layer, and a barrier layer and a third doping layer which are laminated on the second doping layer in sequence. According to the solar cell, parasitic absorption of the back of the cell can be reduced, current can be remarkably improved, meanwhile, the contact performance of the back electrode and the back doping layer is not affected, and the cell efficiency and the double-sided rate are remarkably improved while the process window is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of photovoltaic cells, and in particular relates to a solar cell, a preparation method thereof and a photovoltaic module. Background Art

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and foreign photovoltaic markets are also constantly increasing, and industry manufacturers have focused on the research and development of high-efficiency batteries. TOPCon (Tunnel Oxide Passivated Contact) cells can improve the surface passivation performance of the cell, reduce the metal contact composite current, and effectively increase the open circuit voltage and short circuit current of the cell by sequentially preparing an ultra-thin tunnel oxide layer and a doped polysilicon layer on the back of the silicon substrate. In recent years, the market share of TOPCon cells has risen rapidly, and has gradually surpassed PERC cells to become the mainstream technology for solar cells.

[0003] Both the n+ polarity and the p+ polarity in TOPCon cells have excellent passivation and conductivity properties, and are compatible with traditional industrial production, and have broad development prospects. With the continuous optimization of TOPCon cells, the parasitic absorption of the back polysilicon layer (poly) has become the primary factor limiting the improvement of TOPCon cell efficiency and bifaciality.

[0004] In TOPCon cells, the back polysilicon layer is doped with phosphorus to form a doped polysilicon layer (N+Poly), which has three main functions: 1. Provide field passivation effect; 2. As a phosphorus-rich layer, it greatly improves the contact on the back; 3. Isolates the direct contact between the Ag metal and the silicon substrate, reducing metal recombination. In addition to the above advantages, the parasitic absorption of the polysilicon layer is its biggest disadvantage. Parasitic absorption refers to an optical absorption mechanism that does not generate electron-hole pairs in the silicon body, thereby reducing the utilization rate of light. In order to reduce the recombination of the Ag metal area on the back, the thickness of the polysilicon layer is generally greater than 100nm. Reducing the thickness of the polysilicon layer while ensuring that the passivation of the metal area is not lost has become the main optimization direction of TOPCon cells.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a solar cell, a preparation method thereof and a photovoltaic module. Summary of the invention

[0006] The object of the present invention is to provide a solar cell, a preparation method thereof and a photovoltaic module, so as to take into account the back passivation performance and reduce the back parasitic absorption, thereby improving the cell efficiency.

[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0008] A solar cell, characterized in that the solar cell includes a silicon substrate, the silicon substrate includes a first surface and a second surface arranged opposite to each other, the second surface includes a first area and a second area distributed at intervals, a partial area of ​​the second surface is provided with a tunneling passivation contact structure and a second electrode, the projection of the tunneling passivation contact structure on the second surface of the silicon substrate is located in the first area, the tunneling passivation contact structure includes a tunneling layer directly in contact with the silicon substrate, a second doping layer stacked on the tunneling layer, and a barrier layer and a third doping layer stacked in sequence on the second doping layer, the doping type of the second doping layer and the third doping layer is the same as the doping type of the silicon substrate, and the second electrode is in contact with the third doping layer.

[0009] In one embodiment, the thickness of the third doping layer is greater than or equal to the thickness of the second doping layer; and / or,

[0010] The total thickness of the second doping layer and the third doping layer is 50 nm to 150 nm or 60 nm to 100 nm.

[0011] In one embodiment, the thickness of the second doping layer is 1 nm to 100 nm, and the thickness of the third doping layer is 1 nm to 150 nm; or,

[0012] The thickness of the second doping layer is 1 nm to 50 nm, and the thickness of the third doping layer is 50 nm to 100 nm.

[0013] In one embodiment, a second passivation layer in contact with the second surface of the silicon substrate is disposed on the second region.

[0014] In one embodiment, the second passivation layer extends onto the first region and covers the third doped layer.

[0015] In one embodiment, the second passivation layer is an aluminum oxide passivation layer with a thickness of 2 nm to 7 nm or 3 nm to 6 nm.

[0016] In one embodiment, a second anti-reflection layer is stacked on the second passivation layer, and the second anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm.

[0017] In one embodiment, the silicon substrate is an N-type silicon substrate, and the second doped layer and the third doped layer are N-type doped polysilicon layers; and / or,

[0018] The surface doping concentration of the third doping layer is greater than or equal to the surface doping concentration of the second doping layer; and / or,

[0019] The surface doping concentration of the second doping layer is 3E20cm -3 ~3E21cm-3 or 5E20cm -3 ~2E21cm -3 and / or,

[0020] The surface doping concentration of the third doping layer is 3E20cm -3 ~3E21cm -3 or 5E20cm -3 ~2E21cm -3 and / or,

[0021] The tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0022] The thickness of the tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or,

[0023] The barrier layer is any one or more combinations of a silicon oxide layer and a silicon carbide layer; and / or,

[0024] The thickness of the barrier layer is 0.5 nm to 3 nm or 1.5 nm to 2 nm.

[0025] In one embodiment, a first doping layer and a first electrode are formed on the first surface of the silicon substrate, the doping type of the first doping layer is opposite to the doping type of the silicon substrate, and the first electrode is in contact with the first doping layer.

[0026] In one embodiment, the first doped layer is a P-type doped layer; and / or,

[0027] The surface doping concentration of the first doping layer is 3E18cm -3 ~3E19cm -3 .

[0028] In one embodiment, a first passivation layer and / or a first anti-reflection layer is stacked on the first doped layer.

[0029] In one embodiment, the first passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm; the first anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm.

[0030] In one embodiment, the first region includes a plurality of first sub-regions that are distributed in parallel and at equal intervals, the second electrode includes a plurality of gate lines that are distributed in parallel, and the width of the first sub-region is greater than or equal to the width of the gate line.

[0031] In one embodiment, the width of the first sub-region is 50 μm to 150 μm, and the width of the gate line is 15 μm to 100 μm.

[0032] In one embodiment, a pyramid velvet structure is formed on the first surface of the silicon substrate; and / or,

[0033] The second surface of the silicon substrate is a polished surface.

[0034] Another embodiment of the present invention provides a technical solution as follows:

[0035] A method for preparing a solar cell, the method comprising the following steps:

[0036] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the second surface comprising a first region and a second region distributed at intervals;

[0037] Preparing a tunnel passivation contact structure on the second surface, wherein the tunnel passivation contact structure comprises a tunnel layer, a second doping layer, a barrier layer and a third doping layer stacked in sequence;

[0038] removing the tunnel passivation contact structure on the second region and retaining the tunnel passivation contact structure on the first region;

[0039] A second electrode contacting the third doping layer is prepared on the first region.

[0040] In one embodiment, the preparation method further comprises:

[0041] The third doping layer on the first region is processed by a laser process to form an oxide layer on the surface of the third doping layer on the first region.

[0042] In one embodiment, the laser process is performed in an atmosphere containing oxygen, and the volume concentration of oxygen is 20% to 80%; and / or,

[0043] The laser power in the laser process is 1W to 100W or 30W to 60W; and / or,

[0044] The laser frequency in the laser process is 1kHz to 1000kHz or 300kHz to 600kHz; and / or,

[0045] The laser scanning rate in the laser process is 10000 mm / s to 100000 mm / s or 30000 mm / s to 60000 mm / s; and / or,

[0046] The number of laser processing in the laser process is 1 to 100 times or 1 to 10 times.

[0047] In one embodiment, removing the tunnel passivation contact structure on the second region includes:

[0048] Using the oxide layer as a mask, an alkaline solution is used to remove the second doping layer, the barrier layer and the third doping layer on the second region, and then an acid solution is used to remove the tunneling layer on the second region and the oxide layer on the first region.

[0049] In one embodiment, preparing a tunnel passivation contact structure on the second surface includes:

[0050] Depositing a tunneling layer, a first doped amorphous silicon layer, a barrier layer, and a second doped amorphous silicon layer in sequence on the second surface of the silicon substrate;

[0051] The silicon substrate on which the tunneling layer, the first doped amorphous silicon layer, the barrier layer and the second doped amorphous silicon layer are deposited is annealed at a temperature of 880° C. to 980° C. to transform the doped amorphous silicon layer into a doped polysilicon layer.

[0052] In one embodiment, the preparation method further comprises:

[0053] The light trapping structure is prepared on the first surface and the second surface of the silicon substrate by a texturing process; and / or,

[0054] The second surface of the silicon substrate is polished before preparing the tunnel passivation contact structure.

[0055] In one embodiment, the preparation method further comprises:

[0056] preparing a first doping layer at the first surface, wherein the doping type of the first doping layer is opposite to the doping type of the silicon substrate; and,

[0057] A first electrode is prepared on the first surface and in contact with the first doping layer.

[0058] In one embodiment, the preparation method further comprises:

[0059] Prepare a first passivation layer and / or a first anti-reflection layer on the first surface of the silicon substrate;

[0060] A second passivation layer and / or a second anti-reflection layer is prepared on the second surface of the silicon substrate.

[0061] Another embodiment of the present invention provides a technical solution as follows:

[0062] A photovoltaic component comprises the above-mentioned solar cell.

[0063] Compared with the prior art, the present invention has the following beneficial effects:

[0064] The back of the solar cell of the present invention has only a tunnel passivation contact structure stacked on the metal area, and there is no tunnel passivation contact structure on the non-metal area, which can reduce the parasitic absorption on the back of the cell, and the current can be significantly improved, while the contact performance between the back electrode and the back doping layer is not affected, and the cell efficiency and bifaciality are significantly improved while improving the process window;

[0065] The tunnel passivation contact structure of the back metal area includes two doping layers and a barrier layer. The barrier layer has a certain blocking ability against the penetration of the back electrode paste, which can further reduce the total thickness of the back doping layer, thereby further increasing the open circuit voltage of the battery and improving the battery efficiency.

[0066] The second passivation layer can ensure the passivation performance of the back side of the battery through the non-metallic area on the back. In addition, the second passivation layer has a certain blocking effect on the back slurry. The total thickness of the doped layer on the metal area can be further thinned, thereby increasing the short-circuit current density of the battery without affecting the metallization contact performance, and significantly improving the battery efficiency and bifaciality. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0068] Figure 1 is a schematic structural diagram of a solar cell in Example 1 of the present invention;

[0069] Figure 2 for Figure 1 Schematic diagram of the local structure at A in the middle;

[0070] Figure 3 is a schematic plan view of the second surface of the silicon substrate in Example 1 of the present invention;

[0071] Figure 4 is a plan view schematically showing the second surface and the second electrode in Example 1 of the present invention;

[0072] Figures 5a to 5j is a process flow chart of preparing a solar cell in Example 1 of the present invention;

[0073] Figure 6 Schematic diagram of a laser scanning pattern in a laser process in Example 1 of the present invention;

[0074] Figures 7a to 7c A process flow chart of preparing a first doping layer on the first surface of a silicon substrate in Example 2 of the present invention;

[0075] Figure 8a-8b This is a process flow chart for preparing the mask on the first region in Example 3 of the present invention.

[0076] Description of main reference numerals:

[0077] 10-substrate, 11-first doped layer, 11'-boron-doped amorphous silicon layer, 21-first passivation layer, 31-first anti-reflection layer, 12-tunneling layer, 13-second doped layer, 14-barrier layer, 15-third doped layer, 151-oxide layer, 152-oxide layer, 22-second passivation layer, 32-second anti-reflection layer, 41-first electrode, 42-second electrode, 421-fine gate line, S1-first surface, S2-second surface, S21-first region, S22-second region, 101-first sub-region, 102-second sub-region. DETAILED DESCRIPTION

[0078] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0079] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0080] The present invention discloses a solar cell, comprising a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface arranged opposite to each other, the second surface comprises a first region and a second region distributed at intervals, a partial region of the second surface is provided with a tunneling passivation contact structure and a second electrode, a projection of the tunneling passivation contact structure on the second surface of the silicon substrate is located in the first region, the tunneling passivation contact structure comprises a tunneling layer directly in contact with the silicon substrate, a second doping layer stacked on the tunneling layer, and a barrier layer and a third doping layer stacked in sequence on the second doping layer, the doping types of the second doping layer and the third doping layer are the same as the doping type of the silicon substrate, and the second electrode is in contact with the third doping layer.

[0081] The present invention also discloses a method for preparing a solar cell, comprising the following steps:

[0082] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the second surface comprising a first region and a second region distributed at intervals;

[0083] Prepare a tunnel passivation contact structure on the second surface, the tunnel passivation contact structure comprising a tunnel layer, a second doping layer, a barrier layer and a third doping layer stacked in sequence;

[0084] removing the tunnel passivation contact structure on the second region and retaining the tunnel passivation contact structure on the first region;

[0085] A second electrode contacting the third doping layer is prepared on the first region.

[0086] The invention also discloses a photovoltaic assembly, comprising the solar cell mentioned above.

[0087] The back side of the solar cell of the present invention has only a tunnel passivation contact structure stacked on the metal area, and there is no tunnel passivation contact structure on the non-metal area, which can reduce the parasitic absorption on the back side of the battery, and the current can be significantly improved without affecting the contact performance between the back electrode and the back doping layer, thereby significantly improving the battery efficiency and bifaciality while improving the process window.

[0088] The present invention is further described below with reference to specific examples.

[0089] Embodiment 1:

[0090] Ginseng Figure 1 The solar cell in this embodiment is a schematic diagram of the structure of the solar cell, which is a TOPCon cell, including a silicon substrate 10, Figure 5a As shown, the silicon substrate 10 includes a first surface S1 and a second surface S2 that are relatively arranged, and the second surface S2 includes a first area S21 and a second area S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first area S21 is a back metal area, and the second area S22 is a back non-metal area.

[0091] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0092] Furthermore, a light trapping structure is formed on the first surface S1 of the silicon substrate 10. For example, a pyramid velvet structure can be formed on the first surface S1 of the silicon substrate 10 by alkali texturing, and the size of the pyramid is 0.5μm to 3μm. The second surface S2 of the silicon substrate 10 is a polished surface, which can be the surface of the light trapping structure after chemical polishing, or the surface of the back of the original silicon substrate after direct chemical polishing. For example, in this embodiment, a pyramid velvet structure can be formed on the second surface S2 of the silicon substrate 10 by alkali texturing, and the size of the pyramid is 0.5μm to 3μm, and then the back is alkali polished to obtain a polished surface. Compared with the back of a conventional silicon substrate, a plurality of tower bases will be formed on the polished surface (the tower base is the base left after the pyramid velvet structure is polished).

[0093] In this embodiment, a first doping layer 11 (i.e., an emitter) is formed at the first surface S1 of the silicon substrate 10 by a diffusion process or a PECVD process, thereby forming a PN junction, and generating minority carrier-hole pairs after light exposure. Exemplarily, the first doping layer 11 in this embodiment is a P-type doping layer (i.e., a P+ emitter), which is formed below the first surface S1 of the silicon substrate (i.e., inside the silicon substrate) by a boron doping process, and the surface doping concentration is 3E18cm -3 ~3E19cm -3 , square resistance is 40Ω / sq~300Ω / sq, preferably 150Ω / sq~280Ω / sq.

[0094] Ginseng Figure 1 Combined with Figure 2 As shown, in this embodiment, a tunneling passivation contact structure is provided only on the first region S21 on the second surface S2 of the silicon substrate 10, while no tunneling passivation contact structure is provided on the second region S22.

[0095] Specifically, the tunnel passivation contact structure on the first region S21 includes a tunneling layer 12, a second doping layer 13, a barrier layer 14 and a third doping layer 15 stacked in sequence, and the projection of the tunnel passivation contact structure on the second surface S2 of the silicon substrate 10 is located in the first region S21. The tunneling layer 12 directly contacts the second surface S2 of the silicon substrate 10 on the first region S21, and can provide a good interface passivation effect on the first region S21. The second doping layer 13 and the third doping layer 15 can provide a field passivation effect, and can improve contact and reduce resistance. There is no tunneling layer 12 and doping layer on the second region S22, and the thickness of this region is greatly reduced, which can reduce the parasitic absorption of the back light, improve the short-circuit current density of the battery, and significantly improve the battery efficiency and bifaciality.

[0096] The tunneling layer 12 is made of silicon oxide (SiO X ) layer, silicon oxynitride (SiO X N Y) layer, preferably a silicon oxide layer, with a thickness of 0.5nm to 3nm, preferably 1.5nm to 2.5nm; the barrier layer 14 is silicon oxide (SiO X ) layer, a silicon carbide (SiC) layer, or a combination of both, preferably silicon oxide (SiO X ) layer, with a thickness of 0.5nm to 3nm, preferably 1.5nm to 2nm.

[0097] The doping type of the second doping layer 13 and the third doping layer 15 is the same as the doping type of the silicon substrate. Furthermore, the surface doping concentration of the third doping layer 15 is greater than or equal to the surface doping concentration of the second doping layer 13, the thickness of the third doping layer 15 is greater than or equal to the thickness of the second doping layer 13, and the total thickness of the second doping layer 13 and the third doping layer 15 is 50nm to 150nm, preferably 60nm to 100nm. Specifically, the second doping layer 13 in this embodiment is a phosphorus-doped polysilicon layer with a surface doping concentration of 3E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 , with a thickness of 1nm to 100nm, preferably 1nm to 50nm; the third doped layer 15 is a phosphorus-doped polysilicon layer, and the surface doping concentration is 3E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 , with a thickness of 1 nm to 150 nm, preferably 50 nm to 100 nm.

[0098] In the present invention, a tunneling passivation contact structure of a tunneling layer / a second doping layer / a barrier layer / a third doping layer is provided only in the first region S21 (the back metal region) on the back side of the silicon substrate, and the second region S22 (the back non-metal region) is partially removed. Two doping layers are stacked on the first region S21, which can prevent the electrode slurry from penetrating the doping layer and damaging the underlying tunneling layer 21 during sintering, thereby ensuring the field passivation effect. The thickness of the back side of the second region S22 is greatly reduced, which can reduce the parasitic absorption of light on the back side, increase the short-circuit current density of the battery, and significantly improve the battery efficiency.

[0099] In addition, a barrier layer 14 is introduced between the second doping layer 13 and the third doping layer 15. The barrier layer 14 has a certain blocking ability against the puncture of the back electrode paste, so that the total thickness of the second doping layer 13 and the third doping layer 15 can be further thinned, such as in the present embodiment, it can be thinned to 60nm ~ 100nm, thereby further improving the open circuit voltage (Voc) of the battery, and then improving the battery efficiency.

[0100] The thickness of the barrier layer 14 in the present invention has a great influence on the battery preparation process and battery performance. If the barrier layer 14 is too thin, it cannot guarantee the puncture barrier of the back electrode slurry. If the barrier layer 14 is too thick, it will increase the barrier ability of phosphorus internal expansion and affect the ohmic contact. Therefore, in this embodiment, the thickness of the barrier layer 14 is 0.5nm to 3nm, preferably 1.5nm to 2nm.

[0101] Preferably, in this embodiment, a first passivation layer 21 and a first anti-reflection layer 31 are sequentially stacked on the first surface S1 of the silicon substrate 10, and a second passivation layer 22 and a second anti-reflection layer 32 are sequentially stacked on the second surface S2 of the silicon substrate 10. The second passivation layer 22 and the second anti-reflection layer 32 cover the second doping layer 13 and extend into the second region S22. In the second region S22, the second passivation layer 22 is in direct contact with the silicon substrate 10. The first passivation layer 21 can provide excellent field passivation and chemical passivation effects, the second passivation layer 22 can provide a chemical passivation effect, and the first anti-reflection layer 31 can reduce reflectivity and increase light utilization.

[0102] Exemplarily, the first passivation layer 21 and the second passivation layer 22 are both aluminum oxide passivation layers with a thickness of 2nm to 7nm, preferably 3nm to 6nm; the first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm, preferably a silicon nitride layer. Silicon nitride is chemically inactive, has strong acid and alkali corrosion resistance, and can reduce the sensitivity of the battery to the environment.

[0103] In addition, the first electrode 41 in this embodiment is located on the first surface S1 of the silicon substrate 10 and contacts the first doping layer 11, and the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically on the first area S21 in the second surface S2, and contacts the second doping layer 13.

[0104] Ginseng Figure 3 As shown, in this embodiment, the first region S21 includes a plurality of first sub-regions 101 that are parallel and equally spaced, and the second region S22 includes a plurality of second sub-regions 102 that are parallel and equally spaced, and the first sub-regions 101 and the second sub-regions 102 are staggered. The width of the first sub-region 101 is smaller than the width of the second sub-region 102, for example, the ratio of the widths of the two can be 1: (5-20), preferably, the first region S21 occupies about 10% of the area of ​​the entire second surface S2.

[0105] Combination Figure 4As shown, the second electrode 42 is a gate line electrode, which at least includes a plurality of parallel thin gate lines 421, and the width of the first sub-region 101 is greater than or equal to the width of the thin gate lines 421. Optionally, the second electrode 42 may also include a plurality of main gate lines (not shown) perpendicular to the thin gate lines 421.

[0106] In this embodiment, taking a 210TOPCon battery as an example, the size is 203.396±15mm, there are 230 fine grid lines 421, the width is 15μm to 100μm, and the spacing between adjacent fine grid lines is 0.907±0.015mm. The spacing between adjacent first sub-regions 101 is equal to the spacing between adjacent fine grid lines, and a fine grid line 421 is distributed on each first sub-region 101, and the width of the first sub-region 101 is greater than the width of the fine grid line 421. The width of the first sub-region is 50μm to 150μm, such as the width of the fine grid line is 40μm, and the width of the first sub-region is 80μm.

[0107] The method for preparing a solar cell in this embodiment specifically includes the following steps:

[0108] 1. Double-sided velveting

[0109] Ginseng Figure 5a As shown, a silicon substrate 10 is provided, and the silicon substrate 10 includes a first surface S1 and a second surface S2 that are arranged opposite to each other. The second surface S2 includes a first area S21 and a second area S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first area S21 is a back metal area, and the second area S22 is a back non-metal area.

[0110] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0111] Ginseng Figure 5b As shown, in this embodiment, the first surface S1 and the second surface S2 of the silicon substrate 10 are formed with a pyramid texture structure by an alkali texturing process, and the size of the pyramid is 0.5 μm to 3 μm.

[0112] 2. Boron Diffusion

[0113] Ginseng Figure 5c As shown, a P-type doped first doping layer (i.e., a P+ emitter) 11 is formed at the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, a boron source (e.g., BCl3 or BBr3, etc.) is used in a high-temperature furnace tube for diffusion, and a layer of silicon oxide is formed on the outer layer. After diffusion, the surface doping concentration of the first doping layer is 3E18cm -3 ~3E19cm -3, the square resistance is 40Ω / sq~300Ω / sq, preferably 150Ω / sq~250Ω / sq. In the boron diffusion process, BSG (not shown) is formed on the second surface S2 of the silicon substrate.

[0114] In this embodiment, the outer silicon layer of the first surface S1 of the silicon substrate 10 is transformed into a boron diffusion layer. Figure 5c The total thickness of the silicon substrate 10 and the first doping layer 11 after the boron diffusion is Figure 5b The thickness of the silicon substrate 10 before the boron diffusion is uniform.

[0115] 3. Back polishing

[0116] Ginseng Figure 5d As shown, the silicon substrate after boron diffusion is first passed through a single-sided chain device, and a hydrofluoric acid solution is used to remove the back silicon oxide. The back side is then alkaline polished to remove the edge junction and back side wrap (BSG), and finally cleaned.

[0117] 4. Preparation of back-side tunneling passivation structure

[0118] Ginseng Figure 5e As shown, a tunneling layer 12, a second doping layer 13, a barrier layer 14 and a third doping layer 15 which are stacked in sequence are prepared on the second surface S2.

[0119] Exemplarily, in this embodiment, a PECVD process is used for deposition. First, a silicon oxide tunneling layer is deposited on the back side with a thickness of 0.5nm to 3nm, preferably 1.5nm to 2.5nm; then a phosphorus-doped amorphous silicon layer (first doping layer) is deposited with a thickness of 1nm to 100nm, preferably 1nm to 50nm; then a silicon oxide barrier layer is deposited with a thickness of 0.5nm to 3nm, preferably 1.5nm to 2.5nm; finally, a phosphorus-doped amorphous silicon layer (second doping layer) is deposited with a thickness of 1nm to 150nm, preferably 50nm to 100nm.

[0120] For example, the thicknesses of the silicon oxide tunneling layer, the first phosphorus-doped amorphous silicon layer, the silicon oxide barrier layer and the second phosphorus-doped amorphous silicon layer are 1.8 nm, 50 nm, 1.5 nm and 70 nm respectively, and the total thickness of the back doped layer is 120 nm.

[0121] 5. Laser oxidation

[0122] Ginseng Figure 5f As shown, the third doping layer 15 on the first region S21 is processed by a laser process, and an oxide layer 151 is formed on the surface of the third doping layer 15 on the first region S21.

[0123] The laser process uses the instantaneous high temperature of the laser to form silicon oxide (SiOX ) layer, the silicon oxide layer serves as a mask for subsequent processes.

[0124] Specifically, the laser process is carried out in an atmosphere containing oxygen, and the volume concentration of oxygen is 20% to 80%; the laser power is 1W to 100W, preferably 30W to 60W; the laser frequency is 1kHz to 1000kHz, preferably 300kHz to 600kHz; the laser scanning rate is 10000mm / s to 100000mm / s, preferably 30000mm / s to 60000mm / s; the number of laser processing times is 1 to 100 times, preferably 1 to 10 times, and the thickness of the formed oxide layer 151 is 1nm to 50nm.

[0125] For example, in a specific embodiment, the volume concentration of oxygen in the laser process is 50%, the laser power is 30 W, the laser frequency is 500 kHz, the laser scanning rate is 50000 mm / s, the number of laser processing times is 2 times, and the thickness of the silicon oxide layer formed by oxidation of the surface of the phosphorus-doped amorphous silicon layer is 0.01 nm to 10 nm.

[0126] Ginseng Figure 6 The figure shows the laser scanning pattern in the laser process of this embodiment. The black line portion corresponds to the laser scanning area, that is, the first area S21 (i.e., the metal area), and the blank portion is the second area S22 (i.e., the non-metal area). After the laser process, the first area S21 is a tunneling layer / phosphorus-doped polysilicon layer / barrier layer / phosphorus-doped polysilicon layer / silicon oxide layer structure, and the second area S22 is a tunneling layer / phosphorus-doped polysilicon layer / barrier layer / phosphorus-doped polysilicon layer structure.

[0127] It should be understood that the laser scanning pattern in the present invention can be designed according to different electrode structures, so as to form a patterned silicon oxide mask on the surface of the amorphous silicon layer below the laser scanning area (i.e., the back metal area). The laser scanning patterns for other electrode structures will not be illustrated one by one here.

[0128] 6. Annealing activation

[0129] Annealing treatment is performed in a high temperature annealing furnace at a temperature of 880°C to 980°C, preferably 900°C to 950°C. After annealing, the phosphorus-doped amorphous silicon layer is transformed into a phosphorus-doped polysilicon layer. Phosphorus is activated by annealing to form a tunnel passivation contact structure on the back. After annealing, the surface doping concentration of the second doping layer 13 and the third doping layer 15 is 3E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 .

[0130] For example, the annealing temperature in this embodiment is 910° C., and the surface doping concentration of the second doping layer 13 after annealing is 8E20 cm -3 The surface doping concentration of the third doping layer 15 is 1E21cm -3 .

[0131] 7. De-plating and chemical etching

[0132] Ginseng Figure 5g As shown, a chemical etching process is used to remove the tunnel passivation contact structure on the second region S22 and the oxide layer 151 on the first region S21, and the tunnel passivation contact structure on the first region S21 is retained.

[0133] This step specifically includes:

[0134] Alkali etching: using an alkaline solution in an alkaline washing tank to remove the second doping layer 13, the barrier layer 14 and the third doping layer 15 on the second region S22, and simultaneously remove the front surface and edge plating, the mass fraction of the alkaline solution being 3% to 15%;

[0135] Pickling: using an acid solution in a pickling tank to remove the tunneling layer 12 on the second region S22 and the oxide layer 151 on the first region, and simultaneously remove the PSG on the front side, the mass fraction of the acid solution being 5% to 20%;

[0136] Finally, RCA cleaning is performed. RCA cleaning is a prior art and will not be described in detail here.

[0137] Preferably, the acid solution in this embodiment is obtained by mixing industrial-grade hydrofluoric acid solution (mass fraction ~40%) and water in a certain proportion, and the alkaline solution is obtained by mixing industrial-grade sodium hydroxide solution (mass fraction ~32%) and water in a certain proportion.

[0138] In the prior art, a front chain process (pickling) is usually required before the alkaline etching step, and the silicon oxide mask with edge plating is removed on one side through a chain hydrofluoric acid tank. However, the silicon oxide mask is not prepared by the PECVD process, and no plating is formed on the edge, so there is no need to go through the front chain process.

[0139] During the alkaline etching process, the phosphorus-doped amorphous silicon layer on the second region S22 is corroded, which can reduce the parasitic absorption on the back of the battery and significantly improve the current. The barrier layer 14 can be removed simultaneously during the alkaline etching process due to its thin thickness and holes on the surface.

[0140] Specifically, an additive to protect the silicon oxide mask on the first region S21 is usually added to the alkaline etching solution, such as the EST-10 additive of Jiaxing Shangneng Photovoltaic Material Technology Co., Ltd. The additive contains a protective group and a catalytic component. The protective group will selectively adsorb on the oxide layer to block the contact of the alkali, and the catalytic component will accelerate the reaction between the exposed polysilicon and the alkali. Since the barrier layer 14 is thin and has holes on the surface, it is not a completed oxide layer. When the mixture of alkali and additives is used for wet etching, the alkali will penetrate the barrier layer 14 and then corrode the polysilicon underneath. Since the first region S21 is protected by the completed oxide layer 151, the polysilicon underneath can be prevented from being corroded.

[0141] 8. Preparation of passivation layer

[0142] Ginseng Figure 5h As shown, the first passivation layer 21 and the second passivation layer 22 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate by the ALD process. The first passivation layer 21 and the second passivation layer 22 are both aluminum oxide passivation layers with a thickness of 2nm to 7nm, preferably 3nm to 6nm.

[0143] After the de-plating and chemical etching steps, the tunneling layer and the doped polysilicon layer on the first area S21 can still ensure the passivation effect, while there is no passivation layer protection on the second area S22. Therefore, it is necessary to prepare a second passivation layer 22 on the back side to ensure a good interface passivation effect on the second area S22.

[0144] In addition, under high temperature sintering conditions to ensure good front contact, the second passivation layer 22 has a certain blocking effect on the back paste, so the second doping layer 13 and the third doping layer 15 can be further thinned, thereby improving the short-circuit current density of the battery.

[0145] 9. Preparation of anti-reflection layer

[0146] Ginseng Figure 5i As shown, a first anti-reflection layer 31 and a second anti-reflection layer 32 are respectively prepared on a first surface S1 and a second surface S2 of a silicon substrate by a PECVD process. The first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm.

[0147] 9. Printing metal electrodes

[0148] Ginseng Figure 5j As shown, the first electrode 41 and the second electrode 42 are printed on the front and back sides respectively by screen printing, and then sintering and light injection or electric injection treatment are performed to form ohmic contacts.

[0149] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, and usually include a main gate line and a fine gate line. It is worth noting that since the fine gate line in the second electrode 42 needs to be printed on the first region S21, the width of the first sub-region 101 needs to be greater than the width of the fine gate line 421 in the second electrode 42, so that the fine gate line 421 can be aligned.

[0150] The process flow in this embodiment is texturing → boron diffusion → back polishing → PE-poly → laser → annealing → de-coating → ALD → PECVD → screen printing. TOPCon batteries can be prepared through the above steps, and finally the battery cells are tested, sorted and stored.

[0151] Embodiment 2:

[0152] The structure and preparation method of the solar cell in this embodiment are substantially the same as those in Example 1, except that the first doping layer 11 in Example 1 is prepared below the first surface S1 of the silicon substrate by a boron diffusion process, while the first doping layer 11 in this embodiment is prepared above the first surface S1 of the silicon substrate by a PECVD process.

[0153] Specifically, in this embodiment, a boron-doped amorphous silicon layer 11 ′ is first deposited on the first surface S1 by using a PECVD process, and then a first doped layer 11 , ie, a P-type doped polysilicon layer, is formed after high-temperature oxidation annealing.

[0154] Ginseng Figure 7a As shown, firstly, the silicon substrate 10 is double-sided textured, and the texture process is exactly the same as that in Example 1, which will not be described again here.

[0155] Ginseng Figure 7b As shown, a boron-doped amorphous silicon layer 11' is first deposited on the first surface S1 by a PECVD process. Exemplarily, in the PECVD process, N2O is first introduced to form a silicon oxide layer (not shown) on the first surface S1, then SiH4 and trimethyl boron are introduced to form a boron-doped amorphous silicon layer on the silicon oxide layer, and finally N2O is introduced to form a silicon oxynitride mask (not shown).

[0156] Ginseng Figure 7c As shown, finally, a first doped layer 11 is formed by a high temperature oxidation annealing process. The P-type doped amorphous silicon layer can be transformed into a P-type doped polysilicon layer by the high temperature oxidation annealing process.

[0157] Different from the first embodiment, in the present embodiment, a P-type doped polysilicon layer is prepared on the surface of the silicon substrate 10 by a PECVD process and an annealing method, and the thickness of the silicon substrate 10 is constant during this process. Figure 7c After the annealing, the total thickness of the silicon substrate 10 and the first doping layer 11 is equal to Figure 7bThe total thickness of the silicon substrate 10 and the boron-doped amorphous silicon layer 11' before annealing is greater than Figure 7a The thickness of the silicon substrate 10 before the PECVD process.

[0158] Embodiment 3:

[0159] The structure and preparation method of the solar cell in this embodiment are substantially the same as those in Embodiment 1, except that in step 5 of the preparation method in Embodiment 1, a laser process is used to process the first region S21, thereby forming an oxide layer mask on the surface of the third doping layer 15, and the mask preparation process on the first region S21 in this embodiment is as follows:

[0160] Ginseng Figure 8a As shown, first, in the step of depositing the back tunnel passivation structure, a layer of oxide layer 152, preferably silicon oxide, is deposited on the surface of the third doping layer 15 by using the PECVD process;

[0161] Ginseng Figure 8b As shown, after the annealing process, a laser film opening process is used to remove the mask on the second area S22.

[0162] After annealing, the back structure of the silicon substrate is tunneling layer / phosphorus-doped polysilicon layer / barrier layer / phosphorus-doped polysilicon layer / silicon oxide layer. The laser processing mainly acts on the mask (SiO2). The laser parameters in the laser film opening process are controlled according to the material and thickness of the mask, which will not be repeated here.

[0163] The structure and other manufacturing processes of the solar cell in this embodiment are the same as those in the embodiment, and will not be described again here.

[0164] It can be seen from the above technical solutions that the present invention has at least the following technical effects:

[0165] The back of the solar cell of the present invention has only a tunnel passivation contact structure stacked on the metal area, and there is no tunnel passivation contact structure on the non-metal area, which can reduce the parasitic absorption on the back of the cell, and the current can be significantly improved, while the contact performance between the back electrode and the back doping layer is not affected, and the cell efficiency and bifaciality are significantly improved while improving the process window;

[0166] The tunnel passivation contact structure of the back metal area includes two doping layers and a barrier layer. The barrier layer has a certain blocking ability against the penetration of the back electrode paste, which can further reduce the total thickness of the back doping layer, thereby further increasing the open circuit voltage of the battery and improving the battery efficiency.

[0167] The second passivation layer can ensure the passivation performance of the back side of the battery through the non-metallic area on the back. In addition, the second passivation layer has a certain blocking effect on the back slurry. The total thickness of the doped layer on the metal area can be further thinned, thereby increasing the short-circuit current density of the battery without affecting the metallization contact performance, and significantly improving the battery efficiency and bifaciality.

[0168] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0169] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized in that: The solar cell includes a silicon substrate, the silicon substrate includes a first surface and a second surface arranged opposite to each other, the second surface includes a first area and a second area distributed at intervals, a tunneling passivation contact structure and a second electrode are provided in a partial area of ​​the second surface, the projection of the tunneling passivation contact structure on the second surface of the silicon substrate is located in the first area, the tunneling passivation contact structure includes a tunneling layer directly in contact with the silicon substrate, a second doping layer stacked on the tunneling layer, and a barrier layer and a third doping layer stacked in sequence on the second doping layer, the doping types of the second doping layer and the third doping layer are the same as the doping type of the silicon substrate, and the second electrode is in contact with the third doping layer.

2. The solar cell according to claim 1, characterized in that The thickness of the third doping layer is greater than or equal to the thickness of the second doping layer; and / or, The total thickness of the second doping layer and the third doping layer is 50 nm to 150 nm or 60 nm to 100 nm.

3. The solar cell according to claim 1, characterized in that The thickness of the second doping layer is 1 nm to 100 nm, and the thickness of the third doping layer is 1 nm to 150 nm; or, The thickness of the second doping layer is 1 nm to 50 nm, and the thickness of the third doping layer is 50 nm to 100 nm.

4. The solar cell according to claim 1, characterized in that A second passivation layer in contact with the second surface of the silicon substrate is disposed on the second region.

5. The solar cell according to claim 4, characterized in that: The second passivation layer extends onto the first region and covers the third doped layer.

6. The solar cell according to claim 4, characterized in that: The second passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm.

7. The solar cell according to claim 4 or 5, characterized in that: A second anti-reflection layer is stacked on the second passivation layer. The second anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm.

8. The solar cell according to claim 1, characterized in that The silicon substrate is an N-type silicon substrate, and the second doping layer and the third doping layer are N-type doped polysilicon layers; and / or, The surface doping concentration of the third doping layer is greater than or equal to the surface doping concentration of the second doping layer; and / or, The surface doping concentration of the second doping layer is 3E20cm -3 ~3E21cm -3 or 5E20cm -3 ~2E21cm -3 and / or, The surface doping concentration of the third doping layer is 3E20cm -3 ~3E21cm -3 or 5E20cm -3 ~2E21cm -3 and / or, The tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or, The thickness of the tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or, The barrier layer is any one or more combinations of a silicon oxide layer and a silicon carbide layer; and / or, The thickness of the barrier layer is 0.5 nm to 3 nm or 1.5 nm to 2 nm.

9. The solar cell according to claim 1, characterized in that: A first doping layer and a first electrode are formed on the first surface of the silicon substrate. The doping type of the first doping layer is opposite to the doping type of the silicon substrate, and the first electrode is in contact with the first doping layer.

10. The solar cell according to claim 9, characterized in that: The first doped layer is a P-type doped layer; and / or, The surface doping concentration of the first doping layer is 3E18cm -3 ~3E19cm -3 .

11. The solar cell according to claim 9, characterized in that: A first passivation layer and / or a first anti-reflection layer is stacked on the first doping layer.

12. The solar cell according to claim 11, characterized in that: The first passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm; the first anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer with a thickness of 60nm to 130nm.

13. The solar cell according to claim 1, characterized in that The first region includes a plurality of first sub-regions that are distributed in parallel and at equal intervals, the second electrode includes a plurality of gate lines that are distributed in parallel, and the width of the first sub-region is greater than or equal to the width of the gate line.

14. The solar cell according to claim 13, characterized in that: The width of the first sub-region is 50 μm to 150 μm, and the width of the gate line is 15 μm to 100 μm.

15. The solar cell according to claim 1, characterized in that A pyramid texture structure is formed on the first surface of the silicon substrate; and / or, The second surface of the silicon substrate is a polished surface.

16. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the second surface comprising a first region and a second region distributed at intervals; Preparing a tunnel passivation contact structure on the second surface, wherein the tunnel passivation contact structure comprises a tunnel layer, a second doping layer, a barrier layer and a third doping layer stacked in sequence; removing the tunnel passivation contact structure on the second region and retaining the tunnel passivation contact structure on the first region; A second electrode contacting the third doping layer is prepared on the first region.

17. The preparation method according to claim 16, characterized in that: The preparation method further comprises: The third doping layer on the first region is processed by a laser process to form an oxide layer on the surface of the third doping layer on the first region.

18. The preparation method according to claim 17, characterized in that: The laser process is carried out in an atmosphere containing oxygen, the volume concentration of oxygen being 20% ​​to 80%; and / or, The laser power in the laser process is 1W to 100W or 30W to 60W; and / or, The laser frequency in the laser process is 1kHz to 1000kHz or 300kHz to 600kHz; and / or, The laser scanning rate in the laser process is 10000 mm / s to 100000 mm / s or 30000 mm / s to 60000 mm / s; and / or, The number of laser processing in the laser process is 1 to 100 times or 1 to 10 times.

19. The preparation method according to claim 17, characterized in that: Removing the tunnel passivation contact structure on the second region includes: Using the oxide layer as a mask, an alkaline solution is used to remove the second doping layer, the barrier layer and the third doping layer on the second region, and then an acid solution is used to remove the tunneling layer on the second region and the oxide layer on the first region.

20. The preparation method according to claim 16, characterized in that: Preparing a tunnel passivation contact structure on the second surface includes: Depositing a tunneling layer, a first doped amorphous silicon layer, a barrier layer, and a second doped amorphous silicon layer in sequence on the second surface of the silicon substrate; The silicon substrate on which the tunneling layer, the first doped amorphous silicon layer, the barrier layer and the second doped amorphous silicon layer are deposited is annealed at a temperature of 880° C. to 980° C. to transform the doped amorphous silicon layer into a doped polysilicon layer.

21. The preparation method according to claim 16, characterized in that: The preparation method further comprises: The light trapping structure is prepared on the first surface and the second surface of the silicon substrate by a texturing process; and / or, The second surface of the silicon substrate is polished before preparing the tunnel passivation contact structure.

22. The preparation method according to claim 16, characterized in that: The preparation method further comprises: preparing a first doping layer at the first surface, wherein the doping type of the first doping layer is opposite to the doping type of the silicon substrate; and, A first electrode is prepared on the first surface and in contact with the first doping layer.

23. The preparation method according to claim 22, characterized in that: The preparation method further comprises: Prepare a first passivation layer and / or a first anti-reflection layer on the first surface of the silicon substrate; A second passivation layer and / or a second anti-reflection layer is prepared on the second surface of the silicon substrate.

24. A photovoltaic module, characterized in that: The photovoltaic module comprises a plurality of solar cells according to any one of claims 1 to 15 or solar cells prepared by the preparation method according to any one of claims 16 to 23.

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