Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof, and the solar cell comprises a silicon substrate, a first region of a first surface of the silicon substrate is of a smooth surface structure, and a second region of the silicon substrate is of a suede structure; the first doping structure comprises a first tunneling layer and a first doping layer which are located in the first region; the first passivation / anti-reflection layer is located on the side where the first surface is located; the first electrode is in contact with the first doping layer; the second doping structure comprises a second tunneling layer and a second doping layer which are located on the second surface; the second passivation / anti-reflection layer is located on the side where the second surface is located; the second electrode is in contact with the second doping layer; wherein the first electrode and the second electrode are metal electrodes or composite metal electrodes formed by electroplating and / or chemical plating. According to the invention, the first region is of the smooth surface structure, slotting is facilitated, the electrode is formed by electroplating and / or chemical plating, and the cost is reduced; and meanwhile, the second region is of a suede structure, so that the light reflectivity is reduced, and the cell efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the photovoltaic field, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] Currently, TOPCon batteries have become mainstream products. Their structure determines that silver paste is used for both the front and back electrodes, and they need to be sintered at a high temperature of 850°C to 900°C. The cost is high, and the high-temperature sintering process will cause damage and deformation of the silicon substrate, resulting in a high warping rate, which is not conducive to the development of thin-film production.

[0003] In view of this, it is necessary to provide an improved solar cell and a preparation method thereof to solve the above technical problems. Summary of the invention

[0004] The present invention provides a solar cell and a preparation method thereof, which reduces damage to the battery and lowers the battery cost by optimizing the battery structure and the preparation process.

[0005] In order to achieve one of the above-mentioned invention objects, the present invention adopts the following technical solution:

[0006] A solar cell comprises: a silicon substrate, the silicon substrate having a first surface and a second surface arranged opposite to each other, the first surface having a first area and a second area, the first area being a smooth surface structure, and the second area being a velvet surface structure; a first doping structure, the first doping structure comprising a first tunneling layer located in the first area and a first doping layer located on a side of the first tunneling layer away from the silicon substrate; a first passivation / anti-reflection layer, contacting the first doping layer in the first area; a first electrode, the first electrode being located in the first area, and the first electrode passing through the first passivation / anti-reflection layer and contacting the first doping layer; a second doping structure, the second doping structure comprising a second tunneling layer located in the second surface and a second doping layer located on a side of the second tunneling layer away from the silicon substrate; a second passivation / anti-reflection layer, located on a side of the second doping layer away from the second tunneling layer; a second electrode, the second electrode passing through the second passivation / anti-reflection layer and contacting the second doping layer; wherein the first electrode and the second electrode are metal electrodes or composite metal electrodes formed by electroplating and / or chemical plating.

[0007] In one embodiment, the first passivation / anti-reflection layer has a first groove, and the first electrode is located in the first groove; and / or the second passivation / anti-reflection layer has a second groove, and the second electrode is located in the second groove.

[0008] In one embodiment, the first passivation / antireflection layer has a first groove, the width of the first groove is 1 / 4 to 1 / 15 of the width of the first zone; and / or the width of the first zone is 50 μm to 150 μm, and / or the width of the first groove is 10 μm to 15 μm.

[0009] In one embodiment, the first passivation / anti-reflection layer has a first groove, the first doped layer has a first groove corresponding to the first groove, and the first electrode is located in the first groove and the first groove; and / or, the second passivation / anti-reflection layer has a second groove, the second doped layer has a second groove corresponding to the second groove, and the second electrode is located in the second groove and the second groove.

[0010] In one embodiment, the depth of the first groove in the thickness direction of the silicon substrate is 5nm-50nm; and / or the depth of the first groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness of the first doped layer outside the first groove; and / or the thickness of the first doped layer at the first groove is 30nm-150nm; and / or the depth of the second groove in the thickness direction of the silicon substrate is 5nm-50nm, and / or the depth of the second groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness of the second doped layer outside the second groove, and / or the thickness of the second doped layer at the second groove is 30nm-395nm.

[0011] In one embodiment, the first electrode includes a metal transition layer in contact with the first doped layer and a metal main layer located on a side of the metal transition layer away from the first doped layer; and / or the second electrode includes a metal transition layer in contact with the second doped layer and a metal main layer located on a side of the metal transition layer away from the second doped layer.

[0012] In one embodiment, the metal transition layer is selected from a metal that forms an alloy with silicon under low temperature annealing conditions, and the low temperature annealing temperature is 300°C to 400°C; and / or, the metal transition layer is selected from a combination of at least one or more of a Ni layer, a Ti layer, and a Co layer; and / or, the metal main layer is a Cu layer.

[0013] In one embodiment, the silicon substrate is an N-type silicon wafer, the first surface is a light-receiving surface, and the first doped layer is an N-type doped polysilicon layer with a doping concentration of 1E20 cm -3 ~1E21cm -3 , with a thickness of 35nm to 200nm; the second surface is a backlight surface, and the second doped layer is a P-type doped polysilicon layer with a doping concentration of 1E19cm -3 ~1E20cm -3, thickness is 80nm~400nm.

[0014] A method for preparing a solar cell comprises the following steps: providing a silicon substrate, wherein the silicon substrate has a light-receiving surface and a light-receiving surface that are arranged opposite to each other, wherein the light-receiving surface has a first area and a second area; forming a second tunneling layer on the light-receiving surface, forming a second doped amorphous silicon layer on a side of the second tunneling layer away from the silicon substrate, and forming a second mask layer on a side of the second doped amorphous silicon layer away from the second tunneling layer; removing the film layer plated on the light-receiving surface and polishing the light-receiving surface; forming a first tunneling layer on the polished light-receiving surface, forming a first doped amorphous silicon layer on a side of the first tunneling layer away from the silicon substrate, and forming a first mask layer on a side of the first doped amorphous silicon layer away from the first tunneling layer; annealing, wherein the first doped amorphous silicon layer is transformed into a first doped polycrystalline silicon layer, and the second doped amorphous silicon layer is transformed into a first doped polycrystalline silicon layer. The silicon layer is transformed into a second doped polysilicon layer; after annealing, the first mask layer located in the second area is removed; the film layer coated on the backlight surface and the first doped polysilicon layer located in the second area are removed to form a velvet structure in the second area; a first passivation / anti-reflection layer is formed on a side of the first doped polysilicon layer located in the first area away from the first tunneling layer, and a second passivation / anti-reflection layer is formed on a side of the second doped polysilicon layer away from the second tunneling layer; a first groove is formed on the first passivation / anti-reflection layer to expose the first doped polysilicon layer; a second groove is formed in the gate line area of ​​the second passivation / anti-reflection layer to expose the second doped polysilicon layer; a first electrode is formed in the first groove by electroplating and / or chemical plating, and a second electrode is formed in the second groove by electroplating and / or chemical plating.

[0015] In one embodiment, "removing the film layer coated on the light-receiving surface and polishing the light-receiving surface" includes: using a hydrofluoric acid solution to remove the mask layer coated on the light-receiving surface to expose the coated doped amorphous silicon layer; using a polishing alkali solution to remove the doped amorphous silicon layer coated on the light-receiving surface and polishing the light-receiving surface at the same time; and / or, "removing the film layer coated on the backlight surface and the first doped polysilicon layer located in the second area to form a velvet structure in the second area" includes: using a hydrofluoric acid solution to remove the mask layer coated on the backlight surface to expose the coated doped polysilicon layer; using a velveting alkali solution to remove the doped polysilicon layer coated on the backlight surface and the second doped polysilicon layer located in the second area, and forming a velvet structure in the second area.

[0016] In one embodiment, the width of the first groove is 1 / 4 to 1 / 15 of the width of the first region; or, the width of the first region is 50 μm to 150 μm, and / or the width of the first groove is 10 μm to 15 μm.

[0017] In one embodiment, "electroplating and / or chemical plating" includes: electroplating or chemical plating to form a metal transition layer, the metal transition layer is at least one of a Ni layer, a Ti layer, and a Co layer; annealing to form an alloy between the metal transition layer and silicon; and electroplating or chemical plating to form a metal main layer.

[0018] The beneficial effects of the present invention are as follows: the solar cell and the preparation method thereof of the present invention, the first region is a smooth surface structure, which is conducive to forming a good first tunneling layer and a first doping layer in the first region, improving the passivation effect of the gate line region, and thus improving the open circuit voltage; it can also improve the metal contact of the gate line region, so that the J0 under the metal is reduced, thereby improving the battery efficiency; at the same time, the second region is a velvet structure, which reduces the light reflectivity of the light-receiving surface, and also helps to improve the battery efficiency.

[0019] Furthermore, the first area is a smooth surface structure, which is conducive to grooving the first passivation / anti-reflection layer, and the first electrode is formed by electroplating and / or chemical plating, which can reduce the cost of the gate line; at the same time, the second area is a velvet structure, which reduces the light reflectivity of the light-receiving surface and improves the battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic structural diagram of a solar cell in one embodiment of the present invention;

[0021] Figure 2 is a schematic structural diagram of a solar cell in another embodiment of the present invention, in which part of the first electrode and the second electrode are omitted;

[0022] Figure 3 is a schematic structural diagram of a solar cell in another embodiment of the present invention, in which part of the first electrode and the second electrode are omitted;

[0023] Figure 4 for Figure 3 A partial enlarged view of the middle A;

[0024] Figure 5 for Figure 3 A partial enlarged view of point B in the middle;

[0025] Figure 6 The present invention is a flow chart of a method for preparing a solar cell in one embodiment of the present invention.

[0026] Among them, 100-solar cell, 1-silicon substrate, s1-first surface, s2-second surface, 11-first region, 12-second region, 2-first tunneling layer, 3-first doping layer, 31-first groove, 4-first passivation layer, 5-first anti-reflection layer, 51-first groove, 6-second tunneling layer, 7-second doping layer, 71-second groove, 8-second passivation layer, 9-second anti-reflection layer, 91-second groove, 101-first electrode, 102-second electrode. DETAILED DESCRIPTION

[0027] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0028] In the various drawings of the present invention, for the convenience of illustration, some sizes of structures or parts are exaggerated relative to other structures or parts, and thus, they are only used to illustrate the basic structure of the subject matter of the present invention.

[0029] like Figures 1 to 5 As shown, a solar cell 100 according to a preferred embodiment of the present invention comprises a silicon substrate 1, wherein the silicon substrate 1 has a first surface s1 and a second surface s2 arranged opposite to each other, wherein the first surface s1 comprises a first region 11 and a second region 12; a first doping structure, wherein the first doping structure comprises a first tunneling layer 2 located in the first region 11, and a first doping layer 3 located on a side of the first tunneling layer 2 away from the silicon substrate 1; a first passivation / anti-reflection layer, which contacts the first doping layer 3 in the first region 11; a first electrode 101, wherein the first electrode 101 is located in the first region 11, and the first electrode 101 contacts the first doping layer 3 through the first passivation / anti-reflection layer; a second doping structure, wherein the second doping structure comprises a second tunneling layer 6 located in the second surface s2, and a second doping layer 7 located on a side of the second tunneling layer 6 away from the silicon substrate 1; a second passivation / anti-reflection layer, which is located on a side of the second doping layer 7 away from the second tunneling layer 6; and a second electrode 102, wherein the second electrode 102 contacts the second doping layer 7 through the second passivation / anti-reflection layer. The present invention mainly optimizes the structure of the entire battery, improves the efficiency of the battery, and can also simplify the process steps and process difficulty of the battery.

[0030] The silicon substrate 1 is an N-type silicon wafer with a resistivity of 0.5 Ω·cm to 7 Ω·cm.

[0031] like Figure 1 As shown, the first surface s1 is the light-receiving surface, and the second surface s2 is the backlight surface. Alternatively, the first surface is the backlight surface, and the second surface is the light-receiving surface. The first area 11 is a gate line area for forming the first electrode 101. In order to ensure the manufacturing accuracy, the width w3 of the first area 11 is usually greater than the width of the first electrode 101; the second area 12 is a non-gate line area. The following takes the first surface s1 as the light-receiving surface as an example for detailed description.

[0032] like Figures 2 to 5As shown, the first region 11 is a smooth surface structure, which is convenient for the subsequent preparation of the first doping structure and the first electrode 101. The surface roughness of the smooth surface structure is small, and the reflectivity is between 45% and 55%. On the one hand, it is conducive to forming a good first tunneling layer 2 and the first doping layer 3 in the first region 11, improving the passivation effect of the gate line region, and thus improving the open circuit voltage; it can also improve the metal contact in the gate line region, reduce the J0 under the metal, and thus improve the battery efficiency. On the other hand, it is conducive to grooving the first region 11, providing a guarantee for forming the first electrode 101 by electroplating and / or chemical plating process, reducing the recombination of the first region 11, and improving the battery efficiency.

[0033] like Figures 2 to 5 As shown, the second area 12 is a suede structure, which reduces the reflectivity of the light-receiving surface and improves light absorption, thereby improving the short-circuit current and battery efficiency.

[0034] like Figures 1 to 5 As shown, the first doping structure is only located in the first area 11, and the first area 11 is passivated to avoid direct contact between the first electrode 101 and the silicon substrate 1, thereby reducing metal recombination in the first area 11 and improving battery efficiency; at the same time, it does not affect the light absorption of the second area 12.

[0035] The first tunneling layer 2 is selected from a silicon oxide layer or a silicon oxynitride layer, and has a thickness of 1 nm to 3 nm, and can be 1.5 nm, 2 nm, or 2.5 nm. The first tunneling layer 2 utilizes the quantum tunneling effect to allow electrons to pass smoothly and prevent the recombination of holes.

[0036] The first doping layer 3 is an N-type doping layer, specifically an N-type doped polysilicon layer (n-poly Si), such as a phosphorus-doped polysilicon layer or an arsenic-doped polysilicon layer. The doping concentration of the first doping layer 3 is 1E20 cm -3 ~1E21cm -3 , and / or the thickness of the first doping layer 3 is 35nm to 200nm, preferably 80nm to 100nm.

[0037] The first passivation / anti-reflection layer is located on the side where the light receiving surface is located, and plays a role of passivation and / or reducing reflection. In some embodiments, the first passivation / anti-reflection layer is located in the first area 11, and contacts the first doped layer 3 in the first area 11, and the first electrode 101 passes through the first passivation / anti-reflection layer and contacts the first doped layer 3. In other embodiments, the first passivation / anti-reflection layer is located in the first area 11 and the second area 12, and contacts the first doped layer 3 in the first area 11, and contacts the silicon substrate 1 in the second area 12, and the first electrode 101 passes through the first passivation / anti-reflection layer and contacts the first doped layer 3.

[0038] like Figures 1 to 5 As shown, the first passivation / anti-reflection layer plays a role in passivation and / or reducing reflection on the side where the first surface s1 is located. In one embodiment, the first passivation / anti-reflection layer includes a first passivation layer 4 and a first anti-reflection layer 5 .

[0039] Specifically, the first passivation layer 4 and the first anti-reflection layer 5 are only located in the first area 11 .

[0040] Or the first passivation layer 4 and the first anti-reflection layer 5 are located in the first area 11 and the second area 12, the first passivation layer 4 contacts the first doped layer 3 in the first area 11, and the first passivation layer 4 contacts the silicon substrate 1 in the second area 12, and the second area 12 and the first doped layer 3 are passivated to reduce interface recombination.

[0041] The first passivation layer 4 may be selected from aluminum oxide layer (Al2O3), silicon oxide (SiO x ), the thickness of the first passivation layer 4 is 3nm to 5nm. The present invention preferably uses an aluminum oxide layer as the first passivation layer 4. Aluminum oxide has a good passivation effect and can be formed by an ALD process, so its thickness can be precisely controlled, further ensuring a good passivation effect.

[0042] The first anti-reflection layer 5 is located on the surface of the first passivation layer 4 on the side away from the silicon substrate 1. The first anti-reflection layer 5 is selected from silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), silicon oxide (SiO x ) or a combination of one or more thereof; and / or the thickness of the first anti-reflection layer 5 is 70nm to 90nm, which can further reduce the reflectivity of the side where the first surface s1 is located and improve the utilization rate of light.

[0043] In other embodiments, the first passivation / anti-reflection layer includes the first passivation layer 4. The first passivation layer 4 is only located in the first region 11 and in contact with the first doped layer 3. Or the first passivation layer 4 is located in the first region 11 and the second region 12, in contact with the first doped layer 3 in the first region 11, and in contact with the silicon substrate 1 in the second region 12, and the first electrode 101 passes through the first passivation layer 4 and in contact with the first doped layer 3.

[0044] Or, the first passivation / anti-reflection layer includes a first anti-reflection layer 5. The first anti-reflection layer 5 is only located in the first area 11 and contacts the first doped layer 3. Or the first anti-reflection layer 5 is located in the first area 11 and the second area 12, contacts the first doped layer 3 in the first area 11, and contacts the silicon substrate 1 in the second area 12.

[0045] like Figures 2 to 5 As shown, the first passivation / antireflection layer located in the first region 11 has a first groove 51, the first electrode 101 is located in the first groove 51, and the first electrode 101 is in direct contact with the first doping layer 3. Compared with the prior art, the first region 11 of the present invention is a planar structure, which is convenient for grooves and has little groove damage.

[0046] The width w1 of the first groove 51 is smaller than the width w3 of the first region 11 , ensuring that the first groove 51 is completely located in the first region 11 , so that the first electrode 101 is in contact with the first doping layer 3 .

[0047] In one embodiment, the width w1 of the first slot 51 is 1 / 4 to 1 / 15 of the width w3 of the first area 11. On the one hand, the first area 11 will not be too wide to avoid affecting light absorption. On the other hand, this ratio design reduces the alignment requirements of the slotting process to a certain extent, and even if there is an error in the slotting, the first slot 51 can be prevented from extending to the second area 12.

[0048] Since the parasitic absorption of the doped polysilicon layer material itself causes current loss, it is necessary to reduce the width w3 of the first region 11. The limit is that the width w3 of the first region 11 is consistent with the width of the first electrode 101, so that the best efficiency can be achieved. However, the first electrode 101 needs to be printed on the first passivation contact structure, so the width w3 of the first region 11 cannot be reduced infinitely, otherwise the accuracy of the subsequent process cannot be guaranteed; retaining a certain width of the first passivation contact structure can ensure that the first electrode 101 falls 100% on the first passivation contact structure during preparation.

[0049] In one embodiment, the width w3 of the first region 11 is 50 μm to 150 μm, and / or the width of the first electrode 101 is 10 μm to 15 μm.

[0050] Please refer to Figures 3 to 5As shown, in one embodiment, the first doping layer 3 has a first groove 31 corresponding to the first groove 51, and the first electrode 101 is located in the first groove 51 and the first groove 31, and contacts the first doping layer 3. By providing the first groove 31, the contact area between the first electrode 101 and the first doping layer 3 is increased, and the bonding strength between the first electrode 101 and the first doping layer 3 is enhanced, the metal contact resistance is reduced, and the battery efficiency is improved.

[0051] In one embodiment, the depth d1 of the first groove 31 in the thickness direction of the silicon substrate 1 is 5nm-50nm, and / or the depth d1 of the first groove 31 in the thickness direction of the silicon substrate 1 is not greater than 20% of the thickness d2 of the first doping layer 3 outside the location of the first groove 31, and / or the thickness (d2-d1) of the first doping layer 3 at the location of the first groove 31 is 30nm-150nm, that is, after the first groove 31 is formed, the thickness of the first doping layer 3 retained is 30nm-150nm.

[0052] The present invention optimizes at least one characteristic parameter of the depth d1 of the first groove 31, the ratio of the depth d1 of the first groove 31 to the thickness d2 of the first doping layer 3, and the thickness (d2-d1) of the first doping layer 3 at the first groove 31, thereby ensuring the depth of the first electrode 101 extending into the first doping layer 3 and optimizing the contact area between the first electrode 101 and the first doping layer 3; and avoiding damage to the first doping layer 3 when forming the first groove 51 and the first groove 31, and preventing the doped elements in the first doping layer 3 from penetrating the first tunneling layer 2 under the heat / energy of the groove, thereby destroying the passivation effect of the gate line area.

[0053] In one embodiment, the first electrode 101 is a metal electrode or a composite metal electrode formed by electroplating and / or chemical plating.

[0054] In one embodiment, the first electrode 101 is a composite metal electrode, including a metal transition layer in contact with the first doping layer 3 , and a metal main layer located on a surface of the metal transition layer away from the first doping layer 3 .

[0055] The metal transition layer is selected from metals that can form an alloy with silicon under low-temperature annealing conditions. The temperature of the low-temperature annealing is 300° C. to 400° C. to avoid problems such as battery cell warping caused by high-temperature sintering.

[0056] The metal transition layer is selected from a combination of at least one or more of a Ni layer, a Ti layer, and a Co layer. In an optional embodiment, the metal transition layer is a Ni layer, which can be formed by electroplating or chemical plating, and annealed at 300° C. to 400° C. to form a Ni-Si alloy, thereby reducing contact resistance.

[0057] The metal main body layer is the main body of the first electrode 101, and is preferably a metal with good conductivity, low cost, and certain anti-oxidation and anti-corrosion properties. In one embodiment, the metal main body layer is a Cu layer.

[0058] In addition, the metal transition layer serves as a bridge for the metal electrode to bond with silicon, and its thickness is less than that of the metal main layer. In one embodiment, the thickness of the metal transition layer is 100nm to 500nm, and the thickness of the metal main layer is 3μm to 12μm.

[0059] Please refer to Figures 1 to 5 As shown, the second doping structure covers the entire second surface s2 of the silicon substrate 1, passivates the entire backlight surface of the silicon substrate 1, avoids direct contact between the second electrode 102 and the silicon substrate 1, reduces metal recombination in the gate line area of ​​the backlight surface, and improves battery efficiency.

[0060] The second tunneling layer 6 is selected from a silicon oxide layer or a silicon oxynitride layer, and has a thickness of 1 nm to 3 nm, and can be 1.5 nm, 2 nm, or 2.5 nm.

[0061] The second doping layer 7 is a P-type doping layer, specifically a P-type doped polysilicon layer (p-poly Si). In one embodiment, the second doping layer 7 is a boron-doped polysilicon layer or a gallium-doped polysilicon layer. The thickness of the second doping layer 7 is 80nm to 400nm, preferably 200nm to 300nm; and / or the doping concentration of the second doping layer 7 is 1E19cm -3 ~1E20cm -3 .

[0062] The second passivation / anti-reflection layer has a passivation and / or reflection reduction effect on the side where the second surface s2 is located. In one embodiment, the second passivation / anti-reflection layer includes a second passivation layer 8 located on a side surface of the second doped layer 7 away from the second tunneling layer 6, and a second anti-reflection layer 9 located on a side surface of the second passivation layer 8 away from the first doped layer 7.

[0063] The second passivation layer 8 can be selected from an aluminum oxide layer. On the one hand, aluminum oxide can form a good field passivation effect on the P-type doped polysilicon layer, and on the other hand, the thickness of the aluminum oxide layer is precisely controllable. In an optional embodiment, the thickness of the second passivation layer 8 is 3nm to 5nm.

[0064] Preferably, the second passivation layer 8 is made of the same material and has the same thickness as the first passivation layer 4 and can be formed by synchronous deposition.

[0065] The second anti-reflection layer 9 is selected from one or more combinations of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the second anti-reflection layer 9 is 70 nm to 90 nm, which further reduces the reflectivity and improves the utilization rate of light.

[0066] Preferably, the second anti-reflection layer 9 is made of the same material and has the same thickness as the first anti-reflection layer 5 and can be formed by synchronous deposition.

[0067] In other embodiments, the second passivation / anti-reflection layer includes the second passivation layer 8 . Alternatively, the second passivation / anti-reflection layer includes a second anti-reflection layer 9 , and the second anti-reflection layer 9 is located on a surface of the second doped layer 7 away from the second tunneling layer 6 .

[0068] The second passivation / anti-reflection layer 9 has a second groove 91, which is located in the gate line area on the side of the second surface s2. The second electrode 102 is located in the second groove 91. The second electrode 102 is in direct contact with the second doping layer 7, and high-temperature sintering is not required to allow the slurry to penetrate the second anti-reflection layer 9 and the second passivation layer 8.

[0069] The width w2 of the second slot 91 is 10 μm to 15 μm, which meets the width requirement of the second electrode 102 . The second electrode 102 can also be formed in the second slot 91 by electroplating and / or chemical plating.

[0070] In one embodiment, the second doping layer 7 has a second groove 71 corresponding to the second groove 91. The second electrode 102 is located in the second groove 91 and the second groove 71, and contacts the second doping layer 7. By providing the second groove 71, the bonding strength between the second electrode 102 and the second doping layer 7 is enhanced, the metal contact resistance is reduced, and the battery efficiency is improved.

[0071] In one embodiment, the depth d3 of the second groove 71 in the thickness direction of the silicon substrate 1 is 5nm-50nm, and / or the depth d3 of the second groove 71 in the thickness direction of the silicon substrate 1 is not greater than 20% of the thickness d4 of the second doping layer 7 outside the side where the second groove 71 is located, and / or the thickness (d4-d3) of the second doping layer 7 at the location of the second groove 71 is 30nm-395nm, that is, after the second groove 71 is formed, the thickness of the remaining second doping layer 7 is 30nm-395nm.

[0072] The present invention optimizes at least one of the above characteristic parameters: the depth d3 of the second groove 71, the ratio of the depth d3 of the second groove 71 to the thickness d4 of the first doping layer 3, and the thickness (d4-d3) of the second doping layer 7 at the first groove 31. This ensures the depth of the second electrode 102 extending into the second doping layer 7 and optimizes the contact area between the second electrode 102 and the second doping layer 7; it also avoids damage to the second doping layer 7 when forming the second groove 91 and the second groove 71, and under the heat / energy of the groove, the doping elements in the second doping layer 7 penetrate the second tunneling layer 6 and destroy the passivation effect of the gate line area.

[0073] The second electrode 102 is a metal electrode or a composite metal electrode formed by electroplating and / or chemical plating. In the present invention, the structure, material and process of the second electrode 102 are the same as those of the first electrode 101, and will not be described in detail herein.

[0074] In one embodiment, the second electrode 102 is a nickel-copper composite electrode, including a Ni layer in contact with the second doping layer 7 and a copper layer located on the surface of the Ni layer.

[0075] In summary, in the solar cell 100 of the present invention, the first region 11 of the silicon substrate 1 is a smooth surface structure, which is conducive to forming the first doping structure and the first electrode 101 in the first region 11, reducing the recombination of the gate line region, and improving the cell efficiency; at the same time, the second region 12 is a velvet structure, which reduces the light reflectivity of the light receiving surface and improves the cell efficiency. With such a design, electroplating / chemical plating can be used to form a metal electrode or a composite metal electrode, reducing the amount of silver paste used and reducing costs.

[0076] Please refer to Figure 6 As shown, the present invention also provides a method for preparing a solar cell, which improves production efficiency and reduces production costs on the basis of improving cell efficiency by improving process steps and / or sequence.

[0077] The preparation method of the solar cell comprises the following steps: providing a silicon substrate 1, wherein the silicon substrate 1 has a light-receiving surface and a light-receiving surface that are arranged opposite to each other, and the light-receiving surface has a first area 11 and a second area 12; forming a second tunneling layer 6 on the light-receiving surface, forming a second doped amorphous silicon layer on the side of the second tunneling layer 6 away from the silicon substrate 1, and forming a second mask layer on the side of the second doped amorphous silicon layer away from the second tunneling layer 6; removing the film layer coated on the light-receiving surface and polishing the light-receiving surface; forming a first tunneling layer 2 on the polished light-receiving surface, forming a first doped amorphous silicon layer on the side of the first tunneling layer 2 away from the silicon substrate, and forming a first mask layer on the side of the first doped amorphous silicon layer away from the first tunneling layer 2; annealing, wherein the first doped amorphous silicon layer is transformed into a first doped polycrystalline silicon layer as the first doped layer 3, and the second doped amorphous silicon layer is transformed into a second doped A polysilicon layer is used as the second doped layer 7; after annealing, the first mask layer located in the second area 12 is removed; the film layer coated on the backlight surface and the first doped polysilicon layer located in the second area 12 are removed to form a velvet structure in the second area 12; a first passivation / anti-reflection layer is formed on the side of the first doped polysilicon layer located in the first area 11 away from the first tunneling layer 2, and a second passivation / anti-reflection layer is formed on the side of the second doped polysilicon layer away from the second tunneling layer 6; a first groove 51 is formed on the first passivation / anti-reflection layer located in the first area 11 to expose the first doped polysilicon layer; a second groove 91 is formed in the gate line area of ​​the second passivation / anti-reflection layer to expose the second doped polysilicon layer; a first electrode 101 is formed in the first groove 51 by electroplating and / or chemical plating, and a second electrode 102 is formed in the second groove 91 by electroplating and / or chemical plating.

[0078] In the method, the silicon substrate 1 is an N-type silicon wafer with a resistivity of 0.5 Ω·cm to 7 Ω·cm.

[0079] The light-receiving surface and the backlight surface are both smooth structures, that is, a double-sided polished silicon wafer is used as the silicon substrate 1, which is convenient for the groove process in the subsequent steps and can reduce the damage of the groove. Alternatively, before depositing the second tunneling layer 6, the silicon substrate 1 is polished, preferably polished on both sides to ensure that both sides are planar structures.

[0080] In the present invention, the step involving polishing uses a polishing alkali solution, the polishing alkali solution is 0.2mol / L to 0.5mol / L sodium hydroxide (NaOH), 0.2mol / L to 0.5mol / L potassium hydroxide (KOH), 0.4mol / L to 0.8mol / L tetramethylammonium hydroxide (TMAH), and the polishing time is 100s to 300s.

[0081] After polishing, the reflectivity of the surface of the silicon substrate 1 is between 45% and 55%, and there is no abnormal appearance.

[0082] By adopting the PECVD process, a silicon oxide layer or a silicon oxynitride layer is deposited on the polished silicon substrate 1 as the second tunneling layer 6, with a thickness of 1 nm to 3 nm.

[0083] A PECVD process is used, trimethylboron (TMB), borane (B2H6), boron trifluoride (BF3), or metal gallium (Ga) is used as a P-type doping source, and a P-type doped amorphous silicon layer doped with B or Ga is deposited; the thickness of the P-type doped amorphous silicon layer is 80nm to 400nm, preferably 200nm to 300nm; the doping concentration is 1E19cm -3 ~1E20cm -3 .

[0084] After the P-type doped amorphous silicon layer, nitrous oxide (N2O) and silane (SiH4) are introduced to form a silicon oxide layer as the second mask layer to protect the internal film layer in subsequent processes.

[0085] “Removing the film layer deposited on the light-receiving surface and polishing the light-receiving surface” includes: using a hydrofluoric acid (HF) solution to remove the mask layer deposited on the light-receiving surface to expose the doped amorphous silicon layer deposited on the light-receiving surface; then using a polishing alkali solution to remove the doped amorphous silicon layer deposited on the light-receiving surface, and polishing the light-receiving surface to provide a good plane foundation for the preparation of subsequent film layers. In this process, the second tunneling layer 6 and the second doped amorphous silicon layer on the backlight side are not damaged.

[0086] In the present invention, the concentration of the HF solution used for de-coating is 0.01 mol / L to 0.03 mol / L. The polishing alkali solution is as described above and will not be described in detail.

[0087] In one embodiment, a chain machine and HF solution are used to remove the mask layer deposited on the light-receiving surface; and a tank machine and polishing alkali solution are used to remove the doped amorphous silicon layer plated on the light-receiving surface.

[0088] A PECVD process is adopted to deposit a silicon oxide layer or a silicon oxynitride layer as the first tunneling layer 2 on the polished light-receiving surface, with a thickness of 1 nm to 3 nm.

[0089] A PECVD process is used, using phosphine (PH3) or arsine (AsH3) as an N-type doping source, to deposit an N-type doped amorphous silicon layer, such as a phosphorus-doped amorphous silicon layer, with a thickness of 35nm to 200nm, preferably 80nm to 100nm; the doping concentration is 1E20cm -3 ~1E21cm -3 .

[0090] The first mask layer is formed by a PECVD process, wherein the first mask layer is selected from SiO x layer, or SiN x layer, or SiO x N y The layer has a thickness of 70nm to 90nm and acts as a mask in subsequent processes.

[0091] The annealing temperature of the present invention is 880° C. to 940° C., which simultaneously meets the doping annealing requirements of the first doped amorphous silicon layer and the second doped amorphous silicon layer. The two-step annealing is integrated into one step, which can reduce the fixed asset investment.

[0092] In this step, the N-type doped amorphous silicon layer on the light-receiving side is transformed into an N-type doped polysilicon layer; the P-type doped amorphous silicon layer on the backlight side is transformed into a P-type doped polysilicon layer to form a back junction with the silicon substrate 1 .

[0093] After annealing, the first mask layer located in the second area 12 is removed, that is, a window is opened on the first mask layer in the second area 12 to expose the P-type doped polysilicon layer in this area; the first mask layer located in the first area 11 is retained to protect the first doped polysilicon layer in subsequent processes.

[0094] The width w3 of the remaining first region 11 is 50 μm to 150 μm. If it is too narrow, the accuracy of the subsequent process cannot be guaranteed. If it is too wide, it will have a greater impact on the light absorption of the light-receiving surface.

[0095] In one embodiment, a laser grooving process is used to remove the first mask layer located in the second area 12. In the present invention, the laser grooving process used is selected from green picosecond laser or ultraviolet picosecond laser, and the laser damage is small.

[0096] Specifically, the power of the ultraviolet picosecond laser is 8W to 20W, the spot diameter is 100μm to 150μm, the frequency is 500kHz to 600kHz, and the scanning speed is 45000m / s to 60000m / s.

[0097] The power of green picosecond laser is 20W~50W, the spot diameter is 100μm~150μm, the frequency is 500kHz~600kHz, and the scanning speed is 45000m / s~60000m / s.

[0098] “Removing the film layer plated on the backlight surface and the first doped polysilicon layer located in the second area 12, and forming a velvet structure in the second area 12” includes: using HF solution to remove the mask layer plated on the backlight surface, using velvet alkali solution to remove the N-type doped polysilicon layer plated on the backlight surface, and simultaneously removing the N-type doped polysilicon layer in the second area 12, and forming a velvet structure in the second area 12, and the first tunneling layer 2 and the first doped polysilicon layer are retained in the first area 11 due to the blocking of the first mask layer.

[0099] In one embodiment, a chain machine and HF solution are used to remove the mask layer plated on the backlight surface, and a slot machine and texturing alkali solution are used to remove the doped polysilicon layer plated on the back side and the second doped polysilicon layer located in the second area 12, and a velvet structure is formed in the second area 12.

[0100] In one embodiment, a first passivation layer 4 and a first anti-reflection layer 5 are formed on the side where the light-receiving surface is located, and the first passivation layer 4 and the first anti-reflection layer 5 together constitute the first passivation / anti-reflection layer.

[0101] The first passivation layer 4 is in contact with the first doped layer 3 only in the first region 11, and passivates the first doped layer 3. Alternatively, the first passivation layer 4 is in contact with the first doped layer 3 in the first region 11, and the first passivation layer 4 is in contact with the silicon substrate 1 in the second region 12, and passivates the second region 12 and the first doped layer 3 to reduce interface recombination. The first anti-reflection layer 5 is located on the side of the first passivation layer 4 away from the silicon substrate 1.

[0102] In one embodiment, a tubular Thermal-ALD process is used in a single-chip manner to deposit an aluminum oxide layer on the side where the light-receiving surface is located as the first passivation layer 4, thereby forming a good chemical passivation effect on the side where the light-receiving surface is located.

[0103] The thickness of the first passivation layer 4 is 3 nm to 5 nm. If it is too thin, the film layer may be uneven and the passivation effect is poor; if it is too thick, material is wasted and it is not conducive to the incidence of light.

[0104] In one embodiment, a PECVD process is used to deposit a stacked film of one or more of silicon nitride, silicon oxynitride, and silicon oxide on the side of the first passivation layer 4 away from the silicon substrate 1 as the first anti-reflection layer 5 with a thickness of 70nm to 90nm, thereby reducing the reflectivity while ensuring the transmittance of light.

[0105] In one embodiment, a first passivation layer 4 is formed on the side where the light receiving surface is located as the first passivation / anti-reflection layer. The first passivation layer 4 is in contact with the first doped layer 3 only in the first region 11, and the first doped layer 3 is passivated. Alternatively, the first passivation layer 4 is in contact with the first doped layer 3 in the first region 11, and the first passivation layer 4 is in contact with the silicon substrate 1 in the second region 12. The formation process of the first passivation layer 4 is as described above.

[0106] In another embodiment, a first anti-reflection layer 5 is formed on the side where the light-receiving surface is located as the first passivation / anti-reflection layer. The first anti-reflection layer 5 is in contact with the first doped layer 3 in the first area 11. Alternatively, the first anti-reflection layer 5 is in contact with the first doped layer 3 in the first area 11 and in contact with the silicon substrate 1 in the second area 12, and the formation process of the first anti-reflection layer 5 is as described above.

[0107] In one embodiment, a second passivation layer 8 and a second anti-reflection layer 9 are formed on the backlight surface, and the second passivation layer 8 and the second anti-reflection layer 9 together constitute the second passivation / anti-reflection layer.

[0108] The second passivation layer 8 may be formed by the same process as the first passivation layer 4 .

[0109] The material of the second passivation layer 8 may be the same as or different from that of the first passivation layer 4. The thickness of the second passivation layer 8 may be the same as or different from that of the first passivation layer 4. The first passivation layer 4 and the second passivation layer 8 may be formed in steps to adapt to the differentiated design of the passivation layers on both sides in terms of materials, thickness, etc. For example, the thickness of the first passivation layer 4 is less than the thickness of the second passivation layer 8 to ensure the light transmittance of the light receiving surface. The first passivation layer 4 and the second passivation layer 8 may also be formed simultaneously to simplify the process steps.

[0110] In one embodiment, a tubular Thermal-ALD process is adopted in a single-chip manner to deposit an aluminum oxide layer as the second passivation layer 8 on the side of the second doped layer 7 away from the second tunneling layer 6 , with a thickness of 3 nm to 5 nm, thereby forming a good field passivation effect on the second doped layer 7 .

[0111] The second anti-reflection layer 9 may be formed using the same process as the first anti-reflection layer 5 .

[0112] The material of the second anti-reflection layer 9 may be the same as or different from that of the first anti-reflection layer 5. The thickness of the second anti-reflection layer 9 may be the same as or different from that of the first anti-reflection layer 5. The first anti-reflection layer 5 and the second anti-reflection layer 9 may be formed in steps to adapt to the differentiated design of the anti-reflection layers on both sides in terms of materials, thickness, etc. For example, the thickness of the first anti-reflection layer 5 is less than that of the second anti-reflection layer 9, so as to improve the light transmittance of the film layer located on the light-receiving surface. The first anti-reflection layer 5 and the second anti-reflection layer 9 may also be formed simultaneously to simplify the process steps.

[0113] In one embodiment, a PECVD process is used to deposit a stacked film of one or more of silicon nitride, silicon oxynitride, and silicon oxide on the side of the second passivation layer 8 away from the second doping layer 7 as the second anti-reflection layer 9 with a thickness of 70nm to 90nm, which reduces the reflectivity while ensuring the transmittance of light.

[0114] In one embodiment, a second passivation layer 8 is formed on the side where the backlight surface is located as the second passivation / anti-reflection layer. The formation process of the second passivation layer 8 is as described above.

[0115] In another embodiment, a second anti-reflection layer 9 is formed as the second passivation / anti-reflection layer on a surface of the second doping layer 7 away from the second tunneling layer 6. The formation process of the second anti-reflection layer 9 is as described above.

[0116] As described above, the first groove 51 is formed on the first passivation / anti-reflection layer located in the first area, and the second groove 91 is formed on the second passivation / anti-reflection layer located in the gate line area of ​​the backlight surface, both using a laser groove process with high groove precision. The laser groove process is as described above and will not be described in detail here.

[0117] The width w1 of the first groove 51 is narrower than the first region 11 , ensuring that the first groove 51 is completely located in the first region 11 , so that the first electrode 101 located in the first groove 51 is in contact with the first doped polysilicon layer.

[0118] In one embodiment, the width w1 of the first slot 51 is 1 / 4 to 1 / 15 of the width w3 of the first area 11. On the one hand, the first area 11 will not be too wide to avoid affecting light absorption. On the other hand, this ratio design reduces the alignment requirements of the slotting process to a certain extent. Even if there are errors or work errors during laser slotting, it can ensure that the first slot 51 is completely located in the first area 11 and does not extend to the second area 12.

[0119] In one embodiment, the width w3 of the first region 11 is 50 μm to 150 μm, and / or the width w1 of the first groove 51 is 10 μm to 15 μm.

[0120] Compared with the velvet structure, the first region 11 is a planar structure, laser grooving is simple, and the damage caused is relatively light. In this way, in the subsequent electroplating and chemical plating processes, the metals such as Ni and Cu have a strong bonding force attached to the first doped polysilicon layer, which can reduce the contact resistance.

[0121] The width w2 of the second slot 91 is 10 μm to 15 μm, which meets the width requirement of the second electrode 102 . The second electrode 102 can also be formed in the second slot 91 by electroplating and / or chemical plating.

[0122] The inventors found that when the laser grooving process forms the first groove 31 and the second groove 91, laser damage will be caused to the first doped polysilicon layer and the second doped polysilicon layer inside. Under the laser energy, the first doped polysilicon layer and the second doped polysilicon layer react with the surrounding atmosphere to form a laser damaged layer, for example, react with oxygen in the air to form a silicon oxide layer. The laser damaged layer is not conductive, which will affect the formation of electrodes by the electroplating process, and will also affect the bonding of the electrode to silicon. Furthermore, the method for preparing the solar cell also includes the following steps: before forming the first electrode 101 and the second electrode 102, the damaged layer is removed to reduce the contact resistance between the electrode and the doped polysilicon layer.

[0123] In the present invention, a washing liquid is used to remove the laser damaged layer in the first groove 51 and the second groove 91. The washing liquid is selected from a 0.01 mol / L to 0.05 mol / L HF solution, and the cleaning time is 20s to 100s, preferably 20s to 80s, preferably 20s to 60s, preferably 20s to 40s, preferably 20s to 30s.

[0124] After removing the laser damaged layer, the first electrode 101 and the second electrode 102 are formed in the first slot 51 and the second slot 91 respectively by electroplating and / or chemical plating. The electroplating and / or chemical plating process specifically includes: forming a metal transition layer by electroplating or chemical plating; annealing to form an alloy between the metal transition layer and silicon; and forming a metal main layer by electroplating or chemical plating.

[0125] The metal transition layer can enhance the bonding between the first electrode 101, the second electrode 102 and silicon, and in particular, can form an alloy with the silicon substrate 1 after annealing, with stronger bonding. The metal transition layer can also improve the conductivity of the inner wall of the first slot 51 and the second slot 91, which is conducive to forming a good metal main layer in the subsequent electroplating process.

[0126] The metal transition layer is selected from metals that can form alloys with silicon under low temperature annealing conditions. The low temperature annealing temperature is 300° C. to 400° C., which avoids the problem of cell warping caused by high temperature, and the low temperature annealing cost is low.

[0127] The metal transition layer is at least one of a Ni layer, a Ti layer, and a Co layer. In one embodiment, the metal transition layer is a Ni layer, which can be formed by electroplating or chemical plating, and annealed at 300° C. to 400° C. to form a Ni-Si alloy.

[0128] The metal main body layer is the main body of the first electrode 101 and the second electrode 102, and is preferably a metal with good electrical conductivity, low cost, and certain anti-oxidation and anti-corrosion properties.

[0129] The metal main layer is a Cu layer. In one embodiment, the metal main layer is a Cu layer.

[0130] In addition, the metal transition layer serves as a bridge for combining the metal electrode and silicon, and its thickness is less than that of the metal main layer. The thickness of the metal transition layer is 100nm to 500nm, and the thickness of the metal main layer is 3μm to 12μm.

[0131] In addition, based on any of the above-mentioned preparation methods, the preparation method of the solar cell further includes: forming a first groove 31 corresponding to the first groove 51 on the first doped polysilicon layer. The first electrode 101 is located in the first groove 31 and the first groove 51, and contacts the first doped layer 3. By providing the first groove 31, the contact area between the first electrode 101 and the first doped layer 3 is increased, and the bonding strength between the first electrode 101 and the first doped layer 3 is enhanced, the metal contact resistance is reduced, and the battery efficiency is improved.

[0132] In one embodiment, the depth d1 of the first groove 31 in the thickness direction of the silicon substrate 1 is 5nm-50nm, and / or the depth d1 of the first groove 31 in the thickness direction of the silicon substrate 1 is not greater than 20% of the thickness d2 of the first doped polysilicon layer outside the first groove 31, that is, the depth d1 of the first groove 31 in the thickness direction of the silicon substrate 1 accounts for no more than 20% of the thickness of the first doped polysilicon layer; and / or the thickness (d2-d1) of the first doped layer 3 at the first groove 31 is 30nm-150nm, that is, after the first groove 31 is formed, the thickness of the first doped layer 3 retained is 30nm-150nm.

[0133] Such a configuration not only ensures the depth of the first electrode 101 extending into the first doping layer 3 and optimizes the contact area between the first electrode 101 and the first doping layer 3, but also avoids damage to the first doping layer 3 when forming the first groove 51 and the first groove 31, and avoids the doping elements in the first doping layer 3 penetrating the first tunneling layer 2 under the heat / energy of the groove, thereby destroying the passivation effect of the gate line area.

[0134] In the present invention, the first groove 31 and the first slot 51 are formed by a laser slotting process, which is described above and will not be described in detail herein. Specifically, the first groove 31 is formed when the first slot 51 is formed, that is, in the same process step, the first slot 51 and the first groove 31 are formed successively by a laser slotting process.

[0135] The first passivation / anti-reflection layer is provided with a first groove 51. When the first doped polysilicon layer is provided with the first groove 31, the washing liquid is used to remove the laser damaged layer in the first groove 51 and the first groove 31, and then the first electrode 101 is formed by electroplating and / or chemical plating process.

[0136] In addition, based on any of the above-mentioned preparation methods, the preparation method of the solar cell further includes: forming a second groove 71 corresponding to the second groove 91 on the second doped polysilicon layer. The second electrode 102 is located in the second groove 91 and the second groove 71, and contacts the second doped layer 7. By providing the second groove 71, the bonding strength between the second electrode 102 and the second doped layer 7 is enhanced, the metal contact resistance is reduced, and the battery efficiency is improved.

[0137] In one embodiment, the depth d3 of the second groove 71 in the thickness direction of the silicon substrate 1 is 5nm-50nm, and / or the depth d3 of the second groove 71 in the thickness direction of the silicon substrate 1 is not greater than 20% of the thickness d4 of the second doping layer 7 outside the second groove 71, and / or the thickness (d4-d3) of the second doping layer 7 at the second groove 71 is 30nm-395nm, that is, after the second groove 71 is formed, the thickness of the remaining second doping layer 7 is 30nm-395nm.

[0138] Such a configuration not only ensures the depth of the second electrode 102 extending into the second doping layer 7 and optimizes the contact area between the second electrode 102 and the second doping layer 7, but also avoids damage to the second doping layer 7 when forming the second groove 91 and the second groove 71, and under the heat / energy of the groove, the doping elements in the second doping layer 7 penetrate the second tunneling layer 6 and destroy the passivation effect of the gate line area.

[0139] In the present invention, the second groove 71 and the second slot 91 are formed by a laser slotting process, which is described above and will not be described in detail herein. Specifically, the second groove 71 is formed when the second slot 91 is formed, that is, in the same process step, the second slot 91 and the second groove 71 are formed successively by a laser slotting process.

[0140] When a second groove 91 is provided on the second passivation / anti-reflection layer and a second groove 71 is provided on the second doped polysilicon layer, the washing liquid is used to remove the laser damaged layer in the second groove 91 and the second groove 71, and then the second electrode 102 is formed by electroplating and / or chemical plating process.

[0141] In another embodiment, the present invention can also prepare the first doping structure and the second doping structure separately.

[0142] In the method for preparing the solar cell, the method for preparing the first doping structure comprises the following steps:

[0143] Forming a first tunneling layer 2 on the entire light-receiving surface of the silicon substrate 1, forming the first doped amorphous silicon layer on a side of the first tunneling layer 2 away from the silicon substrate 1, and forming a first mask layer on a side of the first doped amorphous silicon layer away from the first tunneling layer 2;

[0144] Annealing to transform the first doped amorphous silicon layer into a first doped polysilicon layer as the first doped layer 3;

[0145] Grooving the first mask layer in the second region 12 to expose the first doped polysilicon layer;

[0146] removing the exposed first doped polysilicon layer, removing the first doped polysilicon layer located in the second area 12 by using an alkaline solution, and forming a velvet structure in the second area 12;

[0147] The first passivation layer 4 is formed on the side where the light receiving surface is located, and the first anti-reflection layer 5 is formed on the side of the first passivation layer 4 away from the silicon substrate 1, the first passivation layer 4 is in contact with the first doping layer 3 in the first area 11, and the first passivation layer 4 is in contact with the silicon substrate 1 in the second area 12;

[0148] The first groove 51 is formed on the first passivation layer 4 and the first anti-reflection layer 5 located in the first area 11 to expose the first doping layer 3 , and the first electrode 101 is formed in the first groove 51 by electroplating and / or chemical plating.

[0149] In this method, each step and its film layer parameters etc. can adopt the above-mentioned process steps, which will not be described in detail here.

[0150] In the method for preparing the solar cell, the method for preparing the second doping structure comprises the following steps:

[0151] forming the second tunneling layer 6 on the backlight surface of the silicon substrate 1, and forming the second doped amorphous silicon layer on the side of the second tunneling layer 6 away from the silicon substrate 1;

[0152] Annealing, so that the second doped amorphous silicon layer is transformed into a second doped polycrystalline silicon layer as the second doped layer 7;

[0153] forming a second passivation layer 8 on a side of the second doped layer 7 away from the second tunneling layer 7 , and forming a second anti-reflection layer 9 on a side of the second passivation layer 8 away from the second doped layer 7 ;

[0154] Laser grooves are formed in the gate line regions of the second passivation layer 8 and the second anti-reflection layer 9 to form the second grooves, exposing the second doping layer 7;

[0155] Electroplating and / or chemical plating is performed to form a second electrode 102 in the second groove.

[0156] In this method, each step and its film layer parameters etc. can adopt the above-mentioned process steps, which will not be described in detail here.

[0157] In addition, the characteristic parameters of the solar cell 100 of the present invention are applicable to the corresponding structures in the method for preparing the solar cell; the characteristic parameters of the method for preparing the solar cell are applicable to the corresponding characteristics of the solar cell 100. The solar cell 100 can be prepared by the method for preparing the solar cell, or by other preparation methods.

[0158] The method for preparing the solar cell of the present invention will be described in detail below with specific implementations.

[0159] Example 1

[0160] Polishing: Conventional silicon wafer polishing process, both sides of the silicon wafer form a polished surface with a reflectivity of 45% to 55%, with no abnormal appearance; the polishing alkali solution is 0.3 mol / L sodium hydroxide (NaOH) solution, and the polishing time is 200s.

[0161] A 2 nm silicon oxide layer is deposited on the backlight surface of the silicon substrate 1 by using a PECVD process as the second tunneling layer 6 .

[0162] The PECVD process was used to form a P-type doped amorphous silicon layer with a thickness of 250nm and a doping concentration of 1E19cm-1 using borane (B2H6) as a doping source for the P-type structure as the second doped amorphous silicon layer. -3 ~1E20cm -3 .

[0163] After the PECVD equipment deposits the P-type doped amorphous silicon layer, laughing gas (N2O) and silane (SiH4) are introduced to generate SiO x , as the second mask layer.

[0164] In addition to the film layer plated on the light-receiving surface: a chain machine is used to add a 0.01 mol / L HF solution to remove the mask layer plated on the light-receiving surface; a slot machine is used to add a 0.4 mol / L NaOH solution to remove the P-type doped amorphous silicon layer plated on the light-receiving surface.

[0165] A 2 nm silicon oxide layer is deposited on the light-receiving surface of the silicon substrate 1 by using a PECVD process as the first tunneling layer 2 .

[0166] The PECVD process is used to form an N-type doped amorphous silicon layer as the first doped amorphous silicon layer using PH3 as the doping source of the N-type structure, with a thickness of 90nm and a doping concentration of 1E20cm -3 ~1E21cm -3 .

[0167] After the PECVD equipment deposits the N-type doped amorphous silicon layer, laughing gas (N2O) and silane (SiH4) are introduced to generate SiO x , as the first mask layer.

[0168] Annealing: The annealing temperature is 910° C., and the doping annealing requirements of the first doped amorphous layer and the second doped amorphous layer are simultaneously achieved, so that the first doped amorphous silicon layer is transformed into the first doped polycrystalline silicon layer, and the second doped amorphous silicon layer is transformed into the second doped polycrystalline silicon layer.

[0169] In the second region 12 , green light picosecond or ultraviolet picosecond laser grooving is performed to expose the first doped polysilicon layer in the second region 12 . The width w3 of the first region 11 is 100 μm.

[0170] The film layer plated on the backlight surface is removed, and the second area 12 is textured: a chain machine is used to add 0.02mol / L HF solution to remove the mask layer plated on the backlight surface; a slot machine is used to add 0.3mol / L NaOH solution to remove the doped polysilicon layer plated on the backlight surface, and a velvet structure is formed in the second area 12. The first area 11 retains the structure of the polished surface due to the blocking of the retained first mask layer.

[0171] Preparation of double-sided passivation layer: Using ALD process, Al2O3 film is plated on both sides as the first passivation layer 4 and the second passivation layer 8, with a thickness of 4nm, which has a field passivation effect on the p-poly Si layer on the backlight side and a good chemical passivation effect on the n-poly Si layer on the light-receiving side.

[0172] Preparation of double-sided anti-reflection layer: using PECVD process to deposit SiNx film as the first anti-reflection layer 5 on the side where the light-receiving surface is located and the second anti-reflection layer 9 on the side where the backlight surface is located, so as to reduce the double-sided reflectivity.

[0173] Grooving the light-receiving surface: using a laser grooving process, the first groove 51 is formed on the first anti-reflection layer 5 and the first passivation layer 3 of the first region 11, and the width w1 of the first groove 51 is 13 μm, so that the first electrode 101 can be formed by subsequent electroplating or chemical plating.

[0174] Grooving on the backlight surface: using a laser grooving process, laser grooving is performed on the second anti-reflection layer 9 and the second passivation layer 8 in the gate line area of ​​the backlight surface to form the second groove 91, and the width w2 of the second groove 91 is 12μm, so that the second electrode 102 can be formed by subsequent electroplating or chemical plating.

[0175] An HF solution with a concentration of 0.01 to 0.05 mol / L is used to remove surface dust and the laser damaged layer formed by laser grooving, improve the bonding between the metal electrode and silicon, and increase the open circuit voltage (Voc) and short circuit current (Jsc).

[0176] Electroplating / chemical Ni plating, using relevant processes in the prior art to form a uniform and dense nickel plating layer in the first groove 51 and the second groove 91.

[0177] Annealing: The temperature is preferably 300°C to 400°C to form a Ni-Si alloy.

[0178] Electroplating / chemical plating of Cu: using the related process in the prior art to grow Cu in the first slot 51 and the second slot 91 to form a Ni-Cu composite metal electrode.

[0179] Testing and sorting: Testing and sorting of battery cells and storage.

[0180] Example 2

[0181] The difference between Example 2 and Example 1 is only that:

[0182] Grooving on the light-receiving surface: using a laser grooving process, the first groove 51 is formed on the first anti-reflection layer 5 and the first passivation layer 3 of the first region 11, and a first groove 31 corresponding to the first groove 51 is formed on the first doped polysilicon layer, and the width w1 of the first groove 51 and the first groove 31 is 13 μm, so that the first electrode 101 can be formed by subsequent electroplating or chemical plating.

[0183] Grooving on the backlight surface: using a laser grooving process, laser grooving is performed on the second anti-reflection layer 9 and the second passivation layer 8 in the gate line area of ​​the backlight surface to form the second groove 91, and a second groove 71 corresponding to the second groove 91 is formed on the second doped polysilicon layer 7, and the width w2 of the second groove 91 and the second groove 71 is 12μm, so that the second electrode 102 can be formed by subsequent electroplating or chemical plating.

[0184] An HF solution with a concentration of 0.01 to 0.05 mol / L is used to remove surface dust and the laser damaged layer formed by laser grooving, improve the bonding between the metal electrode and silicon, and increase the open circuit voltage (Voc) and short circuit current (Jsc).

[0185] Electroplating / chemical Ni plating, using relevant processes in the prior art to form a uniform and dense nickel plating layer in the first slot 51 and the first groove 31 , the second slot 91 and the second groove 71 .

[0186] Annealing: The temperature is preferably 300°C to 400°C to form a Ni-Si alloy.

[0187] Electroplating / chemical plating of Cu: using the relevant process in the prior art to grow Cu on the nickel plating layer to form a Ni-Cu composite metal electrode.

[0188] In summary, in the solar cell 100 and the preparation method thereof of the present invention, the first area 11 of the silicon substrate 1 is a smooth surface structure, which is conducive to grooving in the first area 11, and the first electrode 101 is formed by electroplating and / or chemical plating processes, which can reduce the electrode cost; at the same time, the second area 12 is a velvet structure, which reduces the light reflectivity of the light-receiving surface and improves the battery efficiency.

[0189] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0190] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, wherein the silicon substrate has a first surface and a second surface arranged opposite to each other, the first surface has a first area and a second area, the first area has a smooth surface structure, and the second area has a velvet surface structure; A first doping structure, wherein the first doping structure includes a first tunneling layer located in the first region and a first doping layer located on a side of the first tunneling layer away from the silicon substrate; a first passivation / anti-reflection layer, contacting the first doped layer in the first region; a first electrode, the first electrode being located in the first region and the first electrode being in contact with the first doping layer through the first passivation / anti-reflection layer; a second doping structure, the second doping structure comprising a second tunneling layer located on the second surface and a second doping layer located on a side of the second tunneling layer away from the silicon substrate; A second passivation / anti-reflection layer, located on a side of the second doped layer away from the second tunneling layer; a second electrode, the second electrode passing through the second passivation / anti-reflection layer and contacting the second doping layer; Wherein, the first electrode and the second electrode are metal electrodes or composite metal electrodes formed by electroplating and / or chemical plating.

2. The solar cell according to claim 1, characterized in that: The first passivation / anti-reflection layer has a first groove, and the first electrode is located in the first groove; And / or, the second passivation / anti-reflection layer has a second groove, and the second electrode is located in the second groove.

3. The solar cell according to claim 2, characterized in that: The first passivation / anti-reflection layer has a first groove, and the width of the first groove is 1 / 4 to 1 / 15 of the width of the first region; and / or The width of the first region is 50 μm to 150 μm, and / or the width of the first groove is 10 μm to 15 μm.

4. The solar cell according to claim 2, characterized in that: The first passivation / anti-reflection layer has a first groove, the first doping layer has a first groove corresponding to the first groove, and the first electrode is located in the first groove and the first groove; And / or, the second passivation / anti-reflection layer has a second groove, the second doping layer has a second groove corresponding to the second groove, and the second electrode is located in the second groove and the second groove.

5. The solar cell according to claim 4, characterized in that: The depth of the first groove in the thickness direction of the silicon substrate is 5nm-50nm; and / or the depth of the first groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness of the first doped layer outside the first groove; and / or the thickness of the first doped layer at the first groove is 30nm-150nm; And / or, the depth of the second groove in the thickness direction of the silicon substrate is 5nm-50nm, and / or the depth of the second groove in the thickness direction of the silicon substrate is not greater than 20% of the thickness of the second doped layer outside the second groove, and / or the thickness of the second doped layer at the second groove is 30nm-395nm.

6. The solar cell according to claim 1, characterized in that: The first electrode comprises a metal transition layer in contact with the first doping layer, and a metal main layer located on a side of the metal transition layer away from the first doping layer; And / or, the second electrode includes a metal transition layer in contact with the second doped layer and a metal main layer located on a side of the metal transition layer away from the second doped layer.

7. The solar cell according to claim 6, characterized in that: The metal transition layer is selected from metals that form alloys with silicon under low temperature annealing conditions, and the low temperature annealing temperature is 300° C. to 400° C.; And / or, the metal transition layer is selected from a combination of at least one or more of a Ni layer, a Ti layer, and a Co layer; And / or, the metal main layer is a Cu layer.

8. The solar cell according to any one of claims 1 to 7, characterized in that: The silicon substrate is an N-type silicon wafer, the first surface is a light-receiving surface, and the first doping layer is an N-type doped polysilicon layer with a doping concentration of 1E20cm -3 ~1E21cm -3 , with a thickness of 35nm to 200nm; the second surface is a backlight surface, and the second doped layer is a P-type doped polysilicon layer with a doping concentration of 1E19cm -3 ~1E20cm -3 , thickness is 80nm~400nm.

9. A method for preparing a solar cell, characterized in that: The steps include: Providing a silicon substrate, wherein the silicon substrate has a light-receiving surface and a backlight surface that are oppositely arranged, and the light-receiving surface has a first area and a second area; forming a second tunneling layer on the backlight surface, forming a second doped amorphous silicon layer on a side of the second tunneling layer away from the silicon substrate, and forming a second mask layer on a side of the second doped amorphous silicon layer away from the second tunneling layer; Removing the film layer coated on the light-receiving surface and polishing the light-receiving surface; forming a first tunneling layer on the polished light-receiving surface, forming a first doped amorphous silicon layer on a side of the first tunneling layer away from the silicon substrate, and forming a first mask layer on a side of the first doped amorphous silicon layer away from the first tunneling layer; Annealing, wherein the first doped amorphous silicon layer is transformed into a first doped polysilicon layer, and the second doped amorphous silicon layer is transformed into a second doped polysilicon layer; After annealing, removing the first mask layer located in the second area; Removing the film layer coated on the backlight surface and the first doped polysilicon layer located in the second area, and forming a velvet structure in the second area; forming a first passivation / anti-reflection layer on a side of the first doped polysilicon layer located in the first region away from the first tunneling layer, and forming a second passivation / anti-reflection layer on a side of the second doped polysilicon layer away from the second tunneling layer; forming a first groove on the first passivation / anti-reflection layer to expose the first doped polysilicon layer; forming a second groove in the gate line region of the second passivation / anti-reflection layer to expose the second doped polysilicon layer; A first electrode is formed by electroplating and / or chemical plating in the first groove, and a second electrode is formed by electroplating and / or chemical plating in the second groove.

10. The method for preparing a solar cell according to claim 9, characterized in that: “Removing the film layer coated on the light-receiving surface and polishing the light-receiving surface” includes: Using a hydrofluoric acid solution to remove the mask layer of the light-receiving surface, so as to expose the doped amorphous silicon layer; Using polishing alkali solution to remove the doped amorphous silicon layer plated around the light-receiving surface, and polishing the light-receiving surface at the same time; And / or, “removing the film layer coated on the backlight surface and the first doped polysilicon layer located in the second area to form a velvet structure in the second area” includes: Using a hydrofluoric acid solution to remove the mask layer of the backlight surface, exposing the doped polysilicon layer; The doped polysilicon layer plated on the backlight surface and the second doped polysilicon layer located in the second area are removed by using a texturing alkali solution, and a textured structure is formed in the second area.

11. The method for preparing a solar cell according to claim 9, characterized in that: The width of the first slot is 1 / 4 to 1 / 15 of the width of the first zone; or, The width of the first region is 50 μm to 150 μm, and / or the width of the first groove is 10 μm to 15 μm.

12. The method for preparing a solar cell according to claim 9, characterized in that: "Electroplating and / or chemical plating" includes: Electroplating or chemical plating forms a metal transition layer, wherein the metal transition layer is at least one of a Ni layer, a Ti layer, and a Co layer; Annealing to form an alloy between the metal transition layer and silicon; The metal bulk layer is formed by electroplating or chemical plating.

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