Back contact battery and photovoltaic module

Abstract

The invention discloses a back contact battery and a photovoltaic module, and relates to the field of photovoltaic technology. The back contact cell includes: a semiconductor substrate; a first current collection layer and a second current collection layer; the multiple columns of bonding pads are distributed on the first surface at intervals in the first direction, and each column of bonding pads comprises a plurality of bonding pads arranged in the second direction; the first column of bonding pads comprises a first bonding pad, and a second bonding pad which is adjacent to the first bonding pad along the second direction and is farther away from the edge of the semiconductor substrate than the first bonding pad; the orthographic projection of the gap between the first bonding pad and the second bonding pad on the first surface is not overlapped with the orthographic projection of the isolation region on the first surface, and the orthographic projection of the first bonding pad and the orthographic projection of the second bonding pad on the first surface are located in the orthographic projection of the same first current collection layer on the first surface. The first bonding pad and the second bonding pad can timely export the current collected by the same first current collection layer at the same time, so that the current is prevented from being excessively concentrated, and the current transmission efficiency and the photoelectric conversion efficiency of the back contact battery are improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a back contact cell and a photovoltaic module. Background Art

[0002] A back-contact cell refers to a solar cell in which the light-facing side of the cell has no electrode, and the positive and negative electrodes are arranged on the backlight side of the cell. This can reduce the shading of the electrode to the cell, increase the short-circuit current of the cell, and improve the energy conversion efficiency of the cell.

[0003] However, the back contact battery with main grid has more light shielding, consumes more grid line materials, and has a smaller effective current collection area on the back, which is not conducive to improving battery efficiency. The current transmission efficiency around the large pad of the back contact battery without main grid is low, which affects the photoelectric conversion efficiency of the back contact battery. Summary of the invention

[0004] The purpose of the present application is to provide a back-contact cell and a photovoltaic module to improve the current transmission efficiency around a larger pad and the photoelectric conversion efficiency of the back-contact cell.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A back contact battery, comprising:

[0007] The semiconductor substrate comprises a first surface and a second surface arranged opposite to each other, wherein the first surface has a first side and a second side opposite to each other along a first direction;

[0008] A first current collection layer and a second current collection layer are arranged on the first surface; the first current collection layer and the second current collection layer are alternately spaced and distributed along the second direction, an isolation region is provided between the first current collection layer and the second current collection layer and the conductivity types are opposite; the first direction intersects with the second direction;

[0009] A plurality of rows of pads are spaced apart on the first surface along a first direction, and each row of pads includes a plurality of pads arranged along a second direction; the row of pads closest to the first edge is a first row of pads, the first row of pads includes a first pad, and the second pad is adjacent to the first pad along the second direction and further away from the edge of the semiconductor substrate than the first pad;

[0010] The orthographic projection of the gap between the first pad and the second pad on the first surface does not overlap with the orthographic projection of the isolation region on the first surface, and the orthographic projections of the first pad and the second pad on the first surface are located inside the orthographic projection of the same first current collection layer on the first surface.

[0011] By adopting the above technical solution, for a back-contact battery without a main grid, the surrounding areas of the first pad and the second pad are the same first current collection layer, and the first pad and the second pad are arranged on the first current collection layer with a larger area, so that the first pad and the second pad can simultaneously and timely guide the current collected by the same first current collection layer, thereby preventing excessive concentration of current and improving the current transmission efficiency and the photoelectric conversion efficiency of the back-contact battery. In addition, when one of the first pad and the second pad has poor contact, the other pad can still collect current normally, ensuring that when one of the pads fails, the current on the first current collection layer with a larger area is normally collected, thereby improving the performance stability of the back-contact battery.

[0012] In some implementations, the area of ​​the first pad is larger than the area of ​​the second pad; thus, the first pad can be conductively connected to the plurality of first fine grids, thereby utilizing the first pad with a larger area to timely guide the current collected by the plurality of first fine grids, thereby further improving the current transmission efficiency. And / or,

[0013] Except for the gap between the first pad and the second pad in the first row of pads, the orthographic projections of the gaps between any two adjacent pads on the first surface overlap with the orthographic projections of the isolation area on the first surface. This arrangement ensures that the first current collection layer and the second current collection layer can be alternately distributed, which is conducive to reducing the area difference between the first current collection layer and the second current collection layer, and further helps to reduce the current difference between the first current collection layer and the second current collection layer.

[0014] In some implementations, the back contact cell further includes a plurality of first fine grids and a plurality of second fine grids extending along the first direction and alternately distributed along the second direction; the plurality of first fine grids are respectively disposed on the plurality of first current collection layers, and the plurality of second fine grids are respectively disposed on the plurality of second current collection layers, so that the current collected by the first current collection layer is promptly derived by using the first fine grids; and the current collected by the second current collection layer is promptly derived by using the second fine grids.

[0015] In some implementations, at least one second fine grid forms a bent section at an end portion close to the first edge, and the bent section is at least partially located between the first pad and the first edge and does not contact the first pad.

[0016] In some implementations, along the second direction, a plurality of first fine grids between the first pad and the edge of the semiconductor substrate are electrically connected to the first pad via an edge busbar. In this arrangement, the current in the area between the first edge and the first pad is derived by using the bent section of the second fine grid and the first pad at the same time, which can not only alleviate the problem of excessive concentration of current collection, but also help to reduce the current difference between the first current collection layer and the second current collection layer.

[0017] In some implementations, an edge busbar extending along the second direction between the first pad and the edge of the semiconductor substrate is further included, and the edge busbar is connected to the first pad and the second pad via a connecting strip and / or a first fine grid extending along the first direction. This ensures the uniformity of current transmission and improves the stability of the back contact battery.

[0018] In some implementations, the pads in a row closest to the second side are the pads in the last row, the pads in the last row closest to the edge of the semiconductor substrate along the second direction are the third pads, and the pads next to the third pads along the second direction are the fourth pads;

[0019] The orthographic projection of the gap between the third pad and the fourth pad on the first surface overlaps with the orthographic projection of the isolation region on the first surface. In this way, near the second side of the semiconductor substrate, the first current collection layer and the second current collection layer are alternately distributed, which is conducive to reducing the area difference between the first current collection layer and the second current collection layer, and further helps to reduce the current difference between the first current collection layer and the second current collection layer.

[0020] In some implementations, the third pad has a laminated structure on a side facing away from the fourth pad, and the laminated structure includes a first doped semiconductor layer and a second doped semiconductor layer stacked. The laminated structure is not connected to the second fine grid, thereby preventing the second fine grid from extending to the vicinity of the first pad. During the printing of the second fine grid, the slurry may extend to contact the first pad, resulting in leakage.

[0021] In some implementations, the row of pads closest to the second side is the last row of pads, along the direction from the first row of pads to the last row of pads;

[0022] In the even-numbered columns of pads, the orthographic projection of the gap between any two adjacent pads along the second direction on the first surface overlaps with the orthographic projection of the isolation area on the first surface; such an arrangement ensures that the second current collection layer can be evenly distributed in the middle area of ​​the first surface, thereby improving the uniformity of current collection by the second current collection layer.

[0023] And / or, the odd-numbered columns of pads include at least two adjacent pads along the second direction, and the orthographic projection of the gap between the two pads on the first surface does not overlap with the orthographic projection of the isolation region on the first surface. This arrangement is conducive to the alignment of the first fine grid along the first direction, and further facilitates the processing and manufacturing of the first fine grid.

[0024] In some implementations, the first current collection layer and the second current collection layer are both doped semiconductor layers, and the back contact battery further includes a passivation layer, which is located on a side of the first current collection layer and the second current collection layer away from the semiconductor substrate;

[0025] The first fine grid passes through the passivation layer and is electrically connected to the first current collection layer, and the second fine grid passes through the passivation layer and is electrically connected to the second current collection layer. The passivation layer can passivate the surface of the doped semiconductor layer, reduce its carrier recombination rate, and further improve the photoelectric conversion efficiency of the back contact battery.

[0026] In some implementations, the first current collection layer and the second current collection layer are both doped semiconductor layers, and the first current collection layer and the semiconductor substrate have the same doping type. With the above technical solution, the first doped semiconductor layer and the first side of the semiconductor substrate will not recombine, so in the process of depositing the first doped semiconductor layer, the distance between the two side edges of the first doped semiconductor layer opposite to each other along the first direction and the edge of the semiconductor substrate can be made smaller or overlapped, such as the edge of the first doped semiconductor layer overlaps or is closer to the first side of the semiconductor substrate, so that the area of ​​the first doped semiconductor layer can be made larger, and the carrier collection efficiency of the first doped semiconductor layer can be improved.

[0027] In some implementations, the first current collection layer and the second current collection layer are both transparent conductive layers. The transparent conductive layer has a high electrical conductivity and can timely conduct the collected carriers to reduce the carrier recombination rate.

[0028] In some implementations, the device further includes a first doped semiconductor layer disposed between the first surface and the first current collection layer and a second doped semiconductor layer disposed between the first surface and the second current collection layer, wherein an overlapping portion is provided between the first doped semiconductor layer and the second doped semiconductor layer, and a projection of the overlapping portion on the first surface at least partially overlaps with a projection of the isolation region on the first surface. Specifically, along the width direction of the opening, the orthographic projection of the opening on the first surface at least partially overlaps with a projection of the isolation region on the first surface, thereby reducing the risk of leakage.

[0029] A photovoltaic module comprises an electrical connector and a back contact cell as described above, wherein the electrical connector is conductively connected to the pad. Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as those of the back contact cell, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0031] Figure 1 A top view of a back contact battery provided in an embodiment of the present application;

[0032] Figure 2 A partial cross-sectional view of a back-contact battery provided by an embodiment of the present application along a direction parallel to the first surface;

[0033] Figure 3 In one embodiment Figure 2 Partial cross-sectional view along AA;

[0034] Figure 4 In one embodiment Figure 2 A partial cross-sectional view along the middle line BB;

[0035] Figure 5 In another embodiment Figure 2 Partial cross-sectional view along AA;

[0036] Figure 6 In another embodiment Figure 2 A partial cross-sectional view along the middle line BB;

[0037] Figure 7 A partial cross-sectional view of a back-contact battery provided in another embodiment of the present application along a direction parallel to the first surface;

[0038] Figure 8 Another partial cross-sectional view of a back-contact battery provided by an embodiment of the present application along a direction parallel to the first surface;

[0039] Fig. 9 A cross-sectional view of the stacked structure provided in an embodiment of the present application.

[0040] Reference numerals:

[0041] 1-first solder pad, 2-edge bus grid, 3-second solder pad, 4-first fine grid, 5-second fine grid, 6-third solder pad, 7-fourth solder pad, 8-first doped semiconductor layer, 9-second doped semiconductor layer, 10-isolation region, 11-bending section, 12-semiconductor substrate, 121-first edge, 122-second edge, 13-passivation layer, 14-transparent conductive layer, 15-first interface layer, 16-second interface layer, 17-laminated structure. DETAILED DESCRIPTION

[0042] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0044] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0045] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0046] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0047] In a back contact cell structure without a main grid, generally multiple fine grids are electrically connected to the busbar through a larger pad to conduct current. In this way, the area of ​​the doped semiconductor layer with the same polarity as the pad around the larger pad is also larger, which can easily lead to a lower current transmission efficiency of the doped semiconductor layer around the larger pad.

[0048] In order to improve the current transmission efficiency around the pad with a larger area, the present application provides a back contact battery without a main grid, see Figure 1 The back contact cell includes a semiconductor substrate 12, a first current collecting layer, a second current collecting layer and a plurality of columns of pads.

[0049] The semiconductor substrate 12 includes a first surface and a second surface that are arranged opposite to each other, that is, the two surfaces that are opposite to each other along the thickness direction of the semiconductor substrate 12 are the first surface and the second surface respectively. The first surface has a first edge 121 and a second edge 122 that are opposite to each other along a first direction, that is, the first edge 121 and the second edge 122 are arranged along the first direction, and the first edge 121 and the second edge 122 both intersect with the first direction. For example, Figure 1The left side is the first side 121, and the right side is the second side 122. In addition, the first surface may correspond to the backlight side of the back contact battery, and the second surface may correspond to the light-facing side of the back contact battery; or the first surface may correspond to the light-facing side of the back contact battery, and the second surface may correspond to the backlight side of the back contact battery. In this application, the first surface corresponds to the backlight side of the back contact battery as an example for explanation.

[0050] The first current collection layer and the second current collection layer are both arranged on the first surface, and the first current collection layer and the second current collection layer are alternately spaced and distributed along the second direction. Specifically, the first current collection layer and the second current collection layer can be alternately spaced and distributed in strips, or can be alternately spaced and distributed in interdigitated shapes. An isolation region 10 is provided between the first current collection layer and the second current collection layer to reduce the carrier recombination rate at the lateral junction of the first current collection layer and the second current collection layer, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery. In addition, the first current collection layer and the second current collection layer have opposite conductivity types, so as to collect and export electrons and holes respectively, which is beneficial to form photocurrent.

[0051] The second direction intersects with the first direction, that is, the first direction is different from the second direction, and the angle between the first direction and the second direction may be an acute angle or a right angle. When the first direction is the length direction of the semiconductor substrate 12, the second direction is the width direction of the semiconductor substrate 12; when the first direction is the width direction of the semiconductor substrate 12, the second direction is the length direction of the semiconductor substrate 12.

[0052] In a back contact battery structure without a main grid, multiple columns of pads are spaced apart on a first surface along a first direction. Specifically, along the first direction, multiple columns of pads are arranged sequentially on the first surface, and there is a preset spacing between two adjacent columns of pads. Each column of pads includes multiple pads arranged along a second direction. The polarities of the multiple pads in the same column are the same; the polarities of the pads in two adjacent columns are opposite, for example Figure 1 The polarities of the first column of pads and the second column of pads from left to right are opposite, and the polarities of the multiple pads in the first column are the same, and the polarities of the multiple pads in the second column are the same. Among them, the column of pads closest to the first edge 121 is the first column of pads, for example Figure 1 The leftmost row of pads is the first row of pads. The first row of pads includes the first pad, for example, the pad closest to the edge of the semiconductor substrate 12 along the second direction in the first row of pads is the first pad 1, that is, Figure 1The top and bottom pads in the first row of pads are first pads 1; of course, the rest of the pads in the first row can also be first pads 1, for example, the second, third, second to last or third to last pad in the first row from top to bottom is first pad 1, but first pad 1 is located at a corner near first edge 121. In some embodiments, first pad 1 is the outermost welding position along the second direction, that is, the outermost pad that actually performs the welding function. Therefore, generally speaking, the area of ​​first pad 1 is greater than or equal to that of pads at other positions. Second pad 3 is adjacent to first pad 1 along the second direction, and second pad 3 is farther away from the edge of semiconductor substrate 12 than first pad 1. That is Figure 1 In the first column of pads, the second pad and the second to last pad from top to bottom is the second pad 3 .

[0053] like Figure 2 and Figure 3 As shown, the orthographic projection of the gap between the first pad 1 and the second pad 3 on the first surface does not overlap with the orthographic projection of the isolation region 10 on the first surface, and the orthographic projections of the first pad 1 and the second pad 3 on the first surface are located inside the orthographic projection of the same first current collection layer on the first surface. Specifically, there is no isolation region 10 passing between the first pad 1 and the second pad 3, and along the second direction, the first current collection layer continuously extends from the position of the first pad 1 to the position of the second pad 3. In other words, the surrounding areas of the first pad 1 and the second pad 3 are all the same first current collection layer.

[0054] By adopting the above technical solution, the surrounding areas of the first pad 1 and the second pad 3 are the same first current collection layer. The first pad 1 and the second pad 3 are arranged on the first current collection layer with a larger area, so that the first pad 1 and the second pad 3 can simultaneously and timely extract the current collected by the same first current collection layer, thereby preventing excessive concentration of current and improving the current transmission efficiency and the photoelectric conversion efficiency of the back contact battery. In addition, when one of the first pad 1 and the second pad 3 has poor contact, the other pad can still collect current normally, ensuring that when one of the pads fails, the current on the first current collection layer with a larger area is normally collected, thereby improving the performance stability of the back contact battery. It should be known that for a back contact battery with a main grid, the main grid can serve the purpose of collecting fine grid current, which can effectively disperse the current, while for a back contact battery without a main grid, the current collection of the large area of ​​the first current collection layer at the same position at the end is uneven, so it is necessary to design two pads to disperse the current and ensure the welding force at the end.

[0055] In some embodiments, Figure 2As shown, the area of ​​the first pad 1 is greater than the area of ​​the second pad 3, that is, the orthographic projection area of ​​the first pad 1 on the first surface is greater than the orthographic projection area of ​​the second pad 3 on the first surface. Specifically, along the second direction, the length of the first pad 1 is greater than the length of the second pad 3; and / or, along the first direction, the width of the first pad 1 is equal to the width of the second pad 3, and the first pad 1 and the second pad 3 are aligned along the second direction. With this technical solution, the first pad 1 can be conductively connected to the multiple first fine grids 4, so that the current collected by the multiple first fine grids 4 can be promptly derived by using the first pad 1 with a larger area, thereby further improving the current transmission efficiency.

[0056] In some embodiments, Figure 2 As shown, a first isolation region is provided on the side of the first pad 1 and the second pad 3 away from the first edge, the first isolation region extends along the first direction, the first isolation region extends close to the first pad 1 and the second pad 3, and the extension line of the first isolation region passes through the gap between the first pad 1 and the second pad 3.

[0057] In some embodiments, except for the gap between the first pad 1 and the second pad 3 in the first row of pads, the orthographic projections of the gaps between any two adjacent pads on the first surface overlap with the orthographic projections of the isolation region 10 on the first surface. Figure 1 In the first column of pads, the gap between any two pads located between the second pad and the second to last pad from top to bottom has the isolation region 10 passing through it, such as Figure 4 As shown, the isolation area 10 passing through the two pads means that there is a second current collection layer between the two pads. This arrangement ensures that the first current collection layer and the second current collection layer can be alternately distributed, which is conducive to reducing the area difference between the first current collection layer and the second current collection layer, and further helps to reduce the current difference between the first current collection layer and the second current collection layer.

[0058] like Figure 1 As shown, the back contact cell includes a plurality of first fine grids 4 and a plurality of second fine grids 5, and the first fine grids 4 and the second fine grids 5 both extend along the first direction, that is, the lengths of the first fine grids 4 and the second fine grids 5 are arranged along the first direction. In addition, the plurality of first fine grids 4 and the plurality of second fine grids 5 are alternately distributed along the second direction, and the plurality of first fine grids 4 are respectively arranged on the plurality of first current collection layers, so that the current collected by the first current collection layers can be promptly derived by using the first fine grids 4; and the plurality of second fine grids 5 are respectively arranged on the plurality of second current collection layers, so that the current collected by the second current collection layers can be promptly derived by using the second fine grids 5.

[0059] The pad is electrically connected to the first fine grid 4 or the second fine grid 5, for example Figure 1In the embodiment, the plurality of pads included in the first column of pads are respectively conductively connected to the plurality of first fine grids 4; the plurality of pads included in the second column of pads are respectively conductively connected to the plurality of second fine grids 5.

[0060] The first fine grid 4 and the second fine grid 5 can be formed by screen printing, electroplating, sputtering or evaporation, etc. In addition, the first fine grid 4 and the second fine grid 5 can be made of silver, copper, aluminum and alloys thereof.

[0061] If the first current collection layer is set entirely between the first pad 1 and the first edge 121 of the semiconductor substrate 12, it will cause excessive concentration of current collection in this area. In order to further alleviate the problem of excessive concentration of current collection, in this embodiment, at least one second fine grid 5 forms a bending section 11 at the end close to the first edge 121, and the bending section 11 is at least partially located between the first pad 1 and the first edge 121 and does not contact the first pad 1. Specifically, the second current collection layer extends between the first pad 1 and the first edge 121, and the bending section 11 of the second fine grid 5 is used to collect the current of the second current collection layer between the first pad 1 and the first edge 121. With such a configuration, the current in the area between the first edge 121 and the first pad 1 is derived by using the bending section 11 of the second fine grid 5 and the first pad 1 at the same time, which can not only alleviate the problem of excessive concentration of current collection, but also help to reduce the current difference between the first current collection layer and the second current collection layer.

[0062] In some embodiments, the bending segment 11 includes a main bending segment extending along the second direction and at least one sub-bending segment extending along the first direction, one end of the sub-bending segment is electrically connected to the main bending segment, and one end of the main bending segment is electrically connected to the main body of the second fine grid 5 extending along the first direction. Figure 2 As shown, the number of sub-bend segments can be two; or, the number of sub-bend segments can be one, three or more. The second fine grid 5 and its bending segment 11 can be integrally formed to facilitate manufacturing and processing, while preventing electrical connection failure of the bending segment 11.

[0063] In some embodiments, Figure 2 and Figure 7 As shown, the back contact cell further includes an edge busbar 2, and along the second direction, a plurality of first fine grids 4 between the first pad 1 and the edge of the semiconductor substrate 12 are electrically connected to the first pad 1 through the edge busbar 2. Specifically, the edge busbar 2 extends along the second direction, and the ends of the plurality of first fine grids 4 between the first pad 1 and the edge of the semiconductor substrate 12 are conductively connected to the edge busbar 2, so that the edge busbar 2 is used to transmit the current collected by the plurality of first fine grids 4 to the first pad 1. In view of the fact that the edge busbar 2 needs to collect the current of the plurality of first fine grids 4, the width of the edge busbar 2 can be set wider to improve the current transmission efficiency.

[0064] In some embodiments, the edge bus grid 2 can be connected to the first pad 1 and the second pad 3 through a connecting strip and / or a first fine grid 4 extending along the first direction. That is, the edge bus grid 2 can be conductively connected to both the first pad 1 and the second pad 3 to ensure the uniformity of current transmission and improve the stability of the back contact battery. Specifically, the edge bus grid 2 and the first pad 1 can be conductively connected through a connecting strip, and the width of the connecting strip can be set wider to ensure normal current transmission. The edge bus grid 2 and the second pad 3 can be conductively connected through a first fine grid 4 to divert part of the current of the edge bus grid 2 to the second pad 3, improve the uniformity of current distribution, and further prevent excessive concentration of current on the first pad 1.

[0065] In some embodiments, Figure 1 As shown, the row of pads closest to the second side 122 is the last row of pads, for example Figure 1 The pad on the rightmost row is the pad in the last row; the pad in the last row that is closest to the edge of the semiconductor substrate 12 along the second direction is the third pad 6, that is, Figure 1 The uppermost and lowermost pads in the middle and last row of pads are the third pads 6. The fourth pad 7 is adjacent to the third pad 6 along the second direction. Figure 1 In the last row of pads, the second pad and the second to last pad from top to bottom are the fourth pad 7 .

[0066] like Figure 8 As shown, the orthographic projection of the gap between the third pad 6 and the fourth pad 7 on the first surface overlaps with the orthographic projection of the isolation region 10 on the first surface. That is, the isolation region 10 passes between the third pad 6 and the fourth pad 7, or in other words, there is a first current collection layer between the third pad 6 and the fourth pad 7. With such an arrangement, near the second edge 122 of the semiconductor substrate 12, it is ensured that the first current collection layer and the second current collection layer can be alternately distributed, which is conducive to reducing the area difference between the first current collection layer and the second current collection layer, and further conducive to reducing the current difference between the first current collection layer and the second current collection layer.

[0067] Specifically, in the last row of pads, the orthographic projection of the gap between any two adjacent pads on the first surface overlaps with the orthographic projection of the isolation region 10 on the first surface. That is, in the last row of pads, the isolation region 10 passes between any two adjacent pads, thereby avoiding the situation where the current collection layer around the third pad 6 is too large, thereby avoiding the situation where the current of the third pad 6 is excessively concentrated.

[0068] In some embodiments, Figure 8As shown, the side of the third pad 6 facing away from the fourth pad 7 has a laminated structure 17, and the laminated structure 17 includes a first doped semiconductor layer 8 and a second doped semiconductor layer 9 stacked. That is, the laminated structure 17 is arranged close to the second edge 122 and on the side of the third pad 6 facing away from the fourth pad 7. Fig. 9 As shown, the second doped semiconductor layer 9 is located on the side of the first doped semiconductor layer 8 close to the semiconductor substrate 12, that is, the second doped semiconductor layer 9 is located between the first doped semiconductor layer 8 and the semiconductor substrate 12. The stacked structure 17 is not connected to the first fine grid 4 and the second fine grid 5, so the arrangement of the stacked structure 17 does not cause leakage; in addition, the stacked structure 17 is not connected to the second fine grid 5, which prevents the second fine grid 5 from extending to the vicinity of the first pad 1. During the printing process of the second fine grid 5, the paste may extend to contact the first pad 1, resulting in leakage.

[0069] In some embodiments, the row of pads closest to the second side 122 is the last row of pads. Along the direction from the first row of pads to the last row of pads, for example Figure 1 In the direction from left to right in the figure, in the even-numbered columns of pads (such as the second column of pads and the fourth column of pads), the orthographic projection of the gap between any two adjacent pads along the second direction on the first surface overlaps with the orthographic projection of the isolation region 10 on the first surface. The pads in the even-numbered columns are all conductively connected to the second fine grid 5. This arrangement ensures that the second current collection layer can be evenly distributed in the middle area of ​​the first surface, thereby improving the uniformity of the current collected by the second current collection layer.

[0070] In other embodiments, the pads in the odd-numbered columns (such as the pads in the first column and the pads in the third column) include at least two adjacent pads along the second direction, and the orthographic projection of the gap between the two pads on the first surface does not overlap with the orthographic projection of the isolation region 10 on the first surface. The pads in the odd-numbered columns are all conductively connected to the first fine grid 4. From top to bottom, the gap between the first and second pads and / or the gap between the first to last and the second to last pads in the odd-numbered columns may not have the isolation region 10 passing through, and the isolation region 10 may pass between any other two adjacent pads. Such a configuration is conducive to the alignment of the first fine grid 4 along the first direction, and further facilitates the processing and manufacturing of the first fine grid 4.

[0071] The orthographic projection of the gap between two adjacent pads along the second direction on the first surface overlaps with the orthographic projection of the isolation region 10 on the first surface. Figure 1 In the two middle columns of pads, the gaps between any two adjacent pads in the same column are all passed through by the isolation region 10. This arrangement ensures that the first current collection layer and the second current collection layer can be alternately distributed in the middle region of the first surface, thereby facilitating the reduction of the current difference between the first current collection layer and the second current collection layer.

[0072] In some embodiments, Figure 3 and Figure 4 As shown, the first current collection layer and the second current collection layer are both doped semiconductor layers; that is, the first current collection layer is the first doped semiconductor layer 8, and the second current collection layer is the second doped semiconductor layer 9; the isolation region 10 is located between the first doped semiconductor layer 8 and the second doped semiconductor layer 9, for example, the gap between the first doped semiconductor layer 8 and the second doped semiconductor layer 9 forms the isolation region 10. The back contact battery also includes a passivation layer 13, which is located on the side of the first current collection layer and the second current collection layer away from the semiconductor substrate 12, that is, the first doped semiconductor layer 8 and the second doped semiconductor layer 9 away from the semiconductor substrate 12, and the passivation layer 13 covers the isolation region 10. The passivation layer 13 can passivate the surface of the doped semiconductor layer, reduce its carrier recombination rate, and further improve the photoelectric conversion efficiency of the back contact battery. The material of the passivation layer 13 may include one or more of silicon nitride, silicon oxynitride, and silicon oxide. In addition, the passivation layer 13 may be a single-layer structure or a multi-layer structure. As for the thickness of the passivation layer 13, it only needs to meet the passivation effect and ensure the contact performance of the fine gate and the doped semiconductor layer.

[0073] The first fine gate 4 and the second fine gate 5 are formed on the side of the passivation layer 13 away from the semiconductor substrate 12. Specifically, the first fine gate 4 passes through the passivation layer 13 to be electrically connected to the first doped semiconductor layer 8, and the second fine gate 5 passes through the passivation layer 13 to be electrically connected to the second doped semiconductor layer 9. The passivation layer 13 may be provided with a first opening corresponding to the first doped semiconductor layer 8 and a second opening corresponding to the second doped semiconductor layer 9. The first fine gate 4 passes through the first opening to be electrically connected to the first doped semiconductor layer 8, and the second fine gate 5 passes through the second opening to be electrically connected to the second doped semiconductor layer 9. Alternatively, the first fine gate 4 passes through the passivation layer 13 to be electrically connected to the first doped semiconductor layer 8 by burning through, and the second fine gate 5 passes through the passivation layer 13 to be electrically connected to the second doped semiconductor layer 9 by burning through.

[0074] In the case where the back contact cell further includes a passivation layer 13, the first doped semiconductor layer 8 may include doped polysilicon; a first interface layer 15 may be provided between the first doped semiconductor layer 8 and the first surface, and the first interface layer 15 is a tunneling oxide layer. The second doped semiconductor layer 9 may also include doped polysilicon; a second interface layer 16 may be provided between the second doped semiconductor layer 9 and the first surface, and the second interface layer 16 is a tunneling oxide layer.

[0075] In other embodiments, Figure 5 and Figure 6As shown, the first current collection layer and the second current collection layer are both transparent conductive layers 14, and the transparent conductive layer 14 includes a transparent conductive oxide layer. For example, the material of the transparent conductive layer 14 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, indium hydroxide, cadmium oxide, cuprous oxide, and fluorine-doped zinc oxide. The transparent conductive layer 14 can be a single-layer film or a laminated film. Specifically, the transparent conductive layer 14 is provided with an opening that runs through its thickness. In this technical solution, the opening of the transparent conductive layer 14 forms an isolation region 10, and the opening separates the two parts of the transparent conductive layer 14 with opposite polarities to prevent leakage. The transparent conductive layers 14 on both sides of the opening are the first current collection layer and the second current collection layer, respectively. The transparent conductive layer 14 has a high electrical conductivity, and can timely guide the collected carriers to reduce the carrier recombination rate.

[0076] In some embodiments, the back contact cell further includes a first doped semiconductor layer 8 and a second doped semiconductor layer 9, wherein the first doped semiconductor layer 8 is located between the first surface and the first current collection layer, that is, the first doped semiconductor layer 8 is located on the side of the first current collection layer close to the first surface. The second doped semiconductor layer 9 is located between the first surface and the second current collection layer, that is, the second doped semiconductor layer 9 is located on the side of the second current collection layer close to the first surface. The edge of the first doped semiconductor layer 8 overlaps with the edge of the second doped semiconductor layer 9 to form an overlapping portion. Specifically, the overlapping portion includes the first doped semiconductor layer 8 and the second doped semiconductor layer 9 stacked on the first surface, and the second doped semiconductor layer 9 is located on the side of the first doped semiconductor layer 8 close to the semiconductor substrate. The projection of the overlapping portion on the first surface at least partially overlaps with the projection of the isolation region 10 on the first surface. Specifically, along the width direction of the opening, the orthographic projection of the opening on the first surface at least partially overlaps with the projection of the isolation region 10 on the first surface, thereby reducing the risk of leakage.

[0077] In the above technical solution, the first fine gate 4 and the second fine gate 5 are formed on the side of the transparent conductive layer 14 away from the semiconductor substrate 12 , and the pad is conductively connected to the first fine gate 4 or the second fine gate 5 .

[0078] When both the first current collection layer and the second current collection layer are transparent conductive layers 14, the first doped semiconductor layer 8 includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon. The second doped semiconductor layer 9 includes one or more of amorphous silicon, nanocrystalline silicon and microcrystalline silicon.

[0079] In actual application, the first doped semiconductor layer 8 includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon. In this case, the doped polycrystalline silicon layer has higher carrier transport characteristics. Therefore, when the first doped semiconductor layer 8 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which is conducive to improving the photoelectric conversion efficiency of the back contact battery. The second doped semiconductor layer 9 may also include one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon.

[0080] In some embodiments, a first interface layer 15 is provided between the first doped semiconductor layer 8 and the semiconductor substrate 12; and / or a second interface layer 16 is provided between the second doped semiconductor layer 9 and the semiconductor substrate 12. The passivation contact structure composed of the interface layer and the semiconductor layer has an excellent interface passivation effect, and can realize the selective collection of carriers, reduce the carrier recombination rate in the area where the semiconductor layer is formed on the surface of the semiconductor substrate 12, and further improve the photoelectric conversion efficiency of the back contact battery. The material and thickness of the first interface layer 15 can be set according to the material of the first doped semiconductor layer 8 and actual needs, and the material and thickness of the second interface layer 16 can be set according to the material of the second doped semiconductor layer 9 and actual needs, and are not specifically limited here.

[0081] Exemplarily, when the first doped semiconductor layer 8 includes a doped polysilicon layer, the first interface layer 15 may be a tunneling oxide layer. The second doped semiconductor layer 9 includes a doped polysilicon layer, and the second interface layer 16 is a tunneling oxide layer.

[0082] Of course, when the first doped semiconductor layer 8 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface layer 15 includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon. When the second doped semiconductor layer 9 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface layer 16 includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon.

[0083] In some embodiments, the first current collection layer and the second current collection layer are both doped semiconductor layers, that is, the first current collection layer is the first doped semiconductor layer 8, and the second current collection layer is the second doped semiconductor layer 9. In terms of conductivity type, the first doped semiconductor layer 8 has the same doping type as the semiconductor substrate 12, that is, the semiconductor substrate 12 and the first doped semiconductor layer 8 are opposite to the doping type of the second doped semiconductor layer 9. Specifically, the semiconductor substrate 12 can be an n-type conductive substrate or a p-type conductive substrate. In the case where the semiconductor substrate 12 is an n-type conductive substrate, the first doped semiconductor layer 8 is also n-type doped, and the semiconductor substrate 12 and the first doped semiconductor layer 8 are doped with group V elements or group VI elements, such as phosphorus, arsenic or antimony; the second doped semiconductor layer 9 is p-type doped, and the second doped semiconductor layer 9 is doped with group III elements, such as boron, gallium, etc.

[0084] When the semiconductor substrate 12 is a p-type conductive substrate, the first doped semiconductor layer 8 is also p-type doped, and the semiconductor substrate 12 and the first doped semiconductor layer 8 are doped with group III elements, such as boron, gallium, etc. The second doped semiconductor layer 9 is n-type doped, and the second doped semiconductor layer 9 is doped with group V elements or group VI elements, such as phosphorus, arsenic, or antimony.

[0085] By adopting the above technical solution, the first doped semiconductor layer 8 and the first edge 121 of the semiconductor substrate 12 will not recombine. Therefore, in the process of depositing the first doped semiconductor layer 8, the distance between the two side edges of the first doped semiconductor layer 8 opposite to each other along the first direction and the edge of the semiconductor substrate 12 can be made smaller or overlapped, such as the edge of the first doped semiconductor layer 8 overlaps with or is closer to the first edge 121 of the semiconductor substrate 12. In this way, the area of ​​the first doped semiconductor layer 8 can be made larger, thereby improving the carrier collection efficiency of the first doped semiconductor layer 8.

[0086] In terms of materials, the materials of the first doped semiconductor layer 8 and the second doped semiconductor layer 9 can be silicon (Si), germanium (Ge), silicon carbide (SiCx) or gallium arsenide (GaAs), etc. The material of the semiconductor substrate 12 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs).

[0087] The embodiment of the present application also provides a photovoltaic module, which includes an electrical connector and a back contact cell provided by any of the above embodiments. The electrical connector can be conductively connected to the pad. Specifically, the electrical connector can extend along the second direction, and each electrical connector is conductively connected to multiple pads in the same column of pads, so as to use the electrical connector to conduct current to the outside of the back contact cell. The electrical connector can be specifically a busbar or a welding strip.

[0088] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned back-contact battery, which will not be elaborated here.

[0089] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0090] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A back contact battery, characterized in that: include: The semiconductor substrate comprises a first surface and a second surface arranged opposite to each other, wherein the first surface has a first side and a second side opposite to each other along a first direction; A first current collection layer and a second current collection layer are disposed on the first surface; The first current collection layer and the second current collection layer are alternately spaced and distributed along a second direction, an isolation region is provided between the first current collection layer and the second current collection layer and the conductivity types are opposite; the first direction and the second direction intersect; A plurality of rows of pads are spaced apart on the first surface along a first direction, and each row of pads includes a plurality of pads arranged along a second direction; a row of pads closest to the first edge is a first row of pads, the first row of pads includes a first pad, and a second pad is adjacent to the first pad along the second direction and further away from the edge of the semiconductor substrate than the first pad; The orthographic projection of the gap between the first pad and the second pad on the first surface does not overlap with the orthographic projection of the isolation region on the first surface, and the orthographic projections of the first pad and the second pad on the first surface are located inside the same orthographic projection of the first current collection layer on the first surface.

2. The back contact cell according to claim 1, characterized in that: The area of ​​the first pad is greater than the area of ​​the second pad; and / or, Except for the gap between the first pad and the second pad in the first row of pads, the orthographic projection of the gap between any two adjacent pads in the first row overlaps with the orthographic projection of the isolation region on the first surface.

3. The back contact cell according to claim 1, characterized in that: The back contact battery also includes a plurality of first fine grids and a plurality of second fine grids extending along the first direction and alternately distributed along the second direction; the plurality of first fine grids are respectively arranged on the plurality of first current collection layers, and the plurality of second fine grids are respectively arranged on the plurality of second current collection layers.

4. The back contact cell according to claim 3, characterized in that: At least one of the second fine grids forms a bending section at an end portion close to the first edge, and the bending section is at least partially located between the first pad and the first edge and does not contact the first pad.

5. The back contact battery according to claim 3, characterized in that: Along the second direction, a plurality of first fine grids between the first pad and the edge of the semiconductor substrate are electrically connected to the first pad through edge bus bars.

6. The back contact cell according to claim 3, characterized in that: It also includes an edge busbar extending between the first pad and the edge of the semiconductor substrate and along the second direction, wherein the edge busbar is connected to the first pad and the second pad via a connection strip extending along the first direction and / or the first fine grid.

7. The back contact cell according to claim 3, characterized in that: The first current collection layer and the second current collection layer are both doped semiconductor layers, and the back contact battery further comprises a passivation layer, wherein the passivation layer is located on a side of the first current collection layer and the second current collection layer away from the semiconductor substrate; The first fine gate passes through the passivation layer and is electrically connected to the first current collection layer, and the second fine gate passes through the passivation layer and is electrically connected to the second current collection layer.

8. The back contact cell according to claim 1, characterized in that The pads in a row closest to the second side are the pads in the last row, the pads in the last row closest to the edge of the semiconductor substrate along the second direction are the third pads, and the pads next to the third pads along the second direction are the fourth pads; An orthographic projection of a gap between the third pad and the fourth pad on the first surface overlaps with an orthographic projection of the isolation region on the first surface.

9. The back contact cell according to claim 8, characterized in that: The side of the third pad facing away from the fourth pad has a stacked structure, the stacked structure includes a first doped semiconductor layer and a second doped semiconductor layer stacked on the first surface, and the second doped semiconductor layer is located on a side of the first doped semiconductor layer close to the semiconductor substrate.

10. The back contact cell according to claim 1, characterized in that: The row of pads closest to the second side is the last row of pads, along the direction from the first row of pads to the last row of pads; In the even-numbered columns of pads, an orthographic projection of a gap between any two adjacent pads along the second direction on the first surface overlaps with an orthographic projection of the isolation region on the first surface; And / or, the odd-numbered columns of pads include at least two adjacent pads along the second direction, and an orthographic projection of a gap between the two pads on the first surface does not overlap with an orthographic projection of the isolation region on the first surface.

11. The back contact cell according to claim 1, characterized in that: The first current collection layer and the second current collection layer are both doped semiconductor layers, and the first current collection layer and the semiconductor substrate have the same doping type.

12. The back contact cell according to claim 1, characterized in that: The first current collection layer and the second current collection layer are both transparent conductive layers.

13. The back contact cell according to claim 12, characterized in that: It also includes a first doped semiconductor layer arranged between the first surface and the first current collection layer, and a second doped semiconductor layer arranged between the first surface and the second current collection layer, wherein there is an overlapping portion between the first doped semiconductor layer and the second doped semiconductor layer, and the projection of the overlapping portion on the first surface at least partially overlaps with the projection of the isolation region on the first surface.

14. A photovoltaic module, characterized in that: The invention comprises an electrical connector and a back-contact battery as claimed in any one of claims 1 to 13, wherein the electrical connector is conductively connected to the pad.

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