LED chip with electrostatic protection function and preparation method thereof

Abstract

The application provides an LED chip with electrostatic protection function and a preparation method thereof, and comprises the following steps: growing an epitaxial layer on a substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are stacked in sequence from bottom to top; etching a through hole on the epitaxial layer to expose the N-type semiconductor layer; preparing a dielectric layer, a reflective layer, a wafer bonding barrier layer and a wafer bonding adhesive layer, and co-crystal bonding the wafer bonding adhesive layer with the wafer bonding adhesive layer on the substrate; removing the substrate; Schottky electrode protection photoetching; preparing an edge-removing layer, and photoetching the epitaxial layer to form a channel; preparing a passivation layer and a Schottky electrode; patterning the passivation layer and the edge-removing layer to prepare an N-face electrode. The Schottky diode arranged below the pad of the LED chip improves the anti-static discharge capacity of the LED without sacrificing the light power.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to an LED chip with electrostatic protection function and a preparation method thereof. BACKGROUND

[0002] LED is the abbreviation of Light-Emitting Diode, and its Chinese name is Light Emitting Diode. Its light emitting principle is that holes in P-type semiconductor and electrons in N-type semiconductor become photons under the action of electric field after radiative recombination. LED chip has many advantages such as low power consumption, high color purity, long service life, small size, fast response time, energy saving and environmental protection, and is widely used in lighting, visible light communication and light emitting display scenes.

[0003] In order to prevent LED from being damaged by electrostatic discharge, the common solution is to connect a Zener diode in reverse parallel with the LED before packaging. When the reverse electrostatic discharge phenomenon occurs, the pulse current generated by electrostatic discharge will flow through the Zener diode to avoid the damage of LED by static electricity.

[0004] However, this solution has the following problems: 1. Before the completion of packaging, the LED chip is likely to fail due to static electricity; 2. The difficulty of installing Zener diode in the packaging process is high, and the packaging process cost is high; 3. Because the Zener diode is placed close to the LED chip in the packaging, the luminous efficiency of the LED packaging will be reduced due to the light absorbed by the Zener diode, thereby reducing the yield of the LED packaging. SUMMARY

[0005] The purpose of the present application is to provide a preparation method of an LED chip with electrostatic protection function, which can solve the problem of LED damaged by electrostatic discharge.

[0006] In order to solve the above technical problems, the present application is implemented as follows:

[0007] On the one hand, the present application provides a preparation method of an LED chip with electrostatic protection function, comprising the following steps:

[0008] S1: growing an epitaxial layer on a substrate, the epitaxial layer comprising an N-type semiconductor layer, an active layer and a P-type semiconductor layer stacked in sequence from bottom to top;

[0009] S2: etching a through hole on the epitaxial layer to expose the N-type semiconductor layer;

[0010] S3: preparing a dielectric layer, the dielectric layer covering the side wall of the through hole;

[0011] S4: preparing a reflective layer on the surface of the P-type semiconductor layer;

[0012] S5: preparing a wafer bonding barrier layer and a wafer bonding adhesive layer on the surface of the epitaxial layer, the wafer bonding barrier layer filling the via and forming an ohmic contact with the N-type semiconductor layer through the via, and the wafer bonding adhesive layer filling the via;

[0013] S6: eutectic bonding the wafer bonding adhesive layer on the substrate with the wafer bonding adhesive layer on the substrate;

[0014] S7: removing the substrate to expose one side of the N-type semiconductor layer;

[0015] S8: protecting the N-type semiconductor layer in the Schottky electrode region, and etching and roughening the N-type semiconductor layer in other unprotected regions;

[0016] S9: preparing a bevel-removing layer on the surface of the exposed N-type semiconductor layer, and patterning the epitaxial layer and the bevel-removing layer to form a channel;

[0017] S10: preparing a passivation layer, and preparing a Schottky electrode on the surface of the N-type semiconductor layer at a position corresponding to the via;

[0018] S11: patterning the passivation layer and the bevel-removing layer;

[0019] S12: preparing an N-face electrode.

[0020] Optionally, the N-type semiconductor layer grown in step S1 is composed of a low-doped N-type semiconductor layer close to the substrate and a high-doped N-type semiconductor layer away from the substrate.

[0021] Optionally, the wafer bonding barrier layer, the N-type semiconductor layer in ohmic contact with the wafer bonding barrier layer, and the Schottky electrode form a Schottky diode; the wafer bonding barrier layer is the cathode of the Schottky diode, and the Schottky electrode is the anode of the Schottky diode.

[0022] Optionally, the N-face electrode prepared in step S12 includes a pad and a finger electrode, the pad of the N-face electrode is located on the surface of the Schottky electrode, and the size of the pad of the N-face electrode is greater than that of the Schottky electrode.

[0023] Optionally, the via prepared in step S2 is located at a position corresponding to the pad of the N-face electrode; the shape of the via is consistent with the shape of the pad of the N-face electrode.

[0024] Optionally, the via is a cylindrical shape; the dielectric layer covers the sidewall of the via to form an annular cylindrical shape, the size of the pad of the N-face electrode is smaller than the size of the large circle of the annular cylindrical shape formed by the dielectric layer; the dielectric layer further includes a finger region, the finger region corresponds to the position of the finger electrode of the N-face electrode, and the width of the finger electrode of the N-face electrode is smaller than the width of the finger region of the dielectric layer.

[0025] Optionally, the trench in step S9 includes a cutting street and a trench around the Schottky diode, and the trench around the Schottky diode separates the Schottky diode from the epitaxial layer of the light emitting region of the LED chip.

[0026] Optionally, when patterning the passivation layer and the edge removal layer in step S11, the pattern includes finger-shaped areas, with the passivation layer and the edge removal layer remaining in the middle area of ​​the fingers, and the size of the remaining passivation layer and the edge removal layer is smaller than the finger electrodes of the N-side electrode.

[0027] In a second aspect, the present application provides an LED chip with electrostatic protection function prepared by the above preparation method.

[0028] Optionally, the LED chip with electrostatic protection function includes:

[0029] substrate;

[0030] An epitaxial layer, the epitaxial layer comprising a P-type semiconductor layer, an active layer, and an N-type semiconductor layer arranged in a direction away from the substrate; the epitaxial layer having a through-channel, the channel separating the epitaxial layer into a Schottky region and a light-emitting region; the N-type semiconductor layer comprising a highly doped N-type semiconductor layer adjacent to the active layer and a low doped N-type semiconductor layer distal to the active layer; a through hole being provided on a side of the epitaxial layer adjacent to the substrate and corresponding to the channel, the through hole exposing the highly doped N-type semiconductor layer in the Schottky region;

[0031] An N-side electrode is provided on the side of the epitaxial layer away from the substrate and forms an ohmic contact with the highly doped N-type semiconductor layer;

[0032] A Schottky electrode is provided between the pad of the N-side electrode and the N-type semiconductor layer in the Schottky region; the Schottky electrode forms a Schottky contact with the low-doped N-type semiconductor layer in the Schottky region;

[0033] Edge removal layer and passivation layer, covering the channel and chip surface;

[0034] A reflective layer, provided on one side of the P-type semiconductor layer in the light emitting region;

[0035] A wafer bonding barrier layer is provided on the side of the epitaxial layer close to the substrate; the wafer bonding barrier layer forms an ohmic contact with the highly doped N-type semiconductor layer in the Schottky region through a through hole;

[0036] The dielectric layer is provided between the wafer bonding barrier layer and the P-type semiconductor layer, isolating the wafer bonding barrier layer from the P-type semiconductor layer, the active layer and the reflective layer. At the cutting path of the LED chip, the dielectric layer is provided between the wafer bonding barrier layer and the passivation layer;

[0037] Wafer bonding adhesive layer, bonding wafer bonding barrier layer and substrate;

[0038] The back metal layer is arranged on the other side of the substrate.

[0039] Beneficial effects of the present invention:

[0040] (1) The method for preparing an LED chip with an electrostatic protection function in the present invention is to prepare a wafer bonding barrier layer and a Schottky electrode at corresponding positions on both sides of the N-type semiconductor layer in the LED chip. The wafer bonding barrier layer forms an ohmic contact with the N-type semiconductor layer, and the Schottky electrode forms a Schottky contact with the N-type semiconductor layer. That is, a Schottky diode is prepared in the LED chip, and the Schottky diode is reversely connected in parallel with the LED chip, thereby improving the anti-electrostatic discharge capability of the LED. The problem of the chip's inability to withstand electrostatic discharge can be solved during the LED chip manufacturing process.

[0041] (2) The Schottky diode is placed under the pad of the N-side electrode of the LED chip, which does not occupy the light-emitting area, and realizes the electrostatic protection of the LED chip without sacrificing the light power.

[0042] (3) A passivation layer and a trimming layer smaller than the finger electrode size are left under the finger electrode of the N-side electrode of the LED chip, which can improve the current expansion of the LED chip. Under high current, the current distribution of the LED chip is more uniform. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 FIG. 1 is a top view schematically showing the process of completing step S2 in an embodiment of the present invention.

[0044] Figure 2 Schematic cross-sectional view of completing step S2 in an embodiment of the present invention.

[0045] Figure 3 Schematic diagram of a top view of completing step S3 in an embodiment of the present invention.

[0046] Figure 4 Schematic cross-sectional view of completing step S3 in an embodiment of the present invention.

[0047] Figure 5 This is a top view schematic diagram of completing step S4 in this embodiment of the present invention.

[0048] Figure 6 Schematic cross-sectional view of completing step S4 in an embodiment of the present invention.

[0049] Figure 7 Schematic cross-sectional view of completing step S5 in an embodiment of the present invention.

[0050] Figure 8 FIG. 1 is a top view schematically showing the process of completing step S9 in an embodiment of the present invention.

[0051] Figure 9 FIG. 1 is a cross-sectional diagram of completing step S9 in an embodiment of the present invention.

[0052] Figure 10 In the embodiment of the present invention Figure 8 Enlarged schematic diagram of point B in the middle.

[0053] Figure 11 FIG. 1 is a cross-sectional diagram of completing step S10 in an embodiment of the present invention.

[0054] Figure 12 FIG. 1 is a top view schematically showing the process of completing step S11 in an embodiment of the present invention.

[0055] Figure 13 This is a comparison chart of light distribution between the LED chip prepared according to the embodiment of the present invention and a common LED.

[0056] Figure 14 FIG. 1 is a top view schematically showing the process of completing step S12 in an embodiment of the present invention.

[0057] Figure 15 Schematic cross-sectional view of completing step S12 in an embodiment of the present invention. DETAILED DESCRIPTION

[0058] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0059] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs.

[0060] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0061] In the present invention, the directions or positional relationships indicated by terms such as "upper", "lower", "horizontal", and "middle" are based on the directions or positional relationships shown in the accompanying drawings. They are relational words determined only for the convenience of describing the structural relationships of the various parts or elements of the present invention. They do not specifically refer to any part or element in the present invention and cannot be understood as limitations on the present invention.

[0062] In the absence of conflict, the embodiments of the present invention and the features thereof may be combined with each other.

[0063] In a first aspect, the embodiments of the present application provide an LED chip with electrostatic protection function and a preparation method thereof. A Schottky diode is arranged below the pad of the N-face electrode of the LED chip, so that the anti-static discharge capability of the LED chip is realized without occupying the light-emitting area.

[0064] The specific process steps for preparing the LED chip with electrostatic protection function are as follows:

[0065] Step S1: An epitaxial layer is grown on the substrate 14, which comprises, from bottom to top, an N-type semiconductor layer 9, an active layer 8 and a P-type semiconductor layer 7 which are stacked in sequence. The N-type semiconductor layer 9 is composed of a low-doped N-type semiconductor layer close to the substrate 14 and a high-doped N-type semiconductor layer away from the substrate (not shown in the figure).

[0066] Step S2: A via hole is etched on the epitaxial layer to expose the high-doped N-type semiconductor layer.

[0067] In some embodiments of the present application, the epitaxial layer is subjected to a first photolithography. After the photolithography is completed, the positions of the Schottky diode on the surface of the epitaxial layer are not protected by photoresist, and other positions are protected by photoresist. Then, an inductively coupled plasma (ICP) etching technology is used to etch the positions of the epitaxial layer without photoresist protection, to etch a via hole to expose the high-doped N-type semiconductor layer. The N-type semiconductor layer 9 below the via hole is the N-type semiconductor layer of the Schottky diode. The shape of the etched via hole is a cylindrical shape, or a racetrack shape (i.e., a combined shape of a long rectangle with a semicircle at each end), a round-cornered square column shape, etc. The top view schematic diagram after etching is shown in Figure 1 , and the cross-sectional schematic diagram is shown in Figure 2 .

[0068] Step S3: A dielectric layer 5 is prepared, which covers the side wall of the via hole.

[0069] In some embodiments of the present application, the photoresist in step S2 is removed, and a plasma-enhanced chemical vapor deposition (PECVD) technology is used to deposit a layer of dielectric material on the surface of the P-type semiconductor layer 7. Then, a second photolithography is performed. After the epitaxial layer is subjected to the photolithography, the photoresist pattern is left, and then the dielectric material is etched. The remaining dielectric material forms the dielectric layer 5, which covers the side wall of the via hole and part of the area at the bottom of the via hole. The top view schematic diagram after the dielectric layer 5 is prepared is shown in Figure 3 , and the cross-sectional schematic diagram is shown in Figure 4 , Figure 4 is Figure 3 the cross-sectional schematic diagram along A-A.

[0070] In some embodiments of the present application, the dielectric layer 5 fills the shape formed by the side wall of the via hole and part of the area at the bottom of the via hole, which is consistent with the shape of the via hole, i.e., a ring-shaped cylinder, a ring-shaped racetrack, a ring-shaped round-cornered square column, etc.

[0071] In some embodiments of the present application, the die cutting path also leaves the dielectric layer 5.

[0072] In some embodiments of the present application, the dielectric layer 5 is also provided with a finger structure. Whether the dielectric layer 5 is designed with a finger structure and the size of the finger structure need to be determined according to the size of the chip. For small size products, such as 10 mil, the finger structure is not needed.

[0073] In some embodiments of the present application, the dielectric material is an insulating material, such as aluminum oxide, silicon nitride, silicon oxide.

[0074] It should be noted that the dielectric layer 5 at the via is used to isolate the P-type semiconductor layer 7, the active layer 8 and the wafer bonding barrier layer 4, and to ensure that the highly doped N-type semiconductor layer of the Schottky diode is in contact with the wafer bonding barrier layer 4, which serves as the cathode electrode of the Schottky diode. The P-type semiconductor layer 7 surface is left with a dielectric layer 5, which is used as a high resistance layer to improve light extraction efficiency, and the die cutting path is left with a dielectric layer 5, which is used as a P-face passivation.

[0075] Step S4: preparing a reflective layer 6 on the surface of the P-type semiconductor layer 7.

[0076] In some embodiments of the present application, after activation on the surface of the epitaxial layer, a vacuum evaporation, magnetron sputtering or other technology is used to evaporate a metal reflective material on the surface of the epitaxial layer, and then a third photoetching is performed. After photoetching of the epitaxial layer, a wet etching method is used to remove the metal reflective material in the cutting path and the corresponding position of the Schottky diode in the middle area, and finally the photoresist is removed to form the reflective layer 6, which is used to improve light extraction efficiency. The top view of the prepared reflective layer 6 is shown in Figure 5 , and the cross-sectional view is shown in Figure 6 .

[0077] In some embodiments of the present application, the reflective layer 6 is also the P-face electrode of the vertical structure LED chip.

[0078] In some embodiments of the present application, the metal reflective material is a metal with reflectivity greater than 90%, such as Ag, Al, etc.

[0079] In some embodiments of the present application, after the metal reflective material is evaporated and alloyed, a metal protective material, such as Ti, can be further evaporated on the surface of the metal reflective material, and then photoetching is performed.

[0080] It should be noted that when the metal reflective material in the middle area of the Schottky diode is photoetched, the photoetching radius should be larger than the small circle radius of the dielectric layer to ensure that there is no reflective layer 6 in the hole above the N-type semiconductor layer of the Schottky diode. The photoetching radius should also be smaller than the large circle radius of the dielectric layer to ensure that the light power is not affected.

[0081] Step S5: preparing wafer bonding barrier layer 4 and wafer bonding adhesive layer 3, wafer bonding barrier layer 4 fills the via and forms ohmic contact with the high-doped N-type semiconductor layer through the via, wafer bonding adhesive layer 3 fills the via.

[0082] In some embodiments of the present application, wafer bonding barrier layer 4 is prepared on the surface of the epitaxial layer by vacuum evaporation or magnetron sputtering technology, and wafer bonding barrier layer 4 forms ohmic contact with the high-doped N-type semiconductor layer through the via. Wafer bonding adhesive layer 3 is evaporated on the surface of wafer bonding barrier layer 4, wafer bonding adhesive layer 3 fills the via to form a flat surface, and the prepared cross-sectional schematic diagram is shown in Figure 7

[0083] In some embodiments of the present application, the material of wafer bonding barrier layer 4 is Cr / Pt / Ti or Cr / Pt / TiW. Wafer bonding barrier layer 4 has two functions: one is to prevent low-melting-point metals from diffusing to the reflective layer to form black spots in eutectic bonding, and the other is to serve as the cathode electrode of the Schottky diode.

[0084] In some embodiments of the present application, the material of wafer bonding adhesive layer 3 is a binary alloy, in which one is a low-melting-point metal and the other is a high-melting-point metal, including but not limited to CuIn, AuIn, AuSn, and NiSn. In the eutectic process, the low-melting-point metal is in a liquid state, which fills the via and finally forms a flat bonding interface.

[0085] Step S6: eutectic bonding wafer bonding adhesive layer 3 with wafer bonding adhesive layer on the substrate.

[0086] In some embodiments of the present application, the substrate 2 with wafer bonding adhesive layer evaporated on the front surface is eutectic bonded with wafer bonding adhesive layer 3.

[0087] In some embodiments of the present application, the back surface of substrate 2 is also evaporated with a back metal layer 1 for back surface conduction of the vertical structure LED.

[0088] Step S7: removing the substrate 14 to expose one side of the N-type semiconductor layer 9.

[0089] In some embodiments of the present application, after the bonding is completed, the chip is turned over and the substrate is removed, and thus the low-doped N-type semiconductor layer is on the top.

[0090] Step S8: protecting the N-type semiconductor layer in the Schottky electrode area, and then etching and roughening the N-type semiconductor layer in the other unprotected area.

[0091] ​In some embodiments of the present application, a protective layer is first deposited using PECVD technology, and then the fourth step of photolithography is performed. After the photolithography is completed, the protective layer at the preset Schottky electrode position has photoresist, and the protective layer in other areas is not protected by photoresist and is etched with BOE. Etching is then performed using ICP etching technology to remove the low-doped N-type semiconductor layer in the unprotected area, and the light extraction efficiency of the chip is improved by roughening the high-doped N-type semiconductor layer. At this time, the low-doped N-type semiconductor layer in the unprotected area is completely removed, and the high-doped N-type semiconductor layer is roughened. The N-type semiconductor layer 9 in the preset Schottky electrode area is not etched and roughened, and the surface of the N-type semiconductor layer 9 in this area is a low-doped N-type semiconductor layer. After completion, a degumming solution is required to remove the photoresist and then the protective layer is corroded with BOE.

[0092] In some embodiments of the present application, the protective layer is made of insulating material, and the insulating material includes aluminum oxide, silicon nitride, and silicon oxide.

[0093] Step S9: preparing a trimming layer 10 on the surface of the exposed N-type semiconductor layer 9, and photolithography the epitaxial layer and the trimming layer 10 to form a channel.

[0094] In some embodiments of the present application, the above-mentioned chip is cleaned, and then the PECVD technology is used to deposit the edge removal layer 10 on the surface of the N-type semiconductor layer 9, and then the fifth step of photolithography is performed. The photoresist protects the light-emitting area and the Schottky diode area, and the unprotected area is corroded. The edge removal layer 10, the N-type semiconductor layer 9, the active layer 8, and the P-type semiconductor layer 7 of the cut path are corroded to form an independent LED die. In addition, the edge removal layer 10, the N-type semiconductor layer 9, the active layer 8, and the P-type semiconductor layer 7 around the Schottky diode are also corroded to form a channel. The purpose of this is to separate the Schottky diode from the light-emitting area of ​​the LED chip. After the epitaxial layer is etched, the photoresist is removed, and the top view schematic diagram after preparation is as shown. Figure 8 As shown, the cross-sectional diagram is as follows Figure 9 As shown, Figure 10 yes Figure 8 A partial enlarged view of point B in the middle.

[0095] In some embodiments of the present application, the edge removal layer is made of insulating material, and the insulating material includes aluminum oxide, silicon nitride, and silicon oxide.

[0096] It should be noted that the radius of the small circle in the edge removal lithography is larger than the radius of the small circle in the dielectric layer, and the radius of the large circle in the edge removal lithography is larger than the lithography radius of the epitaxial layer in step S2 and smaller than the large circle radius of the dielectric layer. The purpose is to completely remove the epitaxial layer around the cathode electrode of the Schottky diode and ensure that the wafer bonding barrier layer 4 in the through hole is not corroded. The width of the edge removal lithography cut street needs to be narrower than the cut street in the reflective layer lithography to ensure that the reflective layer 6 in the light-emitting area is not corroded.

[0097] Step S10: a passivation layer 11 is prepared, and a Schottky electrode 12 is prepared at a position corresponding to the via hole on the surface of the N-type semiconductor layer 9.

[0098] In some embodiments of the present application, the passivation layer 11 is prepared on the edge-removing layer 10, and covers the entire surface of the edge-removing layer 10, the channel bottom and sidewall, and the scribe lane bottom and sidewall. The passivation layer 11 protects the epitaxial structure of the scribe lane from electric leakage, and isolates the epitaxial structure of the LED and the Schottky diode. After the passivation layer 11 is prepared, a sixth photolithography is performed. After the photolithography is completed, the passivation layer 11 and the edge-removing layer 10 at the position of the preset Schottky electrode are etched. Then, the Schottky metal is evaporated on the entire surface of the chip, and the Schottky metal at other positions is stripped after evaporation, and the remaining Schottky metal is the Schottky electrode 12. The Schottky electrode 12 forms a Schottky contact with the low-doped N-type semiconductor layer. The cross-sectional view after the preparation is shown in FIG. 6. Figure 11

[0099] In some embodiments of the present application, the passivation layer 11 is prepared in two steps. A dense passivation layer material is first deposited by atomic layer deposition, and then a passivation layer material is deposited by PECVD technology. The material of the passivation layer 11 also adopts an insulating material, including aluminum oxide, silicon nitride, and silicon oxide.

[0100] In some embodiments of the present application, the Schottky electrode 12 is circular or circular-angled square, or track-shaped, etc. The Schottky electrode 12 is arranged below the pad of the N-face electrode 13, and can be located at the center of the chip or at other positions of the chip. The size of the Schottky electrode needs to be smaller than the size of the small circle in the edge-removing photolithography.

[0101] In some embodiments of the present application, the Schottky metal is Ni / Au or Pt / Au. Ni and Pt have good adhesion with semiconductor materials and high metal work functions. A layer of gold Au is deposited on the Ni or Pt to prevent oxidation of the metal and increase conductivity.

[0102] Step S11: the passivation layer 11 and the edge-removing layer 10 are patterned.

[0103] In some embodiments of the present application, a seventh photolithography is performed. After the photolithography is completed, part of the passivation layer 11 and part of the edge-removing layer 10 at the finger-shaped electrode region of the preset N-face electrode are etched to expose the high-doped N-type semiconductor layer, so that the high-doped N-type semiconductor layer forms an ohmic contact with the N-face electrode 13 prepared subsequently. The top view after the passivation layer 11 and the edge-removing layer 10 are etched is shown in FIG. 7. Figure 12

[0104] Step S12: the N-face electrode 13 is prepared.

[0105] ​​After removing the photoresist of the seventh photoetching, the eighth photoetching is performed. After the photoetching, the N-face electrode metal is evaporated, and then the N-face electrode 13 is peeled off, thus completing the preparation of the chip. The structure of the prepared LED chip with electrostatic protection function is shown in Figure 14 、 15 , Figure 15 is Figure 14 a cross-sectional view at C-C.

[0106] It should be noted that part of the passivation layer 11 and part of the edge removal layer 10 are left in the middle region of the finger-shaped electrode of the N-face electrode 13, which is used to improve the current spreading. Compared with the chip without the passivation layer, the light distribution of the chip of the present application is more uniform under the same current, as shown in Figure 13 , 13a is a light distribution diagram of the LED chip without the passivation layer, and 13b is a light distribution diagram of the LED chip with part of the passivation layer. The lighting current of the two is 100 mA.

[0107] In some embodiments of the present application, for small-size LEDs such as 10 mil LEDs, the N-face electrode has no finger-shaped region, and then part of the passivation layer 11 and part of the edge removal layer 10 need to be etched in the pad region of the N-face electrode, which is used to form ohmic contact between the N-face electrode 13 and the N-type semiconductor layer 9.

[0108] In some embodiments of the present application, the material of the N-face electrode metal includes but is not limited to Cr / Pt / Au, Ti / Al / Ti / Pt / Au, Cr / Al / Cr / Pt / Au.

[0109] In some embodiments of the present application, the pad of the N-face electrode 13 is circular, round square, racetrack-shaped, etc.

[0110] It should be noted that the chips from 6 mil to 80 mil can use the design method of the present application to improve the electrostatic discharge capacity, and the pad radius is designed to be 25 μm to 70 μm.

[0111] In a second aspect, the embodiments of the present application provide an LED chip with electrostatic protection function prepared by the above preparation method.

[0112] In some embodiments of the present application, the LED chip with electrostatic protection function comprises:

[0113] a substrate 2;

[0114] An epitaxial layer, which comprises a P-type semiconductor layer 7, an active layer 8 and an N-type semiconductor layer 9 arranged in a direction away from the substrate; the epitaxial layer has a channel passing through, which separates the epitaxial layer into a Schottky region and a light-emitting region; the N-type semiconductor layer 9 is composed of a high-doped N-type semiconductor layer close to the active layer and a low-doped N-type semiconductor layer away from the active layer; a through hole is arranged on the side of the epitaxial layer close to the substrate 2 and at the position corresponding to the channel, which exposes the high-doped N-type semiconductor layer of the Schottky region;

[0115] An N-face electrode 13 is arranged on the side of the epitaxial layer away from the substrate, which forms an ohmic contact with the high-doped N-type semiconductor layer;

[0116] A Schottky electrode 12 is arranged between the pad of the N-face electrode 13 and the N-type semiconductor layer 9 of the Schottky region; the Schottky electrode 12 forms a Schottky contact with the low-doped N-type semiconductor layer of the Schottky region;

[0117] An edge-removing layer 10 and a passivation layer 11 cover the channel and the surface of the chip;

[0118] A reflective layer 6 is arranged on the side of the P-type semiconductor layer 7 of the light-emitting region;

[0119] A wafer bonding barrier layer 4 is arranged on the side of the epitaxial layer close to the substrate; the wafer bonding barrier layer 4 forms an ohmic contact with the high-doped N-type semiconductor layer of the Schottky region through the through hole;

[0120] A dielectric layer 5 is arranged between the wafer bonding barrier layer 4 and the P-type semiconductor layer 7, which isolates the wafer bonding barrier layer 4 from the P-type semiconductor layer 7, the active layer 8 and the reflective layer 6; at the cutting path of the LED chip, the dielectric layer 5 is arranged between the wafer bonding barrier layer 4 and the passivation layer 11;

[0121] A wafer bonding adhesive layer 3 bonds the wafer bonding barrier layer 4 and the substrate 2;

[0122] A back metal layer 1 is arranged on the other side of the substrate 2. Embodiment 1

[0123] This embodiment takes an LED chip with a size of 700 μm × 700 μm as an example, as shown in FIG. 1, and the specific preparation process is as follows: Figures 1-15

[0124] Step S1: sequentially growing an N-type semiconductor layer 9, an active layer 8 and a P-type semiconductor layer 7 on a substrate 14.

[0125] Specifically, the substrate 14 is a silicon substrate, and the N-type semiconductor layer 9, the active layer 8 and the P-type semiconductor layer 7 are GaN materials.

[0126] ​Step S2: The substrate for growing the epitaxial layer is first cleaned, and then a first photolithography is performed, which is GaN etching photolithography, including 6 sub-steps of baking the adhesive, coating the positive photoresist, pre-baking, exposure, development and hardening. After the photolithography is completed, the surface of the P-type semiconductor layer 7 has no photoresist protection at the positions where the Schottky diode is preset, and other positions are protected by the photoresist. Then, ICP etching technology is used to etch from the P-type semiconductor layer 7, etch away all the P-type semiconductor layer 7 and the active layer 8, the etching depth is about 7000 Å, and a through hole is etched to expose the highly doped N-type semiconductor layer. The N-type semiconductor layer 9 under the through hole is the N-type semiconductor layer of the Schottky diode. The shape of the etched through hole is a cylinder with a radius of 31 μm. The top view schematic diagram of the etching completion and the photoresist removal is shown in Figure 1 , and the cross-sectional schematic diagram is shown in Figure 2 .

[0127] Step S3: Prepare the dielectric layer 5, which covers the side wall of the through hole.

[0128] Specifically, first, the deionized water and alcohol are used for ultrasonic cleaning, and then the PECVD technology is used to deposit a layer of silicon oxide on the surface of the P-type semiconductor layer 7. Then, a second photolithography is performed, which is dielectric layer photolithography, also including 6 sub-steps of baking the adhesive, coating the positive photoresist, pre-baking, exposure, development and hardening. After the photolithography is completed, the photoresist pattern is left, and then the BOE is used to etch the silicon oxide, and the remaining silicon oxide forms the dielectric layer 5. The dielectric layer 5 forms a ring-shaped cylinder in the partial area of the side wall of the through hole and the bottom of the through hole, and is provided with a finger structure, and the dielectric layer is also left in the die core cutting channel.

[0129] In this embodiment, the large radius of the ring-shaped cylinder formed by the dielectric layer 5 in the partial area of the side wall of the through hole and the bottom of the through hole is 40 μm, and the small radius is 23 μm. The width of the finger structure of the dielectric layer 5 in the longitudinal direction is 18 μm, and the width in the transverse direction is 22 μm. The top view schematic diagram after the dielectric layer 5 is prepared is shown in Figure 3 , and the cross-sectional schematic diagram is shown in Figure 4 , Figure 4 is Figure 3 the cross-sectional schematic diagram along A-A.

[0130] Step S4: After Mg activation on the surface of the epitaxial layer (Mg-H bond is broken by annealing method, Mg is activated to improve the hole concentration, reduce the voltage and improve the light extraction efficiency), Ag is evaporated on the surface of the epitaxial layer by vacuum evaporation technology, and then the third photoetching is performed, which is a reflection layer photoetching, including 5 small steps of coating positive photoresist, pre-baking, exposure, development and hardening. The radius of the circular hole of the reflection layer photoetching plate is 35 μm. After the epitaxial layer is photoetched, the Ag in the cutting channel and the corresponding position of the Schottky diode in the middle area is removed by wet etching method, and finally the photoresist is removed to form the reflection layer 6. The top view of the prepared reflection layer 6 is shown in Figure 5 , and the cross-sectional view is shown in Figure 6 .

[0131] Step S5: After cleaning, a wafer bonding barrier layer 4 is prepared on the surface of the epitaxial layer by vacuum evaporation technology, and the material of the wafer bonding barrier layer 4 is Cr / Pt / Ti. The wafer bonding barrier layer 4 forms an ohmic contact with the high-doped N-type semiconductor layer through the via hole. Then the wafer bonding adhesive layer 3 is evaporated on the surface of the wafer bonding barrier layer 4, and the material of the wafer bonding adhesive layer 3 is CuIn. In the eutectic process, In is in liquid state, the via hole is filled flat, and finally a flat bonding interface is formed. The prepared cross-sectional view is shown in Figure 7 .

[0132] Step S6: The substrate 2 with the wafer bonding adhesive layer evaporated on the front surface is eutectically bonded with the wafer bonding adhesive layer 3, and the back surface of the substrate 2 is evaporated with the back metal layer 1.

[0133] Step S7: After the bonding is completed, the chip is turned over, the silicon substrate is thinned to a thickness of 215 μm to 245 μm, and the remaining silicon substrate is removed by wet etching method. At this time, the low-doped N-type semiconductor layer is on the top.

[0134] Step S8: A protective layer of silicon oxide is first deposited by PECVD technology, and then the fourth photoetching is performed, which is a Schottky electrode protection photoetching. The Schottky electrode photoetching includes 6 small steps of baking the adhesive, coating positive photoresist, pre-baking, exposure, development and hardening. After the Schottky electrode protection photoetching is completed, the protective layer in the unprotected area is etched. Then, the low-doped N-type semiconductor layer in the unprotected area is etched by ICP etching technology, and the high-doped N-type semiconductor layer is roughened to improve the light extraction efficiency of the chip. At this time, the low-doped N-type semiconductor layer in the unprotected area is completely removed, and the high-doped N-type semiconductor layer is roughened. The N-type semiconductor layer 9 in the preset Schottky electrode area is not etched and roughened, and the surface of the N-type semiconductor layer 9 in this area is a low-doped N-type semiconductor layer. After the roughening is completed, the photoresist is removed with a stripping solution, and then the protective layer is etched with a BOE solution.

[0135] In this embodiment, the Schottky electrode protection region is in the middle of the chip and is circular, and the radius of the circular hole of the Schottky electrode protection region is 20 μm.

[0136] Step S9: A side-removing layer 10 is formed on the surface of the N-type semiconductor layer, and the material is silicon oxide. A fifth photoetching is performed. The photoetching is side-removing photoetching, which includes six sub-steps of baking the adhesive, coating the positive photoresist, pre-baking, exposure, development and hardening. The photoresist protects the light-emitting region and the Schottky diode region, and the unprotected region is first etched by the BOE solution to remove the side-removing layer 10, and then etched by the hot phosphoric acid solution to etch the semiconductor layer. The hot phosphoric acid solution etches the semiconductor layer of the cutting path and the semiconductor layer around the Schottky diode and forms a channel. After the semiconductor layer is etched, the photoresist is removed by the photoresist removing solution. The top view of the prepared product is shown in Figure 8 , and the cross-sectional view is shown in Figure 9 , Figure 10 is Figure 8 a local enlarged view of B in

[0137] In this embodiment, the radius of the large circle of the side-removing photoetching is 35 μm, and the radius of the small circle is 27 μm. The cutting path width set by the side-removing photoetching is 20 μm, and the cutting path width set by the reflection layer photoetching is 32 μm.

[0138] Step S10: A dense aluminum oxide layer is first deposited on the surface of the side-removing layer 10 by atomic layer deposition, and then a silicon oxide layer is grown on the surface of the aluminum oxide layer by PECVD technology. The aluminum oxide and the silicon oxide form a passivation layer 11, which covers the entire surface of the side-removing layer 10, the cutting path and the cutting path sidewall of the independent LED die, the channel and the channel sidewall around the Schottky diode. After the passivation layer 11 is prepared, a sixth photoetching is performed. The photoetching is Schottky electrode photoetching, which includes six sub-steps of coating the negative photoresist, pre-baking, exposure, post-baking, development and hardening. After the Schottky electrode photoetching is completed, the passivation layer 11 and the side-removing layer 10 at the preset Schottky electrode position are etched by the BOE solution. Then, Ni / Au is evaporated on the entire surface of the chip by vacuum electron beam evaporation technology. After evaporation, the Schottky metal on other parts is peeled off, and the remaining Schottky metal is the Schottky electrode 12. The cross-sectional view is shown in Figure 11 .

[0139] In this embodiment, the Schottky electrode 12 is in the middle of the chip and is circular, and the radius of the Schottky electrode 12 is 12 μm.

[0140] Step S11: After the preparation of the passivation layer 11, the seventh step of photoetching is carried out, which is the de-passivation photoetching. The de-passivation photoetching includes six sub-steps of baking the adhesive, coating the positive photoresist, pre-baking, developing, exposing and hardening. After the photoetching is completed, the BOE solution is used to etch away the partial passivation layer 11 and the partial edge-removing layer 10 at the finger electrode area of the preset N-face electrode, so as to expose the high-doped N-type semiconductor layer, form the ohmic contact between the high-doped N-type semiconductor layer 9 and the subsequently prepared N-face electrode 13, and leave the partial passivation layer 11 and the partial edge-removing layer 10 in the middle area of the finger electrode of the N-face electrode 13. After the etching is completed, the photoresist needs to be removed by the degumming solution. The top view of the chip after the etching of the passivation layer 11 and the edge-removing layer 10 is shown in Figure 12 .

[0141] In this embodiment, the de-passivation photoetching is in the longitudinal direction, the width of the finger structure is set to 16 μm, and the width of the passivation layer in the middle area of the finger structure is set to 5 μm; in the transverse direction, the width of the finger structure is set to 20 μm, and the width of the passivation layer in the middle area of the finger structure is set to 8 μm.

[0142] Step S12: The eighth step of photoetching is carried out, which is the N-electrode photoetching. The N-electrode photoetching includes six sub-steps of coating the negative photoresist, pre-baking, developing, post-baking, exposing and hardening. After the photoetching is completed, the N-face electrode metal is evaporated on the chip by the vacuum evaporation method. The N-face electrode 13 is made by the peeling method after the evaporation, the N-face electrode 13 covers the Schottky electrode 12, the finger high-doped N-type semiconductor layer 9 and the passivation layer 11 in the middle area of the finger, and the preparation of the chip is completed. The structure of the LED chip with the static electricity protection function prepared in this embodiment is shown in Figure 14 , 15 . Figure 15 is Figure 14 the cross-sectional view at C-C.

[0143] In this embodiment, the pad of the N-face electrode 13 is circular, and the radius is 35 μm. The width of the finger electrode of the N-face electrode 13 in the longitudinal direction is 8 μm, and the width of the finger electrode of the N-face electrode 13 in the transverse direction is 12 μm.

[0144] In this embodiment, the N-face electrode metal is Cr / Pt / Au.

[0145] The LED chip with the static electricity protection function is prepared in this embodiment, and the structure is shown in Figure 15As shown, it includes: a substrate 2; an epitaxial layer, the epitaxial layer includes a P-type semiconductor layer 7, an active layer 8 and an N-type semiconductor layer 9 arranged in a direction away from the substrate 2; the N-type semiconductor layer is composed of a high-doped N-type semiconductor layer close to the active layer and a low-doped N-type semiconductor layer away from the active layer; the epitaxial layer has a through channel, and the channel separates the epitaxial layer into a Schottky region and a light-emitting region; a through hole is provided on the side of the epitaxial layer close to the substrate 2 and at a position corresponding to the channel, and the through hole exposes the high-doped N-type semiconductor layer in the Schottky region; an N-side electrode 13 is provided on the side of the epitaxial layer away from the substrate, and forms an ohmic contact with the high-doped N-type semiconductor layer; a Schottky electrode 12 is provided between the pad of the N-side electrode 13 and the N-type semiconductor layer 9 in the Schottky region; the Schottky electrode 1 2 forms a Schottky contact with the low-doped N-type semiconductor layer in the Schottky area; a trimming layer 10 and a passivation layer 11 cover the channel and the chip surface; a reflective layer 6 is provided on the P-type semiconductor layer 7 side of the light-emitting area; a wafer bonding barrier layer 4 is provided on the side of the epitaxial layer close to the substrate 2; the wafer bonding barrier layer 4 forms an ohmic contact with the high-doped N-type semiconductor layer in the Schottky area through the through hole; a dielectric layer 5 is provided between the wafer bonding barrier layer 4 and the P-type semiconductor layer 7, isolating the wafer bonding barrier layer 4 from the P-type semiconductor layer 7, the active layer 8 and the reflective layer 6, and is provided between the wafer bonding barrier layer 4 and the passivation layer 11 at the cutting path; a wafer bonding adhesive layer 3 adheres the wafer bonding barrier layer 4 and the substrate 2; and a back metal layer 1 is provided on the other side of the substrate 2.

[0146] The wafer bonding barrier layer 4, the N-type semiconductor layer 9 in ohmic contact with the wafer bonding barrier layer 4, and the Schottky electrode 12 form a Schottky diode. The wafer bonding barrier layer 4 serves as the Schottky diode's cathode, and the Schottky electrode 12 serves as the Schottky diode's anode. The Schottky diode and the LED chip are connected in anti-parallel, improving the LED chip's resistance to electrostatic discharge. The Schottky diode is placed below the solder pad of the LED chip's N-side electrode 13, eliminating the need for additional light-emitting area and providing electrostatic protection for the LED chip without sacrificing optical power.

[0147] In addition, a passivation layer 11 and a trimming layer 10 smaller than the finger electrodes are left under the finger electrodes of the N-side electrode 13, which can improve the current expansion of the LED chip. Under high current, the current distribution of the LED chip is more uniform.

[0148] Throughout this specification, references to "some embodiments" mean that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. Throughout this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0149] The above embodiments only express several implementation manners of the present application, which are described in a more specific and detailed manner, but cannot be understood as a limitation on the patent scope of the present application. It should be noted that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for preparing an LED chip with an electrostatic protection function, characterized in that: The following steps are involved: S1: growing an epitaxial layer on a substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked in sequence from bottom to top; S2: etching a through hole in the epitaxial layer to expose the N-type semiconductor layer; S3: preparing a dielectric layer, wherein the dielectric layer covers the sidewalls of the through hole; S4: preparing a reflective layer on the surface of the P-type semiconductor layer; S5: preparing a wafer bonding barrier layer and a wafer bonding adhesive layer on the surface of the epitaxial layer, wherein the wafer bonding barrier layer fills the through hole and forms an ohmic contact with the N-type semiconductor layer through the through hole, and the wafer bonding adhesive layer fills the through hole; S6: eutectic bonding the wafer bonding adhesive layer to the wafer bonding adhesive layer on the substrate; S7: removing the substrate to expose one side of the N-type semiconductor layer; S8: Protect the N-type semiconductor layer in the Schottky electrode area, and etch and roughen the N-type semiconductor layer in other unprotected areas; S9: preparing a trimming layer on the surface of the exposed N-type semiconductor layer, and photolithographically forming the epitaxial layer and the trimming layer to form a channel; S10: preparing a passivation layer and preparing a Schottky electrode on the surface of the N-type semiconductor layer and at a position corresponding to the through hole; S11: Patterning passivation layer and edge removal layer; S12: Prepare N electrode.

2. The method for preparing an LED chip according to claim 1, wherein: The N-type semiconductor layer grown in step S1 consists of a low-doped N-type semiconductor layer close to the substrate and a high-doped N-type semiconductor layer far from the substrate.

3. The method for preparing an LED chip according to claim 1, wherein: The wafer bonding barrier layer, the N-type semiconductor layer in ohmic contact with the wafer bonding barrier layer, and the Schottky electrode form a Schottky diode; the wafer bonding barrier layer is the cathode of the Schottky diode, and the Schottky electrode is the anode of the Schottky diode.

4. The method for preparing an LED chip according to claim 1, wherein: The N-side electrode prepared in step S12 includes a pad and a finger electrode. The pad of the N-side electrode is located on the surface of the Schottky electrode, and the pad size of the N-side electrode is larger than that of the Schottky electrode.

5. The method for preparing an LED chip according to claim 4, wherein: The position of the through hole prepared in step S2 corresponds to the pad of the N-side electrode; the shape of the through hole is consistent with the shape of the pad of the N-side electrode.

6. The method for preparing an LED chip according to claim 5, wherein: The through hole is cylindrical; the dielectric layer covers the side wall of the through hole to form an annular cylinder, and the pad size of the N-side electrode is smaller than the large circle size of the annular cylinder formed by the dielectric layer; the dielectric layer also includes a finger-shaped area, the finger-shaped area corresponds to the position of the finger-shaped electrode of the N-side electrode, and the width of the finger-shaped electrode of the N-side electrode is smaller than the width of the finger-shaped area of ​​the dielectric layer.

7. The method for preparing an LED chip according to claim 3, wherein: The trench in step S9 includes the cutting road and the trench around the Schottky diode. The trench around the Schottky diode separates the Schottky diode from the epitaxial layer of the light emitting region of the LED chip.

8. The method for preparing an LED chip according to claim 4, wherein: When the passivation layer and the edge removal layer are patterned in step S11, the pattern includes finger-shaped areas, and the passivation layer and the edge removal layer are left in the middle area of ​​the fingers. The size of the remaining passivation layer and the edge removal layer is smaller than the finger electrodes of the N-side electrode.

9. An LED chip with electrostatic protection function, characterized in that: The method is prepared according to any one of claims 1 to 8.

10. The LED chip with electrostatic protection function according to claim 9, characterized in that: The LED chip includes: substrate; An epitaxial layer, the epitaxial layer comprising a P-type semiconductor layer, an active layer, and an N-type semiconductor layer arranged in a direction away from the substrate; the N-type semiconductor layer comprising a highly doped N-type semiconductor layer proximal to the active layer and a low doped N-type semiconductor layer distal to the active layer; the epitaxial layer having a through-channel, the channel separating the epitaxial layer into a Schottky region and a light-emitting region; a through hole being provided on a side of the epitaxial layer proximal to the substrate and corresponding to the channel, the through hole exposing the highly doped N-type semiconductor layer in the Schottky region; An N-side electrode is provided on the side of the epitaxial layer away from the substrate and forms an ohmic contact with the highly doped N-type semiconductor layer; A Schottky electrode is provided between the pad of the N-side electrode and the N-type semiconductor layer in the Schottky region; the Schottky electrode forms a Schottky contact with the low-doped N-type semiconductor layer in the Schottky region; Edge removal layer and passivation layer, covering the channel and chip surface; A reflective layer, provided on one side of the P-type semiconductor layer in the light emitting region; A wafer bonding barrier layer is provided on a side of the epitaxial layer close to the substrate; the wafer bonding barrier layer forms an ohmic contact with the highly doped N-type semiconductor layer in the Schottky region through the through hole; The dielectric layer is provided between the wafer bonding barrier layer and the P-type semiconductor layer to isolate the wafer bonding barrier layer from the P-type semiconductor layer, the active layer and the reflective layer; at the cutting path of the LED chip, the dielectric layer is provided between the wafer bonding barrier layer and the passivation layer; Wafer bonding adhesive layer, bonding wafer bonding barrier layer and substrate; The back metal layer is arranged on the other side of the substrate.

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