Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a substrate; a first electrode and a second electrode on the substrate; an organic pattern layer between the first electrode and the second electrode; a light emitting element on the organic pattern layer and having a first contact electrode and a second contact electrode on a top surface; a first via layer covering the first electrode and the second electrode and covering a portion of a side surface of the light emitting element; a first lower connection electrode and a second lower connection electrode, the first lower connection electrode connecting the first electrode and the first contact electrode on the first via layer, and the second lower connection electrode connecting the second electrode and the second contact electrode; a second via layer on the first via layer and covering a portion of a side surface of the light emitting element; and a first upper connection electrode connecting the first electrode and the first contact electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0147810 filed in the Korean Intellectual Property Office on October 31, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the same. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms. The display device may be a flat panel display such as a liquid crystal display, a field emission display, a light-emitting display, etc. The light-emitting display device may include an organic light-emitting display device and a micro light-emitting display device, the organic light-emitting display device including an organic light-emitting diode (OLED) element as a light-emitting element, and the micro light-emitting display device including a micro light-emitting diode element (hereinafter referred to as a micro light-emitting element) as a light-emitting element.

[0005] When manufacturing a micro-luminescent display device, a defective bond may occur between the light emitting element and the electrode due to outgassing generated during processing of an organic layer surrounding the micro-luminescent element. Due to such a bond failure, the micro-luminescent element may not emit light. Summary of the invention

[0006] Aspects and features of embodiments of the present disclosure provide a display device and a method of manufacturing the same that can reduce or prevent a micro light emitting element from being electrically connected to a pixel electrode or a common electrode.

[0007] However, the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0008] According to one or more embodiments, a display device includes: a substrate; a first electrode and a second electrode, which are on the substrate and spaced apart from each other; an organic pattern layer, between the first electrode and the second electrode; a light-emitting element, which has a first contact electrode and a second contact electrode on the organic pattern layer and on the top surface; a first through-hole layer, which covers the first electrode and the second electrode and covers a portion of the side surface of the light-emitting element; a first lower connecting electrode and a second lower connecting electrode, the first lower connecting electrode connecting the first electrode and the first contact electrode on the first through-hole layer, and the second lower connecting electrode connecting the second electrode and the second contact electrode; a second through-hole layer, which is on the first through-hole layer and covers a portion of the side surface of the light-emitting element; and a first upper connecting electrode and a second upper connecting electrode, the first upper connecting electrode connecting the first electrode and the first contact electrode on the second through-hole layer, and the second upper connecting electrode connecting the second electrode and the second contact electrode.

[0009] In one or more embodiments, the first via layer includes a first connection hole and a second connection hole, wherein the first connection hole exposes the first electrode, and the second connection hole exposes the second electrode.

[0010] In one or more embodiments, the first lower connection electrode contacts the first electrode through the first connection hole, and the second lower connection electrode contacts the second electrode through the second connection hole.

[0011] In one or more embodiments, the second through hole layer includes a third connection hole and a fourth connection hole, the third connection hole exposing the first lower connection electrode connected to the first electrode, the fourth connection hole exposing the second lower connection electrode connected to the second electrode, and the third connection hole and the fourth connection hole are farther away from the light emitting element than the first connection hole and the second connection hole.

[0012] In one or more embodiments, the first upper connection electrode contacts the first lower connection electrode through the third connection hole, and the second upper connection electrode contacts the second lower connection electrode through the fourth connection hole.

[0013] In one or more embodiments, the first lower connection electrode is between the first contact electrode and the first upper connection electrode on the light emitting element, and the second lower connection electrode is between the second contact electrode and the second upper connection electrode on the light emitting element.

[0014] In one or more embodiments, the light emitting element includes: a third semiconductor layer on the organic pattern layer; a second semiconductor layer on the third semiconductor layer; an active layer on the second semiconductor layer; a first semiconductor layer on the active layer; and an element insulating layer around the light emitting element, wherein a first contact electrode and a second contact electrode are on the first semiconductor layer, the first contact electrode is connected to the first semiconductor layer, and the second contact electrode is connected to the second semiconductor layer.

[0015] In one or more embodiments, the first via layer is lower than the active layer.

[0016] In one or more embodiments, a height of the second via layer is equal to or higher than a height of the light emitting element.

[0017] In one or more embodiments, the second via layer includes a third connection hole overlapping the first contact electrode of the light emitting element and exposing the first lower connection electrode, and a fifth connection hole overlapping the second contact electrode and exposing the second lower connection electrode.

[0018] In one or more embodiments, the first upper connection electrode contacts the first lower connection electrode through the third connection hole, and the second upper connection electrode contacts the second lower connection electrode through the fifth connection hole.

[0019] In one or more embodiments, the first via layer includes a light shielding material.

[0020] In one or more embodiments, the first electrode and the second electrode are spaced apart from each other on the same plane and protrude outward from the light emitting element.

[0021] In one or more embodiments, the first electrode and the second electrode are spaced apart from each other by a first gap on the same plane, and the first gap is smaller than a width of the light emitting element.

[0022] In one or more embodiments, the display device further includes a reflective layer between the first electrode and the second electrode on the substrate, wherein the first electrode and the second electrode are on the same plane and are spaced apart from each other by a first gap, and the first gap is wider than a width of the light emitting element.

[0023] In one or more embodiments, the reflective layer overlaps the light emitting element, and a width of the reflective layer is greater than a width of the light emitting element.

[0024] In one or more embodiments, the width of the organic pattern layer is greater than the width of the light emitting element.

[0025] In one or more embodiments, the organic pattern layer covers a portion of the first electrode and the second electrode and fills a gap space between the first electrode and the second electrode.

[0026] According to one or more embodiments, a method for manufacturing a display device includes: preparing a substrate on which a first electrode and a second electrode are located; forming an organic pattern layer between the first electrode and the second electrode on the substrate; arranging and fixing a light-emitting element on the organic pattern layer; forming a first through-hole layer covering the light-emitting element and having a plurality of connection holes; and forming a first lower connecting electrode and a second lower connecting electrode on the first through-hole layer, the first lower connecting electrode connecting the first electrode and a first contact electrode of the light-emitting element through a plurality of connection holes, and the second lower connecting electrode connecting the second electrode and a second contact electrode of the light-emitting element; forming a second through-hole layer covering a portion of a side surface of the light-emitting element on the first through-hole layer; and forming a first upper connecting electrode and a second upper connecting electrode on the second through-hole layer, the first upper connecting electrode connecting the first electrode and the first contact electrode, and the second upper connecting electrode connecting the second electrode and the second contact electrode.

[0027] In one or more embodiments, the method also includes: forming a partition wall including a light-shielding material on the second through-hole layer; in the area separated by the partition wall, forming a first light conversion layer in the area corresponding to the first sub-pixel, forming a second light conversion layer in the area corresponding to the second sub-pixel, and forming a light-transmitting layer in the area corresponding to the third sub-pixel; and forming a first color filter on the first light conversion layer, forming a second color filter on the second light conversion layer, and forming a third color filter on the light-transmitting layer.

[0028] According to one or more embodiments, a display device includes: a substrate; a first electrode and a second electrode, which are on the substrate and spaced apart from each other; an organic pattern layer, overlapping at least a portion of the first electrode and the second electrode; a light-emitting element, which is on the organic pattern layer and has a first contact electrode and a second contact electrode on one surface; a first through-hole layer, which is on top of the first electrode and the second electrode and exposes the first contact electrode and the second contact electrode of the light-emitting element; a first lower connecting electrode and a second lower connecting electrode, the first lower connecting electrode electrically connecting the first electrode and the first contact electrode on the first through-hole layer, and the second lower connecting electrode electrically connecting the second electrode and the second contact electrode; a second through-hole layer, which is on top of the first through-hole layer; and a first upper connecting electrode and a second upper connecting electrode, the first upper connecting electrode connecting the first electrode and the first contact electrode on the second through-hole layer, and the second upper connecting electrode connecting the second electrode and the second contact electrode.

[0029] According to one or more embodiments, a display device includes: a substrate; a first electrode on the substrate; an organic pattern layer partially overlapping the first electrode; a light-emitting element on the organic pattern layer and having at least one first contact electrode on one surface; a first lower connecting electrode on the first electrode and connecting the first electrode to the first contact electrode of the light-emitting element; a first upper connecting electrode on the first electrode and including a first contact region and a second contact region, the first upper connecting electrode being connected to the first lower connecting electrode in the first contact region and the second contact region, respectively. The first electrode, the first lower connecting electrode, and the first upper connecting electrode overlap each other in the second contact region.

[0030] The display device according to one or more embodiments can reduce or minimize the possibility of disconnection between the light emitting element and the circuit electrode, thereby reducing or minimizing the defect of dark spots of pixels. In addition, light mixing between pixels can be reduced or minimized.

[0031] However, the effects, aspects, and features of the embodiments of the present disclosure are not limited to the above-mentioned effects, aspects, and features, and various other effects, aspects, and features are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0033] Figure 2 is a layout diagram illustrating a display device according to one or more embodiments.

[0034] Figure 3 is a block diagram illustrating a display device according to one or more embodiments.

[0035] Figure 4 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0036] Figure 5 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0037] Figure 6 is a diagram showing a layout of pixels of a display area according to one or more embodiments.

[0038] Figure 7 is a diagram showing the display panel and Figure 6 A cross-sectional view of an example of cross sections corresponding to lines I1 - I1 ′, I2 - I2 ′, and I3 - I3 ′.

[0039] Figure 8 It is shown in detail Figure 7 A cross-sectional view of an example of region A.

[0040] Fig. 9 It is a reference Figure 8 An enlarged view of the described light emitting element.

[0041] Fig.10 Reference Figure 7 A diagram illustrating a contact path between a first electrode and a first contact electrode in a display panel.

[0042] Fig.11 is a diagram showing the display panel and Figure 6 A sectional view of another example of the cross section corresponding to the lines I1 - I1 ′, I2 - I2 ′, and I3 - I3 ′.

[0043] Fig.12 It is shown in detail Fig.11 A cross-sectional view of an example of region B in FIG.

[0044] Fig.13 is a diagram showing the display panel and Figure 6 A sectional view of another example of the cross section corresponding to the lines I1 - I1 ′, I2 - I2 ′, and I3 - I3 ′.

[0045] Fig.14 It is shown in detail Fig.13 A cross-sectional view of an example of region C.

[0046] Fig.15 is a diagram showing the display panel and Figure 6 A sectional view of another example of the cross section corresponding to the lines I1 - I1 ′, I2 - I2 ′, and I3 - I3 ′.

[0047] Fig.16 It is shown Fig.15 A cross-sectional view of an example of region D.

[0048] Fig.17 is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments.

[0049] Figures 18 to 26 is a cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments.

[0050] Fig. 27 It is shown in detail Fig.17 Flow chart of step S110.

[0051] Figures 28 to 34 is a cross-sectional view showing step S110.

[0052] Fig.35 is an example diagram schematically showing a virtual reality device including a display device according to one or more embodiments;

[0053] Fig.36 is an example diagram schematically showing a smart device including a display device according to one or more embodiments;

[0054] Fig.37 is a diagram schematically showing an example of a vehicle including a display device according to one or more embodiments; and

[0055] Fig.38 is a diagram schematically showing an example of a transparent display device including a display device according to one or more embodiments. DETAILED DESCRIPTION

[0056] Embodiments will now be described more fully below with reference to the accompanying drawings. However, the disclosed embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals represent the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0057] In order to describe the embodiments of the present disclosure, some parts irrelevant to the description may not be provided.

[0058] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being "directly on" another element, there may be no intervening elements present.

[0059] In addition, the phrase "in a plan view" means when the object portion is observed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross section taken by vertically cutting the object portion is observed from the side. The term "overlap" or "overlapped" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. In addition, the term "overlap" may include layering, stacking, facing or facing, extending on ..., covering and / or partially covering or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include such as "spaced apart from ... " or "separated from ... " or "offset from ... " and any other suitable equivalent meaning as will be appreciated and understood by a person of ordinary skill in the art. The term "face (face)" and "facing (facing)" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, but still facing each other.

[0060] For ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper" may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatially relative terms are intended to include different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is flipped, a device positioned "below" or "below" another device may be placed "above" the other device. Therefore, the illustrative term "below" may include both the lower position and the upper position. The device may also be oriented in other directions, and therefore the spatially relative terms may be interpreted differently depending on the orientation.

[0061] When an element is referred to as being "connected" or "coupled" to another element, the element may be "directly connected" or "directly coupled" to the other element, or "electrically connected" or "electrically coupled" to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms "comprises," "comprising," "having," "having," "having," "including," and / or "comprising" are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not preclude the presence or addition of other features, integers, steps, operations, elements, parts, and / or any combination thereof.

[0062] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or for the convenience of description and explanation. For example, without departing from the teachings of this article, when discussing a "first element" in the description, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be named in a similar manner.

[0063] In view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0064] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0065] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this specification.

[0066] Hereinafter, one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0067] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0068] refer to Figure 1 The display device 10 is a device for displaying video and / or still images, such as a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation and / or an ultra mobile PC (UMPC), and a display screen for various products such as a television, a laptop computer, a monitor, a billboard and / or an Internet of Things (IOT) device.

[0069] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a miniaturized light-emitting display device using a micro light-emitting diode or a nano light-emitting diode (micro-LED or nano-LED). Hereinafter, the description focuses on the fact that the display device 10 is a micro light-emitting display device, but the present disclosure is not limited thereto. On the other hand, for ease of explanation, a micro light-emitting diode is hereinafter referred to as a light-emitting element.

[0070] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply circuit 500 (see, for example, Figure 3 ).

[0071] The display panel 100 may be formed as a rectangular plane having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. The corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a desired curvature (e.g., a predetermined curvature), or may be formed at right angles. The planar shape of the display panel 100 is not limited to a rectangle, and may be formed as other polygons, a circle, or an ellipse. The display panel 100 may be formed to be flat, but is not limited thereto. For example, the display panel 100 is formed at the left and right ends, and may include a curved portion having a constant curvature or a varying curvature. In addition, the display panel 100 may be formed to be flexible so as to be able to be bent, curved, folded, and / or curled.

[0072] The substrate SUB (eg, Figure 7 ) may include a main area MA and a sub-area SBA.

[0073] The main area MA may include a display area DA displaying an image and a non-display area NDA, which is a peripheral area of ​​the display area DA and is around the display area DA along an edge or periphery of the display area DA (e.g., surrounding the display area DA). The display area DA may include a plurality of pixels displaying an image. For example, a pixel may include a first sub-pixel emitting a first light, a second sub-pixel emitting a second light, and a third sub-pixel emitting a third light.

[0074] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. Figure 1 The sub-region SBA is shown to be unfolded, but the sub-region SBA may be bent, and in this case, the sub-region SBA may be disposed on the bottom surface of the display panel 100. When the sub-region SBA is bent, it may overlap the main region MA in the third direction DR3 which is the thickness direction of the display panel 100. The display driving circuit 250 may be disposed in the sub-region SBA.

[0075] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC) and attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 using a chip on film (COF) method.

[0076] The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. In this way, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, a timing signal, and / or a driving voltage through the circuit board 300. The circuit board 300 may be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on a film.

[0077] The power supply circuit 500 (eg, Figure 3 ) can generate a plurality of panel driving voltages according to an external power supply voltage. The power supply circuit 500 can be formed as an integrated circuit (IC) and attached to the circuit board 300 using a COF method.

[0078] Figure 2 is a layout diagram illustrating a display device according to one or more embodiments. Figure 2 The sub-area SBA is shown unfolded without bending.

[0079] refer to Figure 2 , the display panel 100 may include a main area MA and a sub-area SBA.

[0080] The main area MA may include a display area DA displaying an image and a non-display area NDA as a peripheral area of ​​the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be placed in the center of the main area MA.

[0081] The display area DA may include a plurality of pixels PX for displaying an image, and each of the plurality of pixels PX may include a plurality of sub-pixels SPX. The pixel PX may be defined as a sub-pixel group that is a minimum unit capable of representing a white grayscale.

[0082] The non-display area NDA may be placed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be arranged around the display area DA (e.g., surrounding the display area DA). The non-display area NDA may be an edge area of ​​the display panel 100.

[0083] The first scan driving unit SDC1 and the second scan driving unit SDC2 may be disposed in the non-display area NDA. The first scan driving unit SDC1 is disposed on one side (e.g., the left side) of the display panel 100, and the second scan driving unit SDC2 is disposed on the other side (e.g., the right side) of the display panel 100. However, the first scan driving unit SDC1 and the second scan driving unit SDC2 are not limited thereto. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may receive a scan control signal from the display driving circuit 250, generate a scan signal according to the scan control signal, and output the scan signal to the scan line.

[0084] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be less than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and may be disposed at a lower portion of the display panel 100. In this case, the sub-region SBA may overlap the main region MA in the third direction DR3.

[0085] The sub-area SBA may include a connection area CA, a pad area PA, and a bending area BA.

[0086] The connection area CA is an area protruding from one side of the main area MA in the second direction DR2. One side of the connection area CA may contact the non-display area NDA of the main area MA, and the other side of the connection area CA may contact the bending area BA.

[0087] The pad area PA is an area where the pad PD and the display driving circuit 250 are disposed. The display driving circuit 250 may be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA may be in contact with the bending area BA.

[0088] The bending area BA is a bent area. When the bending area BA is bent, the pad area PA may be disposed below the connection area CA and below the main area MA. The bending area BA may be disposed between the connection area CA and the pad area PA. One side of the bending area BA may contact the connection area CA, and the other side of the bending area BA may contact the pad area PA.

[0089] Figure 3 is a block diagram illustrating a display device according to one or more embodiments.

[0090] refer to Figure 3 , the display area DA includes a plurality of pixels PX, a plurality of scan lines SL (eg, GWL, GCL, GIL, GBL), a plurality of emission control lines EL, and a plurality of data lines DL.

[0091] A plurality of pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 and may be arranged along the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and may be arranged along the first direction DR1. The plurality of scan lines SL may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, a plurality of initialization scan lines GIL, and a plurality of bias scan lines GBL.

[0092] Each of the plurality of sub-pixels SPX may be connected to a write scan line GWL from among a plurality of write scan lines GWL, a control scan line GCL from among a plurality of control scan lines GCL, an initialization scan line GIL from among a plurality of initialization scan lines GIL, a bias scan line GBL from among a plurality of bias scan lines GBL, an emission control line EL from among a plurality of emission control lines EL, and a data line DL from among a plurality of data lines DL. Each of the plurality of sub-pixels SPX may be provided with a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and may emit light through a light emitting element according to the data voltage.

[0093] The non-display area NDA includes a first scan driving unit SDC1 , a second scan driving unit SDC2 , and a display driving circuit 250 .

[0094] Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may include a write scan signal output unit 611, a control scan signal output unit 612, an initialization scan signal output unit 613, a bias scan signal output unit 614, and a light emitting signal output unit 615. Each of the write scan signal output unit 611, the control scan signal output unit 612, the initialization scan signal output unit 613, the bias scan signal output unit 614, and the light emitting signal output unit 615 may receive a scan timing control signal SCS from the timing control circuit 251. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 251, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The initialization scan signal output unit 613 may generate an initialization scan signal according to the scan timing control signal SCS, and sequentially output the initialization scan signal to the initialization scan line GIL. The bias scan signal output unit 614 can generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL. The light emission signal output unit 615 can generate a light emission control signal according to the scan timing control signal SCS, and sequentially output the light emission control signal to the emission control line EL.

[0095] The display driving circuit 250 includes a timing control circuit 251 and a data driving circuit 252 .

[0096] The data driving circuit 252 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixel SPX is selected by the write scan signal of the first scan driving unit SDC1 and the second scan driving unit SDC2, and the analog data voltage may be provided to the selected sub-pixel SPX.

[0097] The timing control circuit 251 may receive digital video data DATA and a timing signal from an external source. The timing control circuit 251 may generate a scan timing control signal SCS and a data timing control signal DCS according to the timing signal to control the display panel 100. The timing control circuit 251 may output the scan timing control signal SCS to the first scan driving unit SDC1 and the second scan driving unit SDC2. The timing control circuit 251 may output the digital video data DATA and the data timing control signal DCS to the data driving circuit 252.

[0098] The power supply circuit 500 may generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply circuit 500 may generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT and provide them to the display panel 100.

[0099] Figure 4 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0100] refer to Figure 4 , the first subpixel SPX1 according to one or more embodiments may be connected to the scan lines GWL, GIL, GCL and GBL, the emission control line EL and the data line DL. For example, the first subpixel SPX1 may be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission control line EL and the data line DL.

[0101] The first subpixel SPX1 according to one embodiment includes a driving transistor DT, a switching element, a capacitor C1 and a first light emitting element LE1. The switching element includes first, second, third, fourth, fifth, and sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0102] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current Ids (hereinafter referred to as a "driving current") flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0103] The first light emitting element LE1 may be a micro light emitting diode.

[0104] The first light emitting element LE1 emits light according to the driving current Ids. The amount of light emitted from the first light emitting element LE1 may be proportional to the driving current Ids. The anode electrode of the first light emitting element LE1 may be connected in parallel to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6 through the first contact path PH1 and the second contact path PH2, and the cathode electrode may be connected in parallel to the second power line VSL to which the second power supply voltage is applied through the third path PH3 and the fourth path PH4. Figures 8 to 10 Describe the parallel connection of the anode electrode and the cathode electrode. Figures 8 to 10 The first contact electrode CTE1 of the first light emitting element LE1 shown in FIG. 8 is an anode electrode, and the second contact electrode CTE2 of the second light emitting element LE2 is a cathode electrode.

[0105] The capacitor C1 is formed between the gate electrode of the driving transistor DT and the first power line VDL to which the first power voltage is applied. The first power voltage may be at a higher level than the second power voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the first power line VDL.

[0106] like Figure 4 As shown in , the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may all be formed as p-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may be formed of polysilicon or an oxide semiconductor.

[0107] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. The gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 may be connected to the emission control line EL. Because the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, they may be turned on when the scan signal of the gate low voltage and the emission signal are applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission control line EL, respectively. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0108] The first electrode of the first transistor ST1 may be connected to the second electrode of the driving transistor DT, and the second electrode of the first transistor ST1 may be connected to the gate electrode of the driving transistor DT. Therefore, when the first transistor ST1 is turned on, the driving transistor DT may be diode-connected. The first electrode of the second transistor ST2 may be connected to the data line DL, and the second electrode of the second transistor ST2 may be connected to the first electrode of the driving transistor DT. The first electrode of the third transistor ST3 may be connected to the gate electrode of the driving transistor DT, and the second electrode of the third transistor ST3 may be connected to the initialization voltage line VIL. The first electrode of the fourth transistor ST4 may be connected to the second electrode of the sixth transistor ST6, and the second electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL. The first electrode of the fifth transistor ST5 may be connected to the first power line VDL, and the second electrode of the fifth transistor ST5 may be connected to the first electrode of the driving transistor DT. The first electrode of the sixth transistor ST6 may be connected to the second electrode of the driving transistor DT, and the second electrode of the sixth transistor ST6 may be connected to the anode electrode of the first light emitting element LE1.

[0109] In addition, the first light emitting element LE1 may be connected in parallel to each of the anode electrode and the cathode electrode to improve reliability.

[0110] Figure 5 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0111] refer to Figure 5 , the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 may be formed as n-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as p-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as n-type MOSFETs may be formed of an oxide semiconductor. In this case, the transistor formed of polysilicon and the transistor formed of an oxide semiconductor may be arranged in different layers.

[0112] Because the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can be turned on when a control scan signal with a gate high voltage is applied to the control scan line GCL, and the third transistor ST3 can be turned on when an initialization scan signal with a gate high voltage is applied to the initialization scan line GIL. In contrast, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, so when a scan signal with a gate low voltage and an emission signal are applied to the write scan line GWL, the bias scan line GBL, and the emission control line EL, respectively, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be turned on.

[0113] Optionally, Figure 5 The fourth transistor ST4 in the embodiment may be formed by an n-type MOSFET. In this case, the active layer of each fourth transistor ST4 may be formed by an oxide semiconductor. When the fourth transistor ST4 is formed by an n-type MOSFET, the fourth transistor ST4 may be turned on when a bias scan signal of a gate high voltage is applied to the bias scan line GBL.

[0114] Optionally, although not in Figure 4 and Figure 5 , but the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5 and the sixth transistor ST6 and the driving transistor DT may all be formed as n-type MOSFETs.

[0115] In one or more embodiments, the circuit diagrams of the second sub-pixel and the third sub-pixel according to one or more embodiments are substantially the same as those in the combination Figure 4 and Figure 5 The circuit diagram of the first sub-pixel SPX1 described is the same, so the description thereof will be omitted.

[0116] Figure 6 is a diagram showing a layout of pixels of a display area according to one or more embodiments.

[0117] refer to Figure 6 , each of the plurality of pixels PX in the display area DA may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 .

[0118] The plurality of pixels PX may be arranged in a matrix form. In each of the plurality of pixels PX, a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 may be arranged along a first direction DR1.

[0119] The first subpixel SPX1 may emit light of a first color, the second subpixel SPX2 may emit light of a second color, and the third subpixel SPX3 may emit light of a third color. Here, the first color light may be light in a blue wavelength band, the second color light may be light in a green wavelength band, and the third color light may be light in a red wavelength band. For example, the blue wavelength band may indicate that the main peak wavelength of light is included in a wavelength band of approximately 370 μm to 460 μm, the green wavelength band may indicate that the main peak wavelength of light is included in a wavelength band of approximately 480 μm to 560 μm, and the red wavelength band may indicate that the main peak wavelength of light is included in a wavelength band of approximately 600 μm to 750 μm.

[0120] The first subpixel SPX1 includes a first electrode APD, a first light emitting element LE1, a second electrode CPD, a first connection hole CT1, a second connection hole CT2, and a first light conversion layer WCL1. The second subpixel SPX2 includes a first electrode APD, a second light emitting element LE2, a second electrode CPD, a first connection hole CT1, a second connection hole CT2, and a second light conversion layer WCL2. The third subpixel SPX3 includes a first electrode APD, a third light emitting element LE3, a second electrode CPD, a first connection hole CT1, a second connection hole CT2, and a light-transmitting layer TPL.

[0121] The first electrode APD and the second electrode CPD may be arranged to be spaced apart from each other. Each of the first electrode APD and the second electrode CPD may have a rectangular planar shape. The first electrode APD and the second electrode CPD may have substantially the same area, but the present disclosure is not limited thereto.

[0122] In one or more embodiments, the area of ​​the first subpixel SPX1, the area of ​​the second subpixel SPX2, and the area of ​​the third subpixel SPX3 are illustrated as being equal, but are not limited thereto. For example, the area of ​​the first subpixel SPX1, the area of ​​the second subpixel SPX2, and the area of ​​the third subpixel SPX3 may be set differently according to the light conversion efficiency of the first light conversion layer WCL1 and the light conversion efficiency of the second light conversion layer WCL2.

[0123] The area of ​​the first electrode APD may be the same as the area of ​​the second electrode CPD, but the present disclosure is not limited thereto.

[0124] The first electrode APD may be electrically connected to the fourth transistors ( CT1 ) of the corresponding sub-pixels SPX1 , SPX2 , and SPX3 through the first connection hole CT1 . Figure 4 and Figure 5 The second electrode of the fourth transistor ST4) and the sixth transistor ( Figure 4 and Figure 5 A second electrode of the sixth transistor ST6 in FIG.

[0125] The second electrode CPD may be connected to the second power line VSL to which the second driving voltage VSS is applied through the second connection hole CT2. Therefore, the second driving voltage VSS may be applied to the second electrode CPD.

[0126] The plurality of light emitting elements LE may emit third light, ie, light in a blue wavelength band.

[0127] The first light conversion layer WCL1 may completely overlap the first light emitting element LE1 of the first sub-pixel SPX1. The area of ​​the first light conversion layer WCL1 is greater than the area of ​​the first light emitting element LE1. The first light conversion layer WCL1 may convert or transform the peak wavelength of the incident light into light of another specific peak wavelength and emit the light. For example, the first light conversion layer WCL1 may convert or transform the third light emitted from the plurality of first light emitting elements LE1 of the first sub-pixel SPX1 into the first light.

[0128] The second light conversion layer WCL2 may completely overlap with the second light emitting element LE2 of the second sub-pixel SPX2. The area of ​​the second light conversion layer WCL2 may be greater than the area of ​​the second light emitting element LE2. The second light conversion layer WCL2 may convert or transform the peak wavelength of the incident light into light of another specific peak wavelength and emit the light. For example, the second light conversion layer WCL2 may convert or transform the third light emitted from the second light emitting element LE2 of the second sub-pixel SPX2 into the second light.

[0129] The light-transmitting layer TPL may completely overlap the third light-emitting element LE3 of the third sub-pixel SPX3. The light-transmitting layer TPL may transmit incident light as it is. For example, the light-transmitting layer TPL may transmit the third light emitted from the third light-emitting element LE3 of the third sub-pixel SPX3 as it is.

[0130] The first connection hole CT1 may be where the first electrode APD is connected to Figure 7 The fourth source connection electrode SBE4 is electrically connected to the first thin film transistor ( Figure 7 The first connection hole CT1 may overlap the first electrode APD.

[0131] The second connection hole CT2 may be a region in which the second electrode CPD is connected to the second power line VSL. The second connection hole CT2 may overlap the second electrode CPD and the second power line VSL.

[0132] Each of the second power supply lines VSL may be electrically connected to a Figure 2Each of the second power lines VSL may include a wiring portion WP extending in the first direction DR1 and a protrusion portion PP protruding from the wiring portion WP in the second direction DR2 and overlapping the second connection hole CT2.

[0133] However, the present disclosure is not limited thereto, and each of the plurality of pixels PX may include four sub-pixels including a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, and the second sub-pixel and the fourth sub-pixel may emit light of the same color. For example, the first sub-pixel may emit a first red light, the second sub-pixel may emit a second green light, the third sub-pixel may emit a blue light, and the fourth sub-pixel may emit a green light. If the pixel PX includes four sub-pixels, the first sub-pixel and the second sub-pixel may be arranged along the first direction DR1, the first sub-pixel and the third sub-pixel may be arranged along the second direction DR2, and the second sub-pixel and the fourth sub-pixel may be arranged along the second direction DR2.

[0134] Figure 7 is a diagram showing the display panel and Figure 6 A cross-sectional view of an example of cross sections corresponding to lines I1 - I1 ′, I2 - I2 ′, and I3 - I3 ′. Figure 8 It is shown in detail Figure 7 A cross-sectional view of an example of region A. Fig. 9 It is a reference Figure 8 An enlarged view of a light emitting element LE is depicted.

[0135] refer to Figure 7 and Figure 8 , the substrate SUB may be made of an insulating material such as glass, polymer resin, etc. If the substrate SUB is made of a polymer resin, the substrate SUB may be a flexible substrate that can be stretched. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0136] The barrier film BR may be disposed on the substrate SUB. The barrier film BR is a film-like object for protecting the transistors of the thin film transistor layer TFTL and the light emitting element layer EML from moisture penetrating through the substrate SUB susceptible to moisture penetration. The barrier film BR may be composed of a plurality of inorganic films stacked alternately. For example, the barrier film BR may be formed as a multilayer alternating inorganic film of one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0137] The first thin film transistor TFT1 may be disposed on the blocking film BR. The first thin film transistor TFT1 may be Figure 5The fourth transistor ST4 or the sixth transistor ST6 shown in FIG. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0138] The first active layer ACT1 of the first thin film transistor TFT1 may be disposed on the barrier film BR. The first active layer ACT1 of the first thin film transistor TFT1 may include polycrystalline silicon, single crystalline silicon, low temperature polycrystalline silicon, and / or amorphous silicon.

[0139] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region overlapping with the first gate electrode G1 in a third direction DR3 that is a thickness direction of the substrate SUB. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 may be regions in which a silicon semiconductor is doped with ions to make it conductive.

[0140] The first gate insulating layer 131 may be disposed on the first channel region CHA1, the first source region S1, the first drain region D1 of the first thin film transistor TFT1, and the barrier film BR. The first gate insulating layer 131 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0141] The first gate metal layer may be disposed on the first gate insulating layer 131. The first gate metal layer may include a first gate electrode G1 of the first thin film transistor TFT1 and a first capacitor electrode CAE1. The first gate electrode G1 may overlap the first active layer ACT1 in the third direction DR3. Figure 7 , the first gate electrode G1 and the first capacitor electrode CAE1 are shown to be spaced apart from each other, but the first gate electrode G1 and the first capacitor electrode CAE1 may be connected to each other. The first gate metal layer may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof.

[0142] The second gate insulating layer 132 may be disposed on the first gate electrode G1 of the first thin film transistor TFT1, the first capacitor electrode CAE1, and the first gate insulating layer 131. The second gate insulating layer 132 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0143] The second gate metal layer may be disposed on the second gate insulating layer 132. The second gate metal layer may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap the first capacitor electrode CAE1 in the third direction DR3. Since the second gate insulating layer 132 has a suitable dielectric constant (eg, a predetermined dielectric constant), the capacitor ( Figure 5 The capacitor C1 in the embodiment may be formed by a first capacitor electrode CAE1, a second capacitor electrode CAE2, and a second gate insulating layer 132 disposed between the first capacitor electrode CAE1 and the second capacitor electrode CAE2. The second gate metal layer may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof.

[0144] The first interlayer insulating film 141 may be disposed on the second capacitor electrode CAE2 and the second gate insulating layer 132. The first interlayer insulating film 141 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0145] The second thin film transistor TFT2 may be disposed on the first interlayer insulating film 141. The second thin film transistor TFT2 may be Figure 5 The first transistor ST1 or the third transistor ST3 shown in FIG. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2.

[0146] The second active layer ACT2 of the second thin film transistor TFT2 may be disposed on the first interlayer insulating film 141. The second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) and / or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0147] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region overlapping with the second gate electrode G2 in the third direction DR3. The second source region S2 may be disposed on one side of the second channel region CHA2, and the second drain region D2 may be disposed on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions that do not overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 and the second drain region D2 may be regions in which the oxide semiconductor is doped with ions to make it conductive.

[0148] The third gate insulating layer 133 may be disposed on the second active layer ACT2 of the second thin film transistor TFT2 and the first interlayer insulating film 141. The third gate insulating layer 133 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0149] The third gate metal layer may be disposed on the third gate insulating layer 133. The third gate metal layer may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap the second active layer ACT2 in the third direction DR3. The third gate metal layer may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or an alloy thereof.

[0150] The second interlayer insulating film 142 may be disposed on the second gate electrode G2 of the second thin film transistor TFT2 and the third gate insulating layer 133. The second interlayer insulating film 142 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0151] The first data metal layer may be disposed on the second interlayer insulating film 142. The first data metal layer may include a first source connection electrode SBE3, a second source connection electrode SBE1, and a third source connection electrode SBE2. The first source connection electrode SBE3 may be connected to the first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 penetrating the first gate insulating layer 131, the second gate insulating layer 132, the first interlayer insulating film 141, the third gate insulating layer 133, and the second interlayer insulating film 142. The second source connection electrode SBE1 may be connected to the second source region S2 of the second active layer ACT2 through a second source connection contact hole BCT1 penetrating the second interlayer insulating film 142 and the third gate insulating layer 133. The third source connection electrode SBE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third source connection contact hole BCT2 penetrating the second interlayer insulating film 142 and the third gate insulating layer 133. The first data metal layer may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof. For example, the first data metal layer may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and / or a third layer made of titanium (Ti).

[0152] The first organic film 160 may be provided to planarize a step caused by the first thin film transistor TFT1 and the second thin film transistor TFT2 on the first source connection electrode SBE3, the second source connection electrode SBE1, and the third source connection electrode SBE2 and the second interlayer insulating film 142. The first organic film 160 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0153] The second data metal layer may be disposed on the first organic film 160. The second data metal layer may include a fourth source connection electrode SBE4 and a second power supply line VSL. The fourth source connection electrode SBE4 may be connected to the first source connection electrode SBE3 through a second pixel contact hole PCT2 penetrating the first organic film 160. The second data metal layer may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or an alloy thereof. For example, the second data metal layer may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and / or a third layer made of titanium (Ti).

[0154] The second organic layer 180 may be disposed on the fourth source connection electrode SBE4, the second power line VSL, and the first organic film 160. The second organic layer 180 may be formed of an organic film such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0155] The light emitting element layer EML may be disposed on the second organic layer 180. The light emitting element layer EML may include a first electrode APD, a second electrode CPD, an organic pattern layer BOL, light emitting elements LE1, LE2, and LE3, a first via layer VIA1, a second via layer VIA2, a lower connection electrode BE1, and an upper connection electrode BE2.

[0156] The first electrode APD and the second electrode CPD may be disposed on the second organic layer 180 to be spaced apart from each other. Each sub-pixel SPX1, SPX2, and SPX3 may include a pair of the first electrode APD and the second electrode CPD. The first electrode APD of each sub-pixel SPX1, SPX2, and SPX3 may be connected to the second organic layer 180 through a corresponding first connection hole CT1 ( Figure 6 The first connection hole CT1 in the source electrode is connected to the fourth source connection electrode SBE4.

[0157] In the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3, the first electrode APD may be connected to the first source region S1 or the first drain region D1 of the first thin film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, a voltage controlled by the first thin film transistor TFT1 in each of the subpixels SPX1, SPX2, and SPX3 may be applied to the first electrode APD. The first electrode APD may be an anode electrode.

[0158] The second electrode CPD can be formed by a second connection hole CT2 ( Figure 6 The second connection hole CT2 in the second electrode CPD is connected to the second power line VSL. Therefore, the second driving voltage VSS can be applied to the second electrode CPD. The second electrode CPD can be a cathode electrode.

[0159] The first electrode APD and the second electrode CPD may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) and / or alloys thereof. In one or more embodiments, the first electrode APD and the second electrode CPD may have a two-layer structure of titanium (Ti) / aluminum (Al) or titanium (Ti) / copper (Cu), and / or may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) and / or titanium (Ti) / copper (Cu).

[0160] The first electrode APD and the second electrode CPD may be spaced apart from each other on the same plane and may be arranged to protrude outward from the light emitting element LE. The first electrode APD and the second electrode CPD may be spaced apart from each other by a first separation distance D1. The first separation distance D1 may be less than a width of the light emitting element LE. The first separation distance D1 may be about 4 μm to 6 μm.

[0161] The organic pattern layer BOL is disposed between the first electrode APD and the second electrode CPD, and may cover the edges of the first electrode APD and the second electrode CPD. The organic pattern layer BOL is used to temporarily fix or adhere the plurality of light emitting elements LE to prevent the plurality of light emitting elements LE from tilting or tipping over in the process of transferring the light emitting elements LE to the display panel 100. That is, the organic pattern layer BOL may be a layer for temporarily adhering the light emitting element LE to the first electrode APD and the second electrode CPD. To facilitate temporary adhesion, the thickness of the organic pattern layer BOL may be greater than the thickness of each of the first electrode APD and the second electrode CPD, but is not limited thereto. After the transfer process of the light emitting element LE is completed, the organic pattern layer BOL may be cured, etc., to produce a strong bond between the light emitting element LE and the organic pattern layer BOL. Unlike conventional (eutectic) bonding processes, the bonding process using the organic pattern layer BOL does not require heat and pressure to damage the light emitting element LE, so it has the effect of preventing defects in the light emitting element LE.

[0162] The organic pattern layer BOL may be an insulating material without electrical connection. In addition, the organic pattern layer BOL may be a photosensitive organic film such as photoresist. Alternatively, the organic pattern layer BOL may be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0163] The detailed description of the organic pattern layer BOL will be referred to later. Figures 17 to 25 This is described in the method of manufacturing the display device 10 .

[0164] The light emitting element LE may be disposed on the organic pattern layer BOL in the opening OA of the first through hole layer VIA1. The light emitting element LE may be a flip-chip micro LED. The flip-chip micro LED refers to an LED in which contact electrodes CTE1 and CTE2 are formed on one surface (e.g., top surface) of the light emitting element LE (e.g., LE: LE1, LE2, LE3).

[0165] Each of the plurality of light emitting elements LE may be formed of an inorganic material such as gallium nitride (GaN).

[0166] Each of the plurality of light emitting elements LE may be formed by growing on a semiconductor substrate such as a silicon substrate and / or a sapphire substrate. The plurality of light emitting elements LE may be directly transferred from the semiconductor substrate to the electrodes APD and CPD of the display panel 100. Alternatively, the plurality of light emitting elements LE may be transferred to the electrodes APD and CPD of the display panel 100 by an electrostatic method using an electrostatic head or by a stamp method using an elastic polymer material such as PDMS and / or silicone as a transfer substrate.

[0167] refer to Fig. 9 , the light emitting element LE may be a light emitting structure including a third semiconductor layer SEM3, a second semiconductor layer SEM2, an active layer MQW, a first semiconductor layer SEM1, a transparent conductive layer TCO, a first contact electrode CTE1, a second contact electrode CTE2 and an element insulating layer INS0. Fig. 9 , shows a flip-chip light emitting element LE in which the first contact electrode CTE1 and the second contact electrode CTE2 are disposed on one side of the light emitting element LE, but is not limited thereto, and a vertical light emitting element LE may also be used. The third semiconductor layer SEM3 may include an undoped semiconductor, and may be a material that is not doped to an n-type or p-type. In one or more embodiments, the third semiconductor layer SEM3 may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and / or InN, but is not limited thereto.

[0168] The second semiconductor layer SEM2 may be disposed on the third semiconductor layer SEM3. The second semiconductor layer SEM2 may be doped with a second conductive dopant such as Si, Ge, Sn, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may be approximately 500 nm to 1 μm.

[0169] The active layer MQW may be disposed on the second semiconductor layer SEM2. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light having a central wavelength range of 450 nm to 495 nm, that is, light in a blue wavelength band.

[0170] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN and / or AlGaN, but is not limited thereto. The thickness of the well layer may be approximately 1 nm to 4 nm, and the thickness of the barrier layer may be approximately 3 nm to 10 nm.

[0171] Alternatively, the active layer MQW may have a structure in which a semiconductor material having a high energy band gap and a semiconductor material having a low band gap energy are alternately stacked with each other, and other group III to group V semiconductor materials may be included according to the wavelength range of the emitted light. The light emitted from the active layer MQW is not limited to the first light (e.g., light in a blue wavelength band), and in some cases, the second light (e.g., light in a green wavelength band) or the third light (e.g., light in a red wavelength band) may be emitted. The thickness of the active layer MQW may be approximately 10 nm to 25 nm.

[0172] The first semiconductor layer SEM1 may be doped with a first conductive dopant such as Mg, Zn, Ca, and / or Ba. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The thickness of the first semiconductor layer SEM1 may be approximately 30 nm to 200 nm.

[0173] In one or more embodiments, a superlattice layer may be further included between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. The superlattice layer may be formed of InGaN and / or GaN. In addition, an electron blocking layer may be further included between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be a layer that suppresses or prevents too many electrons from flowing into the active layer MQW. For example, the electron blocking layer may be p-AlGaN doped with p-type Mg. The thickness of the electron blocking layer may be approximately 10nm to 50nm. The electron blocking layer may be omitted.

[0174] The transparent conductive layer TCO may be disposed on the first semiconductor layer SEM1. The transparent conductive layer TCO may be in direct contact with the first semiconductor layer SEM1. The transparent conductive layer TCO may be transparently formed to emit light. The transparent conductive layer TCO may be formed of a transparent conductive oxide such as indium tin oxide (ITO) and / or indium zinc oxide (IZO). The transparent conductive layer TCO may be omitted.

[0175] The element insulating layer INS0 may be formed to wrap the side surfaces of the third semiconductor layer SEM3, the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1, and the transparent conductive layer TCO, and the top surface of the transparent conductive layer TCO. The element insulating layer INS0 has two openings. For example, the element insulating layer INS0 includes a first opening OP-L1 and a second opening OP-L2. The element insulating layer INS0 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0176] The first contact electrode CTE1 and the second contact electrode CTE2 are disposed on the two openings. For example, the first contact electrode CTE1 may be disposed on the first opening OP-L1 and contact the first semiconductor layer SEM1 via the transparent conductive layer TCO. The second contact electrode CTE2 may be disposed on the second opening OP-L2 and contact the second semiconductor layer SEM2. To this end, the second opening OP-L2 may expose the second semiconductor layer SEM2. The second opening OP-L2 may have a diameter wider than the first opening OP-L1.

[0177] The element insulating layer INS0 may be disposed to cover the side surface of the groove defined by the second opening OP-L2.

[0178] Because the first contact electrode CTE1 and the second contact electrode CTE2 are disposed on the top surface of the light emitting element LE, they may be transparent electrodes. For example, the first contact electrode CTE1 and the second contact electrode CTE2 may be formed of a transparent conductive oxide such as indium tin oxide (ITO) and / or indium zinc oxide (IZO). However, it is not limited thereto, and in one or more embodiments, the first contact electrode CTE1 and the second contact electrode CTE2 may be disposed on the lower surface of the light emitting element LE. When the first contact electrode CTE1 and the second contact electrode CTE2 are disposed on the lower surface of the light emitting element LE, the first contact electrode CTE1 and the second contact electrode CTE2 of the light emitting element LE may be formed as a single layer or multiple layers of a material selected from the group consisting of Ti, Cr, Al, Cu and Au and a transparent conductive oxide. In one or more embodiments, the light emitting element LE may be a vertical light emitting element LE in which the first contact electrode CTE1 is disposed on the upper surface of the light emitting element LE and the second contact electrode CTE2 is disposed on the lower surface of the light emitting element LE. When a vertical light emitting element LE is adopted, a connection structure may be added or deleted to match the electrode structure according to the structure of the light emitting element LE. Referring again to Figure 7 and Figure 8 , the first via layer VIA1 supports the lower connection electrode BE1 and planarizes the step formed by the light emitting element LE.

[0179] The first through hole layer VIA1 may include a plurality of connection holes CH1 and CH2. For example, the first through hole layer VIA1 may include a first connection hole CH1 formed on the first electrode APD and a second connection hole CH2 formed on the second electrode CPD. The first connection hole CH1 exposes the first electrode APD of the light emitting element LE, and the second connection hole CH2 exposes the second electrode CPD of the light emitting element LE. The first through hole layer VIA1 may include a first flat portion VIA1-1 disposed between the light emitting element LE and the connection holes CH1 and CH2, and a second flat portion VIA1-2 disposed on a side away from the light emitting element LE relative to the second connection hole CH2.

[0180] The lower connection electrode BE1 may include a first lower connection electrode BE1-1 and a second lower connection electrode BE1-2. The first lower connection electrode BE1-1 connects the first contact electrode CTE1 with the first electrode APD, and the second lower connection electrode BE1-2 connects the second contact electrode CTE2 with the second electrode CPD. The first lower connection electrode BE1-1 and the second lower connection electrode BE1-2 are spaced apart from each other at the top of the light emitting element LE.

[0181] The first lower connection electrode BE1 - 1 connects the first contact electrode CTE1 and the first electrode APD through the first connection hole CH1 .

[0182] The first lower connection electrode BE1-1 may include a first lower connection portion BE1-11 and a second lower connection portion BE1-12. The first lower connection portion BE1-11 and the second lower connection portion BE1-12 are connected to each other. In one or more embodiments, the first lower connection portion BE1-11 and the second lower connection portion BE1-12 may be formed integrally with each other. The first lower connection portion BE1-11 may be disposed so that it contacts the first contact electrode CTE1 and extends along the side of the first light emitting element LE1 and the first flat portion VIA1-1 to the first electrode APD exposed by the first connection hole CH1. The second lower connection portion BE1-12 may be disposed so as to extend from the first electrode APD exposed by the first connection hole CH1 to the second flat portion VIA1-2.

[0183] The second lower connection electrode BE1-2 is connected to the second contact electrode CTE2 and the second electrode CPD through the second connection hole CH2.

[0184] The second lower connection electrode BE1-2 may include a first lower connection portion BE1-21 and a second lower connection portion BE1-22. The first lower connection portion BE1-21 and the second lower connection portion BE1-22 are connected to each other. The first lower connection portion BE1-21 may be arranged to extend from the second contact electrode CTE2 along the side of the first light emitting element LE1 along the first flat portion VIA1-1 to the second electrode CPD exposed by the second connection hole CH2. The second lower connection portion BE1-22 may be arranged to extend from the second electrode CPD exposed by the second connection hole CH2 along the second flat portion VIA1-2. The first through-hole layer VIA1 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The height of the first through-hole layer VIA1 may be formed to be lower than the height of the light emitting element LE. The height of the first through-hole layer VIA1 may be less than the height of the active layer MQW.

[0185] The second via layer VIA2 is provided on the first via layer VIA1. The second via layer VIA2 supports the upper connection electrode BE2 and planarizes the step formed by the light emitting element LE.

[0186] The upper connection electrode BE2 may include a first upper connection electrode BE2-1 and a second upper connection electrode BE2-2. The first upper connection electrode BE2-1 connects the first contact electrode CTE1 to the second lower connection portion BE1-12, and the second upper connection electrode BE2-2 connects the second contact electrode CTE2 to the second lower connection portion BE1-22. The first upper connection electrode BE2-1 and the second upper connection electrode BE2-2 are spaced apart from each other at the top of the light emitting element LE.

[0187] The second through hole layer VIA2 may include a plurality of connection holes CH3, CH4, CH5, and CH6. For example, the second through hole layer VIA2 may include a third connection hole CH3 and a fifth connection hole CH5 formed on the first light emitting element LE1, a fourth connection hole CH4 formed on the second lower connection portion BE1-12, and a sixth connection hole CH6 formed on the second lower connection portion BE1-22. The third connection hole CH3 exposes the first lower connection electrode BE1-1 in contact with the first contact electrode CTE1. The fourth connection hole CH4 exposes the second lower connection portion BE1-12 connected to the first electrode APD. The fifth connection hole CH5 exposes the second lower connection electrode BE1-2 in contact with the second contact electrode CTE2.

[0188] The second through hole layer VIA2 may be formed to cover the first light emitting element LE1. The second through hole layer VIA2 may be arranged higher than the light emitting element LE. The second through hole layer VIA2 may include a first planarization portion VIA2-1, a second planarization portion VIA2-2, and a third planarization portion VIA2-3. The first planarization portion VIA2-1 may be arranged between the third connection hole CH3 and the fifth connection hole CH5 arranged on the first light emitting element LE1. The third planarization portion VIA2-3 may be arranged outside the fourth connection hole CH4 and the sixth connection hole CH6. The second planarization portion VIA2-2 may be arranged between the first planarization portion VIA2-1 and the third planarization portion VIA2-3. That is, the third planarization portion VIA2-3 may be arranged closer to the outside of the first light emitting element LE1 than the second planarization portion VIA2-2.

[0189] The first upper connection electrode BE2-1 connects the first contact electrode CTE1 and the first electrode APD through the third connection hole CH3 and the fourth connection hole CH4. In one or more embodiments, the first upper connection electrode BE2-1 electrically connects the first contact electrode CTE1 and the first electrode APD through the third connection hole CH3 and the fourth connection hole CH4. Here, "electrically connected" means that another connection layer can be added in the middle.

[0190] The first upper connection electrode BE2-1 may include a first upper connection portion BE2-11 and a second upper connection portion BE2-12. The first upper connection portion BE2-11 and the second upper connection portion BE2-12 are connected to each other. In one or more embodiments, the first upper connection portion BE2-11 and the second upper connection portion BE2-12 may be formed integrally with each other.

[0191] The first upper connection portion BE2-11 may be disposed to extend from the first lower connection portion BE1-11 exposed through the third connection hole CH3 along the second planarization portion VIA2-2 to the second lower connection portion BE1-12 exposed through the fourth connection hole CH4. The second upper connection portion BE2-12 may be disposed to extend from the second lower connection portion BE1-12 exposed through the fourth connection hole CH4 along the third planarization portion VIA2-3.

[0192] The second upper connection electrode BE2 - 2 is connected to the second contact electrode CTE2 and the second electrode CPD through the fifth connection hole CH5 and the sixth connection hole CH6 .

[0193] The second upper connection electrode BE2-2 may include a first upper connection portion BE2-21 and a second upper connection portion BE2-22. The first upper connection portion BE2-21 and the second upper connection portion BE2-22 are connected to each other. The first upper connection portion BE2-21 may be disposed to extend from the first lower connection portion BE1-21 exposed through the fifth connection hole CH5 along the second planarization portion VIA2-2 to the second lower connection portion BE1-22 exposed through the sixth connection hole CH6. The second upper connection portion BE2-22 may be disposed to extend from the second lower connection portion BE1-22 exposed by the sixth connection hole CH6 along the third planarization portion VIA2-3.

[0194] The lower connection electrode BE1 and the upper connection electrode BE2 may include a transparent conductive material (e.g., a transparent conductive oxide) capable of transmitting light, such as indium tin oxide (ITO) and / or indium zinc oxide (IZO). The second through hole layer VIA2 may be formed of the same material as the first through hole layer VIA1. The second through hole layer VIA2 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The height of the first through hole layer VIA1 may be less than the height of the light emitting element LE. The height of the first through hole layer VIA1 may be lower than the height of the active layer MQW.

[0195] The wavelength controlling part 200 may be disposed on the light emitting element layer EML.

[0196] The wavelength control part 200 may include a partition wall PW, a second reflective layer RFL, and a wavelength conversion layer QDL.

[0197] The partition wall PW is arranged to extend in the first direction DR1 and the second direction DR2 and may form a lattice pattern across the entire display area DA. In addition, the partition wall PW may not overlap the plurality of light emitting areas and may overlap the non-light emitting area.

[0198] The partition wall PW may be used to provide a space for the wavelength conversion layer QDL to be formed. The partition wall PW may have a large thickness to provide a space for the wavelength conversion layer QDL to be formed. For example, the partition wall PW may include an organic insulating material so that the partition wall PW may be made thick. The organic insulating material may include, for example, an epoxy-based resin, an acrylic-based resin, a cardo-based resin, and / or an imide-based resin.

[0199] In one or more embodiments, the partition wall PW may include a first partition wall and a second partition wall stacked in sequence. In this case, the length of the first partition wall in the first direction DR1 or the second direction DR2 may be wider than the length of the second partition wall in the first direction DR1 or the second direction DR2. In one or more embodiments, the partition wall PW may block the transmission of light in the non-luminous area. The partition wall PW may also include a light-shielding material, and may include a dye or pigment having a light-shielding property. For example, the partition wall PW may include an inorganic black pigment or an organic black pigment such as carbon black. External light incident on the display device 10 from the outside may cause the problem of distorting the color gamut of the wavelength control part 200. According to this embodiment, the partition wall PW including the light-shielding material is arranged in the wavelength control part 200 so that at least a portion of the external light is absorbed by the light-shielding material. Therefore, the color distortion caused by the reflection of external light can be reduced. In addition, the partition wall PW including the light-shielding material can prevent light from intruding between adjacent light-emitting areas and causing mixing, thereby further improving the color reproduction rate.

[0200] The second reflective layer RFL may be disposed between the partition wall PW and the first light conversion layer WCL1, between the partition wall PW and the second light conversion layer WCL2, and between the partition wall PW and the light transmission layer TPL. The second reflective layer RFL serves to reflect light propagating in a lateral direction from the first light conversion layer WCL1, the second light conversion layer WCL2, and the light transmission layer TPL.

[0201] The second reflective layer RFL may include a highly reflective metal material such as aluminum (Al). The thickness of the second reflective layer RFL may be approximately 0.1 μm.

[0202] Optionally, the second reflective layer RFL may include M (where M is an integer greater than or equal to 2) pairs of first and second layers having different refractive indices to function as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers may be alternately arranged. The first and second layers may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0203] The wavelength conversion layer QDL can convert and / or transform the peak wavelength of the incident light into light of another specific peak wavelength and emit the light. The wavelength conversion layer QDL can convert the blue first light emitted from the light emitting element LE into red second light, green third light, or transmit the blue first light as it is.

[0204] The wavelength conversion layer QDL may be disposed in each light emitting region (of the sub-pixels SPX1, SPX2, and SPX3) separated by the partition wall PW, and may be disposed to be spaced apart from each other. That is, the wavelength conversion layer QDL may be formed into an island pattern spaced apart from each other. The wavelength conversion layer QDL may be disposed to overlap with the first light emitting region of the first sub-pixel SPX1, the second light emitting region of the second sub-pixel SPX2, and the third light emitting region of the third sub-pixel SPX3, respectively. In one or more embodiments, each of the wavelength conversion layers QDL may completely overlap with the first light emitting region, the second light emitting region, and the third light emitting region.

[0205] The wavelength conversion layer QDL includes a first light conversion layer WCL1 overlapping the first light emitting region, a second light conversion layer WCL2 overlapping the second light emitting region, and a light transmitting layer TPL overlapping the third light emitting region.

[0206] The first wavelength conversion layer WCL1 may be disposed to overlap the first light emitting region. The first wavelength conversion layer WCL1 may convert and / or transform the peak wavelength of the incident light into light of another specific peak wavelength and emit the light. In one or more embodiments, the first wavelength conversion layer WCL1 may convert and emit the blue first light emitted from the light emitting element LE of the first light emitting region into a second light, which is red light having a single peak wavelength in the range of about 610 nm to about 650 nm.

[0207] The first wavelength conversion layer WCL1 may include a first base resin BRS1, first wavelength conversion particles WCP1 and scatterers SCP. The first base resin BRS1 may include a light-transmitting organic material. For example, the first base resin BRS1 may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin and / or an imide-based resin.

[0208] The first wavelength conversion particle WCP1 can convert the first light incident from the light emitting element LE into the second light. For example, the first wavelength conversion particle WCP1 can convert the light in the blue wavelength band into the light in the red wavelength band. The first wavelength conversion particle WCP1 can be a quantum dot (QD), a quantum rod, a fluorescent material and / or a phosphorescent material. For example, a quantum dot can be a particle material that emits light of a specific color due to an electron transition from a conduction band to a valence band.

[0209] Quantum dots can be semiconductor nanocrystal materials. Depending on the composition and size of the quantum dots, the quantum dots can have a specific band gap to absorb light and emit light with a unique wavelength. Examples of semiconductor nanocrystals of quantum dots include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group compound nanocrystals, and / or combinations thereof.

[0210] The II-VI compounds are: binary compounds selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; binary compounds selected from the group consisting of InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnT e, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; and a quaternary compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0211] The III-V compounds are: binary compounds selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof; ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb and mixtures thereof; and quaternary compounds selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0212] The IV-VI compound may be selected from the group consisting of: a binary compound selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; a ternary compound selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; and a quaternary compound selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. The IV group element may be selected from the group consisting of Si, Ge and mixtures thereof. The IV group compound may be a binary compound selected from the group consisting of SiC, SiGe and mixtures thereof.

[0213] The binary, ternary or quaternary compound may be present in the particle at a uniform concentration, or may be present in the same particle at a partially different concentration distribution. The quantum dot may also have a core / shell structure in which one quantum dot surrounds another quantum dot. The interface of the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0214] In one or more embodiments, the quantum dot may have a core-shell structure including a core and a shell surrounding the core, wherein the core includes a nanocrystal as described above. The shell of the quantum dot may be used as a protective layer to prevent chemical denaturation of the core to maintain semiconductor properties, and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be monolayer and / or multilayer. Examples of shells for quantum dots include metal or non-metal oxides, semiconductor compounds, and / or combinations thereof.

[0215] For example, metal or nonmetal oxides such as SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 , binary compounds of NiO and / or such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 、CoMn 2 O 4ternary compound, but the present disclosure is not limited thereto.

[0216] In addition, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but is not limited thereto.

[0217] The second light conversion layer WCL2 may be disposed to overlap with the second light emitting region. The second light conversion layer WCL2 may emit light by converting and / or transforming the peak wavelength of the incident light into light of another specific peak wavelength. In one or more embodiments, the second light conversion layer WCL2 converts the blue first light emitted from the light emitting element LE of the second light emitting region into a green third light having a peak wavelength in the range of about 510 nm to 550 nm and emits the green third light.

[0218] The second light conversion layer WCL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2 and scatterers SCP dispersed in the second base resin BRS2.

[0219] The second base resin BRS2 may be made of a material having high light transmittance, may be made of the same material as the first base resin BRS1, and / or may include at least one of the materials exemplified as constituent materials of the first base resin BRS1 and the second base resin BRS2.

[0220] The second wavelength conversion particles WCP2 can convert or transform the peak wavelength of the incident light into another specific peak wavelength. In one or more embodiments, the second wavelength conversion particles WCP2 can convert the blue first light provided from the light emitting element LE into a green third light having a peak wavelength in the range of about 510nm to 550nm and will emit the green third light. Examples of the second wavelength conversion particles WCP2 include quantum dots, quantum rods and / or phosphors. A more specific description of the second wavelength conversion particles WCP2 is substantially the same or similar to the above description in the description of the first wavelength conversion particles WCP1 and will be omitted.

[0221] The light-transmitting layer TPL may be arranged to overlap with the third light-emitting region. The light-transmitting layer TPL may transmit incident light. The light-transmitting layer TPL may directly transmit the blue first light emitted from the light-emitting element LE disposed in the third light-emitting region. The light-transmitting layer TPL may include a third base resin BRS3 and a scatterer SCP dispersed in the third base resin BRS3. Because the third base resin BRS3 is substantially the same as or similar to the above-mentioned first base resin BRS1, a description thereof will be omitted. In one or more embodiments, in the light-transmitting layer TPL, more scatterers SCP may be provided compared to the first wavelength conversion particles WCP1 and the second wavelength conversion particles WCP2.

[0222] The wavelength control part 200 may further include a cap layer CAP. The cap layer CAP may be disposed on the wavelength conversion layer QDL and the partition wall PW. The cap layer CAP may include an inorganic material. For example, the cap layer CAP may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxide. The accompanying drawings show that the cap layer CAP is formed as a single layer, but the present disclosure is not limited thereto. For example, the cap layer CAP may be formed by alternating multiple layers of inorganic layers including at least one of the materials that the cap layer CAP may include. The thickness of the cap layer CAP may be in the range of from 0.05 μm to 2 μm, but is not limited thereto. The cap layer CAP may be disposed on the top, bottom, and side of the wavelength conversion layer QDL to be around the wavelength conversion layer QDL (e.g., to surround the wavelength conversion layer QDL), thereby protecting the wavelength conversion layer QDL from moisture. The cap layer CAP may be composed of multiple inorganic films having different refractive indices. Optionally, the cap layer CAP may include an organic film and have a multilayer structure such as an inorganic film, an organic film and / or an inorganic film. Optionally, the cap layer CAP may also be formed of a low refractive index material having a lower refractive index than the organic layer. When the cap layer CAP is formed of a low refractive index material, total reflection of light emitted from the light emitting element LE and light-converted by passing through the wavelength conversion layer QDL can be prevented. This enables light to be focused upward. When the cap layer CAP is formed of multiple layers, for example, when it includes a first cap layer and a second cap layer and the wavelength conversion layer QDL has a refractive index of 1.5 to 2.0, at least one of the first cap layer and the second cap layer may have a refractive index between 1.1 and 1.5.

[0223] In one or more embodiments, a color filter layer CFL may be disposed on the wavelength controlling part 200. The color filter layer CFL may include a first overcoat layer OC1, a first color filter CF1, a second color filter CF2, a third color filter CF3, and a second overcoat layer OC2.

[0224] The first coating layer OC1 may be disposed on the wavelength control portion 200. The first coating layer OC1 may be disposed directly on the cover layer CAP of the wavelength control portion 200. The first coating layer OC1 may be disposed completely throughout the display area DA and may have a flat surface. The first coating layer OC1 may flatten a step formed by the lower wavelength control portion 200 to facilitate formation of the color filter layer CFL.

[0225] The first coating layer OC1 may include a light-transmitting organic material. For example, the first coating layer OC1 may include an epoxy resin, an acrylic resin, a cardo resin and / or an imide resin. In one or more embodiments, the first coating layer OC1 may be formed of a low refractive index material having a lower refractive index than the cap layer CAP or the wavelength conversion layer QDL. When the first coating layer OC1 has a low refractive index, light converted by the wavelength conversion layer QDL can be prevented from being reflected by the first coating layer OC1, so that the light is focused upward.

[0226] In one or more embodiments, when each light emitting element LE of each sub-pixel SPX is a native LED, the wavelength control part 200 may be omitted. That is, the color filter layer CFL may be disposed on the light emitting element layer EML.

[0227] Alternatively, when each light emitting element LE of each sub-pixel SPX is a native LED, the wavelength control part 200 may be implemented to include phosphor particles without a wavelength conversion material to improve light purity.

[0228] The first color filter CF1 , the second color filter CF2 , and the third color filter CF3 may be disposed on the first overcoating layer OC1 .

[0229] The first color filter CF1 may be disposed in the first light emitting region, the second color filter CF2 may be disposed in the second light emitting region, and the third color filter CF3 may be disposed in the third light emitting region.

[0230] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant (such as a dye or a pigment) that absorbs light of a wavelength other than the wavelength of the corresponding color light. The first color filter CF1 may selectively transmit the second light (e.g., red light) and block or absorb the first light (e.g., blue light) and the third light (e.g., green light). The second color filter CF2 may selectively transmit the third light (e.g., green light) and block or absorb the first light (e.g., blue light) and the second light (e.g., red light). The third color filter CF3 may selectively transmit the first light (e.g., blue light) and block or absorb the second light (e.g., red light) and the third light (e.g., green light). For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter.

[0231] In one or more embodiments, the light incident on the first color filter CF1 may be light converted into the second light in the first wavelength conversion layer WCL1, the light incident on the second color filter CF2 may be light converted into the third light in the second light conversion layer WCL2, and the light incident on the third color filter CF3 may be the first light transmitted through the light-transmitting layer TPL. As a result, the second light transmitted through the first color filter CF1, the third light transmitted through the second color filter CF2, and the first light transmitted through the third color filter CF3 may be emitted to the top of the substrate SUB to achieve full color.

[0232] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb a portion of the light entering from the outside of the display device 10 to reduce the reflected light caused by the external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent color distortion caused by the reflection of the external light. In addition, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can be used to block external light. For example, the first color filter CF1 disposed in the first sub-pixel SPX1 can prevent color mixing by blocking the second color light and the third color light from the outside. The color purity of the sub-pixel SPX can be improved. The plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 can be greater than the plane area of ​​each of the plurality of light-emitting regions. For example, the first color filter CF1 can be greater than the plane area of ​​the first light-emitting region. The second color filter CF2 can be greater than the plane area of ​​the second light-emitting region. The third color filter CF3 can be greater than the plane area of ​​the third light-emitting region. However, it is not limited thereto, and the plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be equal to the plane area of ​​each of the plurality of light-emitting regions. In one or more embodiments, the plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be different. For example, the second color filter CF2 may have the largest area, the third color filter CF3 may have the smallest area, and the first color filter CF1 may have an area between the area of ​​the second color filter CF2 and the area of ​​the third color filter CF3. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be red, green, and blue, respectively.

[0233] The second coating layer OC2 may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The second coating layer OC2 may be disposed directly on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The second coating layer OC2 may be completely disposed in the display area DA and may have a flat surface. The second coating layer OC2 may flatten the step formed by the first color filter CF1, the second color filter CF2, and the third color filter CF3 at the bottom. The second coating layer OC2 may include a light-transmitting organic material and may be substantially the same as or similar to the above-mentioned first coating layer OC1.

[0234] Fig.10 Reference Figure 7 A diagram illustrating a contact path between a first electrode and a first contact electrode in a display panel.

[0235] refer to Fig.10, the first contact electrode CTE1 of the first light emitting element LE1 and the first electrode APD may include a first contact path PH1 passing through the first lower connection electrode BE1 - 1 and a second contact path PH2 passing through the first upper connection electrode BE2 - 1 .

[0236] In addition, the second contact electrode CTE2 and the second electrode CPD of the first light emitting element LE1 may include a first contact path PH3 passing through the second lower connection electrode BE1 - 2 and a second contact path PH4 passing through the second upper connection electrode BE2 - 2 .

[0237] In this way, when there are two contact paths (one contact path between the first contact electrode CTE1 and the first electrode APD and another contact path between the second contact electrode CTE2 and the second electrode CPD), even if a disconnection occurs in one of the contact paths, current can be injected into the light-emitting element LE through the other contact path.

[0238] In this way, the first contact electrode CTE1 and the first electrode APD of the first light emitting element LE1 are connected in parallel, and the second contact electrode CTE2 and the second electrode CPD of the first light emitting element LE1 are connected in parallel, with the effect of reducing resistance.

[0239] In addition, by stacking relatively thin first and second via layers VIA1 and VIA2 instead of a thick single-layer via layer, the generation of degassing can be reduced or minimized, and the chattering phenomenon between the light-emitting elements LE1, LE2, and LE3 and the first via layer VIA1 can be reduced or minimized. Therefore, the damage of the connection electrodes connecting the light-emitting elements LE and the electrodes APD and CPD due to degassing can be reduced or minimized.

[0240] Fig.11 is a diagram showing the display panel and Figure 6 A sectional view of another example of the cross section corresponding to the lines I1 - I1 ′, I2 - I2 ′, and I3 - I3 ′. Fig.12 It is shown in detail Fig.11 A cross-sectional view of an example of region B in FIG.

[0241] Fig.11 and Fig.12 The implementation method and Figure 7 and Figure 8 The difference between the embodiments is that the first via layer VIA1 includes a light shielding material. Fig.11 and Fig.12 In the implementation mode of Figure 7 and Figure 8 The descriptions overlap the descriptions.

[0242] The first via layer VIA1 may be formed lower than the active layer MQW of the first light emitting element LE1 .

[0243] The first via layer VIA1 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. The height of the first via layer VIA1 may be formed to be lower than the height of the first light emitting element LE1. The first via layer VIA1 may include a light shielding material to prevent light from the light emitting element LE of one sub-pixel SPX from traveling to an adjacent sub-pixel SPX. For example, the first via layer VIA1 may include an inorganic black pigment such as carbon black or an organic black pigment.

[0244] Fig.13 is a diagram showing the display panel and Figure 6 A sectional view of another example of the cross section corresponding to the lines I1 - I1 ′, I2 - I2 ′, and I3 - I3 ′. Fig.14 It is shown in detail Fig.13 A cross-sectional view of an example of region C.

[0245] Fig.13 and Fig.14 The implementation method and Figure 7 and Figure 8 The difference of the embodiment of is that the second via layer VIA2 does not overlap with the first light emitting element LE1. Fig.13 and Fig.14 In the implementation method of Figure 7 and Figure 8 The descriptions overlap the descriptions.

[0246] refer to Figure 7 , Figure 8 , Fig.13 and Fig.14 , the second through hole layer VIA2 is arranged not to cover the light emitting element LE. The second through hole layer VIA2 may be arranged to expose the first lower connection electrode BE1-1 and the second lower connection electrode BE1-2 respectively overlapping the first contact electrode CTE1 and the second contact electrode CTE2. Therefore, the second through hole layer VIA2 does not have Figure 8 The second via layer VIA2 has a fourth connection hole CH4 and a sixth connection hole CH6.

[0247] The fourth connection hole CH4 is formed to be positioned closer to the outside of the light emitting element LE than the first connection hole CH1, and the first lower connection electrode BE1-1 exposed by the fourth connection hole CH4 is connected to the first connection hole CH1. The fourth connection hole CH4 may expose the first lower connection electrode BE1-1. The first lower connection electrode BE1-1 exposed by the fourth connection hole CH4 is connected to the first connection hole CH1. Therefore, the first upper connection electrode BE2-1 disposed on the second through-hole layer VIA2 is connected to the first electrode APD along the first lower connection electrode BE1-1 through the fourth connection hole CH4.

[0248] The sixth connection hole CH6 is formed to be positioned closer to the outside of the light emitting element LE than the second connection hole CH2, and the second lower connection electrode BE1-2 exposed by the sixth connection hole CH6 is connected to the second connection hole CH2. The sixth connection hole CH6 may expose the second lower connection electrode BE1-2. The second lower connection electrode BE1-2 exposed by the sixth connection hole CH6 is connected to the second connection hole CH2. Therefore, the second upper connection electrode BE2-2 disposed on the second through-hole layer VIA2 is connected to the second electrode CPD along the second lower connection electrode BE1-2 through the sixth connection hole CH6.

[0249] Fig.15 is a diagram showing the display panel and Figure 6 A sectional view of another example of the cross section corresponding to the lines I1 - I1 ′, I2 - I2 ′, and I3 - I3 ′. Fig.16 It is shown Fig.15 A cross-sectional view of an example of region D.

[0250] Fig.15 and Fig.16 The implementation method and Figure 7 and Figure 8 The embodiment of FIG. 1 is different in that the second organic layer 180 has a groove 180 -R, and the first reflective layer REL is disposed along the groove 180 -R. Fig.15 and Fig.16 In the implementation method of Figure 7 and Figure 8 The descriptions overlap the descriptions.

[0251] refer to Figure 7 , Figure 8 , Fig.15 and Fig.16, the second organic layer 180 has a groove 180-R. The groove 180-R may overlap with the organic pattern layer BOL (for example, in the third direction DR3). The groove 180-R may overlap with the first light emitting element LE1. The first reflective layer REL may be disposed on the groove 180-R. The first reflective layer REL may be made of a highly reflective metal material such as aluminum (Al). The first reflective layer REL may reflect light emitted from the first light emitting element LE1 and traveling in a downward direction of the first light emitting element LE1 to travel in an upward direction of the first light emitting element LE1. Therefore, since the loss of light from the first light emitting element LE1 may be reduced, the light efficiency of the first light emitting element LE1 may be improved. In one or more embodiments, the first reflective layer REL may be formed as a single layer or a plurality of layers. For example, the first reflective layer REL may include M (M is an integer of 2 or greater) pairs of first and second layers having different refractive indices to serve as a distributed Bragg reflector (DBR).

[0252] Fig.17 is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments. Figures 18 to 26 is a cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments. Figures 18 to 26 shows the display panel and Figure 6 An example of a cross section corresponding to the line I1-I1' in FIG. Figures 18 to 26 Some of the attachments Figure 1 In addition, the following will focus on the first light emitting area EA1 of the display device 10.

[0253] First, if Fig.18 As shown in FIG. 1 , a plurality of light emitting elements LE ( Fig.17 , or step S110 in the above process.

[0254] A first light emitting element LE1 is disposed on a fourth adhesive layer ADL4 disposed on a light emitting element substrate ESUB. A plurality of light emitting elements LE are fixed to the fourth adhesive layer ADL4 by adhesion. The light emitting element substrate ESUB may include a material that allows light to be transmitted. For example, the light emitting element substrate ESUB may include a transparent polymer such as polyimide, polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, and the like. The fourth adhesive layer ADL4 may include an adhesive material for bonding a plurality of light emitting elements LE. For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, and the like.

[0255] Will refer to it later Figures 27 to 34To describe the detailed description of the method of transferring a plurality of light emitting elements LE formed on a semiconductor substrate SSUB to a light emitting element substrate ESUB. To facilitate understanding of the description, Figures 19 to 21 A plan view of the accompanying drawings corresponding to the side view of the accompanying drawings is shown. Figures 19 to 21 , the drawing set on the upper side is a shape viewed from the top of the side view set on the lower side.

[0256] Second, if Fig.19 As shown in FIG. , a mask is used to form a thin film transistor layer ( Figure 7 A first electrode APD and a second electrode CPD ( Fig.17 , or step S120 in the above procedure.

[0257] A layer of electrode material is applied on the substrate having the thin film transistor layer. Then, a first electrode APD and a second electrode CPD are formed on the same plane using a photolithography process and are spaced apart from each other.

[0258] Third, if Fig. 20 As shown in FIG. 1 , an organic pattern layer BOL is formed on the first electrode APD and the second electrode CPD. Fig.17 , or step S130 in the above procedure.

[0259] An organic pattern layer BOL is formed between the first electrode APD and the second electrode CPD. The organic pattern layer BOL is formed to cover the edge of the first electrode APD and the edge of the second electrode CPD. The organic pattern layer BOL may be filled in the space between the first electrode APD and the second electrode CPD. The organic pattern layer BOL may be formed to be higher than the height of the first electrode APD and the second electrode CPD. The organic pattern layer BOL may be formed by applying a material to the entire surface using a photolithography process and then using a mask or the like. Alternatively, the organic pattern layer BOL may be applied in a patterned manner using printing or inkjet.

[0260] The organic pattern layer BOL may be a temporary adhesive layer or a temporary fixing layer for temporarily fixing or adhering the plurality of light emitting elements LE in a process of transferring the light emitting elements LE to the display panel 100 .

[0261] The organic pattern layer BOL may be a photosensitive organic film such as a photoresist. Alternatively, the organic pattern layer BOL may be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0262] Fourth, if Fig.21 As shown in FIG. 1 , a plurality of light emitting elements LE on the light emitting element substrate ESUB are fixed to the organic pattern layer BOL ( Fig.17 , or step S140 in the above procedure.

[0263] The light emitting element LE on the light emitting element substrate ESUB is disposed on the organic pattern layer BOL. The light emitting element LE is disposed such that the first contact electrode CTE1 and the second contact electrode CTE2 face the upper surface. The first contact electrode CTE1 may be disposed close to the first electrode APD, and the second contact electrode CTE2 may be disposed close to the second electrode CPD.

[0264] At this time, the plurality of light emitting elements LE may be temporarily fixed by embedding them in the organic pattern layer BOL. For example, the third semiconductor layer SEM3 of each of the plurality of light emitting elements LE may be embedded in the organic pattern layer BOL and fixed.

[0265] If the organic pattern layer BOL is a photosensitive organic film such as a photoresist, the organic pattern layer BOL can be cured (soft baked) at a first temperature, and then at least a portion of the light emitting element LE can be inserted into the organic pattern layer BOL. Then, the organic pattern layer BOL can be completely cured at a second temperature higher than the first temperature. The first temperature may be approximately 100 degrees, and the second temperature may be approximately 230 degrees, but the present disclosure is not limited thereto. In the process of curing the organic pattern layer BOL at the first temperature, because the first temperature is low enough to completely cure the organic pattern layer BOL, the organic pattern layer BOL may be fluid. If the organic pattern layer BOL is spread over an area larger than desired, the organic pattern layer BOL may be formed into a desired shape by etching or ashing after an additional curing process to be described later. In addition, the process of completely curing the organic pattern layer BOL at the second temperature may be performed for approximately 30 minutes.

[0266] Then, the light emitting element substrate ESUB is separated from the light emitting elements LE. For example, ultraviolet light or heat may be applied to the adhesive layer of the light emitting element substrate ESUB to reduce the adhesion of the adhesive layer of the light emitting element substrate ESUB, and then the light emitting element substrate ESUB may be physically or naturally separated from the plurality of light emitting elements LE.

[0267] Next, refer to Fig. 22 , forming a first through hole layer VIA1 to cover the organic pattern layer BOL and having a first connection hole CH1 and a second connection hole CH2 ( Fig.17 , or step S150 in the above procedure.

[0268] The first via layer VIA1 may be formed to be lower than the height of the active layer MQW of the light emitting element LE. The first via layer VIA1 may be applied using a solution process such as spin coating, inkjet printing, or the like.

[0269] Next, a plurality of connection holes CH1 and CH2 are formed in the first via layer VIA1 through an etching process using a mask.

[0270] The first connection hole CH1 exposes the first electrode APD on the first electrode APD, and the second connection hole CH2 exposes the second electrode CPD on the second electrode CPD.

[0271] Next, refer to Fig.23 , a first lower connection electrode BE1-1 and a second lower connection electrode BE1-2 are formed on the first through hole layer VIA1 ( Fig.17 , or step S160 in the above procedure.

[0272] The first lower connection electrode BE1-1 connects the first electrode APD and the first contact electrode CTE1 on the light emitting element LE disposed on the organic pattern layer BOL in each of the sub-pixels SPX1 to SPX4. For example, a lower connection electrode material is deposited on the light emitting element LE and the first via layer VIA1. Thereafter, the first lower connection electrode BE1-1 and the second lower connection electrode BE1-2 spaced apart from each other are formed using a photoresist technique using a mask.

[0273] The first lower connection electrode BE1 - 1 contacts the first electrode APD exposed by the first connection hole CH1 , and the second lower connection electrode BE1 - 2 contacts the second electrode CPD exposed by the second connection hole CH2 .

[0274] Sixth, reference Fig.24 A second through hole layer VIA2 having a plurality of connection holes CH3, CH4, CH5 and CH6 is formed on the first through hole layer VIA1 ( Fig.17 , or step S170 in the above procedure.

[0275] The second via layer VIA2 may be formed to completely cover the light emitting element LE. The second via layer VIA2 may be applied using a solution process such as spin coating, inkjet printing, or the like.

[0276] Next, connection holes CH3 , CH4 , CH5 , and CH6 are formed in the second via layer VIA2 through an etching process using a mask.

[0277] The third connection hole CH3 overlaps the first contact electrode CTE1 and exposes the first lower connection electrode BE1-1, and the fifth connection hole CH5 overlaps the second contact electrode CTE2 and exposes the second lower connection electrode BE1-2. The fourth connection hole CH4 is formed to be positioned closer to the outside of the light emitting element LE than the first connection hole CH1, and the first lower connection electrode BE1-1 exposed by the fourth connection hole CH4 is connected to the first connection hole CH1. The fourth connection hole CH4 may expose the first lower connection electrode BE1-1. The first lower connection electrode BE1-1 exposed by the fourth connection hole CH4 is connected to the first connection hole CH1.

[0278] The sixth connection hole CH6 is formed to be positioned closer to the outside of the light emitting element LE than the second connection hole CH2, and the second lower connection electrode BE1-2 exposed by the sixth connection hole CH6 is connected to the second connection hole CH2. The sixth connection hole CH6 may expose the second lower connection electrode BE1-2. The second lower connection electrode BE1-2 exposed by the sixth connection hole CH6 is connected to the second connection hole CH2.

[0279] Next, refer to Fig.25 , a first upper connection electrode BE2-1 and a second upper connection electrode BE2-2 are formed on the second through hole layer VIA2 ( Fig.17 , or step S180 in the above procedure.

[0280] An upper connection electrode material layer is deposited on the second via layer VIA2. Then, a first upper connection electrode BE2-1 and a second upper connection electrode BE2-2 spaced apart from each other are formed using a photoresist technique using a mask.

[0281] Next, refer to Fig.26 , forming a partition wall PW, a first light conversion layer WCL1 and a light-transmitting layer TPL (see Figure 7 In addition, a color filter layer ( Figure 7 Color filter layer CFL) Fig.17 , or step S190 in the above procedure.

[0282] First, an organic material is applied to the second via layer VIA2 and patterned to form a partition wall PW. A second reflective layer RFL may be formed on an inner surface of a space formed by the partition wall PW.

[0283] Then, the partition wall PW has an opening, and the first light conversion layer WCL1 is formed in the opening. In the area separated by the partition wall PW, the first light conversion layer WCL1 is formed in the first sub-pixel SPX1, the second light conversion layer WCL2 is formed in the second sub-pixel SPX2, and the light-transmitting layer TPL is formed in the third sub-pixel SPX3 (see Figure 7 ).

[0284] Then, the partition wall PW, the light conversion layers WCL and WCL2, and the light transmission layer TPL (see Figure 7 ) Figure 7 The first overcoat layer OC1, the first color filter CF1, the second color filter CF2, the third color filter CF3 and the second overcoat layer OC2 described in FIG.

[0285] Fig. 27 It is shown in detail Fig.17 Flow chart of step S110. Figures 28 to 34 is a cross-sectional view showing step S110.

[0286] In the following, reference will be made to Figures 27 to 34 A process of transferring a plurality of light emitting elements LE formed on the semiconductor substrate SSUB to the light emitting element substrate ESUB is described in detail.

[0287] First, if Fig.28 As shown in FIG. , a plurality of light emitting elements LE are formed on a semiconductor substrate SSUB. Fig. 27 , or step S111 in the above procedure.

[0288] The semiconductor substrate SSUB may be a silicon wafer substrate or a sapphire substrate. A light emitting element material layer is deposited on the entire semiconductor substrate SSUB. The light emitting element material layer may be formed on the semiconductor substrate SSUB by an epitaxial growth process. As an epitaxial growth process, the method of forming the light emitting element material layer may include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), etc. Preferably, metal organic chemical vapor deposition (MOCVD) may be used, but the present disclosure is not limited thereto.

[0289] Next, a transparent conductive material layer is formed on the light emitting element material layer. Then, the plurality of semiconductor material layers and the transparent conductive material layer are etched. Fig. 9 As shown in , the light emitting element material layer may include a third semiconductor layer SEM3, a second semiconductor layer SEM2, an active layer MQW, a first semiconductor layer SEM1, a transparent conductive layer TCO, a first contact electrode CTE1, a second contact electrode CTE2 and an element insulating layer INS0.

[0290] Then, after forming a mask pattern on the light emitting element material layer, the light emitting element material layer and the transparent conductive material layer may be etched according to the mask pattern to form a plurality of light emitting elements LE. The mask pattern may be removed after forming the plurality of light emitting elements LE.

[0291] The light emitting element material layer can be etched by dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. Dry etching allows anisotropic etching and can be suitable for vertical etching. In the case of dry etching, the etching gas can be Cl 2 or 2 , but not limited to this.

[0292] Then, an opening exposing the second semiconductor layer SEM2 is formed on the transparent conductive layer TCO by an etching process. As described above, the etching process may be a dry etching method, a wet etching method, a reactive ion etching (RIE) method, a deep reactive ion etching (DRIE) method, an inductively coupled plasma reactive ion etching (ICP-RIE) method, etc.

[0293] Next, an insulating material layer having a plurality of openings OP1 and OP2 is formed on the semiconductor substrate SSUB on which the light emitting element LE is formed.

[0294] Then, second etching (second etching) is performed to partially remove the insulating material layer to form the light emitting element LE including the element insulating layer INS0.

[0295] Specifically, a second etching (second etching) that partially removes the insulating material layer so that the insulating material layer exposes the top surface of the light emitting element LE but surrounds the side of the light emitting element LE may be performed. Specifically, in this process, at least a portion of the insulating material layer on the top surface of the transparent conductive layer TCO of the light emitting element LE may be removed to define a first opening OP1. In addition, a second opening OP2 may be defined by removing at least a portion of the insulating material layer on the second semiconductor layer SEM2 of the light emitting element LE. The process of partially removing the insulating material layer may be performed by an etching process using a mask.

[0296] Next, a first contact electrode CTE1 in the first opening OP1 and a second contact electrode CTE2 in the second opening OP2 are formed on the light emitting element LE.

[0297] For example, the first contact electrode CTE1 and the second contact electrode CTE2 are formed by stacking a contact electrode material layer on the semiconductor substrate SSUB. Then, the contact electrode material layer is etched by an etching process to form the first contact electrode CTE1 covering the first opening OP1 of the light emitting element LE and the second contact electrode CTE2 covering the second opening OP2. The contact electrode material layer may be formed of a transparent conductive material. For example, the contact electrode material layer may be a transparent conductive oxide such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0298] Second, if Fig.29 As shown in FIG. 1 , a plurality of light emitting elements LE on the semiconductor substrate SSUB are moved to a first adhesive layer ADL1 ( Fig. 27 , or step S112 in the above procedure.

[0299] The first transfer substrate TSUB1 may be made of a transparent material to allow light to pass through. For example, the first transfer substrate TSUB1 may include a transparent polymer such as polyimide, polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The first adhesive layer ADL1 disposed on one surface of the first transfer substrate TSUB1 may include an adhesive material for bonding the plurality of light emitting elements LE. For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc.

[0300] The first contact electrode CTE1 and the second contact electrode CTE2 of each of the plurality of light emitting elements LE may be bonded to the first adhesive layer ADL1 disposed on the first transfer substrate TSUB1. Then, the plurality of light emitting elements LE may be separated from the semiconductor substrate SSUB by a laser lift-off (LLO) process of irradiating the semiconductor substrate SSUB with a laser. The laser may be a KrF excimer laser having a wavelength of approximately 248 nm, but the present disclosure is not limited thereto.

[0301] Third, if Fig.30 As shown in FIG. 1 , a plurality of light emitting elements LE of the first transfer substrate TSUB1 are moved to the first laser separation layer LLO1 ( Fig. 27 , or step S113 in the above procedure.

[0302] The second transfer substrate TSUB2 may be made of a transparent material to allow light to pass therethrough. For example, the second transfer substrate TSUB2 may include a transparent polymer such as polyimide, polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The first laser separation layer LLO1 disposed on the second transfer substrate TSUB2 is a layer that is separable by laser irradiation, and may include, for example, a transparent polymer such as polyimide.

[0303] When heat is applied while one surface of each of the plurality of light emitting elements LE is in contact with the first laser separation layer LLO1, each of the plurality of light emitting elements LE may be adhered or fixed to the first laser separation layer LLO1, and as the adhesive force of the first adhesive layer ADL1 is weakened, each of the plurality of light emitting elements LE may be separated from the first adhesive layer ADL1. One surface of each of the plurality of light emitting elements LE may be opposite to the other surface on which the first contact electrode CTE1 and the second contact electrode CTE2 of each of the plurality of light emitting elements LE are disposed.

[0304] Fourth, if Fig.31 As shown in FIG. 1 , the first laser separation layer LLO1 is etched using the plurality of light emitting elements LE as a mask to form a second laser separation layer LLO2 ( Fig. 27, or step S114 in the above procedure.

[0305] Instead of etching the plurality of light emitting elements LE, dry etching is performed using an etching gas (DEG) that etches only the first laser separation layer LLO1. That is, the first laser separation layer LLO1 is etched using the plurality of light emitting elements LE as a mask. As a result, the first laser separation layer LLO1 that does not overlap with the plurality of light emitting elements LE in the thickness direction of the second transfer substrate TSUB2 can be removed. Therefore, the second laser separation layer LLO2 that overlaps with the plurality of light emitting elements LE can be formed in the thickness direction of the second transfer substrate TSUB2. The second laser separation layer LLO2 can be disposed between each of the plurality of light emitting elements LE and the second transfer substrate TSUB2 in the thickness direction of the second transfer substrate TSUB2.

[0306] Fifth, if Fig.32 and Fig.33 As shown in FIG. 1 , by irradiating the second laser separation layer LLO2 with laser, a plurality of light emitting elements LE are transferred to the third adhesive layer ADL3 on the third transfer substrate TSUB3, and the second laser separation layer LLO2 is removed ( Fig. 27 , or step S115 in the above procedure.

[0307] The third transfer substrate TSUB3 may be made of a transparent material to allow light to pass through. For example, the third transfer substrate TSUB3 may include a transparent polymer such as polyimide, polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The third adhesive layer ADL3 disposed on one surface of the third transfer substrate TSUB3 may include an adhesive material for bonding the plurality of light emitting elements LE. For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc.

[0308] When the first contact electrode CTE1 and the second contact electrode CTE2 of each of the plurality of light emitting elements LE are in contact with the third adhesive layer ADL3 on the third transfer substrate TSUB3 and the laser is irradiated onto the second laser separation layer LLO2, the second laser separation layer LLO2 may be separated into a third laser separation layer LLO3 disposed on one surface of the second transfer substrate TSUB2 and a fourth laser separation layer LLO4 disposed on each of the plurality of light emitting elements LE. Then, the fourth laser separation layer LLO4 remaining on each of the plurality of light emitting elements LE may be removed by a wet etching process. The plurality of light emitting elements LE are not etched, and the fourth laser separation layer LLO4 is etched using an etching material WEG that etches only the fourth laser separation layer LLO4. In one or more embodiments, the adhesive layers ADL1, ADL2, and ADL3 are separated into two laser separation layers by laser irradiation, so that one laser separation layer remains on the relay substrate and the other laser separation layer is disposed on the light emitting element LE, but is not limited thereto. For example, after laser irradiation, the adhesive layers ADL1, ADL2, and ADL3 may remain on the relay substrate or the light emitting element LE, while the adhesive layers ADL1, ADL2, or ADL3 do not exist on the other of the relay substrate and the light emitting element LE. For example, when the second laser separation layer LLO2 is irradiated while the light emitting element LE is in contact with the third adhesive layer ADL3 on the third transfer substrate TSUB3, the second laser separation layer LLO2 may remain on one surface of the second transfer substrate TSUB2 without being disposed on the other side of the light emitting element LE. In this case, the wet etching process for removing the second laser separation layer LLO2 remaining on the light emitting element LE may be omitted.

[0309] Sixth, if Fig.34 As shown in FIG. 1 , a plurality of light emitting elements LE on the third transfer substrate TSUB3 are moved to the fourth adhesive layer ADL4 ( Fig. 27 , or step S116 in the above procedure.

[0310] While one surface of each of the plurality of light emitting elements LE of the third transfer substrate TSUB3 is brought into contact with the fourth adhesive layer ADL4 on the light emitting element substrate ESUB, each of the plurality of light emitting elements LE is separated from the third adhesive layer ADL3. In this case, the adhesive force of the fourth adhesive layer ADL4 may be higher than the adhesive force of the third adhesive layer ADL3. One surface of each of the plurality of light emitting elements LE may be opposite to the other surface of each of the plurality of light emitting elements LE on which the first contact electrode CTE1 and the second contact electrode CTE2 are disposed.

[0311] In one or more embodiments, the following is described: Fig.34, an example of preparing a final interposer substrate by arranging the first contact electrode CTE1 and the second contact electrode CTE2 face-up on the light emitting element substrate ESUB is shown in , but when transferring to a target substrate using a stamp, the light emitting element LE disposed on the final interposer substrate thus prepared can be used. In one or more embodiments, if it is desired to align and transfer the light emitting element LE of the final interposer substrate to the target substrate without using a stamp, then Fig.33 The third transfer substrate TSUB3 can become the light emitting element substrate ESUB as the final interposer. In this case, the reference Fig.34 Step S116 described.

[0312] Fig.35 is an exemplary diagram showing a virtual reality device including a display device according to one or more embodiments. Fig.35 A virtual reality device 1 is shown in which a display device 10 according to one or more embodiments is used.

[0313] refer to Fig.35 The virtual reality device 1 according to one or more embodiments may be a device in the form of glasses. The virtual reality device 1 according to one or more embodiments may include a display device 10, a left eye lens 10a, a right eye lens 10b, a support frame 20, a left leg 30a and a right leg 30b, a reflective member 40, and a display device housing 50.

[0314] Fig.35 The virtual reality device 1 including two legs 30a and 30b is shown. However, the present disclosure is not limited thereto. The virtual reality device 1 according to one or more embodiments may be used for a head-mounted display including a head-mounted band that can be mounted on the head without including the legs 30a and 30b. For example, the virtual reality device 1 according to one or more embodiments may not be limited to Fig.35 The examples shown in and can be applied in various forms and applicable to various electronic devices.

[0315] The display device housing 50 can accommodate the display device 10 and the reflective member 40. The image displayed on the display device 10 can be reflected from the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user can watch the virtual reality image displayed on the display device 10 through the right eye.

[0316] Fig.35It is shown that the display device housing 50 is disposed at the right end of the support frame 20. However, the present disclosure is not limited thereto. For example, the display device housing 50 may be disposed at the left end of the support frame 20. In this case, the image displayed on the display device 10 may be reflected from the reflective member 40 and provided to the left eye of the user via the left eye lens 10a. Therefore, the user can view the virtual reality image displayed on the display device 10 via the left eye. As another example, the display device housing 50 may be disposed at each of the left and right ends of the support frame 20. In this case, the user can view the virtual reality image displayed on the display device 10 via the left eye and the right eye.

[0317] Fig.36 is an exemplary diagram illustrating a smart device including a display device according to one or more embodiments.

[0318] refer to Fig.36 The display device 10 according to one or more embodiments may be applied to a smart watch 2 which is one of smart devices.

[0319] Fig.37 is an exemplary diagram showing a vehicle including a display device according to one or more embodiments. Fig.37 A vehicle in which a display device according to one or more embodiments is used is shown.

[0320] refer to Fig.37 The display devices 10_a, 10_b, and 10_c according to one or more embodiments may be applied to a dashboard of a vehicle, to a central instrument panel of a vehicle, or to a central information display (CID) provided on a dashboard of a vehicle. In addition, each of the display devices 10_d and 10_e according to one or more embodiments may be applied to each interior mirror display of a vehicle instead of each of the side mirrors.

[0321] Fig.38 is an exemplary diagram showing a transparent display device including a display device according to one or more embodiments.

[0322] refer to Fig.38 The display device 10 according to one or more embodiments may be applied to a transparent display device. The transparent display device may transmit light therethrough while displaying an image IM thereon. Therefore, a user located in front of the transparent display device may not only view the image IM displayed on the display device 10, but may also view an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to a transparent display device, Figure 7 The semiconductor substrate SUB of the display device 10 shown in FIG. 1 may include a light-transmitting portion that allows light to be transmitted therethrough, or may be made of a material that allows light to be transmitted therethrough.

[0323] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles and scope of the present disclosure. Therefore, the embodiments of the present disclosure are used in a general and descriptive sense only and not for a limiting purpose.

Claims

1. A display device, comprising: substrate; a first electrode and a second electrode on the substrate and spaced apart from each other; an organic pattern layer, between the first electrode and the second electrode; a light emitting element having a first contact electrode and a second contact electrode on the top surface of the organic pattern layer; a first through-hole layer covering the first electrode and the second electrode and covering a portion of a side surface of the light-emitting element; a first lower connecting electrode and a second lower connecting electrode, wherein the first lower connecting electrode connects the first electrode and the first contact electrode on the first through-hole layer, and the second lower connecting electrode connects the second electrode and the second contact electrode; a second through-hole layer on the first through-hole layer and covering a portion of the side surface of the light-emitting element; as well as A first upper connecting electrode and a second upper connecting electrode, wherein the first upper connecting electrode connects the first electrode and the first contact electrode on the second through-hole layer, and the second upper connecting electrode connects the second electrode and the second contact electrode.

2. The display device according to claim 1, wherein: The first through-hole layer includes a first connection hole and a second connection hole, The first connection hole exposes the first electrode, and the second connection hole exposes the second electrode.

3. The display device according to claim 2, wherein: The first lower connection electrode contacts the first electrode through the first connection hole, and the second lower connection electrode contacts the second electrode through the second connection hole.

4. The display device according to claim 3, wherein: The second through hole layer includes a third connection hole and a fourth connection hole, the third connection hole exposing the first lower connection electrode connected to the first electrode, the fourth connection hole exposing the second lower connection electrode connected to the second electrode, and the third connection hole and the fourth connection hole are farther away from the light emitting element than the first connection hole and the second connection hole.

5. The display device according to claim 4, wherein: The first upper connection electrode contacts the first lower connection electrode through the third connection hole, and the second upper connection electrode contacts the second lower connection electrode through the fourth connection hole.

6. The display device according to claim 1, wherein: The first lower connecting electrode is on the light emitting element between the first contact electrode and the first upper connecting electrode, and The second lower connecting electrode is located between the second contact electrode and the second upper connecting electrode on the light emitting element.

7. The display device according to claim 1, wherein: The light emitting element comprises: a third semiconductor layer, on the organic pattern layer; a second semiconductor layer, on the third semiconductor layer; an active layer on the second semiconductor layer; a first semiconductor layer on the active layer; and An element insulating layer, surrounding the light emitting element, The first contact electrode and the second contact electrode are on the first semiconductor layer, the first contact electrode is connected to the first semiconductor layer, and the second contact electrode is connected to the second semiconductor layer.

8. The display device according to claim 7, wherein: The first via layer is lower than the active layer.

9. The display device according to claim 8, wherein: The height of the second through hole layer is equal to or higher than the height of the light emitting element.

10. The display device according to claim 9, wherein: The second through hole layer includes a third connection hole and a fifth connection hole, the third connection hole overlaps with the first contact electrode of the light emitting element and exposes the first lower connection electrode, and the fifth connection hole overlaps with the second contact electrode and exposes the second lower connection electrode.

11. The display device according to claim 10, wherein: The first upper connection electrode contacts the first lower connection electrode through the third connection hole, and the second upper connection electrode contacts the second lower connection electrode through the fifth connection hole.

12. The display device according to claim 8, wherein: The first through hole layer includes a light shielding material.

13. The display device according to claim 1, wherein: The first electrode and the second electrode are spaced apart from each other on the same plane and protrude outward from the light emitting element.

14. The display device according to claim 13, wherein: The first electrode and the second electrode are spaced apart from each other by a first gap on the same plane, and the first gap is smaller than a width of the light emitting element.

15. The display device according to claim 1, further comprising a reflective layer between the first electrode and the second electrode on the substrate, in, The first electrode and the second electrode are on the same plane and are spaced apart from each other by a first gap, and the first gap is wider than a width of the light emitting element.

16. The display device according to claim 15, wherein: The reflective layer overlaps the light emitting element, and a width of the reflective layer is greater than the width of the light emitting element.

17. The display device according to claim 1, wherein: The width of the organic pattern layer is greater than the width of the light emitting element.

18. The display device according to claim 17, wherein: The organic pattern layer covers a portion of the first electrode and a portion of the second electrode and fills a gap space between the first electrode and the second electrode.

19. A method for manufacturing a display device, comprising: preparing a substrate on which the first electrode and the second electrode are located; forming an organic pattern layer on the substrate between the first electrode and the second electrode; Arranging and fixing a light emitting element on the organic pattern layer; forming a first through-hole layer covering the light-emitting element and having a plurality of connection holes; as well as forming a first lower connection electrode and a second lower connection electrode on the first through-hole layer, wherein the first lower connection electrode connects the first electrode and the first contact electrode of the light-emitting element through the plurality of connection holes, and the second lower connection electrode connects the second electrode and the second contact electrode of the light-emitting element; forming a second through hole layer on the first through hole layer to cover a portion of the side surface of the light emitting element; as well as A first upper connecting electrode and a second upper connecting electrode are formed on the second through hole layer, the first upper connecting electrode connecting the first electrode and the first contact electrode, and the second upper connecting electrode connecting the second electrode and the second contact electrode.

20. The method according to claim 19, further comprising: forming a partition wall including a light shielding material on the second through hole layer; In the region separated by the partition wall, a first light conversion layer is formed in a region corresponding to the first sub-pixel, a second light conversion layer is formed in a region corresponding to the second sub-pixel, and a light-transmitting layer is formed in a region corresponding to the third sub-pixel; as well as A first color filter is formed on the first light conversion layer, a second color filter is formed on the second light conversion layer, and a third color filter is formed on the light-transmitting layer.

21. A display device, comprising: substrate; a first electrode and a second electrode on the substrate and spaced apart from each other; an organic pattern layer overlapping at least a portion of the first electrode and at least a portion of the second electrode; a light emitting element on the organic pattern layer and having a first contact electrode and a second contact electrode on one surface; a first via layer on top of the first electrode and the second electrode and exposing the first contact electrode and the second contact electrode of the light emitting element; a first lower connecting electrode and a second lower connecting electrode, wherein the first lower connecting electrode is electrically connected to the first electrode and the first contact electrode on the first through-hole layer, and the second lower connecting electrode is electrically connected to the second electrode and the second contact electrode; a second via layer on top of the first via layer; as well as A first upper connecting electrode and a second upper connecting electrode, wherein the first upper connecting electrode connects the first electrode and the first contact electrode on the second through-hole layer, and the second upper connecting electrode connects the second electrode and the second contact electrode.

22. A display device, comprising: substrate; a first electrode on the substrate; an organic pattern layer, partially overlapping the first electrode; a light emitting element having at least one first contact electrode on one surface of the organic pattern layer; a first lower connecting electrode on the first electrode and connecting the first electrode to the first contact electrode of the light emitting element; a first upper connecting electrode on the first electrode and comprising a first contact region and a second contact region, the first upper connecting electrode being connected to the first lower connecting electrode in the first contact region and the second contact region, respectively; The first electrode, the first lower connecting electrode and the first upper connecting electrode overlap with each other in the second contact region.

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