Micro-LED wafer bonding method

Abstract

The invention discloses a Micro-LED wafer bonding method, which belongs to the technical field of display, and comprises the following steps: step 1, preparing an epitaxial wafer and a driving substrate, the epitaxial wafer comprising a substrate layer and a pixel layer; 2, a metal layer is evaporated on the pixel layer to serve as a p electrode, and a bonding layer is evaporated on the driving substrate; 3, bonding the metal layer with the bonding layer, and stripping the substrate layer; step 4, etching the pixel of the Micro-LED (Light Emitting Diode); 5, metal Ti is evaporated, and the side wall of the Micro-LED pixel is repaired through photoelectrochemical etching; 6, removing the metal Ti, and evaporating a first passivation layer; 7, forming a first through hole; 8, etching the metal material in the bonding layer; step 9, evaporating a second passivation layer; and step 10, evaporating an interconnection layer, wherein the interconnection layer and the driving substrate are interconnected to serve as an n electrode. Photoelectrochemical etching is used for repairing and correcting the side wall of the Micro-LED pixel, so that the problems of difficulty in depth control, excessive damage, non-uniformity, thermal damage and the like possibly caused by adopting a dry etching method in the whole process can be avoided.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a Micro-LED wafer bonding method. Background Art

[0002] Compared with traditional LCD display technology, micro-LED array display technology can achieve deeper black, higher color saturation and better display effects because each Micro-LED pixel is an independent light-emitting unit that can emit light independently and does not rely on a backlight. Since the size of each Micro-LED pixel is very small, higher requirements are placed on the precise isolation and efficient integration between pixels during the manufacturing process, especially in high-density integrated applications.

[0003] In the process of manufacturing micro-LED arrays, wafer bonding is generally used to integrate multiple small-sized Micro-LED chips onto a large-sized substrate to greatly improve the yield, reduce the scrap rate of a single chip, and reduce production costs. As far as the inventors are aware, dry etching methods (such as ICP etching and inductively coupled plasma etching) are generally used for etching during wafer bonding. However, the use of dry etching methods often has problems such as difficulty in controlling etching depth and uneven processing. Especially when bonding large-area wafers, traditional dry etching is prone to crosstalk and damage between pixels, thereby affecting the display effect and the long-term stability of the device. In addition, after dry etching, thermal annealing is required for repair, which is prone to thermal damage. Summary of the invention

[0004] The purpose of the present invention is to solve the above-mentioned technical problems and provide a Micro-LED wafer bonding method. On the basis of traditional dry etching, photoelectrochemical etching technology that can perform fine etching under low temperature and low damage conditions is added. Photoelectrochemical etching is used to repair and correct the side walls of Micro-LED pixels, which can avoid the problems of depth control difficulty, excessive damage, non-uniformity and thermal damage that may occur when using dry etching methods throughout the process.

[0005] To achieve the above object, the present invention provides the following solution: The present invention discloses a Micro-LED wafer bonding method, comprising the following steps:

[0006] Step 1: preparing an epitaxial wafer and a driving substrate, wherein the epitaxial wafer includes a substrate layer and a pixel layer, wherein the pixel layer includes a P-pole surface and an N-pole surface, wherein the N-pole surface is attached to the substrate layer and the N-pole surface is away from the substrate layer;

[0007] Step 2: evaporating a metal layer as a p-electrode on the P-pole surface of the pixel layer, and evaporating a bonding layer on the driving substrate, wherein the bonding layer includes a leveling area and a bonding area for electrically connecting to the metal layer, and the bonding area is arranged in the leveling area, and at least the bonding area of ​​the leveling area and the bonding area is made of metal;

[0008] Step 3: bonding the metal layer to the bonding layer, and then peeling off the substrate layer;

[0009] Step 4: etching independent Micro-LED pixels on the pixel layer by dry etching;

[0010] Step 5: vapor-depositing metal Ti on the N-pole surface of the Micro-LED pixel as a hard mask, and repairing the sidewall of the Micro-LED pixel by photoelectrochemical etching;

[0011] Step 6: removing the metal Ti and evaporating a first passivation layer, wherein the first passivation layer covers the Micro-LED pixels and the metal layer;

[0012] Step 7: Opening a first through hole on the first passivation layer in the area between the Micro-LED pixels;

[0013] Step 8: etching away the metal material in the bonding layer by dry etching;

[0014] Step 9: evaporating a second passivation layer, wherein the second passivation layer covers the first through hole, and opening a second through hole on the second passivation layer on the N-pole surface of the Micro-LED pixel;

[0015] Step 10: evaporating an interconnection layer, wherein the interconnection layer covers the second passivation layer and the second through hole, and the interconnection layer is interconnected with the driving substrate to serve as an n-electrode.

[0016] Preferably, the pixel layer includes an N-GaN layer, an MQW layer and a P-GaN layer which are arranged in sequence, the N-GaN layer is in contact with the substrate layer, and the P-GaN layer is away from the substrate layer.

[0017] Preferably, the substrate layer is made of silicon or sapphire.

[0018] Preferably, the leveling area is made of metal, glue or oxide.

[0019] Preferably, in step 6, a wet method is used to remove the metal Ti.

[0020] Preferably, the first passivation layer and the second passivation layer are both formed by depositing silicon oxide.

[0021] Preferably, in step 7, the first through hole is etched out by photolithography.

[0022] Preferably, in step 8, the second through hole is etched out by photolithography.

[0023] Preferably, the dry etching in step 4 adopts ICP etching method, and the dry etching in step 8 adopts IBE etching method.

[0024] Preferably, the interconnection layer is a metal grid or an ITO film.

[0025] Compared with the prior art, the present invention has achieved the following technical effects:

[0026] In the Micro-LED wafer bonding method of the present invention, photoelectrochemical etching technology is added to the basis of traditional dry etching. Dry etching is first used for preliminary etching to form independent Micro-LED pixels, and then photoelectrochemical etching is used to repair and correct the side walls of the Micro-LED pixels. Photoelectrochemical etching can perform fine etching under low temperature and low damage conditions, avoiding excessive damage or unevenness problems that may occur in traditional etching methods. Compared with the traditional dry etching throughout the process, photoelectrochemical etching can not only improve the etching accuracy and effectively realize pixel isolation, but also reduce the damage to the material by etching. It can also complete etching in a shorter time, thereby improving production efficiency. Moreover, photoelectrochemical etching is carried out at a lower temperature, which can also avoid thermal damage that may be caused in the traditional etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 is a schematic diagram of an overall process in a Micro-LED wafer bonding method according to one or more embodiments;

[0029] Figure 2 is a schematic cross-sectional view of a wafer bonding process in a Micro-LED wafer bonding method according to one or more embodiments;

[0030] Figure 3 is a cross-sectional schematic diagram of a dry etching process in a Micro-LED wafer bonding method according to one or more embodiments;

[0031] Figure 4is a schematic cross-sectional view of a metal Ti deposition process in a Micro-LED wafer bonding method according to one or more embodiments;

[0032] Figure 5 is a schematic cross-sectional view of a photoelectrochemical etching process in a Micro-LED wafer bonding method according to one or more embodiments;

[0033] Figure 6 is a cross-sectional schematic diagram of a process of removing metal Ti in a Micro-LED wafer bonding method according to one or more embodiments;

[0034] Figure 7 is a schematic cross-sectional view of a first passivation process in a Micro-LED wafer bonding method according to one or more embodiments;

[0035] Figure 8 is a cross-sectional schematic diagram of a first hole opening process in a Micro-LED wafer bonding method according to one or more embodiments;

[0036] Fig. 9 is a cross-sectional schematic diagram of a process of etching a metal layer in a Micro-LED wafer bonding method according to one or more embodiments;

[0037] Fig.10 is a cross-sectional schematic diagram of a second passivation process in a Micro-LED wafer bonding method according to one or more embodiments;

[0038] Fig.11 is a cross-sectional schematic diagram of a second hole opening process in a Micro-LED wafer bonding method according to one or more embodiments;

[0039] Fig.12 is a schematic cross-sectional view of an interconnect layer deposition process in a Micro-LED wafer bonding method according to one or more embodiments;

[0040] Fig.13 for Figure 7 Schematic diagram of top view;

[0041] Fig.14 for Figure 8 Schematic diagram of top view;

[0042] Fig.15 for Fig.11 Schematic top view of .

[0043] Explanation of the accompanying drawings: 1. substrate layer; 2. N-GaN layer; 3. MQW layer; 4. P-GaN layer; 5. metal layer; 6. leveling area; 7. bonding area; 8. driving substrate; 9. metal Ti; 10. first passivation layer; 11. first through hole; 12. second passivation layer; 13. second through hole; 14. interconnection layer. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] This embodiment provides a Micro-LED wafer bonding method, such as Figures 1 to 15 As shown, the following steps are included:

[0046] Step 1: prepare an epitaxial wafer and a driving substrate 8, wherein the epitaxial wafer includes a substrate layer 1 and a pixel layer, wherein the pixel layer includes a P-pole surface and an N-pole surface, wherein the N-pole surface is in contact with the substrate layer 1, and the P-pole surface is away from the substrate layer 1;

[0047] Step 2: a metal layer 5 is evaporated on the P-pole surface of the pixel layer as a p-electrode, and a bonding layer is evaporated on the driving substrate 8, wherein the bonding layer includes a leveling area 6 and a bonding area 7, wherein the bonding area 7 is used to be electrically connected to the metal layer 5, and the bonding area 7 is arranged in the leveling area 6, wherein the bonding area 7 is used to be electrically connected to the metal layer 5, and wherein at least the bonding area 7 is made of metal material, that is, the leveling area 6 may also be made of metal material or non-metal material; since the P-electrode and the bonding area 7 are connected in a surface-to-surface manner, the leveling area 6 is designed to ensure the flatness of the bonding layer;

[0048] Step 3: Bonding the metal layer 5 to the bonding layer, and then peeling off the substrate layer 1;

[0049] Step 4: Etch independent Micro-LED pixels on the pixel layer through dry etching. This is the initial etching.

[0050] Step 5: Evaporate metal Ti9 on the N-pole surface of the Micro-LED pixel as a hard mask, and repair the sidewall of the Micro-LED pixel by photoelectrochemical etching;

[0051] Step 6: remove the metal Ti9, evaporate the first passivation layer 10, and the first passivation layer 10 covers the Micro-LED pixels and the metal layer 5;

[0052] Step 7: Opening a first through hole 11 on the first passivation layer 10 in the area between the Micro-LED pixels;

[0053] Step 8: etching away the metal material in the bonding layer by dry etching, that is, if the leveling area 6 is made of metal, both the leveling area 6 and the bonding area 7 are etched away; if the leveling area 6 is made of non-metallic material, only the bonding area 7 is etched away;

[0054] Step 9: evaporating a second passivation layer 12, the second passivation layer 12 covers the first passivation layer 10 and the first through hole 11, and opening a second through hole 13 in the second passivation layer 12 on the N-pole surface of the Micro-LED pixel;

[0055] Step 10: evaporate an interconnection layer 14, the interconnection layer 14 covers the second passivation layer 12 and the second through hole 13, and the interconnection layer 14 is interconnected with the driving substrate 8 to serve as an n-electrode.

[0056] The present Micro-LED wafer bonding method first uses dry etching for preliminary etching, first etches out independent Micro-LED pixels, and then uses photoelectrochemical etching technology to repair and correct the Micro-LED pixels. Photoelectrochemical etching technology is a high-precision etching method that combines the advantages of light and electrochemical reactions, can achieve more uniform and precise etching, accurately control etching depth and pixel isolation, reduce sidewall damage, reduce non-radiative recombination of the sidewall of the Micro-LED chip, effectively improve the electrical isolation between pixels, and improve the stability of wafer bonding, without problems such as difficult etching depth control and uneven processing. Moreover, it can be carried out at a lower temperature, thereby avoiding possible thermal damage, further improving the yield and productivity of the entire manufacturing process, and its low damage characteristics and short processing time optimize the production process and reduce manufacturing costs.

[0057] Note: Micro-LED is a micro light emitting diode.

[0058] In one embodiment, if Figures 1 to 15 As shown, the pixel layer includes an N-GaN layer 2, an MQW layer 3 and a P-GaN layer 4 arranged in sequence, the N-GaN layer 2 is attached to the substrate layer 1, and the P-GaN layer 4 is away from the substrate layer 1. Note: GaN is gallium nitride. The N-GaN layer means the gallium nitride layer as the N-terminal end, and the P-GaN layer means the gallium nitride layer as the P-terminal end. MQW is a multiple quantum well.

[0059] In one embodiment, if Figures 1 to 15 As shown, the substrate layer 1 is made of silicon or sapphire.

[0060] In one embodiment, if Figures 1 to 15As shown, the leveling area 6 is made of metal, glue or oxide. If the leveling area 6 is made of metal, then in step 8, both the leveling area 6 and the bonding area 7 are etched away. When the leveling area 6 is made of metal, it can be the same as the metal material of the bonding area 7. When the leveling area 6 is made of glue or oxide, it is considered as mixed bonding. For example, PI (polyimide) / metal, SiO 2 / Cu hybrid bonding.

[0061] In one embodiment, if Figures 1 to 15 As shown, in step 6, a wet method is used to remove metal Ti9.

[0062] In one embodiment, if Figures 1 to 15 As shown, the first passivation layer 10 and the second passivation layer 12 are both formed by depositing silicon oxide.

[0063] In one embodiment, if Figures 1 to 15 As shown, in step 7, the first through hole 11 is etched by photolithography.

[0064] In one embodiment, if Figures 1 to 15 As shown, in step 8, the second through hole 13 is etched out by photolithography.

[0065] In one embodiment, if Figures 1 to 15 As shown, the dry etching in step 4 adopts the ICP etching method, and the dry etching in step 8 adopts the IBE etching method.

[0066] Note: ICP etching (Inductively Coupled Plasma Etching) is a process that uses high-frequency electromagnetic fields to excite gas to generate plasma, and removes materials through physical bombardment and chemical reactions. Its basic principle is to use radio frequency power to excite gas to generate plasma in a vacuum and low-pressure environment. The ions and active particles in the plasma bombard the material surface and react chemically under the action of the electric field, thereby removing the material.

[0067] IBE etching (Ion Beam Etching) is a physical etching method that uses high-energy ion beams to precisely bombard the surface of a material in a directional manner to remove the material. IBE etching has strong directionality and can achieve fine processing of the material surface.

[0068] In one embodiment, if Figures 1 to 15 As shown, the interconnection layer 14 is a metal grid or an ITO film.

[0069] Note: IBE etching (Ion Beam Etching) is a physical etching method that uses high-energy ion beams to precisely bombard the surface of a material in a directional manner to remove the material. IBE etching has strong directionality and can achieve fine processing of the material surface.

[0070] In one embodiment, if Figures 1 to 15 As shown, the interconnection layer 14 is a metal grid or an ITO film. Note: ITO is indium tin oxide.

[0071] In one embodiment, if Figures 1 to 15 As shown, before performing step S1, the following steps are also included, and the following steps are mainly machine learning parts:

[0072] Step 1: Collect key data during the die bonding process, including four main input parameters: pressure, temperature, duration, and warpage level, and the corresponding output parameters: bonding force and yield;

[0073] Step 2: Clean the data and use mean filling or interpolation based on similar samples to handle missing values;

[0074] Step 3: Standardize the input features, such as using Z-score standardization;

[0075] Step 4: Use the Gaussian process regression model to train the preprocessed data;

[0076] Step 5: Select an appropriate kernel function to capture the correlation between input parameters and provide a confidence interval for the prediction results;

[0077] Step 6: Evaluate model performance using cross-validation method;

[0078] Step 7: Optimize the hyperparameters of the kernel function by maximizing the marginal likelihood function;

[0079] Step 8: Use mean square error (MSE), mean absolute error (MAE), and coefficient of determination (R 2 ) and other evaluation indicators to comprehensively measure the prediction performance of the Gaussian process regression model;

[0080] Step 9: Use the trained Gaussian process regression model in combination with the Bayesian optimization algorithm to find the input parameter combination that maximizes the bonding yield;

[0081] Step 10: Determine the input parameter combination that maximizes the bonding yield and optimize the production process.

[0082] The present invention uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A Micro-LED wafer bonding method, characterized in that: The following steps are involved: Step 1: preparing an epitaxial wafer and a driving substrate, wherein the epitaxial wafer includes a substrate layer and a pixel layer, wherein the pixel layer includes a P-pole surface and an N-pole surface, wherein the N-pole surface is attached to the substrate layer and the N-pole surface is away from the substrate layer; Step 2: evaporating a metal layer as a p-electrode on the P-pole surface of the pixel layer, and evaporating a bonding layer on the driving substrate, wherein the bonding layer includes a leveling area and a bonding area for electrically connecting to the metal layer, and the bonding area is arranged in the leveling area, and at least the bonding area of ​​the leveling area and the bonding area is made of metal; Step 3: bonding the metal layer to the bonding layer, and then peeling off the substrate layer; Step 4: etching independent Micro-LED pixels on the pixel layer by dry etching; Step 5: vapor-depositing metal Ti on the N-pole surface of the Micro-LED pixel as a hard mask, and repairing the sidewall of the Micro-LED pixel by photoelectrochemical etching; Step 6: removing the metal Ti and evaporating a first passivation layer, wherein the first passivation layer covers the Micro-LED pixels and the metal layer; Step 7: Opening a first through hole on the first passivation layer in the area between the Micro-LED pixels; Step 8: etching away the metal material in the bonding layer by dry etching; Step 9: evaporating a second passivation layer, wherein the second passivation layer covers the first through hole, and opening a second through hole on the second passivation layer on the N-pole surface of the Micro-LED pixel; Step 10: evaporating an interconnection layer, wherein the interconnection layer covers the second passivation layer and the second through hole, and the interconnection layer is interconnected with the driving substrate to serve as an n-electrode.

2. The Micro-LED wafer bonding method according to claim 1, characterized in that: The pixel layer includes an N-GaN layer, an MQW layer, and a P-GaN layer which are arranged in sequence. The N-GaN layer is attached to the substrate layer, and the P-GaN layer is away from the substrate layer.

3. The Micro-LED wafer bonding method according to claim 1 or 2, characterized in that: The substrate layer is made of silicon or sapphire.

4. The Micro-LED wafer bonding method according to claim 1, characterized in that: The leveling area is made of metal, glue or oxide.

5. The Micro-LED wafer bonding method according to claim 1, characterized in that: In step 6, a wet method is used to remove the metal Ti.

6. The Micro-LED wafer bonding method according to claim 1, characterized in that: The first passivation layer and the second passivation layer are both formed by depositing silicon oxide.

7. The Micro-LED wafer bonding method according to claim 1, characterized in that: In step 7, the first through hole is etched out by photolithography.

8. The Micro-LED wafer bonding method according to claim 1, characterized in that: In step 8, the second through hole is etched out by photolithography.

9. The Micro-LED wafer bonding method according to claim 1 or 8, characterized in that: The dry etching in step 4 adopts ICP etching method, and the dry etching in step 8 adopts IBE etching method.

10. The Micro-LED wafer bonding method according to claim 1, characterized in that: The interconnection layer is a metal grid or an ITO film.

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