Micro-led wafer bonding method

Abstract

The application discloses a Micro-LED wafer bonding method, and belongs to the technical field of display, comprising the following steps: step 1: preparing an epitaxial wafer and a driving substrate, the epitaxial wafer comprising a substrate layer and a pixel layer; step 2: evaporating a metal layer on the pixel layer as a p electrode, and evaporating a bonding layer on the driving substrate; step 3: bonding the metal layer and the bonding layer, and peeling off the substrate layer; step 4: etching the Micro-LED pixel; step 5: evaporating metal Ti, and repairing the sidewall of the Micro-LED pixel through photoelectrochemical etching; step 6: removing the metal Ti, and evaporating a first passivation layer; step 7: opening a first through hole; step 8: etching away the metal material in the bonding layer; step 9: evaporating a second passivation layer; and step 10: evaporating an interconnection layer, and interconnecting the interconnection layer and the driving substrate as an n electrode. The sidewall of the Micro-LED pixel is repaired and corrected through photoelectrochemical etching, so that the problems of difficult depth control, excessive damage, non-uniformity and thermal damage that may occur in the whole process of using a dry etching method can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a Micro-LED wafer bonding method. BACKGROUND

[0002] Compared with the traditional LCD display technology, the micro-LED array display technology can realize deeper black, higher color saturation and better display effect because each Micro-LED pixel is an independent light-emitting unit and can emit light independently without relying on a backlight source. Due to the very small size of each Micro-LED pixel, higher requirements are put forward for accurate isolation and efficient integration between pixels during the manufacturing process, especially in high-density integrated applications.

[0003] In the process of manufacturing a micro-LED array, wafer bonding methods are generally used to integrate multiple small-size Micro-LED chips onto a large-size substrate to greatly improve the yield, reduce the scrap rate of individual chips and reduce production costs. In the inventor's knowledge, at present, when wafer bonding is performed, a dry etching method (such as ICP etching, inductive coupled plasma etching) is generally used for etching, but the dry etching method often has problems such as difficulty in controlling etching depth, uneven processing, etc. Especially in large-area wafer bonding, traditional dry etching can easily cause cross-talk and damage between pixels, thereby affecting the display effect and the long-term stability of the device. In addition, after dry etching, thermal annealing is required for repair, which can easily cause thermal damage. SUMMARY

[0004] The purpose of the present application is to solve the above technical problems and provide a Micro-LED wafer bonding method. On the basis of traditional dry etching, a photoelectrochemical etching technology capable of fine etching under low-temperature and low-damage conditions is added. The photoelectrochemical etching is used to repair and correct the sidewall of the Micro-LED pixel, which can avoid problems such as difficulty in controlling etching depth, excessive damage, unevenness and thermal damage that may occur when using a dry etching method throughout the process.

[0005] To achieve the above-mentioned purpose, the present application provides the following solutions: the present application discloses a Micro-LED wafer bonding method, comprising the following steps:

[0006] Step 1: Prepare an epitaxial wafer and a driving substrate, the epitaxial wafer includes a substrate layer and a pixel layer, the pixel layer includes a P-pole surface and an N-pole surface, the N-pole surface is attached to the substrate layer, and the N-pole surface faces away from the substrate layer;

[0007] Step 2: evaporating a metal layer on the P-pole surface of the pixel layer as a p electrode, evaporating a bonding layer on the driving substrate, the bonding layer comprising a planarization area and a bonding area for electrical connection with the metal layer, the bonding area being arranged in the planarization area, at least the bonding area of the planarization area and the bonding area being of metal material;

[0008] Step 3: bonding the metal layer with the bonding layer, and then peeling off the substrate layer;

[0009] Step 4: etching independent Micro-LED pixels on the pixel layer by dry etching;

[0010] Step 5: evaporating metal Ti on the N-pole surface of the Micro-LED pixels as a hard mask, and repairing the sidewalls of the Micro-LED pixels by photoelectrochemical etching;

[0011] Step 6: removing the metal Ti, and evaporating a first passivation layer, the first passivation layer covering the Micro-LED pixels and the metal layer;

[0012] Step 7: opening a first via hole in the first passivation layer at the area between the Micro-LED pixels;

[0013] Step 8: etching away the metal material in the bonding layer by dry etching;

[0014] Step 9: evaporating a second passivation layer, the second passivation layer covering the first via hole, and opening a second via hole in the second passivation layer on the N-pole surface of the Micro-LED pixels;

[0015] Step 10: evaporating an interconnection layer, the interconnection layer covering the second passivation layer and the second via hole, the interconnection layer being interconnected with the driving substrate as an n electrode.

[0016] Preferably, the pixel layer comprises an N-GaN layer, an MQW layer and a P-GaN layer arranged in sequence, the N-GaN layer being attached to the substrate layer, and the P-GaN layer facing away from the substrate layer.

[0017] Preferably, the substrate layer is of silicon material or sapphire material.

[0018] Preferably, the planarization area is of metal material, glue material or oxide material.

[0019] Preferably, the metal Ti is removed by wet method in step 6.

[0020] Preferably, the first passivation layer and the second passivation layer are both deposited by silicon oxide.

[0021] Preferably, in step 7, the first via hole is etched by photoetching.

[0022] Preferably, in step 8, the second via hole is etched by photoetching.

[0023] Preferably, the dry etching in step 4 adopts ICP etching method, and the dry etching in step 8 adopts IBE etching method.

[0024] Preferably, the interconnection layer is a metal mesh or an ITO film.

[0025] The present application has the following technical effects relative to the prior art:

[0026] In the Micro-LED wafer bonding method of the present application, on the basis of traditional dry etching, photoelectrochemical etching technology is added, dry etching is first used for preliminary etching to form independent Micro-LED pixels, and then photoelectrochemical etching is used to repair and correct the sidewalls of the Micro-LED pixels. Photoelectrochemical etching can perform fine etching under low temperature and low damage conditions, avoiding the problems of excessive damage or non-uniformity that may occur in traditional etching methods. Compared with traditional dry etching, photoelectrochemical etching not only improves etching precision and effectively realizes pixel isolation, but also reduces damage to materials during etching, completes etching in a shorter time, improves production efficiency, and avoids thermal damage that may be caused in the traditional etching process. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0028] Figure 1 is a schematic diagram of the overall process in the Micro-LED wafer bonding method according to one or more embodiments;

[0029] Figure 2 is a cross-sectional view of the wafer bonding process in the Micro-LED wafer bonding method according to one or more embodiments;

[0030] Figure 3 is a cross-sectional view of the dry etching process in the Micro-LED wafer bonding method according to one or more embodiments;

[0031] Figure 4is a cross-sectional view of a metal Ti deposition process in a Micro-LED wafer bonding method according to one or more embodiments;

[0032] Figure 5 is a cross-sectional view of a photoelectrochemical etching process in a Micro-LED wafer bonding method according to one or more embodiments;

[0033] Figure 6 is a cross-sectional view of a metal Ti removal process in a Micro-LED wafer bonding method according to one or more embodiments;

[0034] Figure 7 is a cross-sectional view of a first passivation process in a Micro-LED wafer bonding method according to one or more embodiments;

[0035] Figure 8 is a cross-sectional view of a first via process in a Micro-LED wafer bonding method according to one or more embodiments;

[0036] Figure 9 is a cross-sectional view of an etching metal layer process in a Micro-LED wafer bonding method according to one or more embodiments;

[0037] Figure 10 is a cross-sectional view of a second passivation process in a Micro-LED wafer bonding method according to one or more embodiments;

[0038] Figure 11 is a cross-sectional view of a second via process in a Micro-LED wafer bonding method according to one or more embodiments;

[0039] Figure 12 is a cross-sectional view of an interconnection layer deposition process in a Micro-LED wafer bonding method according to one or more embodiments;

[0040] Figure 13 is a top view of Figure 7 ;

[0041] Figure 14 is a top view of Figure 8 ;

[0042] Figure 15 is a top view of Figure 11 .

[0043] Explanation of reference signs: 1, substrate layer; 2, N-GaN layer; 3, MQW layer; 4, P-GaN layer; 5, metal layer; 6, planarization area; 7, bonding area; 8, driving substrate; 9, metal Ti; 10, first passivation layer; 11, first via hole; 12, second passivation layer; 13, second via hole; 14, interconnection layer. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0045] The present embodiment provides a Micro-LED wafer bonding method, as shown in the figure, comprising the following steps: Figures 1 to 15

[0046] Step 1: Prepare an epitaxial wafer and a driving substrate 8, the epitaxial wafer includes a substrate layer 1 and a pixel layer, the pixel layer includes a P-pole surface and an N-pole surface, the N-pole surface is attached to the substrate layer 1, and the P-pole surface is away from the substrate layer 1;

[0047] Step 2: Evaporate a metal layer 5 as a p-electrode on the P-pole surface of the pixel layer, and evaporate a bonding layer on the driving substrate 8, the bonding layer includes a planarization area 6 and a bonding area 7, the bonding area 7 is used for electrical connection with the metal layer 5, the bonding area 7 is arranged in the planarization area 6, the bonding area 7 is used for electrical connection with the metal layer 5, and at least the bonding area 7 in the planarization area 6 and the bonding area 7 is made of metal material, that is, the planarization area 6 can also be made of metal material, or can also be made of non-metal material; since the P-electrode and the bonding area 7 are connected in a surface-to-surface manner, the planarization area 6 is designed to ensure the planarization of the bonding layer;

[0048] Step 3: Bond the metal layer 5 and the bonding layer, and then peel off the substrate layer 1;

[0049] Step 4: Etch independent Micro-LED pixels on the pixel layer by dry etching, which is a preliminary etching;

[0050] Step 5: Evaporate metal Ti 9 as a hard mask on the N-pole surface of the Micro-LED pixel, and repair the side wall of the Micro-LED pixel by photoelectrochemical etching;

[0051] Step 6: Remove the metal Ti 9, evaporate a first passivation layer 10, and the first passivation layer 10 covers the Micro-LED pixel and the metal layer 5;

[0052] ​Step 7: Open a first via hole 11 on the first passivation layer 10 at the area between the Micro-LED pixels;

[0053] Step 8: Etch off the metal material in the bonding layer by dry etching, that is, if the flattening area 6 is a metal material, then the flattening area 6 and the bonding area 7 are etched off, if the flattening area 6 is a non-metal material, then only the bonding area 7 is etched off;

[0054] Step 9: Evaporate a second passivation layer 12, the second passivation layer 12 covers the first passivation layer 10 and the first via hole 11, and a second via hole 13 is opened on the second passivation layer 12 on the N-pole surface of the Micro-LED pixel;

[0055] Step 10: Evaporate an interconnection layer 14, the interconnection layer 14 covers the second passivation layer 12 and the second via hole 13, and the interconnection layer 14 is interconnected with the driving substrate 8 as an n-electrode.

[0056] The Micro-LED wafer bonding method first uses dry etching for preliminary etching, first etching out independent Micro-LED pixels, and then using photoelectrochemical etching technology to repair and correct the Micro-LED pixels. The photoelectrochemical etching technology is a high-precision etching method that combines the advantages of light and electrochemical reaction, can realize more uniform and accurate etching, accurately control the etching depth and pixel isolation, reduce the sidewall damage, reduce the non-radiative recombination of the Micro-LED chip sidewall, effectively improve the electrical isolation between the pixels, and improve the stability of the wafer bonding, without problems such as difficult etching depth control and uneven processing. Moreover, it can be carried out at a relatively low temperature, thereby avoiding possible thermal damage, further improving the yield and productivity of the entire manufacturing process, and optimizing the production process with low damage characteristics and short processing time, thereby reducing the manufacturing cost.

[0057] Note: Micro-LED is a micro light-emitting diode.

[0058] In an embodiment, as shown in Figures 1 to 15 , the pixel layer includes an N-GaN layer 2, an MQW layer 3, and a P-GaN layer 4 arranged in sequence, the N-GaN layer 2 is attached to the substrate layer 1, and the P-GaN layer 4 faces away from the substrate layer 1. Note: GaN is gallium nitride. The N-GaN layer means a gallium nitride layer as an N-pole end, and the P-GaN layer means a gallium nitride layer as a P-pole end. MQW is a multi-quantum well.

[0059] In an embodiment, as shown in Figures 1 to 15 , the substrate layer 1 is made of silicon or sapphire.

[0060] In an embodiment, as shown in Figures 1 to 15As shown, the planarization region 6 is made of metal, glue or oxide. If the planarization region 6 is made of metal, it is etched together with the bonding region 7 in step 8. If the planarization region 6 is made of metal, it can be the same as the metal of the bonding region 7, or if the planarization region 6 is made of glue or oxide, it is considered as hybrid bonding, such as PI (polyimide) / metal, SiO2 / Cu hybrid bonding.

[0061] In an embodiment, as shown in FIG. 6, the metal Ti 9 is removed by wet etching in step 6. Figures 1 to 15

[0062] In an embodiment, as shown in FIG. 6, the metal Ti 9 is removed by wet etching in step 6. Figures 1 to 15

[0063] In an embodiment, as shown in FIG. 6, the metal Ti 9 is removed by wet etching in step 6. Figures 1 to 15

[0064] In an embodiment, as shown in FIG. 6, the metal Ti 9 is removed by wet etching in step 6. Figures 1 to 15

[0065] In an embodiment, as shown in FIG. 6, the metal Ti 9 is removed by wet etching in step 6. Figures 1 to 15

[0066] Note: ICP etching (Inductively Coupled Plasma Etching) is a process method that uses high-frequency electromagnetic field to excite gas to generate plasma, and removes materials through physical bombardment and chemical reaction. The basic principle is that in a vacuum low-pressure environment, the gas is excited to generate plasma by a radio frequency power source. The ions and active particles in the plasma perform bombardment and chemical reaction on the material surface under the action of the electric field, thereby removing the material.

[0067] IBE etching (Ion Beam Etching) is a physical etching method that uses high-energy ion beams to accurately bombard the material surface to remove the material. IBE etching has strong directionality and can achieve fine processing of the material surface.

[0068] In an embodiment, as shown in FIG. 6, the metal Ti 9 is removed by wet etching in step 6. Figures 1 to 15

[0069] Note: IBE etching (Ion Beam Etching) is a physical etching method that uses high-energy ion beams to accurately bombard the material surface to remove the material. IBE etching has strong directionality and can achieve fine processing of the material surface.​​​​​​

[0070] In an embodiment, as shown in FIG. 1, the interconnection layer 14 is a metal mesh or an ITO film. ITO stands for indium tin oxide. Figures 1 to 15

[0071] In an embodiment, as shown in FIG. 2, before step S1, the following steps are further included, which are mainly for the machine learning part: Figures 1 to 15

[0072] Step 1: Collect key data in the chip bonding process, including four main input parameters: pressure, temperature, duration and warpage level, and corresponding output parameters: bonding force and yield rate;

[0073] Step 2: Clean the data, and use mean imputation or interpolation method based on similar samples to handle missing values;

[0074] Step 3: Standardize the input features, such as using Z-score standardization;

[0075] Step 4: Train the preprocessed data using Gaussian process regression model;

[0076] Step 5: Select a suitable kernel function to capture the correlation between input parameters and provide a confidence interval for the prediction result;

[0077] Step 6: Evaluate the model performance using cross-validation method;

[0078] Step 7: Optimize the hyperparameters of the kernel function by maximizing the marginal likelihood function;

[0079] Step 8: Use evaluation indicators such as mean squared error (MSE), mean absolute error (MAE) and coefficient of determination (R 2 ) to comprehensively measure the prediction performance of the Gaussian process regression model;

[0080] Step 9: Use the trained Gaussian process regression model and combine it with the Bayesian optimization algorithm to find the input parameter combination that maximizes the bonding yield rate;

[0081] Step 10: Determine the input parameter combination that maximizes the bonding yield rate to optimize the production process.

[0082] The specific examples in the present application are used to illustrate the principles and implementation methods of the present application. The above examples are only used to help understand the method and core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation method and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.​​

Claims

1. A method for bonding a Micro-LED wafer, characterized in that, The method comprises the following steps: Step 1: preparing an epitaxial wafer and a driving substrate, the epitaxial wafer comprising a substrate layer and a pixel layer, the pixel layer comprising a P-pole surface and an N-pole surface, the N-pole surface being attached to the substrate layer and facing away from the substrate layer; Step 2: evaporating a metal layer on the P-pole surface of the pixel layer as a p electrode, and evaporating a bonding layer on the driving substrate, the bonding layer comprising a planarization area and a bonding area for electrical connection with the metal layer, the bonding area being arranged in the planarization area, at least the bonding area of the planarization area and the bonding area being made of metal; Step 3: bonding the metal layer with the bonding layer, and then peeling off the substrate layer; Step 4: etching independent Micro-LED pixels on the pixel layer by dry etching; Step 5: evaporating metal Ti on the N-pole surface of the Micro-LED pixels as a hard mask, and repairing the sidewalls of the Micro-LED pixels by photoelectrochemical etching; Step 6: removing the metal Ti, evaporating a first passivation layer, and the first passivation layer covering the Micro-LED pixels and the metal layer; Step 7: opening a first via hole in the first passivation layer at the area between the Micro-LED pixels; Step 8: etching away the metal material in the bonding layer by dry etching; Step 9: evaporating a second passivation layer, the second passivation layer covering the first via hole, and opening a second via hole in the second passivation layer on the N-pole surface of the Micro-LED pixels; Step 10: evaporating an interconnection layer, the interconnection layer covering the second passivation layer and the second via hole, and the interconnection layer being interconnected with the driving substrate as an n electrode.

2. The method of claim 1, wherein the Micro-LED wafer bonding method is characterized by, The pixel layer comprises an N-GaN layer, an MQW layer and a P-GaN layer arranged in sequence, the N-GaN layer being attached to the substrate layer, and the P-GaN layer facing away from the substrate layer.

3. The method of claim 1 or 2, wherein the method further comprises: The substrate layer is made of silicon or sapphire.

4. The method of claim 1, wherein the Micro-LED wafer bonding method is characterized by, The planarization area is made of metal, glue or oxide.

5. The method of claim 1, wherein, The metal Ti is removed by wet etching in step 6.

6. The Micro-LED wafer bonding method of claim 1, wherein, The first passivation layer and the second passivation layer are both deposited by silicon oxide.

7. The method of claim 1, wherein the Micro-LED wafer bonding method is characterized by, The first via hole is etched by photolithography etching in step 7.

8. The Micro-LED wafer bonding method of claim 1, wherein, The second via hole is etched by photolithography etching in step 8.

9. The method of claim 1 or 8, wherein, The dry etching in step 4 adopts ICP etching method, and the dry etching in step 8 adopts IBE etching method.

10. The Micro-LED wafer bonding method of claim 1, wherein, The interconnection layer is a metal mesh or an ITO thin film.

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