Display device, method for manufacturing the same, and electronic device including the same

Abstract

A display device, a method for manufacturing the same, and an electronic device including the same are provided. According to one or more embodiments of the present disclosure, a display device includes: a substrate; a bank on the substrate and including an opening; a pixel electrode and a common electrode spaced apart from each other in the opening on the substrate; an organic layer on the pixel electrode and the common electrode in the opening; a light emitting element on the organic layer, and including a first electrode and a second electrode on a top surface of the light emitting element; a first connection electrode connected to the pixel electrode and the first electrode of the light emitting element; and a second connection electrode connected to the common electrode and the second electrode of the light emitting element. The organic layer is on at least a portion of one side surface of the light emitting element and the bottom surface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0148181 filed on October 31, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] One or more embodiments of the present disclosure relate to a display device, a method for manufacturing the same, and an electronic device including the same. Background Art

[0004] With the development of an information-oriented society, there is an increasing demand for display devices for displaying images in various ways. The display device may be a flat panel display device such as a liquid crystal display, a field emission display, and a light-emitting display. The light-emitting display may include an organic light-emitting display including an organic light-emitting diode element as a light-emitting element and an ultra-small light-emitting display including an ultra-small light-emitting diode element (hereinafter, referred to as a micro light-emitting diode element) as a light-emitting element.

[0005] When the micro-luminescent element is a vertical micro-luminescent element in which a first semiconductor layer, an active layer, a second semiconductor layer and an undoped semiconductor layer are stacked sequentially in a vertical direction, the resistance of the undoped semiconductor layer is high, so that the luminous efficiency of the micro-luminescent element may be reduced or the micro-luminescent element may not emit light. Summary of the invention

[0006] Aspects and features of embodiments of the present disclosure provide a display device and a method for manufacturing the same that can reduce or prevent a reduction in luminous efficiency of a micro-light-emitting element or a failure of the micro-light-emitting element to emit light due to resistance of an undoped semiconductor layer.

[0007] However, the present disclosure is not limited to the aspects and features set forth herein. The above and other embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one or more embodiments of the present disclosure, a display device is provided, including: a substrate; a bank on the substrate and including an opening; a pixel electrode and a common electrode spaced apart from each other in the opening on the substrate; an organic layer on the pixel electrode and the common electrode in the opening; a light-emitting element on the organic layer and including a first electrode and a second electrode on a top surface of the light-emitting element; a first connection electrode connected to the pixel electrode and the first electrode of the light-emitting element; and a second connection electrode connected to the common electrode and the second electrode of the light-emitting element. The organic layer is on at least a portion of one side surface and a bottom surface of the light-emitting element.

[0009] The first connection electrode may be on the organic layer between the bank and one side surface of the light emitting element. The second connection electrode may be on the organic layer between the bank and the other side surface of the light emitting element. The other side surface of the light emitting element may be a side surface opposite to the one side surface of the light emitting element.

[0010] The thickness of the organic layer may be smaller than the thickness of the bank.

[0011] The light emitting element may include: a first semiconductor layer connected to the first electrode; an active layer connected to the first semiconductor layer; a second semiconductor layer including a first portion connected to the active layer and a second portion connected to the second electrode; and an undoped semiconductor layer connected to the second semiconductor layer.

[0012] The thickness of the first portion of the second semiconductor layer may be greater than the thickness of the second portion of the second semiconductor layer.

[0013] The undoped semiconductor layer may be on the organic layer. The second semiconductor layer may be on the undoped semiconductor layer. The active layer may be on the first portion of the second semiconductor layer. The first semiconductor layer may be on the active layer. The first electrode may be on the first semiconductor layer. The second electrode may be on the second portion of the second semiconductor layer.

[0014] The thickness of the second electrode may be greater than the thickness of the first electrode.

[0015] The organic layer may be on at least a portion of one side surface of the second semiconductor layer and a side surface and a bottom surface of the undoped semiconductor layer.

[0016] The first connection electrode may be on at least a portion of one side surface of the second semiconductor layer, one side surface of the first semiconductor layer, and one side surface of the active layer.

[0017] The second connection electrode may be on at least a portion of one side surface of the second electrode.

[0018] The second connection electrode may be on at least a portion of a top surface of the second electrode and an entire one side surface of the second electrode.

[0019] The organic layer may be on at least a portion of a top surface of the second portion of the second semiconductor layer.

[0020] An area of ​​the organic layer may be greater than an area of ​​the first connection electrode and an area of ​​the second connection electrode.

[0021] The area of ​​the pixel electrode may be larger than that of the first connection electrode. The area of ​​the common electrode may be larger than that of the second connection electrode.

[0022] The pixel electrode and the common electrode may include an opaque metal material. The first connection electrode and the second connection electrode may include a transparent conductive oxide.

[0023] The thickness of the bank may be about 0.5 μm or more.

[0024] According to one or more embodiments of the present disclosure, a method for manufacturing a display device is provided, including: preparing a plurality of light-emitting elements on a light-emitting element substrate; forming a dam having a plurality of openings on the substrate, and forming a pixel electrode and a common electrode in each of the plurality of openings; forming an organic layer on the pixel electrode and the common electrode in each of the plurality of openings; adhering each of the plurality of light-emitting elements on the light-emitting element substrate to the organic layer in each of the plurality of openings; and forming a first connecting electrode connecting the pixel electrode to a first electrode of the light-emitting element and a second connecting electrode connecting the common electrode to a second electrode of the light-emitting element on the organic layer.

[0025] The method may also include: forming a light blocking layer on the embankment; in the area separated by the light blocking layer, forming a first light conversion layer in the area corresponding to the first sub-pixel, forming a second light conversion layer in the area corresponding to the second sub-pixel, and forming a light-transmitting layer in the area corresponding to the third sub-pixel; and forming a first color filter on the first light conversion layer, forming a second color filter on the second light conversion layer, and forming a third color filter on the light-transmitting layer.

[0026] Adhering each of a plurality of light-emitting elements on a light-emitting element substrate to an organic layer in each of a plurality of openings may include: curing the organic layer in each of the plurality of openings at a first temperature; inserting a portion of each of the plurality of light-emitting elements into the organic layer in each of the plurality of openings; and curing the organic layer at a second temperature higher than the first temperature.

[0027] Adhering each of the plurality of light-emitting elements on the light-emitting element substrate to the organic layer in each of the plurality of openings may include: detaching each of the plurality of light-emitting elements from the light-emitting element substrate by using a stamp having an adhesive layer; inserting a portion of each of the plurality of light-emitting elements into the organic layer in each of the plurality of openings; and detaching each of the plurality of light-emitting elements from the stamp by applying heat to the adhesive layer of the stamp.

[0028] According to one or more embodiments of the present disclosure, an electronic device for providing an image is provided, the electronic device including a display device. The display device includes a substrate; a bank on the substrate and including an opening; a pixel electrode and a common electrode spaced apart from each other on the substrate in the opening; an organic layer on the pixel electrode and the common electrode in the opening; a light-emitting element on the organic layer and including a first electrode and a second electrode on a top surface thereof; a first connecting electrode connected to the pixel electrode and the first electrode of the light-emitting element; and a second connecting electrode connected to the common electrode and the second electrode of the light-emitting element, wherein the organic layer is on at least a portion of a bottom surface and a side surface of the light-emitting element.

[0029] According to one or more embodiments of the present disclosure, a display device is provided, including: a substrate; a pixel electrode and a common electrode, which are spaced apart from each other on the substrate; an insulating layer, which is on the substrate and at least partially overlaps with the pixel electrode and the common electrode; a light-emitting element, which is on the insulating layer and includes a first electrode and a second electrode; a first connecting electrode, which is electrically connected to the pixel electrode and the first electrode of the light-emitting element; and a second connecting electrode, which is electrically connected to the common electrode and the second electrode of the light-emitting element. At least one of the first electrode and the second electrode of the light-emitting element includes a region exposed by the insulating layer.

[0030] According to the foregoing and other embodiments of the present disclosure, both the first electrode and the second electrode of the light-emitting element are on one surface of the light-emitting element, so that the current of the light-emitting element flows through the first electrode, the first semiconductor layer, the active layer, the first part of the second semiconductor layer, the second part of the second semiconductor layer, and the second electrode. Therefore, since the current of the light-emitting element does not flow through the undoped semiconductor layer, the reduction in the luminous efficiency of the micro-light-emitting element or the failure of the micro-light-emitting element to emit light due to the resistance of the undoped semiconductor layer can be reduced or prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other embodiments and features of the present disclosure will become more apparent by describing embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a perspective view showing a display device according to one or more embodiments;

[0033] Figure 2 is a layout diagram showing a display device according to one or more embodiments;

[0034] Figure 3 is a block diagram showing a display device according to one or more embodiments;

[0035] Figure 4is an equivalent circuit diagram showing a sub-pixel according to one or more embodiments;

[0036] Figure 5 is an equivalent circuit diagram showing a sub-pixel according to one or more embodiments;

[0037] Figure 6 is a layout diagram showing a second power line and a plurality of pixels in a display area according to one or more embodiments;

[0038] Figure 7 It is shown in detail Figure 6 An example layout diagram of area A;

[0039] Figure 8 is a diagram showing the display panel and Figure 6 Cross-sectional views of examples of cross sections corresponding to lines I1-I1', I2-I2' and I3-I3';

[0040] Fig.9A and Fig. 9B is a diagram showing the light emitting element and Figure 6 A cross-sectional view of an example of a cross section corresponding to line I2-I2';

[0041] Fig.10 It is shown in detail Figure 6 A layout diagram of another example of area A;

[0042] Fig.11 is a diagram showing the light emitting element and Figure 6 A cross-sectional view of an example of a cross section corresponding to line I3-I3';

[0043] Fig.12 is a flowchart illustrating a method for manufacturing a display device according to one or more embodiments;

[0044] Figures 13 to 19 is a cross-sectional view illustrating a method for manufacturing a display device according to one or more embodiments;

[0045] Fig. 20 It is shown in detail Fig.12 Flow chart of step S110;

[0046] Figure 21 to Figure 27 is a cross-sectional view for explaining step S110;

[0047] Fig.28 is a diagram showing a virtual reality device including a display device according to one or more embodiments;

[0048] Fig.29 is a diagram showing a smart watch including a display device according to one or more embodiments;

[0049] Fig.30 is a diagram showing a dashboard and a center instrument panel of a car including a display device according to one or more embodiments; and

[0050] Fig.31 is a diagram illustrating a transparent display device including a display device according to one or more embodiments. DETAILED DESCRIPTION

[0051] By referring to the detailed description and the accompanying drawings of the embodiments, the aspects and features of the embodiments of the present disclosure and the methods for realizing the same can be more easily understood. Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the present disclosure will be fully conveyed to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described.

[0052] Unless otherwise specified, throughout the drawings and written description, the same reference numerals, characters, or combinations thereof denote the same elements, and therefore, description thereof will not be repeated. In addition, parts not related to the description of one or more embodiments may not be shown to make the description clear.

[0053] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0054] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes of the figures due to, for example, manufacturing techniques and / or tolerances should be expected. In addition, the specific structural or functional descriptions disclosed herein are merely exemplary for the purpose of describing embodiments according to the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the specifically shown regions, but should include deviations in shapes due to, for example, manufacturing.

[0055] For example, an implanted region shown as a rectangle may have rounded or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to be limiting. In addition, as will be appreciated by those skilled in the art, the described embodiments may be modified in a variety of different ways without departing from the spirit and / or scope of the present disclosure.

[0056] In the detailed description, for the purpose of illustration, many specific details are set forth to provide a thorough understanding of various embodiments. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessary confusion of various embodiments.

[0057] For ease of explanation, spatial relative terms such as "below", "below", "down", "below", "above", "on", etc. may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the drawings is turned over, the element described as "below" or "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both above and below orientations. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged at the upper side or lower side of the second part based on the direction of gravity, without being limited to its upper side.

[0058] Furthermore, in this specification, the phrase “on a plane” or “in a plan view” means observing a target portion from the top, and the phrase “in a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0059] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to another element, layer, region, or component or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to another element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to another layer, region, and / or component, or there may be intervening layers, regions, or components. However, "directly connected / directly coupled" refers to a component that is directly connected or directly coupled to another component without an intermediate component. Meanwhile, other expressions describing the relationship between components such as "between," "directly between," or "adjacent to" and "directly adjacent to" can be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0060] For the purposes of the present disclosure, expressions such as "at least one of," "one of," and "selected from," when placed after / before a list of elements, modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of X, Y, and Z," and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as, for example, XYZ, XYY, XZ, YZ, and ZZ, or any variation thereof. Similarly, expressions such as "at least one of A and B" can include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "A and / or B" can include A, B, or A and B. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0061] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first part described below may be referred to as the second element, second component, second region, second layer or second part.

[0062] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0063] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes" and "including" specify the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0064] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms and not as terms of degree, and are intended to allow for inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. In view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "approximately" as used herein include the value and mean within an acceptable range of deviations of the particular value as determined by one of ordinary skill in the art. For example, the term "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0065] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in the reverse order of the described order.

[0066] In addition, any numerical range disclosed and / or cited herein is intended to include all sub-ranges of the same numerical precision contained in the range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value 1.0 and the maximum value 10.0 (and including 1.0 and 10.0), for example, with a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including claims) to explicitly describe any sub-range contained in the scope explicitly described herein. All such ranges are intended to be inherently described in this specification so that the modification for explicitly describing any such sub-range will meet the requirements of Article 33 of the Chinese Patent Law.

[0067] The electronic device or electrical device and / or any other related device or component according to one or more embodiments of the present disclosure described herein can be implemented using any appropriate hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip and / or formed on separate IC chips. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), and / or formed on a substrate.

[0068] In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functions described herein. Computer program instructions are stored in a memory that can be implemented in a computing device using standard storage devices, such as, for example, a random access memory (RAM). Computer program instructions can also be stored in other non-transitory computer-readable media, such as, for example, a CD-ROM, a flash drive, etc. In addition, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, and / or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the spirit and scope of the present disclosure.

[0069] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0070] refer to Figure 1 The display device 10 is a device for displaying moving images and / or still images. The display device 10 can be used as a display screen of various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and / or ultra mobile PCs (UMPCs).

[0071] The display device 10 may be a light-emitting display device such as an organic light-emitting display using an organic light-emitting diode (OLED), a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro-light-emitting display using a micro- or nano-light-emitting diode (LED). In the following description, it is assumed that the display device 10 is a micro-light-emitting display device, but the present disclosure is not limited thereto. In order to simplify the description, the ultra-small light-emitting diode is referred to as a light-emitting element hereinafter.

[0072] The display device 10 includes a display panel 100 , a display driving circuit 250 , a circuit board 300 , and a power supply circuit 500 .

[0073] In a plan view, the display panel 100 may be formed in a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have an appropriate curvature (e.g., a predetermined curvature), or may be at right angles. The planar shape of the display panel 100 is not limited to a rectangular shape, and may be formed in another polygonal shape, a circular shape, or an elliptical shape. The display panel 100 may be formed to be flat, but is not limited thereto. For example, the display panel 100 may include a curved portion formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel 100 may be flexibly formed so that it may be curved, bent, folded, and / or curled.

[0074] The substrate SUB of the display panel 100 (see, for example, Figure 8) may include a main area MA and a sub-area SBA.

[0075] The main area MA may include a display area DA displaying an image and a non-display area NDA, which is a peripheral area of ​​the display area DA and is around the display area DA along an edge or periphery of the display area DA (e.g., surrounding the display area DA). The display area DA may include a plurality of pixels displaying an image. For example, a pixel may include a first sub-pixel emitting a first light, a second sub-pixel emitting a second light, and a third sub-pixel emitting a third light.

[0076] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. Figure 1 exemplarily shows that the sub-region SBA is unfolded, but the sub-region SBA may be bent and, in this case, arranged on the bottom surface of the display panel 100. In the case where the sub-region SBA is bent, it may overlap the main region MA in the third direction DR3 which is the thickness direction of the display panel 100. The display driving circuit 250 may be arranged in the sub-region SBA.

[0077] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC) and attached to the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, and / or an ultrasonic bonding method, but the present disclosure is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 by a chip on film (COF) method.

[0078] The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. Therefore, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, a timing signal, and / or a driving voltage through the circuit board 300. The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on a film.

[0079] The power circuit 500 may generate a plurality of panel driving voltages according to a power voltage from the outside. The power circuit 500 may be formed as an integrated circuit (IC) and attached to the circuit board 300 by a COF method.

[0080] Figure 2 is a layout diagram showing a display device according to one or more embodiments. Figure 2 , the subarea SBA is shown as an example when it is unfolded without bending.

[0081] refer to Figure 2, the display panel 100 may include a main area MA and a sub-area SBA.

[0082] The main area MA may include a display area DA displaying an image and a non-display area NDA as a peripheral area of ​​the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be disposed at the center of the main area MA.

[0083] The display area DA may include a plurality of pixels PX for displaying an image, and each of the plurality of pixels PX may include a plurality of sub-pixels SPX. The pixel PX may be defined as a minimum unit sub-pixel group capable of expressing a white grayscale.

[0084] The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be disposed around the display area DA (e.g., disposed to surround the display area DA). The non-display area NDA may be an edge area of ​​the display panel 100.

[0085] The first scan driver SDC1 and the second scan driver SDC2 may be disposed in the non-display area NDA. The first scan driver SDC1 may be disposed at one side (e.g., the left side) of the display panel 100, and the second scan driver SDC2 may be disposed at the other side (e.g., the right side) of the display panel 100, but the present disclosure is not limited thereto. Each of the first scan driver SDC1 and the second scan driver SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 may receive a scan control signal input from the display driving circuit 250, generate a scan signal in response to the scan control signal, and output the generated scan signal to the scan line.

[0086] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be substantially equal to or less than the length of the main region MA in the first direction DR1. The sub-region SBA may be foldable to be disposed under the display panel 100. In this case, the sub-region SBA may overlap with the main region MA in the third direction DR3.

[0087] The sub-area SBA may include a connection area CA, a pad area PA, and a bending area BA.

[0088] The connection area CA is an area protruding from one side of the main area MA in the second direction DR2. One side of the connection area CA may contact the non-display area NDA of the main area MA, and the other side of the connection area CA may contact the bending area BA.

[0089] The pad area PA is an area on which the pad PD and the display driving circuit 250 are disposed. The display driving circuit 250 may be attached to the driving pad of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA may be in contact with the bending area BA.

[0090] The bending area BA is an area that is bent. When the bending area BA is bent, the pad area PA may be disposed under the connection area CA and the main area MA. The bending area BA may be disposed between the connection area CA and the pad area PA. One side of the bending area BA may contact the connection area CA, and the other side of the bending area BA may contact the pad area PA.

[0091] The non-display power lines NVSL may be disposed in the non-display area NDA, the connection area CA, the bending area BA, and the pad area PA.

[0092] The non-display power line NVSL may be arranged on four sides of the display area DA in the non-display area NDA. The non-display power line NVSL may be arranged around at least three sides of the display area DA (e.g., arranged to surround at least three sides of the display area DA). For example, the non-display power line NVSL may be around the left side, the upper side, and the right side of the display area DA (e.g., may surround the left side, the upper side, and the right side of the display area DA), and may be arranged in at least a portion of the lower side. In addition, the non-display power line NVSL may be arranged outside the first scan driver SDC1 and outside the second scan driver SDC2. For example, the non-display power line NVSL may be arranged on the left side of the first scan driver SDC1 and on the right side of the second scan driver SDC2. The non-display power line NVSL may be arranged at the edge of the first scan driver SDC1 and the substrate SUB and at the edge of the second scan driver SDC2 and the substrate SUB. Optionally, the non-display power line NVSL may overlap with the first scan driver SDC1 and the second scan driver SDC2.

[0093] The non-display power line NVSL may be disposed on the left and right edges in the connection area CA and the bending area BA. The non-display power line NVSL may be connected to the pad PD adjacent to one side edge and the pad PD adjacent to the other side edge from among the pads PD in the pad area PA. The non-display power line NVSL may receive the second driving voltage VSS (see FIG. 1 ) from the power supply circuit 500 disposed on the circuit board 300. Figure 3 ).

[0094] Figure 3 is a block diagram illustrating a display device according to one or more embodiments.

[0095] refer to Figure 3 , the display area DA includes a plurality of pixels PX, a plurality of scan lines SL (eg, GWL, GCL, GIL, GBL), a plurality of emission control lines EL, and a plurality of data lines DL.

[0096] The plurality of pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR2. For example, the plurality of pixels PX may be arranged along the rows and columns of the matrix along the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL may extend in the first direction DR1 while being arranged along the second direction DR2. The plurality of data lines DL may extend in the second direction DR2 while being arranged along the first direction DR1. The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, a plurality of initialization scan lines GIL, and a plurality of bias scan lines GBL.

[0097] Each of the plurality of sub-pixels SPX of the pixel PX may be connected to any one of the write scan lines GWL from the plurality of write scan lines GWL, any one of the control scan lines GCL from the plurality of control scan lines GCL, any one of the initialization scan lines GIL from the plurality of initialization scan lines GIL, any one of the bias scan lines GBL from the plurality of bias scan lines GBL, any one of the emission control lines EL from the plurality of emission control lines EL, and any one of the data lines DL from the plurality of data lines DL. Each of the plurality of sub-pixels SPX may receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and may emit light from its light emitting element according to the data voltage.

[0098] The non-display area NDA includes a first scan driver SDC1 , a second scan driver SDC2 , and a display driving circuit 250 .

[0099] Each of the first scan driver SDC1 and the second scan driver SDC2 may include a write scan signal output unit 611, a control scan signal output unit 612, an initialization scan signal output unit 613, a bias scan signal output unit 614, and an emission signal output unit 615. Each of the write scan signal output unit 611, the control scan signal output unit 612, the initialization scan signal output unit 613, the bias scan signal output unit 614, and the emission signal output unit 615 may receive a scan timing control signal SCS from the timing control circuit 251. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 251, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The initialization scan signal output unit 613 may generate an initialization scan signal in response to the scan timing control signal SCS, and sequentially output the initialization scan signal to the initialization scan line GIL. The bias scan signal output unit 614 can generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL. The emission signal output unit 615 can generate an emission control signal according to the scan timing control signal SCS, and sequentially output the emission control signal to the emission control line EL.

[0100] The display driving circuit 250 includes a timing control circuit 251 and a data driving circuit 252 .

[0101] The data driving circuit 252 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 converts the digital video data DATA into analog data voltages in response to the data timing control signal DCS and outputs them to the data line DL. In this case, the sub-pixel SPX may be selected by the write scan signal of the first scan driver SDC1 and the second scan driver SDC2, and the data voltage may be provided to the selected sub-pixel SPX.

[0102] The timing control circuit 251 may receive digital video data DATA and a timing signal from the outside. The timing control circuit 251 may generate a scan timing control signal SCS and a data timing control signal DCS for controlling the display panel 100 in response to the timing signal. The timing control circuit 251 may output the scan timing control signal SCS to the first scan driver SDC1 and the second scan driver SDC2. The timing control circuit 251 may output the digital video data DATA and the data timing control signal DCS to the data driving circuit 252.

[0103] The power supply circuit 500 may generate a plurality of panel driving voltages according to a power voltage from the outside. For example, the power supply circuit 500 may generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT, and provide them to the display panel 100.

[0104] Figure 4 is an equivalent circuit diagram illustrating a sub-pixel according to one or more embodiments.

[0105] refer to Figure 4 , the sub-pixel SPX according to one or more embodiments may be connected to the scan lines GWL, GIL, GCL and GBL, the emission control line EL and the data line DL. For example, the sub-pixel SPX may be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission control line EL and the data line DL.

[0106] The subpixel SPX according to one or more embodiments includes a driving transistor DT, a switching element, a capacitor C1 and a light emitting element LE. The switching element includes first, second, third, fourth, fifth, and sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0107] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current Ids (hereinafter, referred to as "driving current") flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode of the driving transistor DT.

[0108] The light emitting element LE may be a micro light emitting diode element.

[0109] The light emitting element LE is configured to emit light according to the driving current Ids. The emission amount of the light emitting element LE may be proportional to the driving current Ids. The anode electrode of the light emitting element LE may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode of the light emitting element LE may be connected to the second power line VSL to which the second power voltage is applied.

[0110] The capacitor C1 is formed between the gate electrode of the driving transistor DT and the first power line VDL to which the first power voltage is applied. The first power voltage may be a voltage having a level higher than that of the second power voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode of the capacitor C1 may be connected to the first power line VDL.

[0111] like Figure 4As shown in , the first to sixth transistors ST1 to ST6 and the driving transistor DT may all be formed as p-type metal oxide semiconductor field effect transistors (MOSFETs). In this case, the active layer of each of the driving transistor DT and the first to sixth transistors ST1 to ST6 may be formed of polysilicon.

[0112] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. The gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 may be connected to the emission control line EL. Because the first transistor ST1 to the sixth transistor ST6 are formed as p-type MOSFETs, when the scan signal of the gate low voltage and the emission signal are applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission control line EL, the first transistor ST1 to the sixth transistor ST6 may be turned on. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0113] The first electrode of the first transistor ST1 may be connected to the second electrode of the driving transistor DT, and the second electrode of the first transistor ST1 may be connected to the gate electrode of the driving transistor DT. Therefore, when the first transistor ST1 is turned on, the driving transistor DT may be diode-connected. The first electrode of the second transistor ST2 may be connected to the data line DL, and the second electrode of the second transistor ST2 may be connected to the first electrode of the driving transistor DT. The first electrode of the third transistor ST3 may be connected to the gate electrode of the driving transistor DT, and the second electrode of the third transistor ST3 may be connected to the initialization voltage line VIL. The first electrode of the fourth transistor ST4 may be connected to the second electrode of the sixth transistor ST6, and the second electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL. The first electrode of the fifth transistor ST5 may be connected to the first power line VDL, and the second electrode of the fifth transistor ST5 may be connected to the first electrode of the driving transistor DT. The first electrode of the sixth transistor ST6 may be connected to the second electrode of the driving transistor DT, and the second electrode of the sixth transistor ST6 may be connected to the anode electrode of the light emitting element LE.

[0114] Figure 5 is an equivalent circuit diagram illustrating a sub-pixel according to one or more embodiments.

[0115] refer to Figure 5, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may be configured as a p-type MOSFET, and the first transistor ST1 and the third transistor ST3 may be configured as an n-type MOSFET. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 configured as a p-type MOSFET may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 configured as an n-type MOSFET may be formed of an oxide semiconductor. In this case, the transistor formed of polysilicon and the transistor formed of an oxide semiconductor may be arranged in different layers.

[0116] Since the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 may be turned on when a control scan signal of a gate high voltage is applied to the control scan line GCL, and the third transistor ST3 may be turned on when an initialization scan signal of a gate high voltage is applied to the initialization scan line GIL. On the contrary, since the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may be turned on when an emission signal and a scan signal of a gate low voltage are applied to each of the write scan line GWL, the bias scan line GBL, and the emission control line EL.

[0117] Optionally, in Figure 4 In the embodiment, the fourth transistor ST4 may be formed as an n-type MOSFET. In this case, the active layer of the fourth transistor ST4 may also be formed of an oxide semiconductor. When the fourth transistor ST4 is formed as an n-type MOSFET, when a bias scan signal of a gate high voltage is applied to the bias scan line GBL, the fourth transistor ST4 may be turned on.

[0118] Optionally, although in Figure 4 and Figure 5 Although not shown in the drawings, the first to sixth transistors ST1 to ST6 and the driving transistor DT may all be formed as n-type MOSFETs. In this case, an active layer of each of the driving transistor DT and the first to sixth transistors ST1 to ST6 may be formed of an oxide semiconductor.

[0119] Figure 6 is a layout diagram illustrating a second power line and a plurality of pixels in a display area according to one or more embodiments. Figure 7 It is shown in detail Figure 6 An example layout diagram of area A.

[0120] refer to Figure 6 and Figure 7 , each of the plurality of pixels PX in the display area DA may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , a third sub-pixel SPX3 , and a fourth sub-pixel SPX4 .

[0121] A plurality of pixels PX may be arranged in a matrix. A first subpixel SPX1, a second subpixel SPX2, a third subpixel SPX3, and a fourth subpixel SPX4 in each of a plurality of pixels PX disposed in an Nth (N is a positive integer) row may be arranged in this order along a first direction DR1. A first subpixel SPX1, a fourth subpixel SPX4, a third subpixel SPX3, and a second subpixel SPX2 in each of a plurality of pixels PX disposed in an (N+1)th (N is a positive integer) row may be arranged in this order along a first direction DR1.

[0122] Although it is illustrated that each of the first sub-pixel SPX1, the second sub-pixel SPX2, the third sub-pixel SPX3, and the fourth sub-pixel SPX4 has a rectangular plane shape, the present disclosure is not limited thereto. Each of the first sub-pixel SPX1, the second sub-pixel SPX2, the third sub-pixel SPX3, and the fourth sub-pixel SPX4 may have a quadrilateral shape other than a rectangular shape, a polygonal shape other than a quadrilateral shape, a circular shape, an elliptical shape, and / or an irregular shape. The plane shape of each of the first sub-pixel SPX1, the second sub-pixel SPX2, the third sub-pixel SPX3, and the fourth sub-pixel SPX4 may be defined as the shape of the area defined by the pixel electrode PXE and the common electrode CE. The first sub-pixel SPX1 and the third sub-pixel SPX3 may emit a first light, the second sub-pixel SPX2 may emit a second light, and the fourth sub-pixel SPX4 may emit a third light. Here, the first light may be a light of a green wavelength band, the second light may be a light of a red wavelength band, and the third light may be a light of a blue wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 370 nm to about 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 480 nm to about 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of about 600 nm to about 750 nm. When the first subpixel SPX1 and the third subpixel SPX3 emit light of the first color, light having low light emission efficiency may be compensated.

[0123] In the above content, it is illustrated that the first sub-pixel SPX1 and the third sub-pixel SPX3 emit the same light, but the present disclosure is not limited thereto. For example, the first sub-pixel SPX1 may emit the first light, the second sub-pixel SPX2 may emit the second light, the third sub-pixel SPX3 may emit the third light, and the fourth sub-pixel SPX4 may emit the fourth light. In this case, the fourth light may be light in a monochromatic wavelength band different from the first to third lights, or may be white light which is a mixed light of the first to third lights.

[0124] However, the arrangement and number of the sub-pixels SPX of each of the plurality of pixels PX according to the present disclosure and the emission wavelength band of the sub-pixels SPX are not limited to those described above. For example, each of the plurality of pixels PX may include three sub-pixels SPX arranged in a strip shape. In this case, each of the plurality of pixels PX may include a first sub-pixel emitting a second light, a second sub-pixel emitting a first light, and a third sub-pixel emitting a third light. In each of the plurality of pixels PX, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be sequentially arranged along the first direction DR1.

[0125] Each of the first to fourth subpixels SPX1 to SPX4 includes an opening OA, a pixel electrode PXE, a common electrode CE, a light emitting element LE, an organic layer 210 , a first connection electrode BE1 , a second connection electrode BE2 , a first connection hole CT1 , and a second connection hole CT2 .

[0126] The opening OA may be formed by a bank 190 (see Figure 8 ) separated by the first to fourth sub-pixels SPX1 to SPX4 and may be defined as a region in which the light emitting element LE is disposed in each of the first to fourth sub-pixels SPX1 to SPX4.

[0127] The pixel electrode PXE and the common electrode CE may be disposed to be spaced apart from each other. A portion of the pixel electrode PXE may be disposed in a first portion of the opening OA, and the remaining portion may be disposed in an area other than the opening OA. A portion of the common electrode CE may be disposed in a second portion of the opening OA, and the remaining portion may be disposed in an area other than the opening OA. The pixel electrode PXE and the common electrode CE may have substantially the same area, but the present disclosure is not limited thereto.

[0128] The organic layer 210 may be disposed to overlap the pixel electrode PXE and the common electrode CE in the opening OA. The organic layer 210 may be used to temporarily fix or adhere the light emitting element LE during a process of transferring the light emitting element LE to the display panel 100. That is, the organic layer 210 may be a layer for temporarily adhering the light emitting element LE to the pixel electrode PXE and the common electrode CE in the opening OA.

[0129] The area of ​​the organic layer 210 may be greater than the area of ​​the first connection electrode BE1 and the second connection electrode BE2. The area of ​​the pixel electrode PXE may be greater than the area of ​​the first connection electrode BE1. The area of ​​the common electrode CE may be greater than the area of ​​the second connection electrode BE2.

[0130] The light emitting element LE may have a rectangular planar shape. The light emitting element LE includes a first electrode E1 disposed on one side and a second electrode E2 disposed on the other side. The first electrode E1 and the second electrode E2 may be spaced apart from each other in the second direction DR2.

[0131] The light emitting element LE may completely overlap the organic layer 210. A first portion of the light emitting element LE may overlap the pixel electrode PXE, and a second portion of the light emitting element LE may overlap the common electrode CE.

[0132] The first connection electrode BE1 is used to connect the first electrode E1 of the light emitting element LE to the pixel electrode PXE. To this end, the first connection electrode BE1 may be connected to the first electrode E1 of the light emitting element LE and the pixel electrode PXE. The first connection electrode BE1 may overlap at least a portion of the first electrode E1. The first connection electrode BE1 may overlap at least a portion of the organic layer 210 and at least a portion of the pixel electrode PXE.

[0133] The second connection electrode BE2 is used to connect the second electrode E2 of the light emitting element LE to the common electrode CE. To this end, the second connection electrode BE2 may be connected to the second electrode E2 of the light emitting element LE and the common electrode CE. The second connection electrode BE2 may overlap at least a portion of the second electrode E2. The second connection electrode BE2 may overlap at least a portion of the organic layer 210 and at least a portion of the common electrode CE.

[0134] The first connection hole CT1 may be a hole through which the pixel electrode PXE is electrically connected to the fourth source connection electrode PCE2 (see Figure 8 ) region, the fourth source connection electrode PCE2 is electrically connected to the first thin film transistor TFT1 (see Figure 8 ) of the first source region S1 (see Figure 8 ) or the first drain region D1 (see Figure 8 ). The first connection hole CT1 may overlap with the pixel electrode PXE.

[0135] The second connection hole CT2 may be a region in which the common electrode CE is connected to the second power line VSL. The second connection hole CT2 may overlap the common electrode CE and the second power line VSL.

[0136] Each of the second power lines VSL may be electrically connected to Figure 2Each of the second power lines VSL may include a line portion WP extending in the first direction DR1 and a protrusion PP protruding from the line portion WP in the second direction DR2 and overlapping the second connection hole CT2.

[0137] Figure 8 is a diagram showing the display panel and Figure 6 A cross-sectional view of an example of a cross section corresponding to lines I1 - I1 ′, I2 - I2 ′, and I3 - I3 ′. Fig.9A is a diagram showing the light emitting element and Figure 6 A sectional view of an example of a cross section corresponding to line I2 - I2 ′.

[0138] refer to Figure 8 and Fig.9A , the substrate SUB may be made of an insulating material such as glass and / or a polymer resin. When the substrate SUB is made of a polymer resin, it may be a flexible substrate that can be stretched. The polymer resin may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0139] The barrier layer BR may be disposed on the substrate SUB. The barrier layer BR is a layer for protecting the transistors of the thin film transistor layer TFTL from moisture penetrating through the substrate SUB susceptible to moisture penetration. The barrier layer BR may be formed as a plurality of inorganic layers alternately stacked. For example, the barrier layer BR may be formed of a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer are alternately stacked.

[0140] The first thin film transistor TFT1 may be disposed on the barrier layer BR. The first thin film transistor TFT1 may be Figure 5 The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0141] The first active layer ACT1 of the first thin film transistor TFT1 may be disposed on the barrier layer BR. The first active layer ACT1 of the first thin film transistor TFT1 may include polycrystalline silicon, single crystalline silicon, low temperature polycrystalline silicon and / or amorphous silicon.

[0142] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region overlapping with the first gate electrode G1 in a third direction DR3 that is a thickness direction of the substrate SUB. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 may be regions having conductivity by doping a silicon semiconductor with ions.

[0143] The first gate insulating layer 131 may be disposed on the first channel region CHA1, the first source region S1, the first drain region D1, and the barrier layer BR of the first thin film transistor TFT1. The first gate insulating layer 131 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0144] The first gate metal layer GTL1 may be disposed on the first gate insulating layer 131. The first gate metal layer GTL1 may include a first gate electrode G1 of the first thin film transistor TFT1 and a first capacitor electrode CAE1. The first gate electrode G1 may overlap the first active layer ACT1 in the third direction DR3. Figure 8 The first gate electrode G1 and the first capacitor electrode CAE1 are shown to be spaced apart from each other, but the first gate electrode G1 and the first capacitor electrode CAE1 may be connected to each other. The first gate metal layer GTL1 may be formed as a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof.

[0145] The second gate insulating layer 132 may be disposed on the first gate electrode G1 and the first capacitor electrode CAE1 of the first thin film transistor TFT1 and the first gate insulating layer 131. The second gate insulating layer 132 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0146] The second gate metal layer GTL2 may be disposed on the second gate insulating layer 132. The second gate metal layer GTL2 may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap the first capacitor electrode CAE1 in the third direction DR3. Since the second gate insulating layer 132 has a desired dielectric constant (eg, a predetermined dielectric constant), the capacitor C1 ( Figure 5) may be formed of a first capacitor electrode CAE1, a second capacitor electrode CAE2, and a second gate insulating layer 132 disposed between the first capacitor electrode CAE1 and the second capacitor electrode CAE2. The second gate metal layer GTL2 may be formed as a single layer or a multilayer made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or an alloy thereof.

[0147] The first interlayer insulating layer 141 may be disposed on the second capacitor electrode CAE2 and the second gate insulating layer 132. The first interlayer insulating layer 141 may be formed of an inorganic layer (eg, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0148] The second thin film transistor TFT2 may be disposed on the first interlayer insulating layer 141. The second thin film transistor TFT2 may be Figure 5 The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2.

[0149] The second active layer ACT2 of the second thin film transistor TFT2 may be disposed on the first interlayer insulating layer 141. The second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and / or oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and / or oxygen (O)).

[0150] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region overlapping with the second gate electrode G2 in the third direction DR3. The second source region S2 may be disposed on one side of the second channel region CHA2, and the second drain region D2 may be disposed on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions that do not overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 and the second drain region D2 may be regions having conductivity by doping an oxide semiconductor with ions.

[0151] The third gate insulating layer 133 may be disposed on the second active layer ACT2 of the second thin film transistor TFT2 and the first interlayer insulating layer 141. The third gate insulating layer 133 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0152] The third gate metal layer GTL3 may be disposed on the third gate insulating layer 133. The third gate metal layer GTL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap the second active layer ACT2 in the third direction DR3. The third gate metal layer GTL3 may be formed as a single layer or a multilayer made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or an alloy thereof.

[0153] The second interlayer insulating layer 142 may be disposed on the second gate electrode G2 of the second thin film transistor TFT2 and the third gate insulating layer 133. The second interlayer insulating layer 142 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0154] The first data metal layer DTL1 may be disposed on the second interlayer insulating layer 142. The first data metal layer DTL1 may include a first source connection electrode PCE1, a second source connection electrode SBE1, and a third source connection electrode SBE2. The first source connection electrode PCE1 may be connected to the first drain region D1 of the first active layer ACT1 through a first source connection hole PCT1 penetrating the first gate insulating layer 131, the second gate insulating layer 132, the first interlayer insulating layer 141, the third gate insulating layer 133, and the second interlayer insulating layer 142. The second source connection electrode SBE1 may be connected to the second source region S2 of the second active layer ACT2 through a second source connection hole BCT1 penetrating the second interlayer insulating layer 142 and the third gate insulating layer 133. The third source connection electrode SBE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third source connection hole BCT2 penetrating the second interlayer insulating layer 142 and the third gate insulating layer 133. The first data metal layer DTL1 may be formed as a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof. For example, the first data metal layer DTL1 may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0155] On the second interlayer insulating layer 142 and the first, second, and third source connection electrodes PCE1, SBE1, and SBE2, a first organic layer 160 for planarizing a stepped portion caused by the first and second thin film transistors TFT1 and TFT2 may be provided. The first organic layer 160 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0156] The second data metal layer DTL2 may be disposed on the first organic layer 160. The second data metal layer DTL2 may include a fourth source connection electrode PCE2 and a second power line VSL. The fourth source connection electrode PCE2 may be connected to the first source connection electrode PCE1 through a second pixel connection hole PCT2 penetrating the first organic layer 160. The second power line VSL may be provided with a second driving voltage VSS. The second data metal layer DTL2 may be formed as a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or an alloy thereof. For example, the second data metal layer DTL2 may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0157] The second organic layer 180 may be disposed on the first organic layer 160, the fourth source connection electrode PCE2, and the second power line VSL. The second organic layer 180 may be formed of an organic layer such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0158] The light emitting element layer EML may be disposed on the second organic layer 180. The light emitting element layer EML may include a pixel electrode PXE, a bank 190, a light emitting element LE, a common electrode CE, an organic layer 210, a first connection electrode BE1, a second connection electrode BE2, and a third organic layer 191.

[0159] The bank 190 may be disposed on the second organic layer 180. The bank 190 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The bank 190 may include a light blocking material to prevent light of the light emitting element LE of any one sub-pixel SPX from traveling to an adjacent sub-pixel SPX. For example, the bank 190 may include an organic black pigment or an inorganic black pigment such as carbon black, etc.

[0160] The opening OA may be a region partitioned by the bank 190. The opening OA may be a region in which the bank 190 is not provided and the second organic layer 180 is exposed.

[0161] The pixel electrode layer PXL may include a pixel electrode PXE disposed in each of the sub-pixels SPX1, SPX2, SPX3, and SPX4 and a common electrode CE. The pixel electrode PXE may be referred to as an anode electrode, and the common electrode CE may be referred to as a cathode electrode.

[0162] The pixel electrode PXE and the common electrode CE may be disposed on the second organic layer 180 and the bank 190. The pixel electrode PXE and the common electrode CE may be disposed on the second organic layer 180 in the opening OA. The pixel electrode PXE and the common electrode CE may be disposed on the side surface and the top surface of the bank 190. The pixel electrode PXE and the common electrode CE may be disposed to be separated from each other (e.g., spaced apart).

[0163] The pixel electrode PXE may be connected to the fourth source connection electrode PCE2 through the first connection hole CT1 penetrating the second organic layer 180 and the bank 190. The pixel electrode PXE may be connected to the first source region S1 or the first drain region D1 of the first thin film transistor TFT1 through the first source connection electrode PCE1 and the fourth source connection electrode PCE2. Therefore, a voltage controlled by the first thin film transistor TFT1 may be applied to the pixel electrode PXE.

[0164] The common electrode CE may be connected to the second power line VSL through the second connection hole CT2 penetrating the second organic layer 180 and the bank 190. Therefore, the second driving voltage VSS may be applied to the common electrode CE.

[0165] When the pixel electrode layer PXL is made of a metal material (e.g., an opaque metal material) having a high reflectivity, in the light emitted from the active layer MQW of the light emitting element LE, the light traveling in the downward direction relative to the light emitting element LE can be reflected from the pixel electrode PXE and the common electrode CE to travel in the upward direction relative to the light emitting element LE. Therefore, because the light loss from the light emitting element LE can be reduced, the light efficiency of the light emitting element LE can be improved. For example, the pixel electrode layer PXL can be formed as a single layer or multilayer made of one of molybdenum (Mo), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) and / or an alloy thereof. Specifically, the pixel electrode layer PXL may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), a two-layer structure of titanium (Ti) / copper (Cu) and / or a three-layer structure of titanium (Ti) / copper (Cu) / aluminum (Al), but the present disclosure is not limited thereto.

[0166] The organic layer 210 corresponding to the insulating layer may be provided on the pixel electrode PXE and the common electrode CE in each of the sub-pixels SPX1, SPX2, SPX3, and SPX4. The organic layer 210 is used to temporarily fix or adhere the light-emitting element LE during the process of transferring the light-emitting element LE to the display panel 100. That is, the organic layer 210 may be a layer for temporarily adhering the light-emitting element LE to the pixel electrode PXE and the common electrode CE. The greater the thickness of the organic layer 210, the easier the temporary adhesion is, so the height of the opening OA in which the organic layer 210 is accommodated or the thickness of the bank 190 may be about 0.5 μm or more. The height of the opening OA may be greater than the thickness of the organic layer 210. The thickness of the organic layer 210 may be greater than the thickness of each of the pixel electrodes PXE.

[0167] The organic layer 210 may be in contact with the bottom surface of the light emitting element LE. In addition, the organic layer 210 may be in contact with at least a portion of each of the side surfaces of the light emitting element LE.

[0168] The organic layer 210 may be a photosensitive organic layer such as a photoresist. Alternatively, the organic layer 210 may be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0169] Will refer to it later Figures 12 to 19 A detailed description of the organic layer 210 is described in a method for manufacturing the display device 10 .

[0170] The light emitting element LE in each of the sub-pixels SPX1, SPX2, SPX3, and SPX4 may be disposed on the organic layer 210. Figure 8 and Fig.9A As shown in , the light emitting element LE is exemplified as a lateral type micro LED in which both the first electrode E1 and the second electrode E2 protrude from the top surface of the light emitting element LE and current flows in a lateral direction.

[0171] Each of the plurality of light emitting elements LE may be made of an inorganic material such as gallium nitride (GaN). Each of the plurality of light emitting elements LE may have a length of several micrometers to several hundred micrometers in each of the first direction DR1, the second direction DR2, and the third direction DR3. For example, each of the plurality of light emitting elements LE may have a length of about 100 μm or less in each of the first direction DR1, the second direction DR2, and the third direction DR3.

[0172] The length of the bottom surface of each of the plurality of light emitting elements LE may be longer than the length of the top surface. Fig.9AIt is shown that the angle formed by the side surface connecting the top surface and the bottom surface of each of the plurality of light emitting elements LE and each of the top surface and the bottom surface is 90°, but the present disclosure is not limited thereto. Fig. 9B As shown in , the angle formed by the side surface connecting the top surface and the bottom surface of each of the plurality of light emitting elements LE and the top surface may be an obtuse angle, and the angle formed by the side surface and the bottom surface may be an acute angle. That is, the side surface connecting the top surface and the bottom surface of each of the plurality of light emitting elements LE may be an inclined surface.

[0173] The plurality of light emitting elements LE may be formed by growing on a semiconductor substrate such as a silicon substrate and / or a sapphire substrate. The plurality of light emitting elements LE may be directly transferred from the semiconductor substrate to the organic layer 210 of the display panel 100. Alternatively, the plurality of light emitting elements LE may be transferred to the organic layer 210 of the display panel 100 by an electrostatic method using an electrostatic head or an imprinting method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0174] Each of the plurality of light emitting elements LE includes a first electrode E1, a second electrode E2, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and an undoped semiconductor layer USEM. In one or more embodiments, each of the plurality of light emitting elements LE further includes a passivation layer.

[0175] The undoped semiconductor layer USEM may be disposed on the organic layer 210. The undoped semiconductor layer USEM may be formed as a semiconductor layer not doped with an n-type dopant or a p-type dopant, that is, an undoped semiconductor layer. For example, the undoped semiconductor layer USEM may be one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN not doped with a dopant. For example, the undoped semiconductor layer USEM may be GaN not doped with a dopant.

[0176] The second semiconductor layer SEM2 may be disposed on the undoped semiconductor layer USEM. The second semiconductor layer SEM2 may be one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant such as Si, Ge, Se, and / or Sn. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The second semiconductor layer SEM2 may include a first portion SEM2_1 having a first thickness T1 and a second portion SEM2_2 having a second thickness T2 less than the first thickness T1.

[0177] The active layer MQW may be disposed on the first portion SEM2_1 of the second semiconductor layer SEM2. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first and second semiconductor layers SEM1 and SEM2.

[0178] The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and barrier layers are alternately stacked. At this time, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN and / or AlGaN, but the present disclosure is not limited thereto. Alternatively, the active layer MQW may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, and may include other III- to V-group semiconductor materials according to the wavelength band of the emitted light.

[0179] When the active layer MQW includes InGaN, the color of the emitted light may vary according to the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer MQW may move toward the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer MQW may move toward the blue wavelength band. For example, the active layer MQW of the light emitting element LE that emits the third light (light in the blue wavelength band) may include about 10 wt % to 20 wt % of indium (In).

[0180] The first semiconductor layer SEM1 may be disposed on the active layer MQW. The first semiconductor layer SEM1 may be one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant such as Mg, Zn, Ca, and / or Ba. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg.

[0181] The first electrode E1 may be disposed on at least a portion of the first semiconductor layer SEM1 and may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0182] The second electrode E2 may be disposed on at least a portion of the second portion SEM2_2 of the second semiconductor layer SEM2. Not only are the active layer MQW and the first semiconductor layer SEM1 not disposed on the second portion SEM2_2 of the second semiconductor layer SEM2, but also the second thickness T2 of the second portion SEM2_2 of the second semiconductor layer SEM2 is less than the first thickness T1 of the first portion SEM2_1. Therefore, in order to compensate for the sum of the thickness difference between the first portion SEM2_1 and the second portion SEM2_2 of the second semiconductor layer SEM2, the thickness of the active layer MQW, and the thickness of the first semiconductor layer SEM1, the thickness of the second electrode E2 may be greater than the thickness of the first electrode E1. For example, the thickness of the second electrode E2 may be greater than the sum of the thickness difference between the first portion SEM2_1 and the second portion SEM2_2 of the second semiconductor layer SEM2, the thickness of the active layer MQW, and the thickness of the first semiconductor layer SEM1.

[0183] like Fig.9A As shown in , in the present disclosure, at least one of the first electrode E1 and the second electrode E2 may include a region exposed by the organic layer 210. That is, the entire region of the first electrode E1 may not be covered by the organic layer 210, a partial region of the second electrode E2 may be covered by the organic layer 210, and the remaining region of the second electrode E2 may be exposed without being covered by the organic layer 210.

[0184] The electron blocking layer may be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be a layer for suppressing or preventing too many electrons from flowing into the active layer MQW. For example, the electron blocking layer may be AlGaN and / or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0185] The superlattice layer may be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer may be formed of InGaN and / or GaN. The superlattice layer may be omitted.

[0186] In one or more embodiments, the passivation layer may be a layer for protecting the side surface of the light emitting element LE. The passivation layer may be disposed on the side surface of the first semiconductor layer SEM1, the side surface of the active layer MQW, and the side surface of the second semiconductor layer SEM2. The passivation layer may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0187] The first connection electrode BE1 connects the first electrode E1 of the light emitting element LE to the pixel electrode PXE. The first connection electrode BE1 may be disposed on the top and side surfaces of the first electrode E1 and the top surface of the first semiconductor layer SEM1. The first connection electrode BE1 may be disposed on a passivation layer disposed on at least a portion of one side surface of the first semiconductor layer SEM1, one side surface of the active layer MQW, and one side surface of the second semiconductor layer SEM2. The first connection electrode BE1 may be disposed on a portion of the organic layer 210 disposed between one side surface of the light emitting element LE and the bank 190. The first connection electrode BE1 may be connected to the pixel electrode PXE on the top and side surfaces of the bank 190. That is, the first connection electrode BE1 may contact the pixel electrode PXE on the top and side surfaces of the bank 190.

[0188] The second connection electrode BE2 connects the second electrode E2 of the light emitting element LE to the common electrode CE. The second connection electrode BE2 may be disposed on the top surface and one side surface of the second electrode E2. The second connection electrode BE2 may be disposed on another portion of the organic layer 210 disposed between the bank 190 and the other side surface of the light emitting element LE. The other side surface of the light emitting element LE may be a side surface opposite to one side surface of the light emitting element LE. The second connection electrode BE2 may be connected to the common electrode CE on the top surface and the side surface of the bank 190. That is, the second connection electrode BE2 may be in contact with the common electrode CE on the top surface and the side surface of the bank 190.

[0189] Fig.9A The organic layer 210 is shown to be disposed on one side surface of the second semiconductor layer SEM2, the top surface of the second portion SEM2_2, and at least a portion of one side surface of the second electrode E2, but the present disclosure is not limited thereto. For example, the organic layer 210 may be disposed on a portion of one side surface of the second semiconductor layer SEM2, and may not be disposed on the top surface of the second portion SEM2_2 of the second semiconductor layer SEM2 and at least a portion of one side surface of the second electrode E2. In this case, the second connection electrode BE2 may be disposed on the top surface of the second portion SEM2_2 of the second semiconductor layer SEM2 and at least a portion of one side surface of the second electrode E2 (e.g., the entire one side surface of the second electrode E2).

[0190] The first and second connection electrodes BE1 and BE2 may include a transparent conductive material (eg, transparent conductive oxide (TCO)) capable of transmitting light, such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0191] The light blocking layer BM may be disposed on the bank 190. The light blocking layer BM may overlap the bank 190, and may not overlap the plurality of light emitting elements LE.

[0192] The light blocking layer BM may include a first light blocking layer BM1 and a second light blocking layer BM2 stacked in sequence. The length of the first light blocking layer BM1 in the first direction DR1 or the length of the first light blocking layer BM1 in the second direction DR2 may be longer than the length of the second light blocking layer BM2 in the first direction DR1 or the length of the second light blocking layer BM2 in the second direction DR2. The height of the first light blocking layer BM1 may be greater than the height of the second light blocking layer BM2. The first light blocking layer BM1 and the second light blocking layer BM2 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. The first light blocking layer BM1 and the second light blocking layer BM2 may include a light blocking material to prevent the light of the light emitting element LE of any one sub-pixel SPX from traveling to an adjacent sub-pixel SPX. For example, the first light blocking layer BM1 and the second light blocking layer BM2 may include an organic black pigment or an inorganic black pigment such as carbon black, or the like.

[0193] The third organic layer 191 may be provided to cover the light emitting element LE and the organic layer 210 for planarization in a region separated by the light blocking layer BM. The third organic layer 191 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0194] The first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL may be disposed on the third organic layer 191. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL may be disposed in a region separated by the light blocking layer BM. For example, the first light conversion layer QDL1 may be disposed on the first capping layer CAP1 in the first sub-pixel SPX1 and the third sub-pixel SPX3, the second light conversion layer QDL2 may be disposed on the first capping layer CAP1 in the second sub-pixel SPX2, and the light-transmitting layer TPL may be disposed on the first capping layer CAP1 in the fourth sub-pixel SPX4.

[0195] The first light conversion layer QDL1 may convert a portion of the third light (e.g., light in a blue wavelength band) incident from the light emitting element LE into a first light (e.g., light in a green wavelength band). The first light conversion layer QDL1 may include a first base resin BRS1 and first wavelength conversion particles WCP1. The first base resin BRS1 may include a light-transmitting organic material. For example, the first base resin BRS1 may include an epoxy resin, an acrylic resin, a cardo resin, and / or an imide resin. The first wavelength conversion particles WCP1 may convert a portion of the third light (e.g., light in a blue wavelength band) incident from the light emitting element LE into a first light (e.g., light in a green wavelength band). The first wavelength conversion particles WCP1 may be quantum dots (QD), quantum rods, fluorescent materials, and / or phosphorescent materials. The first light conversion layer QDL1 may also include a material such as titanium dioxide (TiO 2 ) light diffuser.

[0196] The second light conversion layer QDL2 may convert a portion of the third light (e.g., light in a blue wavelength band) incident from the light emitting element LE into a second light (e.g., light in a red wavelength band). The second light conversion layer QDL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 may include a light-transmitting organic material. For example, the second base resin BRS2 may include an epoxy resin, an acrylic resin, a cardo resin, and / or an imide resin. The second wavelength conversion particles WCP2 may convert a portion of the third light (e.g., light in a blue wavelength band) incident from the light emitting element LE into a second light (e.g., light in a red wavelength band). The second wavelength conversion particles WCP2 may be quantum dots (QD), quantum rods, fluorescent materials, and / or phosphorescent materials. The second light conversion layer QDL2 may also include a material such as titanium dioxide (TiO 2 ) light diffuser.

[0197] The light-transmitting layer TPL may include a light-transmitting organic material, such as epoxy resin, acrylic resin, cardo resin, imide resin, etc.

[0198] In the present disclosure, a third light conversion layer may be provided instead of the light-transmitting layer TPL. In this case, the third light conversion layer may include a material different from that of the first light conversion layer QDL1 and the second light conversion layer QDL2. For example, the first light conversion layer QDL1 may include quantum dots that convert light in a blue wavelength band into light in a green wavelength band, the second light conversion layer QDL2 may include quantum dots that convert light in a blue wavelength band into light in a red wavelength band, and the third light conversion layer may include a blue phosphor. In addition, each of the first light conversion layer QDL1, the second light conversion layer QDL2, and the third light conversion layer may include a material such as titanium dioxide (TiO 2) light dispersant and quantum dots. In this case, the titanium dioxide (TiO 2 ) particles may be greater than the titanium dioxide (TiO 2 ) particles or the amount of titanium dioxide (TiO 2 )The number of particles.

[0199] The first capping layer CAP1 may be disposed between the third organic layer 191 and the first light conversion layer QDL1, between the third organic layer 191 and the second light conversion layer QDL2, between the third organic layer 191 and the light-transmitting layer TPL, between the light blocking layer BM and the first light conversion layer QDL1, between the light blocking layer BM and the second light conversion layer QDL2, and between the light blocking layer BM and the light-transmitting layer TPL. The first capping layer CAP1 may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer). The first capping layer CAP1 may be disposed on the top surface of the light blocking layer BM.

[0200] The reflective layer RF may be disposed between the light blocking layer BM and the first light conversion layer QDL1, between the light blocking layer BM and the second light conversion layer QDL2, and between the light blocking layer BM and the light-transmitting layer TPL. The reflective layer RF may be disposed on the first capping layer CAP1 disposed on the side surface of the first light blocking layer BM1 and the side surface of the second light blocking layer BM2. The reflective layer RF is used to reflect light traveling in a lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL.

[0201] The reflective layer RF may include a metal material having high reflectivity such as aluminum (Al). The thickness of the reflective layer RF may be about 0.1 μm.

[0202] Optionally, the reflective layer RF may include M (M is an integer of 2 or more) pairs of first and second layers having different refractive indices to serve as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers may be alternately arranged. The first and second layers may be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0203] The second capping layer CAP2 may be disposed on the first capping layer CAP1, the first light conversion layer QDL1, the second light conversion layer QDL2 and the light transmitting layer TPL. The second capping layer CAP2 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer and / or an aluminum oxide layer.

[0204] The first capping layer CAP1 and the second capping layer CAP2 are used to protect the first wavelength conversion particles WCP1 of the first light conversion layer QDL1 and the second wavelength conversion particles WCP2 of the second light conversion layer QDL2 from moisture or oxygen, so that the first light conversion layer QDL1, the second light conversion layer QDL2 and the light transmitting layer TPL can be encapsulated by the first capping layer CAP1 and the second capping layer CAP2.

[0205] In addition, the first capping layer CAP1 and the second capping layer CAP2 may be formed of a low refractive index material having a lower refractive index than the fourth organic layer 192, and in this case, total reflection of light converted in the first light conversion layer QDL1 or the second light conversion layer QDL2 may be prevented or minimized in the first capping layer CAP1 and the second capping layer CAP2. Therefore, the light converted in the first light conversion layer QDL1 or the second light conversion layer QDL2 may be gathered on top of the first light conversion layer QDL1 or the second light conversion layer QDL2. For example, the refractive index of at least one of the first capping layer CAP1 and the second capping layer CAP2 may be approximately 1.1 to 1.5, and the refractive index of each of the first base resin BRS1 of the first light conversion layer QDL1, the second base resin BRS2 of the second light conversion layer QDL2, and the light transmitting layer TPL may be approximately 1.5 to 2.0.

[0206] Alternatively, the fourth organic layer 192 may also be formed of a low refractive index material, and in this case, it is possible to prevent or minimize the light converted in the first light conversion layer QDL1 or the second light conversion layer QDL2 from being totally reflected by the fourth organic layer 192. Therefore, the light converted in the first light conversion layer QDL1 or the second light conversion layer QDL2 may be gathered on top of the first light conversion layer QDL1 or the second light conversion layer QDL2.

[0207] The fourth organic layer 192 may be disposed on the second capping layer CAP2. The fourth organic layer 192 may be formed of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0208] When the light emitting element LE of the first sub-pixel SPX1, the light emitting element LE of the second sub-pixel SPX2, and the light emitting element LE of the third sub-pixel SPX3 emit light in the blue wavelength band, the first light conversion layer QDL1 and the second light conversion layer QDL2 need to perform wavelength conversion. However, the present disclosure is not limited thereto, and when the light emitting element LE of the first sub-pixel SPX1 emits light of a first color, the light emitting element LE of the second sub-pixel SPX2 emits light of a second color, and the light emitting element LE of the third sub-pixel SPX3 emits light of a third color, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL may be omitted.

[0209] Optionally, when the light-emitting element LE of the first subpixel SPX1 emits light of a first color, the light-emitting element LE of the second subpixel SPX2 emits light of a second color, and the light-emitting element LE of the third subpixel SPX3 emits light of a third color, the first light conversion layer QDL1 and the second light conversion layer QDL2 may include phosphor particles instead of wavelength conversion particles to increase color purity.

[0210] A plurality of color filters CF1, CF2, and CF3 may be disposed on the fourth organic layer 192. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0211] The first color filter CF1 provided in the first sub-pixel SPX1 and the third sub-pixel SPX3 may transmit the first light (e.g., light in the green wavelength band), and may absorb or block the third light (e.g., light in the blue wavelength band). Therefore, the first color filter CF1 may transmit the first light (e.g., light in the green wavelength band) converted by the third light (e.g., light in the blue wavelength band) emitted from the light emitting element LE through the first light conversion layer QDL1, and may absorb or block the third light (e.g., light in the blue wavelength band) not converted by the first light conversion layer QDL1. Therefore, the first sub-pixel SPX1 may emit the first light (e.g., light in the green wavelength band).

[0212] The second color filter CF2 disposed in the second subpixel SPX2 may transmit the second light (e.g., light in the red wavelength band), and may absorb or block the third light (e.g., light in the blue wavelength band). Therefore, the second color filter CF2 may transmit the second light (e.g., light in the red wavelength band) converted from the third light (e.g., light in the blue wavelength band) emitted from the light emitting element LE through the second light conversion layer QDL2, and may absorb or block the third light (e.g., light in the blue wavelength band) not converted by the second light conversion layer QDL2. Therefore, the second subpixel SPX2 may emit the second light (e.g., light in the red wavelength band).

[0213] The third color filter CF3 provided in the fourth subpixel SPX4 can transmit the third light (e.g., light in the blue wavelength band). Therefore, the third color filter CF3 can transmit the third light (e.g., light in the blue wavelength band) emitted from the light emitting element LE and passing through the light-transmitting layer TPL. Therefore, the fourth subpixel SPX4 can emit the third light (e.g., light in the blue wavelength band).

[0214] The region where the first, second, and third color filters CF1, CF2, and CF3 overlap may serve to block light. The region where the first, second, and third color filters CF1, CF2, and CF3 overlap may overlap the bank 190 and the light blocking layer BM.

[0215] A fifth organic layer 193 for planarization may be disposed on the plurality of color filters CF1, CF2, and CF3. The fifth organic layer 193 may be formed of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0216] according to Figure 8 and Fig.9A , both the first electrode E1 and the second electrode E2 of the light emitting element LE are disposed on the top surface of the light emitting element LE, so that the current of the light emitting element LE flows through the first electrode E1, the first semiconductor layer SEM1, the active layer MQW, the first portion SEM2_1 of the second semiconductor layer SEM2, the second portion SEM2_2 of the second semiconductor layer SEM2, and the second electrode E2. Therefore, since the current of the light emitting element LE does not flow through the undoped semiconductor layer USEM, the reduction in the light emitting efficiency of the micro light emitting element or the failure of the micro light emitting element to emit light due to the resistance of the undoped semiconductor layer USEM can be reduced or prevented.

[0217] In addition, in each of the sub-pixels SPX1 to SPX4, the organic layer 210 is disposed on the pixel electrode PXE and the common electrode CE, the light emitting element LE is disposed on the organic layer 210, the first electrode E1 of the light emitting element LE is connected to the pixel electrode PXE by using the first connection electrode BE1, and the second electrode E2 of the light emitting element LE is connected to the common electrode CE by using the second connection electrode BE2. Therefore, in the process of transferring the plurality of light emitting elements LE to the display panel 100 by using the organic layer 210, the plurality of light emitting elements LE may be temporarily fixed or adhered. In addition, although the organic layer 210 is used for temporary adhesion, the first electrode E1 of the light emitting element LE may be electrically connected to the pixel electrode PXE, and the second electrode E2 of the light emitting element LE may be electrically connected to the common electrode CE.

[0218] Furthermore, when the plurality of light emitting elements LE are adhered to the bonding electrode provided on each of the plurality of pixel electrodes PXE by using eutectic bonding for adhesion by heat and pressure, the bonding electrode of each of the plurality of light emitting elements LE and the bonding electrode of each of the plurality of pixel electrodes PXE need to be accurately aligned, so that when the alignment is deviated, a defect that the light emitting element LE does not light up may be caused. In contrast, in the present disclosure, it is only necessary to provide each of the plurality of light emitting elements LE on the organic layer 210 for temporary adhesion at the opening OA defined by the bank 190, so that alignment accuracy as in the case when adhesion is performed by eutectic bonding is not required.

[0219] Furthermore, in the case of eutectic bonding, heat and pressure are required to adhere the bonding electrode of each of the plurality of light emitting elements LE to the bonding electrode of each of the pixel electrodes PXE, but the light emitting element LE may be tilted or damaged by the heat and pressure. In contrast, in the present disclosure, since heat and pressure are not required, the light emitting element LE is not tilted or damaged by the heat and pressure. Figure 8 The third subpixel SPX3 is not shown in the figure, but the third subpixel SPX3 may be formed substantially the same as the first subpixel SPX1. Therefore, the description of the third subpixel SPX3 is omitted.

[0220] Fig.10 It is shown in detail Figure 6 Layout diagram of another example of area A. Fig.11 is shown with Figure 6 A cross-sectional view of an example of a cross section of a light emitting element corresponding to line I3 - I3 ′.

[0221] Fig.10 and Fig.11 The implementation method and Figure 7 and Fig.9A The difference between the embodiments is that the distance L1_1 from the light emitting element LE to one end of the first connection electrode BE1 and the distance L2_1 from the light emitting element LE to one end of the second connection electrode BE2 are less than Figure 7 and Fig.9A The distances L1 and L2 of the embodiment. Fig.10 and Fig.11 In the implementation mode of Figure 7 and Fig.9A Redundant parts of the description.

[0222] refer to Figure 7 , Fig.9A , Fig.10 and Fig.11, the distances L1 and L1_1 from the light emitting element LE to one end of the first connection electrode BE1 can be adjusted to accommodate the size of each of the sub-pixels SPX1, SPX2, SPX3, and SPX4. Figure 7 and Fig.9A As shown in , when the number of pixels PX per unit area is small and the size of each of the sub-pixels SPX1, SPX2, SPX3, and SPX4 is large, the distance L1 from the light emitting element LE to one end of the first connection electrode BE1 may increase. Fig.10 and Fig.11 As shown in , when the number of pixels PX per unit area is large and the size of each of the sub-pixels SPX1, SPX2, SPX3, and SPX4 is small, the distance L1_1 from the light emitting element LE to one end of the first connection electrode BE1 may be reduced. One end of the first connection electrode BE1 may be a portion in contact with the pixel electrode PXE.

[0223] In addition, the distances L2 and L2_1 from the light emitting element LE to one end of the second connection electrode BE2 may be adjusted to accommodate the size of each of the sub-pixels SPX1, SPX2, SPX3, and SPX4. Figure 7 and Fig.9A As shown in , when the number of pixels PX per unit area is small and the size of each of the sub-pixels SPX1, SPX2, SPX3, and SPX4 is large, the distance L2 from the light emitting element LE to one end of the second connection electrode BE2 may increase. Fig.10 and Fig.11 As shown in , when the number of pixels PX per unit area is large and the size of each of the sub-pixels SPX1, SPX2, SPX3 and SPX4 is small, the distance L2_1 from the light emitting element LE to one end of the second connection electrode BE2 can be reduced. One end of the second connection electrode BE2 can be a portion in contact with the common electrode CE.

[0224] Fig.12 is a flowchart illustrating a method for manufacturing a display device according to one or more embodiments. Figures 13 to 19 is a cross-sectional view illustrating a method for manufacturing a display device according to one or more embodiments. Figures 13 to 19 shows the display panel and Figure 6 Examples of cross sections corresponding to lines I1-I1', I2-I2', and I3-I3' in FIG.

[0225] First, if Fig.13 As shown in FIG. 1 , a plurality of light emitting elements LE ( Fig.12 , or step S110 in the above process.

[0226] A plurality of light emitting elements LE are arranged on a fourth adhesive layer arranged on the light emitting element substrate ESUB. The plurality of light emitting elements LE are adhered and fixed to the fourth adhesive layer. The light emitting element substrate ESUB may include a material that allows light to pass therethrough. For example, the light emitting element substrate ESUB may include a transparent polymer such as polyimide, polyester, polyacrylic resin, polyepoxy resin, polyethylene, polystyrene, polyethylene terephthalate, etc. The fourth adhesive layer may include an adhesive material for adhering the plurality of light emitting elements LE. For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc.

[0227] Will refer to it later Figure 20 to Figure 26 A detailed description of a method of moving a plurality of light emitting elements LE formed on a semiconductor substrate SSUB to a light emitting element substrate ESUB will be described.

[0228] Second, a thin film transistor layer TFTL is formed on the substrate SUB, and a bank 190, a pixel electrode PXE, and a common electrode CE are formed on the thin film transistor layer TFTL by using a mask. Fig.12 , or step S120 in the above procedure.

[0229] A barrier layer BR is formed on the substrate SUB, and a first channel region CHA1 , a first source region S1 , and a first drain region D1 of the first thin film transistor TFT1 are formed on the barrier layer BR using a photolithography process.

[0230] Then, a first gate insulating layer 131 is formed on the first channel region CHA1, the first source region S1, the first drain region D1 of the first thin film transistor TFT1, and the barrier layer, and a first gate electrode G1 and a first capacitor electrode CAE1 of the first thin film transistor TFT1 are formed on the first gate insulating layer 131. The first channel region CHA1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1 may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, and / or amorphous silicon.

[0231] Then, a second gate insulating layer 132 is formed on the first gate insulating layer 131 , the first gate electrode G1 of the first thin film transistor TFT1 , and the first capacitor electrode CAE1 , and a second capacitor electrode CAE2 is formed on the second gate insulating layer 132 using a photolithography process.

[0232] Then, a first interlayer insulating layer 141 is formed on the second gate insulating layer 132 and the second capacitor electrode CAE2, and a second channel region CHA2, a second source region S2, and a second drain region D2 of the second thin film transistor TFT2 are formed using a photolithography process on the first interlayer insulating layer 141. The second channel region CHA2, the second source region S2, and the second drain region D2 of the second thin film transistor TFT2 may include an oxide semiconductor including indium (In), gallium (Ga), and / or oxygen (O).

[0233] Then, a third gate insulating layer 133 is formed on the first interlayer insulating layer 141 , the second channel region CHA2 , the second source region S2 , and the second drain region D2 of the second thin film transistor TFT2 , and a second gate electrode G2 of the second thin film transistor TFT2 is formed on the third gate insulating layer 133 using a photolithography process.

[0234] Then, a second interlayer insulating layer 142 is formed on the third gate insulating layer 133 and the second gate electrode G2 of the second thin film transistor TFT2. In addition, a first source connection hole PCT1 passing through the first gate insulating layer 131, the second gate insulating layer 132, the first interlayer insulating layer 141, the third gate insulating layer 133, and the second interlayer insulating layer 142, a second source connection hole BCT1 passing through the second interlayer insulating layer 142 and the third gate insulating layer 133, and a third source connection hole BCT2 passing through the second interlayer insulating layer 142 and the third gate insulating layer 133 are formed using a photolithography process. In addition, a first source connection electrode PCE1, a second source connection electrode SBE1, and a third source connection electrode SBE2 are formed on the second interlayer insulating layer 142 using a photolithography process.

[0235] Then, the first organic layer 160 is formed on the second interlayer insulating layer 142, the first source connection electrode PCE1, the second source connection electrode SBE1, and the third source connection electrode SBE2, and the first connection hole CT1 and the second connection hole CT2 respectively exposing the fourth source connection electrode PCE2 and the second power line VSL are formed on the first organic layer 160 by using a photolithography process. In addition, the pixel electrode PXE and the common electrode CE disposed on the second organic layer 180 and the bank 190 are formed by using a photolithography process. Each of the pixel electrodes PXE is disposed in the corresponding first connection hole CT1, and the common electrode CE disposed in the second connection hole CT2 and the disposed pixel electrode PXE are formed.

[0236] Third, if Fig.15 As shown in FIG. 1 , an organic layer 210 is formed on the pixel electrode PXE and the common electrode CE in the opening OA. Fig.12 , or step S130 in the above procedure.

[0237] The organic layer 210 may be a temporary adhesive layer, a short-term adhesive layer, and / or a temporary pinning layer for temporarily fixing or adhering the plurality of light emitting elements LE in a process of transferring the plurality of light emitting elements LE to the display panel 100. The thickness of the organic layer 210 may be less than the height of the opening OA or the thickness of the bank 190.

[0238] The organic layer 210 may be a photosensitive organic layer such as a photoresist. Alternatively, the organic layer 210 may be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0239] Fourth, if Fig.16 As shown in FIG. 1 , a plurality of light emitting elements LE on the light emitting element substrate ESUB are fixed to the organic layer 210 ( Fig.12 , or step S140 in the above procedure.

[0240] The stamp may include an adhesive layer having a thickness thicker than the fourth adhesive layer of the light emitting element substrate ESUB, and the plurality of light emitting elements LE may be detached from the fourth adhesive layer. Each of the plurality of light emitting elements LE detached from the light emitting element substrate ESUB and transferred to the stamp may be embedded and temporarily fixed in the organic layer 210. At this time, a portion of each of the plurality of light emitting elements LE may be embedded and temporarily fixed in the organic layer 210. For example, the undoped semiconductor layer USEM of each of the plurality of light emitting elements LE may be embedded and fixed in the organic layer 210.

[0241] When the organic layer 210 is a photosensitive organic layer such as a photoresist, after hardening (e.g., soft baking) the organic layer 210 at a first temperature, at least a portion of each of the plurality of light emitting elements LE is embedded in the organic layer 210. Then, the organic layer 210 may be completely cured at a second temperature higher than the first temperature. The first temperature may be approximately 100 degrees, and the second temperature may be approximately 230 degrees, but the present disclosure is not limited thereto. In the process of curing the organic layer 210 at the first temperature, because the first temperature is too low to completely cure the organic layer 210, the organic layer 210 may have fluidity, and thus the organic layer 210 may be spread over the opening OA. In addition, the process of completely curing the organic layer 210 at the second temperature may be performed for approximately 30 minutes.

[0242] Alternatively, since at least a portion of the light emitting element LE is inserted and embedded in the organic layer 210 , the organic layer 210 may remain between the bottom surface of the light emitting element LE and the pixel electrode PXE and between the bottom surface of the light emitting element LE and the common electrode CE.

[0243] Alternatively, when the fluidity of the organic layer 210 is high, the organic layer 210 may be pushed toward the edge of the opening OA by the light emitting element LE, and in this case, the organic layer 210 may be removed between the bottom surface of the light emitting element LE and the pixel electrode PXE and between the bottom surface of the light emitting element LE and the common electrode CE, or the organic layer 210 having a very small height may be provided. That is, the organic layer 210 may not be provided between the bottom surface of the light emitting element LE and the pixel electrode PXE and between the bottom surface of the light emitting element LE and the common electrode CE, or may be provided with a very small height.

[0244] Alternatively, when the fluidity of the organic layer 210 is small or the organic layer 210 is hard, the depth of the light emitting element LE inserted or embedded in the organic layer 210 is very small, or the light emitting element LE may be disposed on the organic layer 210 without being inserted or embedded in the organic layer 210 .

[0245] Then, by applying heat to the adhesive layer of the stamp to reduce the thickness of the adhesive layer, the stamp can be separated from the plurality of light emitting elements LE.

[0246] Fifth, if Fig.17 As shown in FIG. 1 , a first connection electrode BE1 and a second connection electrode BE2 are formed using a photolithography process. Fig.12 , or step S150 in the above process.

[0247] The first connection electrode BE1 connects the first electrode E1 of the light emitting element LE disposed on the organic layer 210 to the pixel electrode PXE in each of the subpixels SPX1 to SPX4. The second connection electrode BE2 connects the second electrode E2 of the light emitting element LE to the common electrode CE in each of the subpixels SPX1 to SPX4.

[0248] Sixth, if Fig.18 As shown in FIG. , a light blocking layer BM and a third organic layer 191 ( Fig.12 , or step S160 in the above procedure.

[0249] A first light blocking layer BM1 of the light blocking layer BM may be formed on the bank 190 , and a second light blocking layer BM2 of the light blocking layer BM may be formed on the first light blocking layer BM1 .

[0250] Fig.18The example in which the step portion extending to the side surface of the first light blocking layer BM1, a portion of the top surface of the first light blocking layer BM1, and the side surface of the second light blocking layer BM2 is formed because the length of the bottom surface of the second light blocking layer BM2 in the second direction DR2 is shorter than the length of the top surface of the first light blocking layer BM1 in the second direction DR2 is shown, but the present specification is not limited thereto. For example, the length of the bottom surface of the second light blocking layer BM2 in the second direction DR2 may be substantially the same as the length of the top surface of the first light blocking layer BM1 in the second direction DR2, and therefore, the side surface of the first light blocking layer BM1 and the side surface of the second light blocking layer BM2 may be connected without the step portion. Alternatively, the length of the bottom surface of the second light blocking layer BM2 in the second direction DR2 may be substantially the same as the length of the top surface of the first light blocking layer BM1 in the second direction DR2, but the angle at which the side surface of the first light blocking layer BM1 is inclined relative to the bottom surface of the first light blocking layer BM1 may be different from the angle at which the side surface of the second light blocking layer BM2 is inclined relative to the bottom surface of the second light blocking layer BM2. When the stepped portion is reduced or removed, occurrence of uneven light reflection such as light leakage due to diffuse reflection of light may be prevented or minimized. The third organic layer 191 may be formed to cover the light emitting element LE in a region partitioned by the light blocking layer BM.

[0251] Seventh, such as Fig.19 As shown in FIG. 1 , in the region separated by the light blocking layer BM, a first light conversion layer QDL1, a second light conversion layer QDL2, and a light-transmitting layer TPL are formed on the third organic layer 191, and color filters CF1, CF2, and CF3 are formed on the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL ( Fig.12 , or step S170 in the above procedure.

[0252] First, the first capping layer CAP1 covering the third organic layer 191 and the light blocking layer BM is formed, and the reflective layer RF is formed on the first capping layer CAP1 disposed on the side surface of the light blocking layer BM.

[0253] Then, in the area separated by the light blocking layer BM, a first light conversion layer QDL1 is formed in the area corresponding to the first subpixel SPX1, a second light conversion layer QDL2 is formed in the area corresponding to the second subpixel SPX2, and a light transmitting layer TPL is formed in the area corresponding to the fourth subpixel SPX4.

[0254] Then, a second capping layer CAP2 is formed on the first capping layer CAP1 , the first light conversion layer QDL1 , the second light conversion layer QDL2 , and the light transmitting layer TPL, and a fourth organic layer 192 is formed on the second capping layer CAP2 .

[0255] Then, a plurality of color filters CF1 , CF2 , and CF3 are formed on the fourth organic layer 192 , and a fifth organic layer 193 is formed on the plurality of color filters CF1 , CF2 , and CF3 .

[0256] like Figures 12 to 19 As shown in FIG. 1 , in each of the sub-pixels SPX1 to SPX4, an organic layer 210 may be formed on the pixel electrode PXE and the common electrode CE, and the light emitting element LE may be fixed to the organic layer 210 by disposing a portion of the light emitting element LE to be embedded in the organic layer 210 and then completely curing the organic layer 210. Therefore, in a process of transferring the plurality of light emitting elements LE to the display panel 100, each of the plurality of light emitting elements LE may be easily fixed.

[0257] Fig. 20 It is shown in detail Fig.12 Flow chart of step S110. Figure 21 to Figure 27 It is a cross-sectional view for explaining step S110.

[0258] In the following, reference will be made to Figure 20 to Figure 26 A process of moving a plurality of light emitting elements LE formed on a semiconductor substrate SSUB to a light emitting element substrate ESUB is described in detail.

[0259] First, if Fig.21 As shown in FIG. 1 , a plurality of light emitting elements LE ( Fig. 20 , or step S111 in the above procedure.

[0260] The semiconductor substrate SSUB may be a silicon wafer substrate or a sapphire substrate. A light emitting element material layer is deposited on the entire surface of the semiconductor substrate SSUB. The light emitting element material layer may be formed on the semiconductor substrate SSUB by an epitaxial growth process. As an epitaxial growth process, methods for forming the light emitting element material layer may include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), etc. Preferably, metal organic chemical vapor deposition (MOCVD) may be used, but the present disclosure is not limited thereto. Fig.9A As shown in , the light emitting element material layer may include an undoped semiconductor layer USEM, a second semiconductor layer SEM2, an active layer MQW and a first semiconductor layer SEM1.

[0261] Then, after forming a mask pattern on the light emitting element material layer, the light emitting element material layer may be etched according to the mask pattern to form a plurality of light emitting elements LE. The mask pattern may be removed after forming the plurality of light emitting elements LE.

[0262] The light emitting element material layer may be etched by a dry etching method, a wet etching method, a reactive ion etching (RIE) method, a deep reactive ion etching (DRIE) method, an inductively coupled plasma reactive ion etching (ICP-RIE) method, etc. The dry etching method may be suitable for vertical etching because anisotropic etching may be performed. When the dry etching method is used, the etching gas may be Cl 2 or 2 , but not limited to this.

[0263] Then, a first electrode E1 is formed on the first semiconductor layer SEM1 in each of the plurality of light emitting elements LE, and a second electrode E2 is formed on the second portion SEM2_2 of the second semiconductor layer SEM2. In order to compensate for the sum of the thickness difference between the first portion SEM2_1 and the second portion SEM2_2 of the second semiconductor layer SEM2, the thickness of the active layer MQW, and the thickness of the first semiconductor layer SEM1, the thickness of the second electrode E2 may be greater than the thickness of the first electrode E1. For example, the thickness of the second electrode E2 may be greater than the sum of the thickness difference between the first portion SEM2_1 and the second portion SEM2_2 of the second semiconductor layer SEM2, the thickness of the active layer MQW, and the thickness of the first semiconductor layer SEM1.

[0264] Then, a passivation layer covering side surfaces of the first semiconductor layer SEM1 , the active layer MQW, the second semiconductor layer SEM2 , and the undoped semiconductor layer USEM in each of the plurality of light emitting elements LE may be formed.

[0265] Second, if Fig. 22 As shown in FIG. 1 , a plurality of light emitting elements LE on the semiconductor substrate SSUB are moved to a first adhesive layer ADL1 ( Fig. 20 , or step S112 in the above procedure.

[0266] The first transfer substrate TSUB1 may be made of a transparent material to allow light to pass therethrough. For example, the first transfer substrate TSUB1 may include a transparent polymer such as polyimide, polyester, polyacrylic resin, polyepoxy resin, polyethylene, polystyrene, polyethylene terephthalate, etc. The first adhesive layer ADL1 disposed on one surface of the first transfer substrate TSUB1 may include an adhesive material for adhering the plurality of light emitting elements LE. For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc.

[0267] The first electrode E1 and the second electrode E2 of each of the plurality of light emitting elements LE may be adhered to the first adhesive layer ADL1 disposed on the first transfer substrate TSUB1. Then, the plurality of light emitting elements LE may be separated from the semiconductor substrate SSUB by a laser lift-off (LLO) process of irradiating laser to the semiconductor substrate SSUB. The laser may be a KrF excimer laser having a wavelength of approximately 248 nm, but the present disclosure is not limited thereto.

[0268] Third, if Fig.23 As shown in FIG. 1 , a plurality of light emitting elements LE on the first transfer substrate TSUB1 are moved to the first laser separation layer LLO1 ( Fig. 20 , or step S113 in the above procedure.

[0269] The second transfer substrate TSUB2 may be made of a transparent material to allow light to pass therethrough. For example, the second transfer substrate TSUB2 may include a transparent polymer such as polyimide, polyester, polyacrylic resin, polyepoxy resin, polyethylene, polystyrene, polyethylene terephthalate, etc. The first laser separation layer LLO1 disposed on the second transfer substrate TSUB2 may be a layer that can be separated by laser irradiation, and may include, for example, a transparent polymer such as polyimide.

[0270] When heat is applied in a state where one surface of each of the plurality of light emitting elements LE is in contact with the first laser separation layer LLO1, each of the plurality of light emitting elements LE may be adhered or fixed to the first laser separation layer LLO1, and as the viscosity of the first adhesive layer ADL1 is weakened, each of the plurality of light emitting elements LE may be separated from the first adhesive layer ADL1. One surface of each of the plurality of light emitting elements LE may be an opposite surface to the other surface on which the first electrode E1 and the second electrode E2 are disposed at each of the plurality of light emitting elements LE.

[0271] Fourth, if Fig.24 As shown in FIG. 1 , the first laser separation layer LLO1 is etched using the plurality of light emitting elements LE as a mask, and a second laser separation layer LLO2 ( Fig. 20 , or step S114 in the above procedure.

[0272] The plurality of light emitting elements LE are not etched but dry-etched using an etching gas DEG, in which only the first laser separation layer LLO1 is etched. That is, the first laser separation layer LLO1 is etched using the plurality of light emitting elements LE as a mask. Therefore, the first laser separation layer LLO1 that does not overlap with the plurality of light emitting elements LE in the thickness direction of the second transfer substrate TSUB2 can be removed. Therefore, the second laser separation layer LLO2 that overlaps with the plurality of light emitting elements LE in the thickness direction of the second transfer substrate TSUB2 can be formed. The second laser separation layer LLO2 can be disposed between each of the plurality of light emitting elements LE and the second transfer substrate TSUB2 in the thickness direction of the second transfer substrate TSUB2.

[0273] When the second laser separation layer LLO2 is not separated for each of the plurality of light emitting elements LE, when some of the light emitting elements LE are selectively transferred from the plurality of light emitting elements LE in a subsequent process, laser shock occurring between some of the light emitting elements LE irradiated with laser and the second laser separation layer LLO2 may propagate between the remaining light emitting elements LE and the second laser separation layer LLO2. In this case, some of the remaining light emitting elements LE may fall off the second laser separation layer LLO2 during the process of selectively transferring some of the light emitting elements LE.

[0274] However, in the present disclosure, the second laser separation layer LLO2 can be separated for each of the multiple light emitting elements LE, so that the laser shock occurring between some of the light emitting elements LE irradiated with laser and the second laser separation layer LLO2 in a subsequent process can be prevented from propagating between the remaining light emitting elements LE and the second laser separation layer LLO2.

[0275] Fifth, if Fig.25 and Fig.26 As shown in FIG. 1 , the second laser separation layer LLO2 is irradiated with laser to move the plurality of light emitting elements LE to the third adhesive layer ADL3 on the third transfer substrate TSUB3, and the second laser separation layer LLO2 ( Fig. 20 , or step S115 in the above procedure.

[0276] The third transfer substrate TSUB3 may be made of a transparent material to allow light to pass therethrough. For example, the third transfer substrate TSUB3 may include a transparent polymer such as polyimide, polyester, polyacrylic resin, polyepoxy resin, polyethylene, polystyrene, polyethylene terephthalate, etc. The third adhesive layer ADL3 disposed on one surface of the third transfer substrate TSUB3 may include an adhesive material for adhering the plurality of light emitting elements LE. For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc.

[0277] When the second laser separation layer LLO2 is irradiated with laser in a state where the first electrode E1 and the second electrode E2 of each of the multiple light emitting elements LE are in contact with the third adhesive layer ADL3 on the third transfer substrate TSUB3, the second laser separation layer LLO2 can be separated into a third laser separation layer LLO3 arranged on a surface of the second transfer substrate TSUB2 and a fourth laser separation layer LLO4 arranged on each of the multiple light emitting elements LE.

[0278] Then, if Fig.26 As shown in , the fourth laser separation layer LLO4 remaining on each of the plurality of light emitting elements LE can be removed by a wet etching process. The fourth laser separation layer LLO4 is etched using an etching material WEG, wherein the plurality of light emitting elements LE are not etched and only the fourth laser separation layer LLO4 is etched.

[0279] Sixth, if Fig. 27 As shown in FIG. 1 , a plurality of light emitting elements LE on the third transfer substrate TSUB3 are moved to the fourth adhesive layer ADL4 ( Fig. 20 , or step S116 in the above procedure.

[0280] In a state where one surface of each of the plurality of light emitting elements LE on the third transfer substrate TSUB3 is in contact with the fourth adhesive layer ADL4 on the light emitting element substrate ESUB, each of the plurality of light emitting elements LE is separated from the third adhesive layer ADL3. In this case, the viscosity of the fourth adhesive layer ADL4 may be greater than the viscosity of the third adhesive layer ADL3. One surface of each of the plurality of light emitting elements LE may be an opposite surface to the other surface on which the first electrode E1 and the second electrode E2 are disposed at each of the plurality of light emitting elements LE.

[0281] Fig.28 is a diagram illustrating a virtual reality device including a display device according to one or more embodiments. Fig.28 A virtual reality device 1 to which a display device 10_1 according to one or more embodiments is applied is shown.

[0282] refer to Fig.28 The virtual reality device 1 according to one or more embodiments may be a glasses-type device. The virtual reality device 1 according to one or more embodiments may include a display device 10_1, a left lens 10a, a right lens 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display device storage 50.

[0283] although Fig.28The virtual reality device 1 including the temples 30a and 30b is shown, but the virtual reality device 1 according to one or more embodiments may be applied to a head mounted display including a headband that can be worn on the head instead of the temples 30a and 30b. That is, the virtual reality device 1 according to one or more embodiments is not limited to Fig.28 The device shown in the figure can be applied to various electronic devices in various forms.

[0284] The display device storage 50 may store the display device 10_1 and the reflective member 40. The image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the right eye of the user through the right lens 10b. Therefore, the user may observe the virtual reality image displayed on the display device 10_1 through the right eye.

[0285] although Fig.28 The display device storage 50 is shown to be disposed at the right end of the support frame 20, but the present disclosure is not limited thereto. For example, the display device storage 50 may be disposed at the left end of the support frame 20, and in this case, the image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the left eye of the user through the left lens 10a. Therefore, the user may observe the virtual reality image displayed on the display device 10_1 through the left eye. Alternatively, the display device storage 50 may be disposed at both the left and right ends of the support frame 20. In this case, the user may observe the virtual reality image displayed on the display device 10_1 through both the left and right eyes.

[0286] Fig.29 is a diagram illustrating a smart watch including a display device according to one or more embodiments.

[0287] refer to Fig.29 According to one or more embodiments, the display device 10_2 may be applied to a smart watch 2 which is one of smart devices.

[0288] Fig.30 is a diagram showing a dashboard and a center instrument panel of a car including a display device according to one or more embodiments. Fig.30 A car to which the display device according to one or more embodiments is applied is shown.

[0289] refer to Fig.30 The display devices 10_a, 10_b and 10_c according to one or more embodiments may be applied to a dashboard of a car, a central instrument panel of a car or a central information display (CID) of a dashboard of a car. In addition, the display devices 10_d and 10_e according to one or more embodiments may be applied to a room mirror display instead of a rearview mirror of a car.

[0290] Fig.31 is a diagram illustrating a transparent display device including a display device according to one or more embodiments.

[0291] refer to Fig.31 , the display device 10_3 according to one or more embodiments may be applied to a transparent display device. The transparent display device may display an image IM and may also transmit light. Therefore, a user located on the front side of the transparent display device may observe an object RS or a background on the rear side of the transparent display device and an image IM displayed on the display device 10_3. When the display device 10_3 is applied to a transparent display device, the substrate SUB of the display device 10_3 may include a light-transmitting portion capable of transmitting light, or may be made of a material capable of transmitting light.

[0292] However, it should be understood that the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features described herein. By reference to the claims (and the equivalents of the claims should be included in the claims), the above and other aspects of the present disclosure will become more obvious to those of ordinary skill in the art to which the present disclosure belongs.

Claims

1. A display device, comprising: substrate; a bank on the substrate and including an opening; a pixel electrode and a common electrode spaced apart from each other in the opening on the substrate; an organic layer in the opening on the pixel electrode and the common electrode; a light emitting element on the organic layer and including a first electrode and a second electrode on a top surface of the light emitting element; a first connecting electrode connected to the pixel electrode and the first electrode of the light emitting element; as well as a second connecting electrode connected to the common electrode and the second electrode of the light emitting element, The organic layer is on at least a portion of one side surface and a bottom surface of the light emitting element.

2. The display device according to claim 1, wherein: The first connection electrode is on the organic layer between the bank and the one side surface of the light emitting element, The second connection electrode is on the organic layer between the bank and the other side surface of the light emitting element, and The other side surface of the light emitting element is a side surface opposite to the one side surface of the light emitting element.

3. The display device according to claim 1, wherein: The thickness of the organic layer is smaller than the thickness of the bank.

4. The display device according to claim 1, wherein: The light emitting element comprises: a first semiconductor layer connected to the first electrode; an active layer connected to the first semiconductor layer; a second semiconductor layer including a first portion connected to the active layer and a second portion connected to the second electrode; and An undoped semiconductor layer is connected to the second semiconductor layer.

5. The display device according to claim 4, wherein: A thickness of the first portion of the second semiconductor layer is greater than a thickness of the second portion of the second semiconductor layer.

6. The display device according to claim 4, wherein: The undoped semiconductor layer is on the organic layer, The second semiconductor layer is on the undoped semiconductor layer, The active layer is on the first portion of the second semiconductor layer, The first semiconductor layer is on the active layer, The first electrode is on the first semiconductor layer, and The second electrode is on the second portion of the second semiconductor layer.

7. The display device according to claim 6, wherein: The thickness of the second electrode is greater than the thickness of the first electrode.

8. The display device according to claim 4, wherein: The organic layer is on at least a portion of one side surface of the second semiconductor layer and a side surface and a bottom surface of the undoped semiconductor layer.

9. The display device according to claim 4, wherein: The first connection electrode is on at least a portion of one side surface of the second semiconductor layer, one side surface of the first semiconductor layer, and one side surface of the active layer.

10. The display device according to claim 6, wherein: The second connection electrode is on at least a portion of one side surface of the second electrode.

11. The display device according to claim 10, wherein: The second connection electrode is on at least a portion of a top surface of the second electrode and the entire one side surface of the second electrode.

12. The display device according to claim 6, wherein: The organic layer is on at least a portion of a top surface of the second portion of the second semiconductor layer.

13. The display device according to claim 1, wherein: An area of ​​the organic layer is larger than an area of ​​the first connection electrode and an area of ​​the second connection electrode.

14. The display device according to claim 1, wherein: The area of ​​the pixel electrode is larger than the area of ​​the first connecting electrode, and An area of ​​the common electrode is larger than an area of ​​the second connection electrode.

15. The display device according to claim 1, wherein: The pixel electrode and the common electrode include an opaque metal material, and The first connection electrode and the second connection electrode include a transparent conductive oxide.

16. The display device according to claim 1, wherein: The thickness of the bank is 0.5 μm or more.

17. A method for manufacturing a display device, comprising: preparing a plurality of light emitting elements on a light emitting element substrate; forming a bank having a plurality of openings on a substrate, and forming a pixel electrode and a common electrode in each of the plurality of openings; forming an organic layer on the pixel electrode and the common electrode in each of the plurality of openings; adhering each of the plurality of light emitting elements on the light emitting element substrate to the organic layer in each of the plurality of openings; as well as A first connection electrode connecting the pixel electrode to the first electrode of the light emitting element and a second connection electrode connecting the common electrode to the second electrode of the light emitting element are formed on the organic layer.

18. The method according to claim 17, further comprising: forming a light blocking layer on the bank; In the regions separated by the light blocking layer, a first light conversion layer is formed in the region corresponding to the first sub-pixel, a second light conversion layer is formed in the region corresponding to the second sub-pixel, and a light-transmitting layer is formed in the region corresponding to the third sub-pixel; as well as A first color filter is formed on the first light conversion layer, a second color filter is formed on the second light conversion layer, and a third color filter is formed on the light-transmitting layer.

19. The method according to claim 17, wherein: Adhering each of the plurality of light emitting elements on the light emitting element substrate to the organic layer in each of the plurality of openings includes: curing the organic layer in each of the plurality of openings at a first temperature; inserting a portion of each of the plurality of light emitting elements into the organic layer in each of the plurality of openings; and The organic layer is cured at a second temperature higher than the first temperature.

20. The method according to claim 17, wherein: Adhering each of the plurality of light emitting elements on the light emitting element substrate to the organic layer in each of the plurality of openings includes: detaching each of the plurality of light emitting elements from the light emitting element substrate by using a stamp having an adhesive layer; inserting a portion of each of the plurality of light emitting elements into the organic layer in each of the plurality of openings; and Each of the plurality of light emitting elements is detached from the stamp by applying heat to the adhesive layer of the stamp.

21. A display device, comprising: substrate; a pixel electrode and a common electrode spaced apart from each other on the substrate; an insulating layer, on the substrate and at least partially overlapping the pixel electrode and the common electrode; a light emitting element, on the insulating layer, and comprising a first electrode and a second electrode; a first connecting electrode electrically connected to the pixel electrode and the first electrode of the light emitting element; as well as a second connecting electrode electrically connected to the common electrode and the second electrode of the light emitting element, At least one of the first electrode and the second electrode of the light emitting element includes a region exposed by the insulating layer.

22. An electronic device for providing an image, comprising: Display device, including substrate; a bank on the substrate and including an opening; a pixel electrode and a common electrode spaced apart from each other on the substrate in the opening; an organic layer in the opening on the pixel electrode and the common electrode; a light emitting element on the organic layer and including a first electrode and a second electrode on a top surface thereof; a first connecting electrode connected to the pixel electrode and the first electrode of the light emitting element; as well as a second connecting electrode connected to the common electrode and the second electrode of the light emitting element, The organic layer is on at least a portion of a bottom surface and one side surface of the light emitting element.

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