Display panel, display device and preparation method of display panel

Abstract

The invention provides a display panel, a display device and a preparation method of the display panel, the display panel comprises a substrate, a first electrode, a second electrode, a first insulating layer, a second insulating layer and an active layer, the first electrode is arranged on one side of the substrate, and the first insulating layer is at least partially arranged on one side, away from the substrate, of the first electrode and comprises a first hole; the second insulating layer is at least partially arranged on the side, away from the substrate, of the first pole and comprises a second hole, and the first hole is communicated with the second hole. The second electrode is arranged on the sides, away from the substrate, of the first insulating layer and the second insulating layer, and the active layer is arranged on the side, away from the substrate, of the second electrode, extends into the first hole and the second hole and is connected with the first electrode. Wherein the dielectric constant in the second insulating layer is greater than that in the first insulating layer, and the orthographic projection of the first insulating layer on the substrate is respectively overlapped with the orthographic projections of the first pole and the second pole on the substrate.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a display panel, a display device, and a method for manufacturing a display panel. Background Art

[0002] With the diversification of consumer market demands, consumers have higher and higher requirements for display devices. For most consumers, high-resolution and high-refresh-rate displays can bring smoother gaming and visual experiences. In order to achieve higher-specification display effects, higher requirements are placed on the performance of thin-film transistor devices in the array substrate that drives the panel display. Summary of the invention

[0003] The embodiments of the present application provide a display panel, a display device, and a method for manufacturing a display panel, which can improve the reliability of thin film transistors.

[0004] In a first aspect, an embodiment of the present application provides a display panel, which includes a substrate, a first pole, a second pole, a first insulating layer, a second insulating layer and an active layer, wherein the first pole is arranged on one side of the substrate, the first insulating layer is at least partially arranged on the side of the first pole away from the substrate and includes a first hole, the second insulating layer is at least partially arranged on the side of the first pole away from the substrate and includes a second hole, and the first hole is connected to the second hole.

[0005] The second electrode is arranged on the side of the first insulating layer and the second insulating layer away from the substrate, and the active layer is arranged on the side of the second electrode away from the substrate, and extends into the first hole and the second hole and is connected to the first electrode. The dielectric constant in the second insulating layer is greater than the dielectric constant in the first insulating layer, and the orthographic projection of the first insulating layer on the substrate overlaps with the orthographic projection of the first electrode and the second electrode on the substrate respectively.

[0006] In some embodiments, the active layer is disposed in contact with the sidewall of the second hole;

[0007] In some embodiments, the active layer includes a first portion disposed in contact with the first electrode, a second portion disposed in contact with the second electrode, and a connecting portion connecting the first portion and the second portion;

[0008] Wherein, at least a portion of the connecting portion is disposed in contact with the side wall of the second hole;

[0009] In some embodiments, the display panel further includes a control electrode located on a side of the active layer facing away from the substrate, and a third insulating layer located between the control electrode and the active layer;

[0010] In the radial direction of the first hole, the projection of the control electrode and the projection of the connecting portion are arranged to overlap;

[0011] In some embodiments, a contact area between the active layer and the sidewall of the second hole is greater than a contact area between the active layer and the sidewall of the first hole.

[0012] In some embodiments, the active layer is spaced apart from the sidewall of the first hole;

[0013] In some embodiments, the thin film transistor includes an insulating portion disposed in the first hole, the dielectric constant of the insulating portion is greater than the dielectric constant of the first insulating layer, and the insulating portion is located between the active layer and the sidewall of the first hole;

[0014] In some embodiments, the insulating portion and the second insulating layer include the same material;

[0015] In some embodiments, the second insulating layer includes an insulating portion.

[0016] In some embodiments, the second insulating layer is completely located in the first hole and is disposed in contact with the sidewall of the first hole.

[0017] In some embodiments, the second insulating layer is at least partially located on a side of the first insulating layer facing away from the substrate;

[0018] In some embodiments, an orthographic projection of the first hole on the substrate overlaps and exceeds an orthographic projection of the second hole on the substrate.

[0019] In some embodiments, the second insulating layer includes a body portion located on a side of the first insulating layer facing away from the substrate, and an insulating portion located in the first hole;

[0020] The active layer is attached to the main body portion and the wall surface of the insulating portion facing the second hole;

[0021] In some embodiments, the main body is disposed in contact with a surface of the first insulating layer facing away from the substrate.

[0022] In some embodiments, the first insulating layer is disposed on a side of the second insulating layer facing away from the substrate, and an orthographic projection of the first hole on the substrate covers and exceeds an orthographic projection of the second hole on the substrate;

[0023] Wherein, the second pole is arranged to cover the side wall of the first hole;

[0024] In some embodiments, a surface of the first insulating layer facing away from the substrate is disposed in contact with the second electrode;

[0025] In some embodiments, the second insulating layer adheres to and covers a portion of the structure of the first electrode.

[0026] In some embodiments, the active layer is disposed in contact with the sidewall of the first hole;

[0027] In some embodiments, the active layer includes a first portion disposed in contact with the first electrode, a second portion disposed in contact with the second electrode, and a connecting portion connecting the first portion and the second portion;

[0028] Wherein, at least a portion of the connecting portion is disposed in contact with the side wall of the first hole;

[0029] In some embodiments, a portion of the structure in the connecting portion is disposed in contact with the side wall of the second hole;

[0030] In some embodiments, the orthographic projections of the first hole and the second hole on the substrate coincide;

[0031] In some embodiments, the thickness of the second insulating layer is greater than the thickness of the first insulating layer.

[0032] In some embodiments, the material density in the first insulating layer is less than the material density in the second insulating layer; and / or, the first insulating layer comprises an organic material and the second insulating layer comprises an inorganic material;

[0033] In some embodiments, the first insulating layer and the second insulating layer include the same material;

[0034] In some embodiments, the material of the first insulating layer includes at least one of silicon oxide and polyimide;

[0035] In some embodiments, a material of the second insulating layer includes at least one of silicon oxide and silicon nitride.

[0036] In a second aspect, an embodiment of the present application provides a method for preparing a thin film transistor, comprising:

[0037] forming a first electrode on one side of the substrate;

[0038] A first insulating layer and a second insulating layer are formed on a side of the first electrode facing away from the substrate, the first insulating layer includes a first hole, the second insulating layer includes a second hole, and the dielectric constant in the second insulating layer is greater than the dielectric constant in the first insulating layer;

[0039] A second pole is formed on the side of the first insulating layer and the second insulating layer facing away from the substrate, and the orthographic projection of the first insulating layer on the substrate overlaps with the orthographic projection of the first pole and the second pole on the substrate respectively;

[0040] An active layer is formed on a side of the second electrode facing away from the substrate. The active layer extends into the first hole and the second hole and is connected to the first electrode.

[0041] In some embodiments, the step of forming a first insulating layer and a second insulating layer on a side of the first electrode facing away from the substrate includes:

[0042] forming a first insulating layer and a first hole on one side of the substrate;

[0043] forming a second insulating material layer on a side of the first insulating layer facing away from the substrate, wherein the second insulating material layer fills the first hole;

[0044] The partial structure of the second insulating material layer located in the first hole is removed to form a second insulating layer and a second hole. The second insulating layer includes a main body located on the side of the first insulating layer away from the substrate, and an insulating portion located in the first hole and attached to the side wall of the first hole.

[0045] In a third aspect, an embodiment of the present application provides a display device, which includes a display panel in any of the aforementioned embodiments, or a display panel prepared by a preparation method in any of the aforementioned embodiments.

[0046] The embodiment of the present application provides a display panel, a display device and a method for manufacturing a display panel, wherein a first insulating layer is added, the first insulating layer itself has a relatively small dielectric constant, and the orthographic projection of the first insulating layer on the substrate can be overlapped with the orthographic projections of the first pole and the second pole on the substrate at the same time, so that the presence of the first insulating layer can effectively reduce the parasitic capacitance generated by the overlap of the first pole and the second pole, improve the signal transmission efficiency of the thin film transistor, reduce the problem of uneven display or brightness reduction, and improve reliability. The presence of the second insulating layer helps to maintain the good characteristics of the thin film transistor itself and improve the operating performance of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] Figure 1 is a schematic diagram of a cross-sectional structure of a display panel in the related art;

[0049] Figure 2 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application;

[0050] Figure 3 is a schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present application;

[0051] Figure 4 is a schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present application;

[0052] Figure 5 is a schematic cross-sectional structure diagram of another display panel provided in an embodiment of the present application;

[0053] Figure 6 yes Figure 2 Schematic diagram of the enlarged structure at the middle area Q;

[0054] Figure 7 is a structural schematic diagram of a display device provided in an embodiment of the present application;

[0055] Figure 8 is a flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0056] Figures 9a to 9d It is a process structure schematic diagram of a method for preparing a display panel provided in an embodiment of the present application;

[0057] Fig.10 is a flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0058] Figures 11a to 11c It is a process structure schematic diagram of a method for preparing a display panel provided in an embodiment of the present application.

[0059] Marking Description:

[0060] 10. Substrate;

[0061] 20. First pole;

[0062] 30. a first insulating layer; 31. a first hole;

[0063] 40. Second Pole;

[0064] 50. active layer; 51. first portion; 52. second portion; 53. connecting portion;

[0065] 60. second insulating layer; 61. second hole; 62. main body; 63. insulating part;

[0066] 70. Control pole;

[0067] 80. The third insulating layer;

[0068] 91, source; 92, drain;

[0069] 60', second insulating material layer;

[0070] X, thickness direction; DETAILED DESCRIPTION

[0071] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0072] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0073] Thin film transistors are usually installed in display panels. In high refresh rate, low energy consumption, and demultiplexing display panel products, thin film transistors need to have a large on-state current to meet the charging rate requirements, or reduce the size of the thin film transistor to achieve narrow borders and high transmittance. Short channel technology can greatly increase the on-state current of the device and reduce the size of the device. If the channel is reduced to within 1 micron, the on-state current can be increased by more than 4 times compared to conventional thin film transistors.

[0074] See also Figure 1 In the related art, the channel structure in the thin film transistor can be set as a vertical channel, which can greatly reduce the channel size and improve the current passing capacity of the thin film transistor per unit area. However, in this solution, the overlapping area between the source 91 and the drain 92 in the thin film transistor is large, and a large overlapping area will produce a large parasitic capacitance. The presence of parasitic capacitance will increase the signal delay of the signal line, resulting in uneven display or reduced brightness, and it is also easy to increase power consumption, which is not conducive to long-term use.

[0075] Regarding the above issues, please refer to Figures 2 to 5 An embodiment of the present application provides a display panel, which includes a substrate 10, a first pole 20, a second pole 40, a first insulating layer 30, a second insulating layer 60 and an active layer 50. The first pole 20 is arranged on one side of the substrate 10, the first insulating layer 30 is at least partially arranged on the side of the first pole 20 away from the substrate 10 and includes a first hole 31, the second insulating layer 60 is at least partially arranged on the side of the first pole 20 away from the substrate 10 and includes a second hole 61, and the first hole 31 is connected to the second hole 61.

[0076] The second pole 40 is disposed on the side of the first insulating layer 30 and the second insulating layer 60 away from the substrate 10, and the active layer 50 is disposed on the side of the second pole 40 away from the substrate 10, and extends into the first hole 31 and the second hole 61 and is connected to the first pole 20. The dielectric constant in the second insulating layer 60 is greater than the dielectric constant in the first insulating layer 30, and the orthographic projection of the first insulating layer 30 on the substrate 10 overlaps with the orthographic projection of the first pole 20 and the second pole 40 on the substrate 10, respectively.

[0077] The display panel includes a conductor structure, a semiconductor structure and an insulating structure, wherein the first electrode 20 and the second electrode 40 are both conductor structures, the active layer 50 is a semiconductor structure, and the first insulating layer 30 and the second insulating layer 60 are insulating structures. On this basis, through the cooperation between different structures, a thin film transistor exists in the display panel.

[0078] A thin film transistor is a transistor made of thin film materials. It is an insulated gate effect transistor, mainly composed of a conductor structure, a semiconductor structure and an insulating layer. The conductor structure includes a first electrode 20, a second electrode 40 and a control electrode 70, the semiconductor structure includes an active layer 50, and the insulating layer is used to insulate and separate different conductor structures and semiconductor structures.

[0079] Optionally, the control electrode 70 is a gate electrode in a thin film transistor, one of the first electrode 20 and the second electrode 40 is a source electrode in the thin film transistor, and the other is a drain electrode in the thin film transistor. Since the first electrode 20 is located on the side of the active layer 50 facing the substrate 10, the first electrode 20 can not only serve as a source electrode or a drain electrode, but also play a light shielding role, reducing part of the ambient light passing through the first electrode 20 to irradiate the active layer 50 and affecting the structural stability of the active layer 50, thereby improving the overall structural stability of the thin film transistor.

[0080] The substrate 10 is a film layer structure used to support the display panel, and the thin film transistor is arranged on one side of the substrate 10. The substrate 10 may include various materials, such as glass, metal or plastic. Optionally, the substrate 10 may include a flexible material. The flexible material mentioned here refers to a material that can be twisted, bent, folded or curled. The flexible material may include ultra-thin glass, metal or plastic.

[0081] The first electrode 20 is disposed on one side of the substrate 10, the first insulating layer 30 and the second insulating layer 60 are at least partially disposed on the side of the first electrode 20 away from the substrate 10, the second electrode 40 is disposed on the side of the first insulating layer 30 and the second insulating layer 60 away from the substrate 10, the first electrode 20 and the second electrode 40 are both conductive, and at least one of the first insulating layer 30 and the second insulating layer 60 can insulate and separate the first electrode 20 from the second electrode 40. The first insulating layer 30 and the second insulating layer 60 can have a variety of positional relationships, such as Figure 4 As shown, the first insulating layer 30 may be at least partially located on the side of the second insulating layer 60 facing away from the substrate 10, or as shown in FIG. Figure 2 and Figure 3 As shown, the second insulating layer 60 may be at least partially located on the side of the first insulating layer 30 facing away from the substrate 10, or as shown in FIG. Figure 5 As shown, the first insulating layer 30 may also be disposed on the same layer as the second insulating layer 60 , which is not limited in the embodiment of the present application.

[0082] The active layer 50 is arranged on the side of the first pole 20 and the second pole 40 away from the substrate 10 and is connected to the first pole 20 and the second pole 40. The active layer 50 includes a semiconductor material. Further, the active layer 50 includes a channel region corresponding to the control pole 70 and a source region and a drain region located on different sides of the channel region. One of the source region and the drain region is connected to the first pole 20, and the other is connected to the second pole 40.

[0083] In order to meet the connection requirements between the active layer 50 and the first pole 20 and the second pole 40, a first hole 31 needs to be opened in the first insulating layer 30, and a second hole 61 needs to be opened in the second insulating layer 60. Part of the structure in the first pole 20 can be exposed relative to the first hole 31 and the second hole 61, so that the active layer 50 arranged on the side of the second pole 40 away from the substrate 10 can extend into the first hole 31 and the second hole 61 and be connected to the first pole 20.

[0084] It should be noted that, considering that there are various positional relationships between the first insulating layer 30 and the second insulating layer 60, there are also various sizes and positional relationships between the first hole 31 and the second hole 61. For example, Figure 4 As shown, the first insulating layer 30 is at least partially located on the side of the second insulating layer 60 facing away from the substrate 10, or as shown in FIG. Figure 2 and Figure 3 As shown, the second insulating layer 60 is at least partially located on the side of the first insulating layer 30 facing away from the substrate 10, and the first hole 31 and the second hole 61 are arranged side by side and connected in the thickness direction X of the substrate 10. At this time, the orthographic projection of the first hole 31 on the substrate 10 can be completely located within the orthographic projection of the second hole 61 on the substrate 10, or the orthographic projections of the first hole 31 and the second hole 61 on the substrate 10 can also only partially overlap.

[0085] In other embodiments, such as Figure 5As shown, the second insulating layer 60 can also be located in the first hole 31, that is, the first insulating layer 30 and the second insulating layer 60 are arranged in the same layer. In this case, the first hole 31 and the second hole 61 are located at the same height position in the thickness direction X of the substrate 10, and the first hole 31 can include the entire space of the second hole 61. At this time, the first pole 20 is exposed relative to the second hole 61, and the active layer 50 located on the side of the second pole 40 away from the substrate 10 can extend into the second hole 61 and be connected to the first pole 20.

[0086] The embodiment of the present application does not limit the specific positional relationship between the first insulating layer 30 and the second insulating layer 60, and the positional relationship between the first hole 31 and the second hole 61. As long as the orthographic projection of the first insulating layer 30 on the substrate 10 overlaps with the orthographic projection of the first pole 20 and the second pole 40 on the substrate 10, and the active layer 50 can be connected to the first pole 20 by extending into the first hole 31 and the second hole 61.

[0087] The dielectric constant in the second insulating layer 60 is greater than the dielectric constant in the first insulating layer 30. The dielectric constant refers to the degree of polarization of a substance in an electric field. When an electric field acts on a substance, the charges inside the substance will be redistributed and form polarized charges under the action of the electric field, generating a local electric field. The size of the dielectric constant depends on the molecular structure and chemical composition of the substance.

[0088] In the related art, the first electrode 20 and the second electrode 40 are often insulated by only one insulating layer, and there is an overlapping area between the first electrode 20 and the second electrode 40. On this basis, in order to improve the use characteristics of the thin film transistor, the insulating layer often has a larger dielectric constant, and the larger dielectric constant leads to a smaller effect on the parasitic capacitance generated between the first electrode 20 and the second electrode 40. The presence of parasitic capacitance will increase the signal delay of the signal line, resulting in uneven display or reduced brightness, and it is also easy to increase power consumption, which is not conducive to long-term use.

[0089] In view of this, the embodiment of the present application adds a first insulating layer 30, which has a relatively small dielectric constant, and the orthographic projection of the first insulating layer 30 on the substrate 10 can overlap with the orthographic projections of the first pole 20 and the second pole 40 on the substrate 10, respectively. In this way, the presence of the first insulating layer 30 can effectively reduce the parasitic capacitance generated by the overlap of the first pole 20 and the second pole 40, improve the signal transmission efficiency of the thin film transistor, reduce the problem of uneven display or brightness reduction, and improve display reliability. The presence of the second insulating layer 60 helps to maintain the good characteristics of the thin film transistor itself and improve the operating performance of the thin film transistor.

[0090] It should be noted that the embodiment of the present application does not limit the positional relationship of the second insulating layer 60 relative to the first pole 20 and the second pole 40. Optionally, the orthographic projection of the second insulating layer 60 on the substrate 10 may only overlap with the orthographic projection of the first pole 20 on the substrate 10, or the orthographic projection of the second insulating layer 60 on the substrate 10 may also overlap with the orthographic projection of the first pole 20 and the second pole 40 on the substrate 10 at the same time.

[0091] In some embodiments, Figures 2 to 5 As shown, the active layer 50 is disposed in contact with the side wall of the second hole 61 .

[0092] The active layer 50 is disposed in contact with the sidewall of the second hole 61, that is, the active layer 50 can be in direct contact with the second insulating layer 60. Figure 3 As shown, the active layer 50 can be arranged in contact with the side wall of the first hole 31, or as shown in Figure 2 As shown, the active layer 50 may also be spaced apart from the side wall of the first hole 31 , that is, the active layer 50 may be in direct contact with the first insulating layer 30 , or the active layer 50 may also be arranged without contact with the first insulating layer 30 , which is not limited in the embodiment of the present application.

[0093] Generally, the performance characteristics of a thin film transistor will be affected by the insulating layer in contact with the active layer 50. On this basis, in the embodiment of the present application, the active layer 50 is laminated with the side wall of the second hole 61 so that the active layer 50 can be in contact with the second insulating layer 60, thereby reducing the adverse effects on the flow of electrons or holes in the active layer 50 with the help of the second insulating layer 60 with a high dielectric constant, thereby improving the operating reliability and performance characteristics of the thin film transistor.

[0094] In some embodiments, the active layer 50 includes a first portion 51 disposed in contact with the first pole 20, a second portion 52 disposed in contact with the second pole 40, and a connecting portion 53 connecting the first portion 51 and the second portion 52. At least a portion of the connecting portion 53 is disposed in contact with the side wall of the second hole 61.

[0095] The first portion 51 is disposed on the side of the first electrode 20 away from the substrate 10 and connected to the first electrode 20, and the first portion 51 corresponds to one of the source region and the drain region in the active layer 50. The second portion 52 is disposed on the side of the second electrode 40 away from the substrate 10 and connected to the second electrode 40, and the second portion 52 corresponds to the other of the source region and the drain region in the active layer 50. The connecting portion 53 is used to connect the first portion 51 and the second portion 52 and extends along the thickness direction X of the substrate 10, and the connecting portion 53 corresponds to the channel region in the active layer 50. Further optionally, the display panel further includes a control electrode 70 located on the side of the active layer 50 away from the substrate 10, and a third insulating layer 80 located between the control electrode 70 and the active layer 50, and in the radial direction of the first hole 31, the projection of the control electrode 70 overlaps with the projection of the connecting portion 53, so that the control electrode 70 can control whether the connecting portion 53 is turned on, thereby realizing the control of the thin film transistor being turned off.

[0096] At least a portion of the connecting portion 53 is arranged in contact with the side wall of the second hole 61, wherein the connecting portion 53 can be arranged only in contact with the side wall of the second hole 61, or can be arranged in contact with the side walls of the first hole 31 and the second hole 61 at the same time, that is, the connecting portion 53 can be arranged only in contact with the second insulating layer 60, or can be arranged in contact with the first insulating layer 30 and the second insulating layer 60 at the same time, and the embodiment of the present application is not limited to this.

[0097] In the embodiment of the present application, by fitting at least a portion of the connecting portion 53 to the sidewall of the second hole 61, the adverse effect on the flow of electrons or holes in the connecting portion 53 is reduced by means of the second insulating layer 60 with a high dielectric constant, thereby improving the operational reliability and performance characteristics of the thin film transistor. At the same time, by adjusting the axial dimensions of the first hole 31 and the second hole 61 and the positional relationship between the two, the length of the channel region is limited, meeting the use needs of different situations, and having strong practicality.

[0098] In some embodiments, the contact area between the active layer 50 and the sidewall of the second hole 61 is greater than the contact area between the active layer 50 and the sidewall of the first hole 31 .

[0099] It should be noted that in the embodiments of the present application, Figure 2 As shown, the active layer 50 may be disposed only in contact with the sidewall of the second hole 61, or as shown in FIG. Figure 3 As shown, the active layer 50 can also be arranged in contact with the side wall of the first hole 31 and the side wall of the second hole 61 at the same time, as long as the contact area between the active layer 50 and the side wall of the second hole 61 is greater than the contact area between the active layer 50 and the side wall of the first hole 31.

[0100] In the embodiment of the present application, compared with the active layer 50 and the second insulating layer 60, the active layer 50 and the first insulating layer 30 have a smaller contact area, which can reduce the adverse effect of the first insulating layer 30 on the particle movement process in the active layer 50, thereby improving the performance characteristics of the thin film transistor.

[0101] In some embodiments, Figure 2 , Figure 4 as well as Figure 5 As shown, the active layer 50 is spaced apart from the sidewall of the first hole 31 .

[0102] The active layer 50 is spaced apart from the side wall of the first hole 31, that is, the active layer 50 does not contact the first insulating layer 30, wherein other structures different from the first insulating layer 30 may exist between the active layer 50 and the side wall of the first hole 31, and relative isolation between the active layer 50 and the first insulating layer 30 is achieved by means of this structure.

[0103] In the embodiment of the present application, the active layer 50 and the first insulating layer 30 are spaced apart from each other, so that the adverse effect of the contact between the active layer 50 and the first insulating layer 30 on the particle movement process in the active layer 50 can be reduced, thereby further improving the performance characteristics of the thin film transistor.

[0104] In some embodiments, see Figure 2 and Figure 6 The thin film transistor includes an insulating portion 63 disposed in the first hole 31 , the dielectric constant of the insulating portion 63 is greater than the dielectric constant of the first insulating layer 30 , and the insulating portion 63 is located between the active layer 50 and the sidewall of the first hole 31 .

[0105] The insulating portion 63 is a structure including insulating material and having a dielectric constant greater than that of the first insulating layer 30. The insulating portion 63 is sandwiched between the active layer 50 and the side wall of the first hole 31, that is, the existence of the insulating portion 63 can achieve mutual isolation between the active layer 50 and the first insulating layer 30, thereby improving the performance characteristics of the thin film transistor.

[0106] It should be noted that the embodiment of the present application does not limit the material composition of the insulating portion 63, as long as the dielectric constant of the insulating portion 63 is greater than the dielectric constant of the first insulating layer 30. Optionally, the insulating portion 63 and the second insulating layer 60 include the same material. Further optionally, the second insulating layer 60 includes the insulating portion 63, that is, the insulating portion 63 is a part of the second insulating layer 60, and the second insulating layer 60 partially extends into the first hole 31 and is arranged in contact with the side wall of the first hole 31. This design can reduce the types of insulating materials in the thin film transistor while improving the performance characteristics of the thin film transistor, which helps to reduce costs and helps to simplify the preparation process.

[0107] In some optional embodiments, such as Figure 5 As shown, the second insulating layer 60 is completely located in the first hole 31 and is disposed in close contact with the side wall of the first hole 31 .

[0108] In the embodiment of the present application, the insulating portion 63 is the entire structure of the second insulating layer 60, and the second insulating layer 60 does not extend beyond the surface of the first insulating layer 30 away from the substrate 10. This can improve the performance characteristics of the thin film transistor while reducing the impact of the existence of the second insulating layer 60 on the overall thickness of the display panel, which is conducive to a lightweight design.

[0109] In some embodiments, the second insulating layer 60 is at least partially located on a side of the first insulating layer 30 facing away from the substrate 10 .

[0110] like Figure 3 As shown, the second insulating layer 60 may be completely located on the side of the first insulating layer 30 facing away from the substrate 10, or as shown in FIG. Figure 2 As shown, the second insulating layer 60 may also be only partially located on the side of the first insulating layer 30 away from the substrate 10. During the preparation process, the second insulating layer 60 is formed after the first insulating layer 30, and the formed first insulating layer 30 can cover and fit part of the structure in the first pole 20, and the formed second insulating layer 60 can be in contact with the second pole 40, so that the cooperation between the first insulating layer 30 and the second insulating layer 60 helps to further improve the insulation reliability between the first pole 20 and the second pole 40. Among them, there may be other film layer structures between the first insulating layer 30 and the second insulating layer 60, or there may be no other film layer structures, which is not limited in the embodiment of the present application.

[0111] In some embodiments, the orthographic projection of the first hole 31 on the substrate 10 covers and exceeds the orthographic projection of the second hole 61 on the substrate 10 .

[0112] In the embodiment of the present application, the orthographic projection sizes of the first hole 31 and the second hole 61 on the substrate 10 are not completely consistent, and the orthographic projection of the first hole 31 on the substrate 10 covers and exceeds the orthographic projection of the second hole 61 on the substrate 10, so that during the preparation process of the second insulating layer 60, part of the structure in the second insulating layer 60 will be in the first hole 31. Optionally, as Figure 2 and Figure 6 As shown, the second insulating layer 60 includes a main body 62 located on the side of the first insulating layer 30 away from the substrate 10 and an insulating portion 63 located in the first hole 31 . The active layer 50 is attached to the main body 62 and the wall of the insulating portion 63 facing the second hole 61 .

[0113] The body portion 62 is a partial structure of the second insulating layer 60 located on the side of the first insulating layer 30 away from the substrate 10, and the insulating portion 63 is a partial structure of the second insulating layer 60 located in the first hole 31. The body portion 62 and the insulating portion 63 are connected and arranged as a whole, and the two are formed together in the same process. Among them, the body portion 62 can be arranged in affixed with the second pole 40, and the insulating portion 63 can be arranged in affixed with the first pole 20.

[0114] It can be seen from the accompanying drawings that the second hole 61 is formed by the main body 62 and the insulating part 63. Specifically, the second hole 61 includes a first sub-hole formed by the main body 62 and a second sub-hole formed by the insulating part 63. The first sub-hole is connected to the second sub-hole to form the second hole 61.

[0115] In the embodiment of the present application, the insulating portion 63 in the second insulating layer 60 is set deep into the first hole 31, so that the insulating portion 63 is used to isolate the active layer 50 and the side wall of the first hole 31, and the active layer 50 can have a larger contact area with the second insulating layer 60, which is beneficial to improve the performance characteristics of the thin film transistor.

[0116] It should be noted that the second insulating layer 60 and the first insulating layer 30 may be directly in contact with each other in the thickness direction X of the substrate 10, or other film structures may be sandwiched between the two. Optionally, the main body 62 is arranged in contact with the surface of the first insulating layer 30 facing away from the substrate 10, that is, there is no other film structure between the first insulating layer 30 and the second insulating layer 60.

[0117] In some embodiments, the first insulating layer 30 is disposed on the side of the second insulating layer 60 facing away from the substrate 10, and the orthographic projection of the first hole 31 on the substrate 10 covers and exceeds the orthographic projection of the second hole 61 on the substrate 10; wherein the second pole 40 covers the side wall of the first hole 31.

[0118] In addition to Figure 2 and Figure 3 As shown, the second insulating layer 60 may be at least partially located outside the first insulating layer 30 on a side facing away from the substrate 10, such as Figure 4 As shown, the first insulating layer 30 may also be completely located on the side of the first insulating layer 30 facing away from the substrate 10. In this way, during the preparation process, the first insulating layer 30 is formed after the second insulating layer 60, and the formed second insulating layer 60 may cover and fit a part of the structure in the first pole 20, and optionally, the second insulating layer 60 fits and covers a part of the structure of the first pole 20. The formed first insulating layer 30 may be in contact with the second pole 40, and optionally, the surface of the first insulating layer 30 facing away from the substrate 10 is fitted with the second pole 40.

[0119] Furthermore, in order to meet the need for spacing between the active layer 50 and the sidewall of the first hole 31, the embodiment of the present application also limits the size of the first hole 31 and the second hole 61, so that the orthographic projection of the first hole 31 on the substrate 10 covers and exceeds the orthographic projection of the second hole 61 on the substrate 10. On this basis, it can be seen from the accompanying drawings that the sidewall of the first hole 31 will be arranged in contact with the second pole 40, and the second pole 40 can achieve the spacing between the sidewall of the first hole 31 and the active layer 50, thereby reducing the adverse effects on the use of the thin film transistor caused by the contact between the active layer 50 and the sidewall of the first hole 31, which is conducive to improving the performance characteristics of the thin film transistor.

[0120] In some embodiments, Figure 3 As shown, the active layer 50 is disposed in contact with the side wall of the first hole 31 .

[0121] The active layer 50 is arranged in contact with the side wall of the first hole 31, that is, the active layer 50 can be in direct contact with the first insulating layer 30. On this basis, the active layer 50 can extend from the first hole 31 to the side of the first insulating layer 30 away from the substrate 10 by means of the side wall of the first hole 31, so as to meet the connection requirements of the active layer 50 relative to the first pole 20 and the second pole 40.

[0122] In some embodiments, the active layer 50 includes a first portion 51 disposed in contact with the first electrode 20, a second portion 52 disposed in contact with the second electrode 40, and a connecting portion 53 connecting the first portion 51 and the second portion 52. At least a portion of the connecting portion 53 is disposed in contact with the side wall of the first hole 31.

[0123] In the embodiment of the present application, the connecting portion 53 can be arranged to fit with the side wall of the first hole 31 , thereby extending in the thickness direction X, thereby meeting the connection requirements of the connecting portion 53 relative to the first part 51 and the second part 52 .

[0124] In some optional embodiments, a portion of the structure in the connecting portion 53 is disposed in contact with the sidewall of the second hole 61. In other words, the connecting portion 53 is in contact with both the first insulating layer 30 and the second insulating layer 60.

[0125] In the embodiment of the present application, the connecting portion 53 is in contact with the side wall of the first hole 31 and the side wall of the second hole 61 , so that the connecting portion 53 can be extended in the thickness direction X with the help of the first insulating layer 30 and the second insulating layer 60 to meet the structural requirements of the active layer 50 .

[0126] In some embodiments, the thickness of the second insulating layer 60 is greater than the thickness of the first insulating layer 30 .

[0127] In the embodiment of the present application, since the thickness of the second insulating layer 60 is greater than the thickness of the first insulating layer 30, the contact area between the connecting portion 53 and the second insulating layer 60 is greater than the contact area between the connecting portion 53 and the first insulating layer 30. This can reduce the adverse effect of the first insulating layer 30 on the particle movement process in the active layer 50, which is beneficial to improving the performance characteristics of the thin film transistor.

[0128] In some embodiments, the material density in the first insulating layer 30 is less than the material density in the second insulating layer 60; and / or, the first insulating layer 30 includes an organic material and the second insulating layer 60 includes an inorganic material.

[0129] Density refers to the ratio of the actual material part (excluding pores) in a material to the total volume. The material density in the first insulating layer 30 is positively correlated with its corresponding dielectric constant. Similarly, the material density in the second insulating layer 60 is also positively correlated with its corresponding dielectric constant. On this basis, by setting the material density in the first insulating layer 30 to be smaller than the material density in the second insulating layer 60, it helps to make the dielectric constant corresponding to the first insulating layer 30 smaller than the dielectric constant corresponding to the second insulating layer 60, and then the storage capacitance generated between the first electrode 20 and the second electrode 40 can be reduced with the help of the first insulating layer 30, and the corresponding performance characteristics of the thin film transistor can be improved with the help of the second insulating layer 60, thereby improving its use stability.

[0130] It should be noted that, for the solution in which the material density in the first insulating layer 30 and the second insulating layer 60 is different, the first insulating layer 30 and the second insulating layer 60 may include the same material, or the first insulating layer 30 and the second insulating layer 60 may also include different materials, which is not limited in the embodiment of the present application. Optionally, the first insulating layer 30 and the second insulating layer 60 include the same material. Further optionally, the materials of the first insulating layer 30 and the second insulating layer 60 both include silicon oxide.

[0131] In other solutions, considering that the film structure including inorganic materials often has a larger dielectric constant than the film structure including organic materials, the first insulating layer 30 can be configured to include organic materials, and the second insulating layer 60 can be configured to include inorganic materials, so that while the insulation performance of the first insulating layer 30 and the second insulating layer 60 is satisfied, the dielectric constant corresponding to the first insulating layer 30 is smaller than the dielectric constant corresponding to the second insulating layer 60, thereby reducing the storage capacitance generated between the first electrode 20 and the second electrode 40 with the help of the first insulating layer 30.

[0132] The present embodiment does not limit the material composition of the first insulating layer 30 and the second insulating layer 60. Optionally, the material of the first insulating layer 30 includes at least one of polyimide and silicon oxide, wherein polyimide is a high temperature resistant organic material that can withstand the preparation process of the active layer 50 and the second electrode 40 formed after the first insulating layer 30.

[0133] In some alternative embodiments, the material of the second insulating layer 60 includes at least one of silicon oxide and silicon nitride.

[0134] Second, see Figure 8 9 , an embodiment of the present application provides a method for preparing a display panel, including:

[0135] S100: forming a first electrode in sequence on one side of the substrate.

[0136] See also Figure 9a In step S100, the first electrode 20 may be a source or a drain of a thin film transistor.

[0137] S110: forming a first insulating layer and a second insulating layer on a side of the first electrode facing away from the substrate.

[0138] See also Figure 9b In step S110, the first insulating layer 30 includes a first hole 31, the second insulating layer 60 includes a second hole 61, and the dielectric constant in the second insulating layer 60 is greater than the dielectric constant in the first insulating layer 30. The preparation order and relative position relationship of the first insulating layer 30 and the second insulating layer 60 are not limited in the embodiment of the present application. Exemplarily, the first insulating layer 30 may be formed first, and then the second insulating layer 60 may be formed, so that the second insulating layer 60 is at least partially located on the side of the first insulating layer 30 away from the substrate 10. Alternatively, the second insulating layer 60 may be formed first, and then the first insulating layer 30 may be formed, so that the first insulating layer 30 is at least partially located on the side of the second insulating layer 60 away from the substrate 10.

[0139] S120: forming a second electrode on the first insulating layer and the second insulating layer at a side facing away from the substrate.

[0140] See also Fig.9c In step S120, the second electrode 40 is located on the side of the first insulating layer 30 and the second insulating layer 60 away from the substrate 10, and the first insulating layer 30 and the second insulating layer 60 can insulate and separate the first electrode 20 and the second electrode 40, so as to meet the operation requirements of the thin film transistor. At the same time, the orthographic projection of the first insulating layer 30 with a smaller dielectric constant on the substrate 10 overlaps with the orthographic projection of the first electrode 20 and the second electrode 40 on the substrate 10, so that the parasitic capacitance between the first electrode 20 and the second electrode 40 can be reduced with the help of the first insulating layer 30, thereby improving the reliability of the thin film transistor.

[0141] S130 : forming an active layer 50 on the side of the second electrode 40 facing away from the substrate 10 .

[0142] See also Figure 9d In step S130 , the structure in the active layer 50 located on the side of the second pole 40 away from the substrate 10 can be connected to the second pole 40 and extend into the first hole 31 and the second hole 61 to be connected to the first pole 20 .

[0143] In some embodiments, see Fig.10 As shown in FIG11 , step S110 includes:

[0144] S111: forming a first insulating layer and a first hole on one side of the substrate.

[0145] See also Fig.11a In step S111 , the first insulating layer 30 is formed before the second insulating layer 60 , and the first insulating layer 30 is provided with a first hole 31 , and a part of the structure in the first electrode 20 is exposed at the first hole 31 .

[0146] S112: forming a second insulating material layer on a side of the first insulating layer facing away from the substrate.

[0147] See also Fig.11b In step S112, the second insulating material layer 60' can be a full-surface structure and is used to subsequently form the second insulating layer 60, wherein the second insulating material layer 60' is filled in the first hole 31, that is, the second insulating material layer 60' is partially located on the side of the first insulating layer 30 away from the substrate 10, and partially located in the first hole 31 and arranged on the same layer as the first insulating layer 30.

[0148] S113: removing a portion of the structure in the first hole in the second insulating material layer.

[0149] See also Fig.11c In step S113, a portion of the structure of the second insulating material layer 60' located in the first hole 31 is removed, and a portion of the structure in the first hole 31 is retained to form a second insulating layer 60 and a second hole 61. The second insulating layer 60 includes a main body portion 62 located on the side of the first insulating layer 30 facing away from the substrate 10, and an insulating portion 63 located in the first hole 31 and bonded to the side wall of the first hole 31.

[0150] In the embodiment of the present application, the insulating portion 63 in the second insulating layer 60 is set deep into the first hole 31, so that the insulating portion 63 is used to isolate the active layer 50 and the side wall of the first hole 31, and the active layer 50 can have a larger contact area with the second insulating layer 60, which is beneficial to improve the performance characteristics of the thin film transistor.

[0151] Third, see Figure 7 An embodiment of the present application provides a display device, which includes a display panel as in any of the aforementioned embodiments, or a display device includes a display panel prepared by the preparation method of any of the aforementioned embodiments.

[0152] It should be noted that the display device provided in the embodiment of the present application has the beneficial effects of the display panel and the preparation method thereof in any of the aforementioned embodiments. Please refer to the aforementioned description of the beneficial effects of the display panel and the preparation method thereof for details, and the embodiment of the present application will not be repeated.

[0153] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted for facilitating the understanding of this application and are not intended to limit the present invention. Any technician in the technical field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be subject to the scope defined in the attached claims.

[0154] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: include: substrate; A first electrode is arranged on one side of the substrate; A first insulating layer, at least partially disposed on a side of the first electrode away from the substrate and comprising a first hole; A second insulating layer, at least partially disposed on a side of the first electrode away from the substrate and comprising a second hole, wherein the second hole is connected to the first hole; A second electrode is arranged on a side of the first insulating layer and the second insulating layer away from the substrate; An active layer, arranged on a side of the second pole away from the substrate, extending into the first hole and the second hole and connected to the first pole; The dielectric constant in the second insulating layer is greater than the dielectric constant in the first insulating layer, and the orthographic projection of the first insulating layer on the substrate overlaps with the orthographic projections of the first pole and the second pole on the substrate respectively.

2. The display panel according to claim 1, characterized in that: The active layer is disposed in contact with the side wall of the second hole; Preferably, the active layer includes a first portion disposed in contact with the first pole, a second portion disposed in contact with the second pole, and a connecting portion connecting the first portion and the second portion; Wherein, at least a portion of the connecting portion is disposed in contact with a side wall of the second hole; Preferably, the display panel further comprises a control electrode located on a side of the active layer away from the substrate, and a third insulating layer located between the control electrode and the active layer; In the radial direction of the first hole, the projection of the control electrode and the projection of the connecting portion are arranged to overlap; Preferably, a contact area between the active layer and the side wall of the second hole is larger than a contact area between the active layer and the side wall of the first hole.

3. The display panel according to claim 2, characterized in that: The active layer is spaced apart from the sidewall of the first hole; Preferably, the display panel comprises an insulating portion disposed in the first hole, the dielectric constant of the insulating portion is greater than the dielectric constant of the first insulating layer, and the insulating portion is located between the active layer and the side wall of the first hole; Preferably, the insulating portion and the second insulating layer comprise the same material; Preferably, the second insulating layer includes the insulating portion; Preferably, the second insulating layer is completely located in the first hole and is disposed in contact with the side wall of the first hole.

4. The display panel according to claim 3, characterized in that: The second insulating layer is at least partially located on a side of the first insulating layer facing away from the substrate; Preferably, the orthographic projection of the first hole on the substrate covers and exceeds the orthographic projection of the second hole on the substrate; Preferably, the second insulating layer comprises a main body portion located on a side of the first insulating layer facing away from the substrate, and an insulating portion located in the first hole; The active layer is attached to the main body and the wall surface of the insulating portion facing the second hole; Preferably, the main body is arranged in contact with a surface of the first insulating layer facing away from the substrate.

5. The display panel according to claim 3, characterized in that: The first insulating layer is arranged on a side of the second insulating layer away from the substrate, and the orthographic projection of the first hole on the substrate covers and exceeds the orthographic projection of the second hole on the substrate; Wherein, the second electrode is arranged to cover the side wall of the first hole; Preferably, a surface of the first insulating layer facing away from the substrate is arranged in contact with the second electrode; Preferably, the second insulating layer adheres to and covers a portion of the structure of the first electrode.

6. The display panel according to claim 1, characterized in that: The active layer is disposed in contact with the side wall of the first hole; Preferably, the active layer includes a first portion disposed in contact with the first pole, a second portion disposed in contact with the second pole, and a connecting portion connecting the first portion and the second portion; Wherein, at least a portion of the connecting portion is disposed in contact with a side wall of the first hole; Preferably, a part of the structure in the connecting portion is arranged to fit the side wall of the second hole; Preferably, the orthographic projections of the first hole and the second hole on the substrate coincide with each other; Preferably, the thickness of the second insulating layer is greater than the thickness of the first insulating layer.

7. The display panel according to any one of claims 1 to 6, characterized in that: The material density in the first insulating layer is less than the material density in the second insulating layer; and / or the first insulating layer comprises an organic material and the second insulating layer comprises an inorganic material; Preferably, the first insulating layer and the second insulating layer comprise the same material; Preferably, the material of the first insulating layer includes at least one of silicon oxide and polyimide; Preferably, a material of the second insulating layer includes at least one of silicon oxide and silicon nitride.

8. A method for preparing a display panel, characterized in that: include: forming a first electrode on one side of the substrate; Forming a first insulating layer and a second insulating layer on a side of the first electrode away from the substrate, the first insulating layer comprising a first hole, the second insulating layer comprising a second hole, and the dielectric constant in the second insulating layer being greater than the dielectric constant in the first insulating layer; A second pole is formed on the first insulating layer and the second insulating layer at a side away from the substrate, wherein the orthographic projection of the first insulating layer on the substrate overlaps with the orthographic projection of the first pole and the second pole on the substrate respectively; An active layer is formed on a side of the second pole facing away from the substrate. The active layer extends into the first hole and the second hole and is connected to the first pole.

9. The preparation method according to claim 8, characterized in that: The step of forming a first insulating layer and a second insulating layer on a side of the first electrode facing away from the substrate comprises: forming the first insulating layer and the first hole on one side of the substrate; forming a second insulating material layer on a side of the first insulating layer away from the substrate, wherein the second insulating material layer fills the first hole; The partial structure of the second insulating material layer located in the first hole is removed to form a second insulating layer and a second hole, wherein the second insulating layer includes a main body located on the side of the first insulating layer away from the substrate, and an insulating portion located in the first hole and bonded to the side wall of the first hole.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 7, or a display panel prepared by the preparation method according to any one of claims 8 to 9.

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