Display device and method for manufacturing display device

Abstract

A display device and a method for manufacturing the same are provided. The display device includes a substrate including a display area in which an emission area is disposed and a non-display area around the display area, a circuit layer on the substrate, and an element layer on the circuit layer, wherein the non-display area includes a dam area in which at least one dam portion surrounding the display area is arranged and spaced apart from the display area, and a bonding area between an edge of the substrate and the dam area, wherein the circuit layer includes a barrier layer on the substrate, a buffer layer on the barrier layer, and two or more inorganic insulating layers on the buffer layer and including an inorganic insulating material, the display device further includes a groove in a portion of the bonding region spaced apart from the dam region and an edge of the substrate, and penetrates the barrier layer and the buffer layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0146784 filed in the Korean Intellectual Property Office on October 30, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to a display device and a method for manufacturing the display device. Background Art

[0004] As the information-oriented society develops, more and more demands may be placed on display devices that display images in various ways. For example, display devices are employed in various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs.

[0005] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element (such as an inorganic semiconductor), and a micro light-emitting display device including a micro light-emitting element.

[0006] An organic light-emitting display device may generally use a plurality of light-emitting elements to display images, each of which includes a light-emitting layer made of an organic light-emitting material. As described above, an organic light-emitting display device uses self-luminous elements to realize image display, and therefore may have relatively superior performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle compared to other display devices.

[0007] One surface of the display device may include a display area where an image is displayed and a non-display area as a periphery of the display area. An emission area emitting light having corresponding brightness and color may be arranged in the display area.

[0008] That is, the display device may include: a substrate including a display area and a non-display area, a circuit layer including a plurality of pixel drivers located on the substrate and corresponding to a plurality of emission areas, respectively, an element layer including a plurality of light-emitting elements located on the circuit layer and corresponding to the plurality of emission areas, respectively, and an encapsulation layer located on the element layer.

[0009] The encapsulation layer may include a first encapsulation layer of an inorganic insulating material bonded to the circuit layer in the non-display area. The penetration of oxygen or moisture or other contaminants may be blocked by such an encapsulation layer, and rapid degradation of organic light emitting materials and the like of the element layer may be prevented or relatively reduced.

[0010] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0011] According to some embodiments, the encapsulation layer may include a first encapsulation layer covering the element layer, a second encapsulation layer including an organic insulating material, and a third encapsulation layer covering the second encapsulation layer. According to some embodiments, each of the first and third encapsulation layers may include an inorganic insulating material.

[0012] According to some embodiments, the non-display area of ​​the substrate may include a dam area at which at least one dam surrounding the display area is arranged, and a junction area between the dam area and an edge of the substrate.

[0013] According to some embodiments, the sequentially stacked inorganic insulating materials may be located in the bonding region. That is, a bonding structure between the inorganic insulating materials may be provided in the bonding region. Therefore, the generation of an oxygen or moisture permeation path from the edge of the substrate toward the display region may be relatively reduced or delayed.

[0014] To this end, the second encapsulation layer may be limitedly positioned in a region surrounded by the at least one dam.

[0015] However, in the process of forming the second encapsulation layer, if an organic insulating material greater than that filling a region surrounded by at least one dam is dropped, the organic insulating material may overflow to a bonding region around the at least one dam.

[0016] In addition, as the width of the non-display area is reduced so as to reduce the ratio of the non-display area in the display surface of the display device, the width of the bonding area may also be reduced. In this case, the organic insulating material overflowing to the bonding area may extend to the edge of the substrate.

[0017] Therefore, a lifting defect of the inorganic insulating material stacked in the bonding region may easily occur. In addition, an oxygen or moisture permeation path from the edge of the substrate toward the display region may be generated through the gap between the inorganic insulating materials.

[0018] In view of the above, aspects of the present disclosure include a display device capable of preventing or reducing a warping defect caused by an organic insulating material overflowing to a bonding region and a method of manufacturing the display device.

[0019] According to some embodiments of the present disclosure, a display device includes: a substrate including a display area in which a plurality of emission areas are arranged and a non-display area around the display area, a circuit layer located on the substrate, and a component layer located on the circuit layer. According to some embodiments, the non-display area includes a dam area in which at least one dam portion surrounding the display area is arranged and spaced apart from the display area, and a bonding area between an edge of the substrate and the dam area. According to some embodiments, the circuit layer includes a barrier layer located on the substrate, a buffer layer located on the barrier layer, and two or more inorganic insulating layers located on the buffer layer and including an inorganic insulating material. According to some embodiments, the display device further includes a groove located in a portion of the bonding area, spaced apart from the dam area and the edge of the substrate, and penetrating the barrier layer and the buffer layer.

[0020] According to some embodiments, the two or more inorganic insulating layers extend to a first boundary region in contact with the dam region in the bonding region. According to some embodiments, the first crack dam is provided by side surfaces of the two or more inorganic insulating layers. According to some embodiments, the first crack dam is spaced apart from the groove.

[0021] According to some embodiments, the display device further includes an encapsulation layer located on the element layer and a touch sensor layer located on the encapsulation layer. According to some embodiments, the encapsulation layer includes a first encapsulation layer located on the element layer and including an inorganic insulating material; a second encapsulation layer located on the first encapsulation layer in the display area and including an organic insulating material; and a third encapsulation layer located on the first encapsulation layer, covering the second encapsulation layer and including an inorganic insulating material. According to some embodiments, the touch sensor layer includes a touch buffer layer located on the third encapsulation layer and including an inorganic insulating material, and a touch interlayer insulating layer located on the touch buffer layer and including an inorganic insulating material. According to some embodiments, the first encapsulation layer extends to the edge of the substrate and covers at least one dam and a groove. According to some embodiments, the second encapsulation layer is located in an area surrounded by at least one dam. According to some embodiments, the touch interlayer insulating layer extends to a third boundary area, which is a remaining area in the bonding area except for the second boundary area in contact with the edge of the substrate. According to some embodiments, a second crack dam including a side surface of the touch interlayer insulating layer is provided.

[0022] According to some embodiments, the second crack dam is located between an edge of the substrate and the groove. According to some embodiments, the touch interlayer insulating layer overlaps the groove.

[0023] According to some embodiments, the second crack dam is located between the groove and the first crack dam.

[0024] According to some embodiments, at least a portion of the touch buffer layer or at least a portion of the third encapsulation layer extends to the third boundary region. According to some embodiments, the second crack dam also includes a side surface of the touch buffer layer or a side surface of the third encapsulation layer.

[0025] According to some embodiments, some of the organic insulating material of the second encapsulation layer overflowing to the bonding region extends to a portion of the bonding region between the dam region and the groove and is accommodated on a portion of the first encapsulation layer overlapping the groove.

[0026] According to some embodiments, the substrate includes: a main region including a display region and a non-display region, and a sub-region protruding from one side of the main region. According to some embodiments, the groove faces other sides of the edge of the main region except for one side connected to the sub-region.

[0027] According to some embodiments, the two or more inorganic insulating layers include a first gate insulating layer covering the first semiconductor layer on the buffer layer, a second gate insulating layer covering the first gate conductive layer on the first gate insulating layer, a first interlayer insulating layer covering the second gate conductive layer on the second gate insulating layer, a third gate insulating layer covering the second semiconductor layer on the first interlayer insulating layer, and a second interlayer insulating layer covering the third gate conductive layer on the third gate insulating layer.

[0028] According to some embodiments, the circuit layer further includes one or more planarization layers located on the second interlayer insulating layer and comprising an organic insulating material. According to some embodiments, the element layer includes a plurality of anode electrodes respectively located in a plurality of emission regions; a pixel defining layer located in a non-emission region between the plurality of emission regions and covering an edge of each of the plurality of anode electrodes; a spacing layer located on a portion of the pixel defining layer; a plurality of light-emitting layers respectively located on the plurality of anode electrodes; and a cathode electrode located on the pixel defining layer, the spacing layer, and the plurality of light-emitting layers. According to some embodiments, each of the at least one dam portion includes two or more dam layers stacked sequentially. According to some embodiments, each of the two or more dam layers is the same layer as one of the one or more planarization layers, the pixel defining layer, and the spacing layer.

[0029] According to some embodiments of the present disclosure, a method for manufacturing a display device includes: providing a substrate including a display area in which a plurality of emission areas are arranged and a non-display area around the display area; and forming a circuit layer on the substrate. According to some embodiments, the non-display area includes a dam area spaced apart from the display area and surrounding the display area, and a bonding area between an edge of the substrate and the dam area. According to some embodiments, forming the circuit layer includes forming a barrier layer by stacking an inorganic insulating material on the substrate, forming a buffer layer by stacking an inorganic insulating material on the barrier layer, and forming a groove by partially removing the barrier layer and the buffer layer. According to some embodiments, the groove is located in a portion of the bonding area and is spaced apart from the dam area and the edge of the substrate.

[0030] According to some embodiments, the bonding region further includes a first boundary region in contact with the dam region and a second boundary region in contact with an edge of the substrate. According to some embodiments, forming the circuit layer further includes, before forming the groove, forming a first semiconductor layer on the buffer layer; forming a first gate insulating layer covering the first semiconductor layer by stacking an inorganic insulating material on the buffer layer; forming a first gate conductive layer on the first gate insulating layer; forming a second gate insulating layer covering the first gate conductive layer by stacking an inorganic insulating material on the first gate insulating layer; forming a second gate conductive layer on the second gate insulating layer; forming a first interlayer insulating layer covering the second gate conductive layer by stacking an inorganic insulating material on the second gate insulating layer; forming a second interlayer insulating layer on the first interlayer insulating layer; forming a second gate conductive layer on the second gate insulating layer; forming a second gate conductive layer on the second gate insulating layer; forming a second gate conductive layer on the second gate insulating layer; forming a second gate conductive layer on the second gate insulating layer; forming a second gate conductive layer on the second gate insulating layer; forming a second gate conductive layer on the second gate insulating layer; forming a second gate conductive layer on the first interlayer insulating layer; forming a second gate conductive layer on the second gate conductive layer; forming a second gate conductive layer on the second gate conductive layer; forming a second gate conductive layer on the second gate conductive layer; forming a second gate conductive layer on the second gate conductive layer; forming a second gate conductive layer on the second gate conductive layer; forming a second gate conductive layer on the first interlayer insulating ... first interlayer insulating layer; forming a second gate conductive layer on the second gate conductive layer; forming a second gate conductive layer on the second gate conductive layer; forming a second gate conductive layer on the second gate conductive layer; forming a second A semiconductor layer; a third gate insulating layer covering the second semiconductor layer is formed by stacking an inorganic insulating material on the first interlayer insulating layer; a third gate conductive layer is formed on the third gate insulating layer; a second interlayer insulating layer covering the third gate conductive layer is formed by stacking an inorganic insulating material on the third gate insulating layer; and a first crack dam including the side surfaces of the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer is formed by partially removing the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer. According to some embodiments, after forming the first crack dam, the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer extend to the first boundary region. According to some embodiments, the first crack dam is spaced apart from the groove.

[0031] According to some embodiments, the method further includes: after forming the circuit layer, forming an element layer on the circuit layer; forming an encapsulation layer on the element layer; and forming a touch sensor layer on the encapsulation layer. According to some embodiments, forming the encapsulation layer includes: forming a first encapsulation layer including an inorganic insulating material on the element layer; forming a second encapsulation layer including an organic insulating material on the first encapsulation layer; and forming a third encapsulation layer covering the second encapsulation layer and including an inorganic insulating material on the first encapsulation layer. According to some embodiments, forming the touch sensor layer includes: forming a touch buffer layer by stacking an inorganic insulating material on the third encapsulation layer; forming a first touch conductive layer on the touch buffer layer; forming a touch interlayer insulating layer covering the first touch conductive layer by stacking an inorganic insulating material on the touch buffer layer; forming a second crack dam including a side surface of the touch interlayer insulating layer by partially removing the touch interlayer insulating layer; forming a second touch conductive layer on the touch interlayer insulating layer; and forming a touch planarization layer covering the second touch conductive layer by stacking an organic insulating material on the touch interlayer insulating layer. According to some embodiments, after forming the second crack dam, the touch interlayer insulating layer extends to a third boundary region that is a remaining region except for the second boundary region in the bonding region.

[0032] According to some embodiments, the second crack dam is located between an edge of the substrate and the groove. The touch interlayer insulating layer overlaps the groove.

[0033] According to some embodiments, the second crack dam is located between the groove and the first crack dam.

[0034] According to some embodiments, when forming the second crack dam, the touch buffer layer or the third encapsulation layer is partially removed. According to some embodiments, at least a portion of the touch buffer layer or at least a portion of the third encapsulation layer extends to the third boundary region. According to some embodiments, the second crack dam also includes a side surface of the touch buffer layer or a side surface of the third encapsulation layer.

[0035] According to some embodiments, after forming the element layer, at least one dam portion surrounding the display area is located in the dam area. According to some embodiments, forming the second encapsulation layer includes a process of dripping a liquid organic insulating material on the first encapsulation layer, a process of extending the liquid organic insulating material into an area surrounded by the at least one dam portion, and a process of curing the liquid organic insulating material. According to some embodiments, in the process of extending the liquid organic insulating material, some of the liquid organic insulating material overflowing into the bonding area extends into a portion of the bonding area located between the dam area and the groove, and is accommodated on a portion of the first encapsulation layer overlapping the groove.

[0036] According to some embodiments, when providing a substrate, the substrate includes a main area including a display area and a non-display area, and a sub-area protruding from one side of the main area. According to some embodiments, when forming the groove, the groove faces the other side of the edge of the main area except the side connected to the sub-area.

[0037] According to some embodiments, when forming the first crack dam, a plurality of first contact holes are also formed. When forming the groove, a plurality of second contact holes are also formed. According to some embodiments, each of the plurality of first contact holes reaches one of the first semiconductor layer, the first gate conductive layer, and the second gate conductive layer. According to some embodiments, each of the plurality of second contact holes reaches one of the second semiconductor layer and the third gate conductive layer.

[0038] According to some embodiments, forming the circuit layer further comprises: forming a first source-drain conductive layer on the second interlayer insulating layer after forming the groove; forming a first planarization layer covering the first source-drain conductive layer by stacking an organic insulating material on the second interlayer insulating layer; forming a second source-drain conductive layer on the first planarization layer; and forming a second planarization layer covering the second source-drain conductive layer by stacking an organic insulating material on the first planarization layer. According to some embodiments, forming the element layer comprises forming a plurality of anode electrodes in a plurality of emission regions; forming a pixel defining layer covering edges of the plurality of anode electrodes in a non-emission region between the plurality of emission regions, and forming a spacer layer on a portion of the pixel defining layer; forming a plurality of light-emitting layers on the plurality of anode electrodes; and forming a cathode electrode on the pixel defining layer, the spacer layer, and the plurality of light-emitting layers. According to some embodiments, each of the at least one dam portion comprises two or more dam layers stacked sequentially. According to some embodiments, each of the two or more dam layers is the same layer as one of the first planarization layer, the second planarization layer, the pixel defining layer, and the spacer layer.

[0039] According to some embodiments, a display device includes a substrate, a circuit layer on the substrate, and a component layer on the circuit layer.

[0040] According to some embodiments, a substrate includes a display area in which a plurality of emission areas are arranged and a non-display area around the display area.

[0041] According to some embodiments, the non-display area includes a dam area spaced apart from the display area and in which at least one dam surrounding the display area is arranged, and a bonding area surrounding the dam area.

[0042] According to some embodiments, the circuit layer includes a barrier layer on a substrate, a buffer layer on the barrier layer, and two or more inorganic insulating layers on the buffer layer and including an inorganic insulating material.

[0043] According to some embodiments, the display device further includes a groove located in a portion of the bonding region, spaced apart from the dam region and an edge of the substrate, and penetrating the barrier layer and the buffer layer.

[0044] According to some embodiments, the display device may further include an encapsulation layer on the element layer and a touch sensor layer on the encapsulation layer.

[0045] According to some embodiments, the encapsulation layer may include a first encapsulation layer located on the element layer and including an inorganic insulating material, a second encapsulation layer located on the first encapsulation layer in the display area and including an organic insulating material, and a third encapsulation layer covering the second encapsulation layer and including an inorganic insulating material.

[0046] According to some embodiments, some of the organic insulating material of the second encapsulation layer overflowing into the bonding region may extend to a portion of the bonding region between the dam region and the groove and may be accommodated on a portion of the first encapsulation layer overlapping the groove.

[0047] That is, some of the organic insulating material overflowing to the bonding region is accommodated in the groove and thus may not extend to the edge of the substrate.

[0048] Therefore, a warping defect caused by overflow of the organic insulating material to the bonding region may be prevented or reduced.

[0049] However, features of the embodiments of the present disclosure are not limited to those described above, and various other features are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and other aspects and features of the present disclosure will become more apparent by describing in more detail various aspects of some embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0051] Figure 1 is a perspective view showing a display device according to some embodiments;

[0052] Figure 2 It is shown Figure 1 A plan view of a display device;

[0053] Figure 3 is along Figure 2 A cross-sectional view taken along line A-A';

[0054] Figure 4 is a diagram showing that according to some embodiments Figure 2 a layout diagram of part B;

[0055] Figure 5 It is shown Figure 4 An equivalent circuit diagram of a light-emitting pixel driver;

[0056] Figure 6 It is shown Figure 3 A plan view of a touch sensor layer;

[0057] Figure 7 It is shown Figure 6 an enlarged view of part C;

[0058] Figure 8 is along Figure 7 A cross-sectional view taken along the line D-D';

[0059] Fig. 9 is a diagram showing that according to some embodiments Figure 2 A plan view of a substrate;

[0060] Fig.10 , Fig.11 , Fig.12 and Fig.13 According to some embodiments, Fig. 9 A cross-sectional view taken along the line E-E';

[0061] Fig.14 and Fig.15 is a flowchart illustrating a method for manufacturing a display device according to some embodiments; and

[0062] Figures 16 to 28 is a diagram showing that according to some embodiments Fig.14 and Fig.15 Process diagram of the manufacturing method. DETAILED DESCRIPTION

[0063] Now, various aspects of some embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. However, the embodiments can be provided in different forms and should not be construed as limiting. Throughout the present disclosure, the same reference numerals indicate the same parts. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0064] In order to describe the embodiments of the present disclosure, some of parts not related to the description may be provided out of sequence.

[0065] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0066] In addition, the phrase "in a plan view" means when an object portion is viewed from above, and the phrase "in a cross-sectional view" means when a schematic cross-sectional view obtained by vertically cutting an object portion is viewed from the side. The term "overlap" or "overlapped" means that the first object may be above or below the second object, or on the side of the second object, and vice versa. In addition, the term "overlap" may include layers, stacks, facing or facing, extending above, covering or partially covering, or any other suitable terms that a person of ordinary skill in the art will appreciate and understand. The expression "non-overlapping" may include meanings such as "separated from..." or "set beside..." or "offset from..." and any other suitable equivalents that a person of ordinary skill in the art will appreciate and understand. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0067] For ease of description, spatially relative terms "below", "beneath", "lower", "above", "upper" or the like may be used herein to describe the relationship between one element or component and another element or component as shown in the figures. It should be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, in the case where the device shown in the drawings is turned over, a device positioned "below" or "below" another device may be placed "above" the other device. Accordingly, the illustrative term "below" may include both the lower position and the upper position. The device may also be oriented in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0068] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements interposed therebetween. It should also be understood that when the terms “comprises,” “comprising,” “has,” “have,” “having,” “includes,” and / or “including,” are used, they may specify the presence of stated features, integers, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, operations, elements, components, and / or any combination thereof.

[0069] It should be understood that although the terms "first", "second", "third" or the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or for the convenience of its description and explanation. For example, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element", and the "second element" and the "third element" may be referred to in a similar manner without departing from the spirit and scope of the present disclosure herein.

[0070] As used herein, the terms "about" or "approximately" are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0071] In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or separately and may be understood to be equivalent to "and / or". In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of..." is intended to include "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0072] Unless otherwise defined or implied, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined in this specification, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense.

[0073] Hereinafter, aspects of some embodiments will be described in more detail with reference to the accompanying drawings.

[0074] Figure 1 is a perspective view showing a display device according to some embodiments. Figure 2 It is shown Figure 1 A plan view of a display device. Figure 3 is along Figure 2 A cross-sectional view taken along line AA'. Figure 4 is a diagram showing that according to some embodiments Figure 2 Layout diagram of part B.

[0075] Reference Figure 1 The display device 100 is a device for displaying moving images or still images. The display device 100 can be used as a display screen of various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs).

[0076] The display device 100 may be a light-emitting display device, such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro light-emitting display using a micro or nano light-emitting diode (LED). Hereinafter, a case where the display device 100 is an organic light-emitting display device will be mainly described, but the present disclosure may be applied to a display device including an organic insulating material, an organic light-emitting material, and a metal material.

[0077] The display device 100 may be formed to be flat, but is not limited thereto according to the embodiments of the present disclosure. For example, the display device 100 may include a bent portion formed at the left and right ends and having a constant curvature or a variable curvature. In addition, the display device 100 may be formed to be flexible so that it can be bent, curved, folded, or curled without damaging the display device 100.

[0078] The display device 100 may include a substrate 110 , a display driving circuit 200 , and a circuit board 300 .

[0079] The substrate 110 may include a main area MA positioned on one surface (hereinafter, referred to as a display surface) at which an image is displayed, and a sub area SBA protruding from one side of the main area MA.

[0080] The main area MA may include a display area DA and a non-display area NDA, in which a plurality of emission areas EA emitting light having corresponding colors and brightness are arranged (see FIG. Figure 4 ) for displaying images, the non-display area NDA is arranged around the display area DA (eg, outside the periphery or coverage area of ​​the display area DA).

[0081] A portion of the sub-area SBA may be deformed to be curved, so that another portion of the sub-area SBA may face the rear surface of the substrate 110 and overlap with the main area MA.

[0082] Figure 11 shows a state in which the sub-area SBA is expanded to be positioned side by side with the main area MA. Figure 2 and Figure 3 A state in which a portion of the sub-area SBA is bent is shown.

[0083] Reference Figure 2 In a plan view, the display area DA may be formed in a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a curvature (e.g., a set or predetermined curvature), or may be a right angle. The planar shape of the display area DA is not limited to a rectangular shape, and may be formed in another polygonal shape, a circular shape, or an elliptical shape. In addition, a thickness direction of the display device 100 may be a direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2, i.e., a third direction DR3.

[0084] The display area DA may occupy most of the main area MA. The display area DA may be positioned at the center of the main area MA.

[0085] Reference Figure 3 , a display device 100 according to some embodiments may include a substrate 110 including a display area DA and a non-display area NDA, a circuit layer 120 positioned on the substrate 110 , and an element layer 130 positioned on the circuit layer 120 .

[0086] The display device 100 according to some embodiments may further include an encapsulation layer 140 positioned on the element layer 130 and a touch sensor layer 150 positioned on the encapsulation layer 140 .

[0087] The display device 100 according to some embodiments may further include a polarization layer 160 positioned on the touch sensor layer 150 and overlapping the element layer 130 .

[0088] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled.

[0089] Alternatively, the substrate 110 may be formed of an insulating material such as glass or the like.

[0090] The element layer 130 may include a plurality of light emitting elements LE respectively positioned in a plurality of emission areas EA (see Figure 5 ).

[0091] The circuit layer 120 may include a plurality of light emitting pixel drivers EPD (see FIG. 1 ) electrically connected to the plurality of light emitting elements LE of the element layer 130, respectively. Figure 4 ).

[0092] The encapsulation layer 140 may cover the element layer 130 and may extend into the non-display area NDA to contact the circuit layer 120. The encapsulation layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are alternately stacked.

[0093] The touch sensor layer 150 may be positioned in the main area MA on the encapsulation layer 140. The touch sensor layer 150 may include a touch electrode for sensing a touch of a person or an object.

[0094] The polarizing layer 160 blocks external light reflected from the touch sensor layer 150 , the encapsulation layer 140 , the element layer 130 , and the circuit layer 120 , and interfaces thereof, and this is to prevent or reduce degradation of visibility of an image due to external light reflection.

[0095] The display device 100 may further include a cover window positioned on the polarizing layer 160. The cover window may be attached to the polarizing layer 160 by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR) film. The cover window may be made of an inorganic material such as glass or an organic material such as a plastic or polymer material. Due to the cover window, the touch sensor layer 150, the encapsulation layer 140, the element layer 130, and the circuit layer 120 may be protected from electrical and physical impacts on the display surface.

[0096] The display driving circuit 200 may be provided as an integrated circuit (IC) chip.

[0097] The display driving circuit 200 may be mounted on the sub-area SBA of the substrate 110 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto.

[0098] For example, the display driving circuit 200 may be attached to the circuit board 300 by a chip on film (COF) method.

[0099] The display driving circuit 200 can transmit the data signal Vdata (see Figure 5 ) is supplied to the circuit layer 120 (see Figure 3 ) data line DL (see Figure 5 ).

[0100] The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0101] The circuit board 300 may be bonded to the signal pad SPD positioned at the edge of the sub-area SBA of the substrate 110 using a low resistance and high reliability material such as anisotropic conductive film or SAP (see Figure 6 and Fig. 9 ), and can be electrically connected to the circuit layer 120.

[0102] The display device 100 may further include a touch driving circuit 400 for driving the touch sensor layer 150 .

[0103] The touch driving circuit 400 may be prepared as an integrated circuit (IC) chip and mounted on the circuit board 300 .

[0104] The touch driving circuit 400 may apply a touch driving signal to a plurality of driving electrodes provided on the touch sensor layer 150 , receive a touch sensing signal of each of a plurality of touch nodes through a plurality of sensing electrodes, and sense a charge change amount of mutual capacitance based on the touch sensing signal.

[0105] That is, the touch driving circuit 400 may determine whether a user's touch has been made, whether a user is nearby, etc., according to the touch sensing signal of each of the plurality of touch nodes. The user's touch refers to direct contact of an object (such as a pen or a user's finger) with the front surface of the display device 100. The user's proximity means that an object (such as a pen or a user's finger) is positioned away from the front surface of the display device 100, such as hovering.

[0106] Reference Figure 4 , the display area DA of the display device 100 may include a plurality of emission areas EA. In addition, the display area DA may further include a non-emission area positioned in a gap between the plurality of emission areas EA.

[0107] A plurality of light emitting pixel drivers EPD electrically connected to the plurality of light emitting elements LE of the plurality of emission areas EA, respectively, may be arranged side by side in the main area MA in the first direction DR1 and the second direction DR2. The plurality of light emitting pixel drivers EPD may be electrically connected to the plurality of light emitting elements LE of the element layer 130, respectively, located in the plurality of emission areas EA (see Figure 5 ).

[0108] The emission area EA may have a rhombus shape or a rectangular shape in a plan view. However, this is only an example, and the planar shape of the emission area EA is not limited to Figure 4 That is, in a plan view, the emission area EA may have a polygonal shape such as a square, a pentagon, a hexagon, etc., or may have a circular or elliptical shape including edges of curved lines.

[0109] The emission area EA may include a first emission area EA1 that emits light of a first color in a wavelength band (e.g., a set or predetermined wavelength band), a second emission area EA2 that emits light of a second color in a wavelength band lower than the wavelength band of the first color, and a third emission area EA3 that emits light of a third color in a wavelength band lower than the wavelength band of the second color.

[0110] For example, the first color may be red having a wavelength band of approximately 600 nanometers (nm) to 750 nm. The second color may be green having a wavelength band of 480 nm to 560 nm (or approximately 480 nm to 560 nm). The third color may be blue having a wavelength band of 370 nm to 460 nm (or approximately 370 nm to 460 nm).

[0111] The first emission regions EA1 and the third emission regions EA3 may be alternately arranged in at least one of the first direction DR1 and the second direction DR2.

[0112] The second emission areas EA2 may be arranged side by side in at least one of the first direction DR1 and the second direction DR2.

[0113] In addition, the second emission region EA2 may be adjacent to the first emission region EA1 and the third emission region EA3 in oblique directions DR4 and DR5 intersecting the first direction DR1 and the second direction DR2 .

[0114] A plurality of pixels PX displaying their own brightness and color may be provided by the first emission area EA1 , the second emission area EA2 , and the third emission area EA3 adjacent to each other among the emission areas EA.

[0115] In other words, the pixel PX may be a basic unit for displaying various colors including white at brightness (eg, set or predetermined brightness).

[0116] Each of the plurality of pixels PX may include at least one first emission region EA1, at least one second emission region EA2, and at least one third emission region EA3 adjacent to each other. Therefore, each of the plurality of pixels PX may display various colors by mixing light emitted from the first emission region EA1, the second emission region EA2, and the third emission region EA3 adjacent to each other.

[0117] Figure 5 It is shown Figure 4 Equivalent circuit diagram of the light-emitting pixel driver.

[0118] Reference Figure 5 , one of the plurality of light emitting elements LE of the element layer 130 may be electrically connected between one of the plurality of light emitting pixel drivers EPD of the circuit layer 120 and the second power source ELVSS.

[0119] That is, the anode electrode of the light emitting element LE is electrically connected to the light emitting pixel driver EPD, and the cathode electrode of the light emitting element LE may be applied with the second power ELVSS lower than the first power ELVDD.

[0120] The capacitor Cel connected in parallel with the light emitting element LE refers to a parasitic capacitance between the anode electrode and the cathode electrode.

[0121] The circuit layer 120 may further include a first power line VDL transmitting a first power source ELVDD, a gate initialization voltage line VGIL transmitting a gate initialization voltage VGINT, and an anode initialization voltage line VAIL transmitting an anode initialization voltage VAINT.

[0122] The circuit layer 120 may also include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0123] A light-emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 configured to generate a driving current for driving the light-emitting element LE, two or more transistors (e.g., second to seventh transistors T2 to T7) electrically connected to the first transistor T1, and at least one capacitor (e.g., a first pixel capacitor PC1).

[0124] The first transistor T1 and the light emitting element LE are connected in series between the first power source ELVDD and the second power source ELVSS.

[0125] The first transistor T1 may be electrically connected between a first node N1 and a second node N2. The first node N1 is electrically connected to a first electrode (eg, source electrode) of the first transistor T1. The second node N2 is electrically connected to a second electrode (eg, drain electrode) of the first transistor T1.

[0126] In other words, the first electrode (eg, source electrode) of the first transistor T1 may be electrically connected to the first power line VDL through the fifth transistor T5. In addition, the second electrode (eg, drain electrode) of the first transistor T1 may be electrically connected to the anode electrode of the light emitting element LE through the sixth transistor T6.

[0127] The first pixel capacitor PC1 may be electrically connected between the first power line VDL and a third node N3. The third node N3 is electrically connected to the gate electrode of the first transistor T1.

[0128] That is, the gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the first pixel capacitor PC1 .

[0129] Therefore, the potential of the gate electrode of the first transistor T1 may be maintained at the voltage charged in the first power line VDL.

[0130] The second transistor T2 may be electrically connected between the data line DL and the first node N1.

[0131] In other words, the second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 may be turned on by the scan write signal GW of the scan write line GWL. Figure 5 As shown in , the second pixel capacitor PC2 may be electrically connected between the gate electrode of the second transistor T2 and the third node N3.

[0132] That is, the first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0133] The fifth transistor T5 may be electrically connected between the first node N1 and the first power line VDL.

[0134] The sixth transistor T6 may be electrically connected between the second node N2 and a fourth node N4. The fourth node N4 is electrically connected to the anode electrode of the light emitting element LE.

[0135] That is, the fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0136] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode electrode of the light emitting element LE.

[0137] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the emission control line ECL.

[0138] When the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2 , a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 may be a difference voltage between the first power source ELVDD and the data signal Vdata.

[0139] In this case, when a voltage difference between a gate electrode of the first transistor T1 and a first electrode of the first transistor T1, i.e., a gate-source voltage difference becomes equal to or greater than a threshold voltage, the first transistor T1 may be turned on, thereby generating a drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0140] Then, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series with the light emitting element LE between the first power line VDL and the second power line VSSPL. Therefore, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as a driving current of the light emitting element LE.

[0141] Therefore, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0142] The third transistor T3 may be electrically connected between the second node N2 and the third node N3. That is, the third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 may be turned on by the gate control signal GC of the gate control line GCL.

[0143] By turning on the third transistor T3 , a voltage difference between the second node N2 and the third node N3 may be initialized.

[0144] The fourth transistor T4 may be electrically connected between the gate initialization voltage line VGIL and the third node N3. That is, the fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VGIL. The fourth transistor T4 may be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0145] The potential of the third node N3 may be initialized by the turned-on fourth transistor T4.

[0146] The third transistor T3 and the fourth transistor T4 may be provided as N-type MOSFETs.

[0147] The seventh transistor T7 may be electrically connected between the fourth node N4 and the anode initialization voltage line VAIL. That is, the seventh transistor T7 may be electrically connected between the anode electrode of the light emitting element LE and the anode initialization voltage line VAIL. The seventh transistor T7 may be turned on by the bias control signal GB of the bias control line GBL.

[0148] The potential of the fourth node N4 may be initialized by the turned-on seventh transistor T7.

[0149] According to some embodiments, among the first to seventh transistors T1 to T7, the third transistor T3 and the fourth transistor T4 may be provided as N-type MOSFETs, and other transistors except the third transistor T3 and the fourth transistor T4 (i.e., the first transistor T1, the second transistor T2, and the fifth to seventh transistors T5 to T7) may be provided as P-type MOSFETs.

[0150] Therefore, according to some embodiments, the circuit layer 120 may include a first semiconductor layer for providing a P-type MOSFET and a second semiconductor layer for providing an N-type MOSFET.

[0151] Figure 6 It is shown Figure 3 A plan view of the touch sensor layers. Figure 7 It is shown Figure 6An enlarged view of portion C of FIG. Figure 8 is along Figure 7 A cross-sectional view taken along line D-D'.

[0152] Figure 6 The touch sensor layer 150 of the capacitance method is shown. In this case, the touch driving circuit 400 can sense the touch based on whether the capacitance fluctuates. However, for ease of description, Figure 6 are examples only, and the touch sensor layer 150 according to some embodiments is not limited to Figure 6 As shown in .

[0153] To simplify the description, Figure 6 Only some of the components of touch sensor layer 150 are shown.

[0154] Reference Figure 6 , the touch sensor layer 150 may be positioned in the main area MA. The touch sensor layer 150 may include a touch sensing area TSA for sensing a user's touch and a touch peripheral area TPA around the touch sensing area TSA.

[0155] The touch sensing area TSA has a width wider than the display area DA and may be similar to the display area DA. Therefore, the touch peripheral area TPA which is the periphery of the touch sensing area TSA may be similar to the non-display area NDA which is the periphery of the display area DA.

[0156] For example, the touch sensing area TSA may overlap the display area DA and an edge of the non-display area NDA that contacts the display area DA. In this case, the touch peripheral area TPA may overlap the remaining portion of the non-display area NDA that does not correspond to the touch sensing area TSA.

[0157] The touch sensor layer 150 may include sensor electrodes SE and dummy electrodes DE which are arranged in a matrix in the touch sensing area TSA and generate mutual capacitance, and sensor lines TL1 , TL2 , and RL positioned in the touch peripheral area TPA.

[0158] The sensor electrodes SE may include driving electrodes TE (touch driving electrodes) to which driving signals are applied, and sensing electrodes RE (receiving electrodes) for sensing a voltage charged with mutual capacitance with the driving electrodes TE.

[0159] The sensor lines TL1 , TL2 , and RL may include a first driving line TL1 , a second driving line TL2 , and a sensing line RL.

[0160] Each of the first and second driving lines TL1 and TL2 may be electrically connected to two or more driving electrodes TE extending in the second direction DR2 among the driving electrodes TE.

[0161] The first driving line TL1 may extend from one side of the touch sensing area TSA facing the sub-area SBA to the sub-area SBA in the second direction DR2 .

[0162] The second driving line TL2 may extend from the other side of the touch sensing area TSA away from the sub-area SBA to the sub-area SBA in the second direction DR2. A portion of the second driving line TL2 may extend parallel to one side of the touch sensing area TSA in the first direction DR1.

[0163] The sensing line RL may be electrically connected to two or more sensing electrodes RE extending in the first direction DR1 among the sensing electrodes RE.

[0164] The sensing line RL may extend from the other side of the touch sensing area TSA to the sub-area SBA in the first direction DR1.

[0165] The sensing electrodes RE may be arranged in parallel in the first direction DR1. The sensing electrodes RE adjacent in the first direction DR1 may be electrically connected to each other through the protrusions in the first direction DR1.

[0166] The driving electrodes TE may be arranged in parallel in the second direction DR2. The driving electrodes TE adjacent to each other in the second direction DR2 may be connected to each other through the bridge electrode BE in the second direction DR2 (see FIG. Figure 7 ) are electrically connected to each other.

[0167] Each of the driving electrode TE and the sensing electrode RE may have a shape surrounding the dummy electrode DE positioned at the center thereof.

[0168] Each of the plurality of dummy electrodes DE may be spaced apart from the driving electrode TE or the sensing electrode RE surrounding it. The dummy electrode DE may be maintained in a floating state.

[0169] although Figure 6 It is shown that each of the driving electrode TE, the sensing electrode RE, and the dummy electrode DE has a rhombus planar shape, but the embodiments of the present disclosure are not limited to Figure 6 For example, the planar shapes of the driving electrode TE, the sensing electrode RE, and the dummy electrode DE may be a quadrilateral shape other than a rhombus shape, a polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape.

[0170] The display device 100 according to some embodiments may include a signal pad SPD positioned in the second sub-region SB2 and connected to the circuit board 300 .

[0171] The signal pads SPD may include display signal pads DPD that transmit and receive signals to drive the circuit layer 120 , and touch signal pads (eg, first and second touch pads TPD1 and TPD2 ) that transmit and receive signals to drive the touch sensor layer 150 .

[0172] For example, the second sub-region SB2 may include a display pad area DPDA adjacent to the display driving circuit 200 , and first and second touch pad areas TPDA1 and TPDA2 positioned on both sides of the display pad area DPDA.

[0173] For example, a display signal pad DPD for transmitting and receiving a signal to be transmitted to the circuit layer 120 or the display driving circuit 200 may be positioned in the display pad area DPDA.

[0174] A plurality of first touch pads TPD1 electrically connected to the first driving line TL1 and the second driving line TL2 , respectively, may be positioned in the first touch pad area TPDA1 .

[0175] A plurality of second touch pads TPD2 electrically connected to the sensing lines RL, respectively, may be positioned in the second touch pad area TPDA2.

[0176] Reference Figure 7 , the driving electrodes TE and the sensing electrodes RE may be spaced apart from each other.

[0177] The bridge electrode BE may electrically connect the driving electrodes TE adjacent to each other in the second direction DR2.

[0178] although Figure 7 The bridging electrode BE having a shape including at least one bent portion is shown, but the shape of the bridging electrode BE according to some embodiments is not limited to Figure 7 As shown in .

[0179] The driving electrodes TE adjacent in the second direction DR2 may be electrically connected to each other through two or more bridge electrodes BE In this way, the reliability of the electrical connection between the driving electrodes TE may be improved.

[0180] although Figure 7 It is shown that two bridging electrodes BE parallel to each other are positioned between driving electrodes TE adjacent to each other in the second direction DR2, but the embodiments of the present disclosure are not limited to Figure 7 As shown in .

[0181] The bridge electrode BE may be electrically connected to the driving electrode TE through the touch contact hole TCNT.

[0182] The touch contact hole TCNT can be formed by touching the interlayer insulating layer 152 (see Figure 8) extends to the bridging electrode BE.

[0183] The driving electrode TE, the sensing electrode RE, and the bridging electrode BE may have a grid or mesh structure in a plan view. The dummy electrode DE may also have a grid or mesh structure in a plan view. In this way, since the overlapping width of the driving electrode TE, the sensing electrode RE, the dummy electrode DE, and the bridging electrode BE in the emission area EA can be reduced, the reduction in light emission efficiency caused by the driving electrode TE, the sensing electrode RE, the dummy electrode DE, and the bridging electrode BE can be reduced.

[0184] Reference Figure 8 , a display device 100 according to some embodiments may include a substrate 110 , a circuit layer 120 on the substrate 110 , and an element layer 130 on the circuit layer 120 .

[0185] The display device 100 according to some embodiments may further include an encapsulation layer 140 on the element layer 130 and a touch sensor layer 150 on the encapsulation layer 140 .

[0186] The substrate 110 may be made of a material having flexible properties that enable bending, folding, curling, or the like.

[0187] The substrate 110 may include a display area DA at which the emission area EA is arranged, and a non-display area NDA arranged around the display area DA (eg, outside the periphery or footprint of the display area DA).

[0188] The substrate 110 may include a main area MA including a display area DA and a non-display area NDA, and a sub area SBA protruding from one side of the main area MA.

[0189] The circuit layer 120 may include a plurality of light emitting pixel drivers EPD respectively corresponding to the plurality of emission areas EA.

[0190] Each of the plurality of light emitting pixel drivers EPD may include first to seventh transistors T1 to T7 (see Figure 5 ) and at least one capacitor (eg, a first pixel capacitor PC1) (see Figure 5 ).

[0191] Figure 8 The first transistor T1 to the seventh transistor T7 of the light emitting pixel driver EPD are shown (see Figure 5 ) includes a first transistor T1, a second transistor T2, a fourth transistor T4 and a sixth transistor T6.

[0192] According to some embodiments, the circuit layer 120 may include a barrier layer 121 positioned on the substrate 110 , a buffer layer 122 positioned on the barrier layer 121 , and two or more inorganic insulating layers 123 to 127 positioned on the buffer layer 122 and including an inorganic insulating material.

[0193] The buffer layer 122 may cover the first light blocking layer LB1 on the barrier layer 121 .

[0194] The two or more inorganic insulating layers 123 to 127 may include a first gate insulating layer 123 positioned on the buffer layer 122, a second gate insulating layer 124 positioned on the first gate insulating layer 123, a first interlayer insulating layer 125 positioned on the second gate insulating layer 124, a third gate insulating layer 126 positioned on the first interlayer insulating layer 125, and a second interlayer insulating layer 127 positioned on the third gate insulating layer 126.

[0195] The first gate insulating layer 123 may cover the first semiconductor layers CH1 , E11 , E21 , CH2 , E12 , E22 , CH6 , E16 , and E26 on the buffer layer 122 .

[0196] The second gate insulating layer 124 may cover the first gate conductive layers G1 , G2 , and G6 on the first gate insulating layer 123 .

[0197] The first interlayer insulating layer 125 may cover the second gate conductive layers CAE and LB2 on the second gate insulating layer 124 .

[0198] The third gate insulating layer 126 may cover the second semiconductor layers CH4 , E14 , and E24 on the first interlayer insulating layer 125 .

[0199] The second interlayer insulating layer 127 may cover the third gate conductive layer G4 on the third gate insulating layer 126 .

[0200] According to some embodiments, the circuit layer 120 may also include a first planarization layer 128 covering the first source-drain conductive layer VGIL, NACE, DCE and ANCE1 on the second interlayer insulating layer 127 and including an organic insulating material, and a second planarization layer 129 covering the second source-drain conductive layer ANCE2 and DL on the first planarization layer 128 and including an organic insulating material.

[0201] In other words, the circuit layer 120 of the display device 100 according to some embodiments may include a barrier layer 121 positioned on the substrate 110, a buffer layer 122 positioned on the barrier layer 121 and covering the first light blocking layer LB1, first semiconductor layers CH1, E11, E21, CH2, E12, E22, CH6, E16 and E26 positioned on the buffer layer 122, a first gate insulating layer 123 covering the first semiconductor layers, first gate conductive layers G1, G2 and G6 positioned on the first gate insulating layer 123, a second gate insulating layer 124 covering the first gate conductive layer, a second gate conductive layer CAE and LB2 positioned on the second gate insulating layer 124, A first interlayer insulating layer 125 covering the second gate conductive layer, a second semiconductor layer CH4, E14 and E24 positioned on the first interlayer insulating layer 125, a third gate insulating layer 126 covering the second semiconductor layer, a third gate conductive layer G4 positioned on the third gate insulating layer 126, a second interlayer insulating layer 127 covering the third gate conductive layer, a first source-drain conductive layer ANCE1, VGIL and DCE positioned on the second interlayer insulating layer 127, a first planarizing layer 128 covering the first source-drain conductive layer, a second source-drain conductive layer DL and ANCE2 positioned on the first planarizing layer 128, and a second planarizing layer 129 covering the second source-drain conductive layer.

[0202] The barrier layer 121 and the buffer layer 122 may include different inorganic insulating materials.

[0203] The first semiconductor layer on the buffer layer 122 may include a first transistor T1, a second transistor T2, a fifth transistor T5 (see Figure 5 ), the sixth transistor T6 and the seventh transistor T7 (see Figure 5 )'s channel portions CH1, CH2 and CH6, first electrode portions E11, E12 and E16, and second electrode portions E21, E22 and E26.

[0204] The first gate conductive layer on the first gate insulating layer 123 may include a first transistor T1, a second transistor T2, a fifth transistor T5 (see FIG. 1 ), which are provided as P-type MOSFETs. Figure 5 ), the sixth transistor T6 and the seventh transistor T7 (see Figure 5 )'s gate electrodes G1, G2 and G6.

[0205] Since the fifth transistor T5 and the seventh transistor T7 have the same structure as those of the first transistor T1 , the second transistor T2 , and the sixth transistor T6 , redundant description will be omitted below.

[0206] In each of the first transistor T1 , the second transistor T2 , and the sixth transistor T6 , the channel portions CH1 , CH2 , and CH6 may overlap the gate electrodes G1 , G2 , and G6 .

[0207] A channel portion CH1 of the first transistor T1 may overlap the first light blocking layer LB1 on the barrier layer 121 .

[0208] In each of the first, second and sixth transistors T1, T2 and T6, first electrode portions E11, E12 and E16 may be connected to one end of channel portions CH1, CH2 and CH6, and second electrode portions E21, E22 and E26 may be connected to the other end of channel portions CH1, CH2 and CH6.

[0209] The first electrode portion E11 of the first transistor T1 may be connected to the second electrode portion E22 of the second transistor T2 .

[0210] The second electrode portion E21 of the first transistor T1 may be connected to the first electrode portion E16 of the sixth transistor T6 .

[0211] The second gate conductive layer on the second gate insulating layer 124 may include a capacitor electrode CAE and a second light blocking layer LB2 .

[0212] The capacitor electrode CAE may overlap the gate electrode G1 of the first transistor T1 .

[0213] Therefore, the first pixel capacitor PC1 (see Figure 5 ) may be provided by an overlapping region between the capacitor electrode CAE and the gate electrode G1 of the first transistor T1.

[0214] The second semiconductor layer on the first interlayer insulating layer 125 may include a third transistor T3 provided as an N-type MOSFET (see Figure 5 ) and a channel portion CH4, a first electrode portion E14 and a second electrode portion E24 of each of the fourth transistor T4.

[0215] The third gate conductive layer on the third gate insulating layer 126 may include a third transistor T3 provided as an N-type MOSFET (see Figure 5 ) and a gate electrode G4 of each of the fourth transistors T4.

[0216] In the third transistor T3 (see Figure 5 ) and in each of the fourth transistor T4, the channel portion CH4 may overlap the second light blocking layer LB2.

[0217] Since the third transistor T3 has the same structure as that of the fourth transistor T4 , redundant description will be omitted below.

[0218] A channel portion CH4 of the fourth transistor T4 may overlap the gate electrode G4 of the fourth transistor T4 .

[0219] The first electrode portion E14 of the fourth transistor T4 may be connected to one end of the channel portion CH4 of the fourth transistor T4 , and the second electrode portion E24 of the fourth transistor T4 may be connected to the other end of the channel portion CH4 of the fourth transistor T4 .

[0220] The first source-drain conductive layer on the second interlayer insulating layer 127 may include a first anode connection electrode ANCE1 , a data connection electrode DCE, a gate initialization voltage line VGIL, and a node auxiliary connection electrode NACE.

[0221] The second source-drain conductive layer on the first planarization layer 128 may include a second anode connection electrode ANCE2 and a data line DL.

[0222] The data link electrode DCE may be electrically connected to the first electrode portion E12 of the second transistor T2 through the first data link hole DCH1.

[0223] The data line DL may be electrically connected to the data link electrode DCE through the second data link hole DCH2.

[0224] Therefore, the data line DL may be electrically connected to the first electrode portion E12 of the second transistor T2 through the data connection electrode DCE.

[0225] The anode electrode 131 of the element layer 130 may be positioned on the second planarization layer 129 .

[0226] The first anode connection electrode ANCE1 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode connection hole ANCH1 .

[0227] The second anode connection electrode ANCE2 may be electrically connected to the first anode connection electrode ANCE1 through the second anode connection hole ANCH2 .

[0228] The anode electrode 131 may be electrically connected to the second anode connection electrode ANCE2 through the third anode connection hole ANCH3 .

[0229] Therefore, the anode electrode 131 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first and second anode connection electrodes ANCE1 and ANCE2 .

[0230] Each of the first data connection hole DCH1 and the first anode connection hole ANCH1 may penetrate the second interlayer insulating layer 127 , the third gate insulating layer 126 , the first interlayer insulating layer 125 , the second gate insulating layer 124 , and the first gate insulating layer 123 .

[0231] The first contact hole CT1 may extend from the second interlayer insulating layer 127 to one of the first semiconductor layer, the first gate conductive layer, and the second gate conductive layer.

[0232] That is, the first data connection hole DCH1 and the first anode connection hole ANCH1 extend from the second interlayer insulating layer 127 to the first semiconductor layer and thus may be included in the first contact hole CT1.

[0233] Each of the second anode connection hole ANCH2 and the second data connection hole DCH2 may penetrate the first planarization layer 128 .

[0234] The gate initialization voltage line VGIL may be electrically connected to the first electrode portion E14 of the fourth transistor T4 through the gate initialization voltage connection hole VGCH.

[0235] The node auxiliary connection electrode NACE may be electrically connected to the second electrode portion E24 of the fourth transistor T4 through the node auxiliary connection hole NACH.

[0236] The second contact hole CT2 may extend from the second interlayer insulating layer 127 to one of the second semiconductor layer and the third gate conductive layer.

[0237] Each of the gate initialization voltage connection hole VGCH and the node auxiliary connection hole NACH may penetrate the second interlayer insulating layer 127 and the third gate insulating layer 126 .

[0238] The second contact hole CT2 may extend from the second interlayer insulating layer 127 to one of the second semiconductor layer and the third gate conductive layer.

[0239] That is, the gate initialization voltage connection hole VGCH and the node auxiliary connection hole NACH extend from the second interlayer insulating layer 127 to the second semiconductor layer and thus may be included in the second contact hole CT2 .

[0240] The element layer 130 on the circuit layer 120 may include a plurality of light emitting elements LE positioned in the first emission area EA1 , the second emission area EA2 , and the third emission area EA3 , respectively.

[0241] Each of the plurality of light emitting elements LE may include a structure in which a light emitting layer 133 is positioned between an anode electrode 131 and a cathode electrode 134 facing each other.

[0242] According to some embodiments, the element layer 130 may include a plurality of anode electrodes 131 respectively positioned in a plurality of emission areas EA, a pixel defining layer 132 positioned in a non-emission area NEA and covering an edge of the anode electrode 131, a spacer layer 132' positioned on a portion of the pixel defining layer 132, a plurality of light emitting layers 133 respectively positioned on the plurality of anode electrodes 131, and a cathode electrode 134 positioned on the plurality of light emitting layers 133, the pixel defining layer 132, and the spacer layer 132'.

[0243] Alternatively, each of the plurality of light emitting elements LE may further include a first common layer 135 positioned between the anode electrode 131 and the light emitting layer 133 , and a second common layer 136 positioned between the light emitting layer 133 and the cathode electrode 134 .

[0244] The encapsulation layer 140 may be positioned on the circuit layer 120 and cover the element layer 130 .

[0245] The encapsulation layer 140 serves to block oxygen or moisture from penetrating into the element layer 130 , and to reduce electrical or physical impacts on the circuit layer 120 and the element layer 130 .

[0246] The encapsulation layer 140 may include: a first encapsulation layer 141 positioned on the circuit layer 120, covering the component layer 130 and including an inorganic insulating material, a second encapsulation layer 142 positioned on the first encapsulation layer 141, overlapping the component layer 130 and including an organic insulating material, and a third encapsulation layer 143 positioned on the first encapsulation layer 141, covering the second encapsulation layer 142 and including an inorganic insulating material.

[0247] Touch sensor layer 150 may be positioned on encapsulation layer 140 .

[0248] According to some embodiments, the touch sensor layer 150 may include a touch buffer layer 151 positioned on the encapsulation layer 140 , a touch interlayer insulating layer 152 positioned on the touch buffer layer 151 , and a touch planarizing layer 153 positioned on the touch interlayer insulating layer 152 .

[0249] The touch interlayer insulating layer 152 may cover the bridge electrode BE on the touch buffer layer 151 .

[0250] The touch planarization layer 153 may cover the driving electrodes TE and the sensing electrodes RE on the touch interlayer insulating layer 152 .

[0251] Each of the touch buffer layer 151 and the touch interlayer insulating layer 152 may include an inorganic insulating material.

[0252] The touch planarization layer 153 may include an organic insulating material. For example, the touch planarization layer 153 may be made of a negative photoresist material that can be formed by a low temperature process.

[0253] Polarizing layer 160 may be positioned on touch sensor layer 150 .

[0254] For example, the polarizing layer 160 may be attached to the touch planarizing layer 153 through an adhesive layer between the polarizing layer 160 and the touch planarizing layer 153 .

[0255] Fig. 9 is a diagram showing that according to some embodiments Figure 2 A plan view of the substrate.

[0256] Reference Fig. 9 , the substrate 110 of the display device 100 according to some embodiments may include a main area MA corresponding to a display surface and a sub area SBA protruding from one side of the main area MA.

[0257] The main area MA may include a display area DA in which the emission area EA is arranged and a non-display area NDA arranged around the display area DA.

[0258] The non-display area NDA may include a dam area DMA spaced apart from and surrounding the display area DA, and a bonding area JNA positioned between an edge of the substrate 110 and the dam area DMA.

[0259] One or more dam portions DM1 and DM2 (see Fig.10 ) can be arranged in the dam area DMA.

[0260] At least one dam serves to limit a region where the organic insulating material of the second encapsulation layer 142 widely spreads. That is, the arrangement range of the second encapsulation layer 142 may be limited to a region surrounded by one or more dams DM1 and DM2.

[0261] In the bonding area JNA, a bonding structure of an inorganic insulating material may be arranged by sequentially stacking inorganic insulating materials included in the circuit layer 120 , the encapsulation layer 140 , and the touch sensor layer 150 .

[0262] The non-display area NDA may further include a scan driving circuit area SCDA positioned adjacent to at least one edge of the display area DA in the first direction DR1.

[0263] The circuit layer 120 may include a scan driving circuit positioned in the scan driving circuit area SCDA.

[0264] For example, the display driving circuit 200 or the circuit board 300 may supply a scan control signal to the scan driving circuit based on the digital video data and the timing signal.

[0265] The scan driving circuits of the scan driving circuit area SCDA may sequentially supply signals to the wirings in the first direction DR1 based on the scan control signals.

[0266] For example, the wiring in the first direction DR1 may include a scan write line GWL for transmitting a scan write signal GW, an emission control line ECL for transmitting an emission control signal EC, a scan initialization line GIL for transmitting a scan initialization signal GI, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0267] Fig. 9 A case is shown in which the scan driving circuit area SCDA is a portion of the non-display area NDA adjacent to both corners of the display area DA in the first direction DR1 , but this is nothing more than an example.

[0268] The sub-region SBA may include a bending area BA deformed to be bent, and first and second sub-regions SB1 and SB2 respectively contacting both sides of the bending area BA.

[0269] The first sub-region SB1 is positioned between the main area MA and the bending area BA. One side of the first sub-region SB1 may contact the non-display area NDA of the main area MA, and the other side of the first sub-region SB1 may contact the bending area BA.

[0270] The second sub-region SB2 is spaced apart from the main region MA via the bending region BA, and is positioned on the bottom surface of the substrate 110 through the bending region BA deformed to be curved. That is, since the bending region BA is deformed to be curved, the second sub-region SB2 may overlap with the main region MA in the thickness direction of the substrate 110 (ie, the third direction DR3).

[0271] One side of the second sub-region SB2 may be in contact with the bending area BA. The other side of the second sub-region SB2 may be in contact with a portion of the edge of the substrate 110.

[0272] The signal pads SPD connected to the circuit board 300 and the display driving circuit 200 may be positioned in the second sub-region SB2 .

[0273] The display device 100 according to some embodiments further includes a groove SGR positioned in a portion of the bonding area JNA and spaced apart from the dam area DMA and an edge of the substrate 110 .

[0274] According to some embodiments, the groove SGR may be a through groove that exposes the substrate 110 while penetrating at least one insulating layer among the insulating layers of the circuit layer 120 extending to the edge of the substrate 110. That is, the groove SGR may penetrate the buffer layer 122 and the barrier layer 121 covering the substrate 110.

[0275] Since the stepped portion is generated by the groove SGR, a portion of the first encapsulation layer 141 positioned on the bonding area JNA may include a groove in which the stepped portion of the groove SGR is replicated. Therefore, the organic insulating material of the second encapsulation layer 142 that has overflowed to the bonding area JNA is accommodated in the groove of the first encapsulation layer 141 and may not extend to the edge of the substrate 110.

[0276] The groove SGR according to some embodiments may be referred to as a storage valley, a storage groove, a receiving groove, an auxiliary valley, an auxiliary groove, or the like because it is a member for providing an auxiliary valley for receiving overflowing organic insulating material of the second encapsulation layer 142 .

[0277] The groove SGR may face other sides of the edge of the main area MA except for a side connected to the sub area SBA.

[0278] For example, when the edge of the main area MA includes a first side and a second side facing each other in the first direction DR1 and a third side and a fourth side facing each other in the second direction DR2, and the sub-area SBA is connected to the fourth side of the main area MA, the groove SGR may extend to face the first side, the third side and the second side of the edge of the main area MA.

[0279] This is to prevent or reduce the situation where the wiring positioned between the sub-area SBA and the side of the display area DA facing the sub-area SBA is disconnected due to the groove SGR.

[0280] Fig.10 , Fig.11 , Fig.12 and Fig.13 According to some embodiments, Fig. 9 A cross-sectional view taken along line EE'.

[0281] Reference Fig.10 According to some embodiments, the circuit layer 120 of the display device 100 may further include a circuit layer 120 positioned in the non-display area NDA and transmitting the second power source ELVSS (see Figure 5 ) and a second power connection auxiliary line VSCAL electrically connected between the second power line VSSPL and the cathode electrode 134.

[0282] The second power supply line VSSPL may include a second power supply main line VSSPL1 positioned in the first source-drain conductive layer and a second power supply sub line VSSPL2 positioned in the second source-drain conductive layer.

[0283] The second power sub line VSSPL2 may be electrically connected to the second power main line VSSPL1 through a connection hole penetrating the first planarization layer 128 .

[0284] The second power supply connection auxiliary line VSCAL may be the same layer as the anode electrode 131 .

[0285] The cathode electrode 134 may be electrically connected to the second power connection auxiliary line VSCAL through the hole from which the pixel defining layer 132 is removed, and may be electrically connected to the second power line VSSPL through the second power connection auxiliary line VSCAL.

[0286] According to some embodiments, the display device 100 may further include one or more dam portions DM1 and DM2 positioned in the dam area DMA of the non-display area NDA.

[0287] The one or more dam portions DM1 and DM2 may include two or more dam layers DML11 , DML12 , and DML13 , and DML21 , DML22 , DML23 , and DML24 , respectively, which are sequentially stacked.

[0288] Each of the two or more dam layers DML11 , DML12 , and DML13 and DML21 , DML22 , DML23 , and DML24 may be the same layer as one of the one or more planarization layers 128 and 129 included in the circuit layer 120 , and the pixel defining layer 132 and the spacer layer 132 ′ included in the element layer 130 .

[0289] That is, each of the two or more dam layers DML11 , DML12 , and DML13 and DML21 , DML22 , DML23 , and DML24 may be the same layer as one of the first planarization layer 128 , the second planarization layer 129 , the pixel defining layer 132 , and the spacer layer 132 ′.

[0290] For example, the one or more dams DM1 and DM2 may include a first dam DM1 surrounding the display area DA and a second dam DM2 surrounding the first dam DM1 .

[0291] The first dam portion DM1 may include a first dam layer DML11 , a second dam layer DML12 , and a third dam layer DML13 provided on the same layer as the second planarization layer 129 , the pixel defining layer 132 , and the spacer layer 132 ′.

[0292] The second dam portion DM2 may include fourth, fifth, sixth, and seventh dam layers DML21, DML22, DML23, and DML24 provided on the same layer as the first and second planarization layers 128, 129, the pixel defining layer 132, and the spacer layer 132'.

[0293] According to some embodiments, the first planarization layer 128 , the second planarization layer 129 , the pixel defining layer 132 , and the spacer layer 132 ′ including an organic insulating material may be spaced apart from the dam area DMA.

[0294] Since the one or more dam portions DM1 and DM2 are positioned in the dam area DMA, the stack structure of the inorganic insulating material may be positioned in the bonding area JNA.

[0295] The barrier layer 121 and the buffer layer 122 may extend to the edge of the substrate 110 .

[0296] The two or more inorganic insulating layers 123 to 127 positioned on the buffer layer 122 may extend to the first boundary area BNDA1 in contact with the dam area DMA in the bonding area JNA. That is, the first gate insulating layer 123, the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127 positioned on the buffer layer 122 may extend only to the first boundary area BNDA1 of the bonding area JNA.

[0297] Therefore, at the edge of the first boundary area BNDA1 , side surfaces of the two or more inorganic insulating layers 123 to 127 are exposed, so that the first crack dam CRD1 may be provided through the side surfaces of the two or more inorganic insulating layers 123 to 127 .

[0298] In other words, the first crack dam CRD1 may be a stepped portion caused by side surfaces of the first, second, first, third, and second interlayer insulating layers 123 , 124 , 125 , 126 , and 127 positioned on the buffer layer 122 .

[0299] Since the two or more inorganic insulating layers 123 to 127 do not extend to the edge of the substrate 110 due to the first crack dam CRD1 , it is possible to prevent or reduce a crack caused by an external impact from extending from a boundary of the substrate 110 to the display area DA.

[0300] According to some embodiments, encapsulation layer 140 may include a first encapsulation layer 141 covering element layer 130, a second encapsulation layer 142 positioned on first encapsulation layer 141 and made of an organic insulating material, and a third encapsulation layer 143 covering second encapsulation layer 142. Each of first encapsulation layer 141 and third encapsulation layer 143 may include an inorganic insulating material.

[0301] The second encapsulation layer 142 may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and the like.

[0302] The second encapsulation layer 142 may be prepared by a process in which a liquid organic insulating material is dropped onto the first encapsulation layer 141 , spread to cover the display area DA, and then cured.

[0303] The range in which the organic insulating material of the second encapsulation layer 142 extends may be limited by the one or more dam portions DM1 and DM2 of the dam area DMA.

[0304] That is, the second encapsulation layer 142 may be positioned in a region surrounded by the one or more dams DM1 and DM2 .

[0305] Thus, in the bonding area JNA, the first encapsulation layer 141 may be in contact with the two or more inorganic insulation layers 123 to 127 of the circuit layer 120 , and the third encapsulation layer 143 may be in contact with the first encapsulation layer 141 .

[0306] The touch sensor layer 150 may include a touch buffer layer 151 positioned on the third encapsulation layer 143 , a touch interlayer insulating layer 152 positioned on the touch buffer layer 151 , and a touch planarizing layer 153 positioned on the touch interlayer insulating layer 152 .

[0307] The touch planarization layer 153 may include an organic insulating material and may be positioned in the display area DA. The touch planarization layer 153 may extend to a portion of the non-display area NDA but be spaced apart from the dam area DMA.

[0308] According to some embodiments, first encapsulation layer 141 may extend to an edge of substrate 110 .

[0309] In addition, the inorganic insulating layer positioned on the first encapsulation layer 141, i.e., the third encapsulation layer 143, the touch buffer layer 151 and the touch interlayer insulating layer 152 may extend to a third boundary area BNDA3 which is a remaining area in the bonding area JNA except for the second boundary area BNDA2 in contact with the edge of the substrate 110.

[0310] The third boundary area BNDA3 , which is an area between the dam area DMA and the second boundary area BNDA2 , may include the first boundary area BNDA1 .

[0311] That is, the third encapsulation layer 143 , the touch buffer layer 151 , and the touch interlayer insulating layer 152 may extend only to the third boundary area BNDA3 of the bonding area JNA.

[0312] Therefore, at the edge of the third boundary area BNDA3, the side surface of at least one of the third encapsulation layer 143, the touch buffer layer 151 and the touch interlayer insulating layer 152 is exposed, so that a second crack dam CRD2 can be provided through the side surfaces of the third encapsulation layer 143, the touch buffer layer 151 and the touch interlayer insulating layer 152.

[0313] In other words, the second crack dam CRD2 may be a stepped portion caused by side surfaces of the third encapsulation layer 143 , the touch buffer layer 151 , and the touch interlayer insulating layer 152 positioned on the first encapsulation layer 141 .

[0314] Since the third encapsulation layer 143 , the touch buffer layer 151 , and the touch interlayer insulating layer 152 do not extend to the edge of the substrate 110 due to the second crack dam CRD2 , it is possible to prevent or reduce cracks caused by external impact from extending from the edge of the substrate 110 to the display area DA.

[0315] The display device 100 according to some embodiments further includes a groove SGR positioned in a portion of the bonding area JNA and penetrating the barrier layer 121 and the buffer layer 122 .

[0316] The groove SGR may be spaced apart from the edge of the substrate 110 and the dam area DMA.

[0317] The first encapsulation layer 141 extends to the edge of the substrate 110 and thus covers the groove SGR.

[0318] In addition, a portion of the first encapsulation layer 141 covering the groove SGR positioned in the bonding area JNA may replicate the stepped portion of the groove SGR and may be formed in a groove shape.

[0319] Therefore, the warping defect in the bonding area JNA may be prevented or reduced by the groove SGR.

[0320] That is, in the process of forming the second encapsulation layer 142 , the liquid organic insulating material dropped onto the display area DA may be widely spread in a region surrounded by the one or more dam portions DM1 and DM2 arranged in the dam area DMA.

[0321] However, when the liquid organic insulating material having an amount greater than a critical amount drops due to a process error, the expansion of the organic insulating material is not limited by the one or more dams DM1 and DM2 , so that some of the organic insulating material may overflow to the bonding area JNA.

[0322] In this case, if Fig.11As shown in, according to some embodiments, when some of the organic insulating material RSD overflowing into the bonding area JNA extends to a portion of the bonding area JNA between the dam area DMA and the groove SGR and reaches the groove SGR, it can be accommodated on a portion of the first encapsulation layer 141 formed in a groove shape while overlapping the groove SGR.

[0323] Therefore, some of the organic insulating material overflowing into the bonding area JNA is blocked by the groove SGR, thereby preventing or reducing its extension to the edge of the substrate 110 .

[0324] Therefore, the bonding between the first encapsulation layer 141 and the third encapsulation layer 143 in the bonding area JNA may be reliably maintained, which can prevent or reduce a warping defect.

[0325] Therefore, the life span and quality reliability of the display device 100 may be improved.

[0326] like Fig.10 and Fig.11 As shown in , according to some embodiments, the first crack dam CRD1 may be spaced apart from the groove SGR.

[0327] That is, the first crack dam CRD1 may be located adjacent to the dam area DMA as compared to the groove SGR.

[0328] Therefore, the groove SGR may be covered by the first encapsulation layer 141 .

[0329] In this manner, a difference between the width of the first encapsulation layer 141 overlapping the groove SGR and the width of the groove SGR may be reduced so that an amount of the organic insulating material that may be accommodated on the first encapsulation layer 141 overlapping the groove SGR may be increased.

[0330] In addition, if Fig.10 and Fig.11 As shown in , according to some embodiments, the second crack dam CRD2 may be positioned between the edge of the substrate 110 and the groove SGR.

[0331] Therefore, the third encapsulation layer 143 , the touch buffer layer 151 , and the touch interlayer insulating layer 152 positioned on the first encapsulation layer 141 may overlap the groove SGR.

[0332] In this manner, the width of the third boundary area BNDA3 as the bonding area between the first encapsulation layer 141 and the third encapsulation layer 143 in the bonding area JNA becomes widened so that the bonding between the first encapsulation layer 141 and the third encapsulation layer 143 may become relatively reliable.

[0333] Alternatively, if Fig.12 and Fig.13As shown in , according to some embodiments, the second crack dam CRD2 ′ may be positioned between the groove SGR and the first crack dam CRD1 .

[0334] In this case, the second boundary area BNDA2 ′ contacting the edge of the substrate 110 in the bonding area JNA may be wide enough to include the groove SGR.

[0335] In addition, the third boundary area BNDA3 ′, which is a remaining area except the second boundary area BNDA2 ′ in the bonding area JNA, may include the first boundary area BNDA1 corresponding to the first crack dam CRD1 .

[0336] In this manner, when the second crack dam CRD2 ′ is positioned between the groove SGR and the first crack dam CRD1 , the third encapsulation layer 143 , the touch buffer layer 151 , and the touch interlayer insulating layer 152 positioned on the first encapsulation layer 141 may not overlap the groove SGR.

[0337] Therefore, if Fig.13 As shown in FIG. 1 , some of the organic insulating material RSD accommodated on a portion of the first encapsulation layer 141 overlapping the groove SGR is exposed without being covered by the third encapsulation layer 143 , the touch buffer layer 151 , and the touch interlayer insulating layer 152 , and thus may be more easily removed.

[0338] Next, a method for manufacturing the display device 100 according to some embodiments will be described.

[0339] Fig.14 and Fig.15 is a flowchart illustrating a method for manufacturing a display device according to some embodiments. Figures 16 to 28 is a diagram showing that according to some embodiments Fig.14 and Fig.15 Process diagram of the manufacturing method.

[0340] Reference Fig.14 , a method of manufacturing the display device 100 according to some embodiments may include providing a substrate 110 (operation S10 ), and forming a circuit layer 120 on the substrate 110 (operation S20 ).

[0341] In the operation of providing the substrate 110 (operation S10), the substrate 110 may include a main area MA and a sub-area SBA protruding from one side of the main area MA, the main area MA including a display area DA where the emission area EA is arranged and a non-display area NDA arranged around the display area DA.

[0342] The non-display area NDA may include a dam area DMA surrounding the display area DA and spaced apart from the display area DA, and a bonding area JNA positioned between an edge of the substrate 110 and the dam area DMA.

[0343] The bonding area JNA may include a first boundary area BNDA1 in contact with the dam area DMA, and second boundary areas BNDA2 and BNDA2 ′ in contact with the edge of the substrate 110 .

[0344] Operation S20 of forming the circuit layer 120 may include forming a barrier layer 121 by stacking an inorganic insulating material on the substrate 110 (operation S201), forming a buffer layer 122 by stacking an inorganic insulating material on the barrier layer 121 (operation S203), and forming a groove SGR (i.e., a storage valley) by partially removing the barrier layer 121 and the buffer layer 122 (operation S232).

[0345] According to some embodiments, operation S20 of forming the circuit layer 120 may further include forming a first light blocking layer LB1 (operation S202 ) before forming the buffer layer 122 (operation S203 ).

[0346] According to some embodiments, operation S20 of forming the circuit layer 120 may further include: before operation S232 of forming the groove SGR, forming a first semiconductor layer on the buffer layer 122 (operation S211), forming a first gate insulating layer 123 covering the first semiconductor layer by stacking an inorganic insulating material on the buffer layer 122 (operation S212), forming a first gate conductive layer on the first gate insulating layer 123 (operation S213), forming a second gate insulating layer 124 covering the first gate conductive layer by stacking an inorganic insulating material on the first gate insulating layer 123 (operation S214), forming a second gate conductive layer on the second gate insulating layer 124 (operation S215), forming a second gate conductive layer covering the second gate conductive layer by stacking an inorganic insulating material on the second gate insulating layer 124, and forming a second gate conductive layer covering the second gate conductive layer by stacking an inorganic insulating material on the second gate insulating layer 124. A first interlayer insulating layer 125 is formed (operation S216), a second semiconductor layer is formed on the first interlayer insulating layer 125 (operation S221), a third gate insulating layer 126 covering the second semiconductor layer is formed by stacking an inorganic insulating material on the first interlayer insulating layer 125 (operation S222), a third gate conductive layer is formed on the third gate insulating layer 126 (operation S223), a second interlayer insulating layer 127 covering the third gate conductive layer is formed by stacking an inorganic insulating material on the third gate insulating layer 126 (operation S224), and a first crack dam CRD1 is formed by partially removing the second interlayer insulating layer 127, the third gate insulating layer 126, the first interlayer insulating layer 125, the second gate insulating layer 124 and the first gate insulating layer 123 (operation S231).

[0347] In operation S231 of forming the first crack dam CRD1 , a first contact hole CT1 extending from the second interlayer insulating layer 127 to one of the first semiconductor layer, the first gate conductive layer, and the second gate conductive layer may be arranged together with the first crack dam CRD1 .

[0348] In operation S232 of forming the groove SGR, a second contact hole CT2 extending from the second interlayer insulating layer 127 to one of the second semiconductor layer and the third gate conductive layer may be arranged together with the groove SGR.

[0349] According to some embodiments, operation S20 of forming the circuit layer 120 may further include: after operation S232 of forming the groove SGR, forming a first source-drain conductive layer on the second interlayer insulating layer 127 (operation S241), forming a first planarization layer 128 covering the first source-drain conductive layer by stacking an organic insulating material on the second interlayer insulating layer 127 (operation S242), forming a second source-drain conductive layer on the first planarization layer 128 (operation S243), and forming a second planarization layer 129 covering the second source-drain conductive layer by stacking an organic insulating material on the first planarization layer 128 (operation S244).

[0350] Reference Fig.15 According to some embodiments, the manufacturing method of the display device 100 may further include: after operation S20 of forming the circuit layer 120, forming the element layer 130 on the circuit layer 120 (operation S30), forming the encapsulation layer 140 on the element layer 130 (operation S40), and forming the touch sensor layer 150 on the encapsulation layer 140 (operation S50).

[0351] Operation S30 of forming the element layer 130 may include: forming an anode electrode 131 in the emission area EA (operation S310); forming a pixel defining layer 132 covering the edge of the anode electrode 131 in the non-emission area NEA between the emission areas EA, and forming a spacer layer 132' on a portion of the pixel defining layer 132 (operation S320); forming a light-emitting layer 133 on the anode electrode 131 (operation S330); and forming a cathode electrode 134 on the pixel defining layer 132, the spacer layer 132' and the light-emitting layer 133 (operation S340).

[0352] Operation S40 of forming the encapsulation layer 140 may include: forming a first encapsulation layer 141 including an inorganic insulating material on the element layer 130 (operation S410), forming a second encapsulation layer 142 including an organic insulating material on the first encapsulation layer 141 (operation S420), and forming a third encapsulation layer 143 covering the second encapsulation layer 142 and including an inorganic insulating material on the first encapsulation layer 141 (operation S430).

[0353] Operation S50 of forming the touch sensor layer 150 may include: forming a touch buffer layer 151 by stacking an inorganic insulating material on the third encapsulation layer 143 (operation S510), forming a first touch conductive layer on the touch buffer layer 151 (operation S520), forming a touch interlayer insulating layer 152 covering the first touch conductive layer by stacking an inorganic insulating material on the touch buffer layer 151 (operation S530), forming second crack dams CRD2 and CRD2' by partially removing the touch interlayer insulating layer 152 (operation S540), forming a second touch conductive layer on the touch interlayer insulating layer 152 (operation S550), and forming a touch planarization layer 153 covering the second touch conductive layer by stacking an organic insulating material on the touch interlayer insulating layer 152 (operation S560).

[0354] For example, in operation S520 of forming the first touch conductive layer, the first touch conductive layer may include the bridge electrode BE.

[0355] Then, in operation S550 of forming the second touch conductive layer, the second touch conductive layer may include driving electrodes TE and sensing electrodes RE.

[0356] In operation S540 of forming the second crack dams CRD2 and CRD2 ′, the touch contact hole TCNT extending to the bridge electrode BE may be located together with the second crack dams CRD2 and CRD2 ′.

[0357] Reference Fig.16 In operation S10 of providing the substrate 110 , the substrate 110 may include a display area DA and a non-display area NDA, and the non-display area NDA may include a dam area DMA and a bonding area JNA.

[0358] The display area DA may include the emission area EA.

[0359] The dam area DMA may be spaced apart from the display area DA.

[0360] The bonding area JNA may be positioned between the dam area DMA and an edge of the substrate 110 .

[0361] In operation S201 of forming the barrier layer 121 , the barrier layer 121 that completely covers one surface of the substrate 110 may be formed by stacking an inorganic insulating material on the substrate 110 .

[0362] The barrier layer 121 may extend to the edge of the substrate 110 .

[0363] In operation S202 of forming the first light blocking layer LB1 , the first light blocking layer LB1 may be formed by partially removing the light blocking material on the barrier layer 121 .

[0364] In operation S203 of forming the buffer layer 122 , the buffer layer 122 covering the first light blocking layer LB1 may be formed by stacking an inorganic insulating material on the barrier layer 121 .

[0365] The buffer layer 122 may include an inorganic insulating material having a composition or component different from that of the barrier layer 121 .

[0366] The buffer layer 122 may completely overlap one surface of the substrate 110 .

[0367] In operation S211 of forming the first semiconductor layers CH1, E11, E21, CH2, E12, E22, CH6, E16, and E26, the first semiconductor layers CH1, E11, E21, CH2, E12, E22, CH6, E16, and E26 may be formed by partially removing the first semiconductor material layer on the buffer layer 122.

[0368] The first semiconductor layer may include a first transistor T1, a second transistor T2, a fifth transistor T5 (see Figure 5 ), the sixth transistor T6 and the seventh transistor T7 (see Figure 5 )'s channel portions CH1, CH2 and CH6, first electrode portions E11, E12 and E16, and second electrode portions E21, E22 and E26.

[0369] The first semiconductor layers CH1, E11, E21, CH2, E12, E22, CH6, E16, and E26 may include a silicon semiconductor.

[0370] In operation S212 of forming the first gate insulating layer 123 , the first gate insulating layer 123 covering the first semiconductor layers CH1 , E11 , E21 , CH2 , E12 , E22 , CH6 , E16 , and E26 may be formed by stacking an inorganic insulating material on the buffer layer 122 .

[0371] In operation S212 of forming the first gate insulating layer 123 , the first gate insulating layer 123 may extend to the edge of the substrate 110 while completely overlapping one surface of the substrate 110 .

[0372] In operation S213 of forming the first gate conductive layers G1 , G2 , and G6 , the first gate conductive layers G1 , G2 , and G6 may be formed by partially removing the conductive material layer on the first gate insulating layer 123 .

[0373] The first gate conductive layer may include a first transistor T1, a second transistor T2, a fifth transistor T5 (see FIG. Figure 5 ), the sixth transistor T6 and the seventh transistor T7 (see Figure 5)'s gate electrodes G1, G2 and G6.

[0374] In operation S214 of forming the second gate insulating layer 124 , the second gate insulating layer 124 covering the first gate conductive layers G1 , G2 , and G6 may be formed by stacking an inorganic insulating material on the first gate insulating layer 123 .

[0375] In operation S214 of forming the second gate insulating layer 124 , the second gate insulating layer 124 may extend to the edge of the substrate 110 while completely overlapping one surface of the substrate 110 .

[0376] In operation S215 of forming the second gate conductive layers CAE and LB2 , the second gate conductive layers CAE and LB2 may be formed by partially removing the conductive material layer on the second gate insulating layer 124 .

[0377] The second gate conductive layer may include a capacitor electrode CAE and a second light blocking layer LB2.

[0378] In operation S216 of forming the first interlayer insulating layer 125 , the first interlayer insulating layer 125 covering the second gate conductive layers CAE and LB2 may be formed by stacking an inorganic insulating material on the second gate insulating layer 124 .

[0379] In operation S216 of forming the first interlayer insulating layer 125 , the first interlayer insulating layer 125 may extend to the edge of the substrate 110 while completely overlapping one surface of the substrate 110 .

[0380] In operation S221 of forming the second semiconductor layers CH4 , E14 , and E24 , the second semiconductor layers CH4 , E14 , and E24 may be formed by partially removing the second semiconductor material layer on the first interlayer insulating layer 125 .

[0381] The second semiconductor layer may include a third transistor T3 provided as an N-type MOSFET (see Figure 5 ) and the channel portion CH4, the first electrode portion E14 and the second electrode portion E24 of the fourth transistor T4.

[0382] The second semiconductor layers CH4, E14, and E24 may include an oxide semiconductor.

[0383] In operation S222 of forming the third gate insulating layer 126 , the third gate insulating layer 126 covering the second semiconductor layers CH4 , E14 , and E24 may be formed by stacking an inorganic insulating material on the first interlayer insulating layer 125 .

[0384] In operation S222 of forming the third gate insulating layer 126 , the third gate insulating layer 126 may extend to the edge of the substrate 110 while completely overlapping one surface of the substrate 110 .

[0385] In operation S223 of forming the third gate conductive layer G4 , the third gate conductive layer G4 may be formed by partially removing the conductive material layer on the third gate insulating layer 126 .

[0386] The third gate conductive layer may include a fourth transistor T4 and a third transistor T3 provided as N-type MOSFETs (see Figure 5 )'s gate electrode G4.

[0387] In operation S224 of forming the second interlayer insulating layer 127 , the second interlayer insulating layer 127 covering the third gate conductive layer G4 may be formed by stacking an inorganic insulating material on the third gate insulating layer 126 .

[0388] In operation S224 of forming the second interlayer insulating layer 127 , the second interlayer insulating layer 127 may extend to the edge of the substrate 110 while completely overlapping one surface of the substrate 110 .

[0389] Reference Fig.17 In operation S231 of forming the first crack dam CRD1 , the first crack dam CRD1 and the first contact hole CT1 may be formed by partially removing the second interlayer insulating layer 127 , the third gate insulating layer 126 , the first interlayer insulating layer 125 , the second gate insulating layer 124 , and the first gate insulating layer 123 .

[0390] The first contact hole CT1 may extend from the second interlayer insulating layer 127 to one of the first semiconductor layer, the first gate conductive layer, and the second gate conductive layer.

[0391] The first contact hole CT1 may include a first data connection hole DCH1 and a first anode connection hole ANCH1.

[0392] The first data connection hole DCH1 may penetrate the second interlayer insulating layer 127 , the third gate insulating layer 126 , the first interlayer insulating layer 125 , the second gate insulating layer 124 , and the first gate insulating layer 123 , and may reach the first electrode portion E12 of the second transistor T2 .

[0393] The first anode connection hole ANCH1 may penetrate the second interlayer insulating layer 127 , the third gate insulating layer 126 , the first interlayer insulating layer 125 , the second gate insulating layer 124 , and the first gate insulating layer 123 , and may reach the second electrode portion E26 of the sixth transistor T6 .

[0394] The first crack dam CRD1 may include side surfaces of the first gate insulating layer 123 , the second gate insulating layer 124 , the first interlayer insulating layer 125 , the third gate insulating layer 126 , and the second interlayer insulating layer 127 positioned on the buffer layer 122 .

[0395] Due to the first crack dam CRD1, the first gate insulating layer 123, the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126 and the second interlayer insulating layer 127 positioned on the buffer layer 122 may extend to the first boundary area BNDA1 contacting the dam area DMA in the bonding area JNA.

[0396] Reference Fig.18 In operation S232 of forming the groove SGR, the groove SGR may be formed by partially removing the buffer layer 122 and the barrier layer 121 .

[0397] The groove SGR may be positioned in a portion of the bonding area JNA and be spaced apart from the dam area DMA and the edge of the substrate 110 , and may penetrate the buffer layer 122 and the barrier layer 121 .

[0398] In operation S232 of forming the groove SGR, a portion of the bonding area JNA of the substrate 110 may be exposed by the groove SGR.

[0399] Then, in operation S232 of forming the groove SGR, a second contact hole CT2 may be formed by partially removing the second interlayer insulating layer 127 and the third gate insulating layer 126 as well as the buffer layer 122 and the barrier layer 121 .

[0400] The second contact hole CT2 may extend from the second interlayer insulating layer 127 to one of the second semiconductor layer and the third gate conductive layer.

[0401] The second contact hole CT2 may include a gate initialization voltage connection hole VGCH and a node auxiliary connection hole NACH.

[0402] The gate initialization voltage connection hole VGCH may penetrate the second interlayer insulating layer 127 and the third gate insulating layer 126 and may reach the first electrode portion E14 of the fourth transistor T4.

[0403] The node auxiliary connection hole NACH may penetrate the second interlayer insulating layer 127 and the third gate insulating layer 126 and may reach the second electrode portion E24 of the fourth transistor T4.

[0404] Reference Fig.19In operation S241 of forming the first source-drain conductive layers ANCE1 , DCE, VGIL, and NACE, the first source-drain conductive layers ANCE1 , DCE, VGIL, and NACE may be formed by partially removing the conductive material layer on the second interlayer insulating layer 127 .

[0405] The first source-drain conductive layer may include a first anode connection electrode ANCE1 , a data connection electrode DCE, a gate initialization voltage line VGIL, and a node auxiliary connection electrode NACE.

[0406] The first anode connection electrode ANCE1 may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode connection hole ANCH1 .

[0407] The data link electrode DCE may be electrically connected to the first electrode portion E12 of the second transistor T2 through the first data link hole DCH1.

[0408] The gate initialization voltage line VGIL may be electrically connected to the first electrode portion E14 of the fourth transistor T4 through the gate initialization voltage connection hole VGCH.

[0409] The node auxiliary connection electrode NACE may be electrically connected to the second electrode portion E24 of the fourth transistor T4 through the node auxiliary connection hole NACH.

[0410] In operation S242 of forming the first planarization layer 128 , the first planarization layer 128 covering the first source-drain conductive layers ANCE1 , DCE, VGIL, and NACE may be formed by stacking an organic insulating material on the second interlayer insulating layer 127 .

[0411] In addition, the second data connection hole DCH2 and the second anode connection hole ANCH2 may be formed by partially removing the first planarization layer 128 .

[0412] In addition, a dam layer positioned at the same layer as the first planarization layer 128 may be positioned in the dam area DMA of the non-display area NDA.

[0413] For example, the fourth dam layer DML21 of the second dam portion DM2 may be positioned at the same layer as the first planarization layer 128 .

[0414] Next, in operation S243 of forming the second source-drain conductive layers ANCE2 and DL, the second source-drain conductive layers ANCE2 and DL may be formed by partially removing the conductive material layer on the first planarization layer 128 .

[0415] The second source-drain conductive layer ANCE2 and DL may include a second anode connection electrode ANCE2 and a data line DL.

[0416] The second anode connection electrode ANCE2 may be electrically connected to the first anode connection electrode ANCE1 through the second anode connection hole ANCH2 .

[0417] The data line DL may be electrically connected to the data link electrode DCE through the second data link hole DCH2.

[0418] In operation S244 of forming the second planarization layer 129 , the second planarization layer 129 covering the second source-drain conductive layers ANCE2 and DL may be formed by stacking an organic insulating material on the first planarization layer 128 .

[0419] In addition, the third anode connection hole ANCH3 may be formed by partially removing the second planarization layer 129 .

[0420] In addition, a dam layer positioned at the same layer as the second planarization layer 129 may be positioned in the dam area DMA of the non-display area NDA.

[0421] For example, the first dam layer DML11 of the first dam portion DM1 and the fifth dam layer DML22 of the second dam portion DM2 may be positioned at the same layer as the second planarization layer 129 .

[0422] Thus, the circuit layer 120 may be formed (operation S20 ).

[0423] Reference Fig. 20 In operation S310 of forming the anode electrode 131 , the anode electrode 131 may be positioned in the emission area EA by partially removing the conductive material layer on the second planarization layer 129 .

[0424] The anode electrode 131 may be electrically connected to the second anode connection electrode ANCE2 through the third anode connection hole ANCH3 .

[0425] In operation S320 of forming the pixel defining layer 132 and the spacer layer 132 ′, the pixel defining layer 132 positioned in the non-emission area NEA and the spacer layer 132 ′ positioned on a portion of the pixel defining layer 132 may be provided by partially removing the organic insulating material on the second planarization layer 129 using a halftone mask.

[0426] The pixel defining layer 132 may cover an edge of the anode electrode 131 .

[0427] The pixel defining layer 132 may extend to a portion of the non-display area NDA, and may be spaced apart from the dam area DMA.

[0428] In addition, a dam layer positioned at the same layer as the pixel defining layer 132 and the spacer layer 132 ′ may be positioned in the dam area DMA of the non-display area NDA.

[0429] For example, the second dam layer DML12 of the first dam portion DM1 and the sixth dam layer DML23 of the second dam portion DM2 may be positioned at the same layer as the pixel defining layer 132 , and the third dam layer DML13 of the first dam portion DM1 and the seventh dam layer DML24 of the second dam portion DM2 may be positioned at the same layer as the spacer layer 132 ′.

[0430] Therefore, one or more dam portions DM1 and DM2 may be arranged in the dam area DMA.

[0431] In operation S330 of forming the light emitting layer 133 , the first common layer 135 and the light emitting layer 133 may be positioned on the anode electrode 131 by selectively depositing an organic material.

[0432] In operation S340 of forming the cathode electrode 134 , after forming the second common layer 136 covering the pixel defining layer 132 , the spacer layer 132 ′, and the light emitting layer 133 by completely stacking organic materials, the cathode electrode 134 may be positioned on the second common layer 136 by stacking a conductive material layer.

[0433] Thus, the element layer 130 including the light emitting element LE may be formed (operation S30 ).

[0434] Next, in operation S410 of forming the first encapsulation layer 141 , the first encapsulation layer 141 may be formed by stacking an inorganic insulating material on the cathode electrode 134 .

[0435] The first encapsulation layer 141 may extend to the edge of the substrate 110 while completely overlapping one surface of the substrate 110 .

[0436] Therefore, the first encapsulation layer 141 covers the groove SGR, and thus may include a groove corresponding to the groove SGR.

[0437] Reference Fig.21 In operation S420 of forming the second encapsulation layer 142 , at least one second encapsulation layer 142 may be formed by dropping a liquid organic insulating material onto the display area DA, widely spreading it, and then curing it.

[0438] In this case, the range in which the liquid organic insulating material spreads may be limited to a region surrounded by the one or more dams DM1 and DM2 .

[0439] However, when the amount of the liquid organic insulating material is greater than a critical amount corresponding to the width of a region surrounded by the one or more dams DM1 and DM2 , the liquid organic insulating material may exceed the one or more dams DM1 and DM2 to overflow to the joint area JNA.

[0440] In this case, some of the organic insulating material RSD overflowing to the bonding area JNA may be received in a groove corresponding to the groove SGR of the first encapsulation layer 141. Therefore, some of the organic insulating material RSD overflowing to the bonding area JNA may be prevented from reaching the edge of the substrate 110.

[0441] Reference Fig. 22 In operation S430 of forming the third encapsulation layer 143 , the third encapsulation layer 143 covering the second encapsulation layer 142 may be formed by stacking an inorganic insulating material on the first encapsulation layer 141 .

[0442] In operation S430 of forming the third encapsulation layer 143 , the third encapsulation layer 143 may extend to the edge of the substrate 110 while completely overlapping one surface of the substrate 110 .

[0443] Thus, the encapsulation layer 140 may be formed (operation S40 ).

[0444] In operation S510 of forming the touch buffer layer 151 , the touch buffer layer 151 may be formed by stacking an inorganic insulating material on the third encapsulation layer 143 .

[0445] In operation S510 of forming the touch buffer layer 151 , the touch buffer layer 151 may extend to the edge of the substrate 110 while completely overlapping one surface of the substrate 110 .

[0446] In operation S520 of forming the first touch conductive layer, the first touch conductive layer including the bridge electrode BE may be formed by partially removing the conductive material layer on the touch buffer layer 151 .

[0447] In operation S530 of forming the touch interlayer insulating layer 152 , the touch interlayer insulating layer 152 covering the bridge electrode BE may be formed by stacking an inorganic insulating material on the touch buffer layer 151 .

[0448] In operation S530 of forming the touch interlayer insulating layer 152 , the touch interlayer insulating layer 152 may extend to the edge of the substrate 110 while completely overlapping one surface of the substrate 110 .

[0449] Reference Fig.23 In operation S540 of forming the second crack dam CRD2 , the second crack dam CRD2 and the touch contact hole TCNT may be formed by partially removing the third encapsulation layer 143 , the touch buffer layer 151 , and the touch interlayer insulating layer 152 positioned on the first encapsulation layer 141 .

[0450] The touch contact hole TCNT may penetrate the touch interlayer insulating layer 152 and reach the bridge electrode BE.

[0451] The second crack dam CRD2 may include side surfaces of the third encapsulation layer 143 , the touch buffer layer 151 , and the touch interlayer insulating layer 152 positioned on the first encapsulation layer 141 .

[0452] Due to the second crack dam CRD2 , the third encapsulation layer 143 , the touch buffer layer 151 , and the touch interlayer insulating layer 152 may extend to the third boundary area BNDA3 which is a remaining area except the second boundary area BNDA2 contacting the edge of the substrate 110 in the bonding area JNA.

[0453] According to some embodiments, the second crack dam CRD2 may be positioned between the edge of the substrate 110 and the groove SGR.

[0454] Meanwhile, in operation S540 of forming the second crack dam CRD2, the third encapsulation layer 143 or the touch buffer layer 151 may not be sufficiently exposed to the etching process due to the reduction in the intensity or processing time of the etching process. In this way, damage to the bridge electrode BE due to over-etching may be prevented or reduced.

[0455] For example, Fig.24 As shown in FIG. 1 , the second crack dam CRD2 may include a portion of a side surface of the third encapsulation layer 143, and side surfaces of the touch buffer layer 151 and the touch interlayer insulating layer 152. In this case, another portion of the third encapsulation layer 143 may remain in the second boundary area BNDA2.

[0456] For example, Fig.25 As shown in FIG. 1 , the second crack dam CRD2 may include a portion of a side surface of the touch buffer layer 151 and a side surface of the touch interlayer insulating layer 152. In this case, another portion of the touch buffer layer 151 and the third encapsulation layer 143 may remain in the second boundary area BNDA2.

[0457] like Fig.26 As shown in , according to some embodiments, the second crack dam CRD2 ′ may be positioned between the groove SGR and the first crack dam CRD1 , and may include side surfaces of the third encapsulation layer 143 , the touch buffer layer 151 , and the touch interlayer insulating layer 152 .

[0458] Alternatively, if Fig. 27 As shown in , due to the reduction in the intensity or processing time of the etching process, the second crack dam CRD2' may include a portion of the side surface of the third encapsulation layer 143, and the side surfaces of the touch buffer layer 151 and the touch interlayer insulating layer 152. In this case, another portion of the third encapsulation layer 143 may remain in the second boundary area BNDA2'.

[0459] Reference Fig.28In operation S550 of forming the second touch conductive layer, the second touch conductive layer including the driving electrode TE and the sensing electrode RE may be formed by partially removing the conductive material layer on the touch interlayer insulating layer 152 .

[0460] The driving electrode TE may be electrically connected to the bridge electrode BE through the touch contact hole TCNT.

[0461] In operation S560 of forming the touch planarization layer 153 , the touch planarization layer 153 covering the driving electrode TE and the sensing electrode RE may be formed by partially stacking an organic insulating material on the touch interlayer insulating layer 152 .

[0462] Thus, the touch sensor layer 150 may be formed (operation S50 ).

[0463] However, the effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate including a display area in which a plurality of emission areas are arranged and a non-display area around the display area; A circuit layer, wherein the circuit layer is located on the substrate; as well as a component layer, the component layer being located on the circuit layer, Wherein, the non-display area includes: a dam region in which at least one dam portion surrounding the display region is arranged and the dam region is spaced apart from the display region; and A bonding area, the bonding area is located between the edge of the substrate and the dam area, wherein the circuit layer includes: a barrier layer, the barrier layer being located on the substrate; a buffer layer, the buffer layer being located on the barrier layer; and two or more inorganic insulating layers, the two or more inorganic insulating layers being located on the buffer layer and comprising an inorganic insulating material, The display device further includes a groove located in a portion of the bonding region, spaced apart from the dam region and the edge of the substrate, and penetrating the barrier layer and the buffer layer.

2. The display device according to claim 1, wherein: The two or more inorganic insulating layers extend to a first boundary region in the bonding region that contacts the dam region, providing a first crack dam by side surfaces of the two or more inorganic insulating layers, and The first crack dam is spaced apart from the groove.

3. The display device according to claim 2, further comprising: A packaging layer, the packaging layer is located on the component layer; as well as a touch sensor layer, the touch sensor layer being located on the packaging layer, Wherein, the encapsulation layer comprises: a first encapsulation layer, the first encapsulation layer being located on the component layer and comprising an inorganic insulating material; a second encapsulation layer, the second encapsulation layer being located on the first encapsulation layer in the display area and comprising an organic insulating material; and a third encapsulation layer, the third encapsulation layer is located on the first encapsulation layer, covers the second encapsulation layer, and comprises an inorganic insulating material, Wherein, the touch sensor layer comprises: a touch buffer layer, the touch buffer layer being located on the third encapsulation layer and comprising an inorganic insulating material; and a touch interlayer insulating layer, the touch interlayer insulating layer being located on the touch buffer layer and comprising an inorganic insulating material, wherein the first encapsulation layer extends to the edge of the substrate and covers the at least one dam and the groove, The second encapsulation layer is located in a region surrounded by the at least one dam portion, The touch interlayer insulating layer extends to a third boundary region, the third boundary region being a remaining region of the bonding region except for a second boundary region contacting the edge of the substrate, and A second crack dam including a side surface of the touch interlayer insulating layer is provided.

4. The display device according to claim 3, wherein: The second crack dam is located between the edge of the substrate and the groove, and The touch interlayer insulating layer overlaps the groove.

5. The display device according to claim 3, wherein: The second crack dam is located between the groove and the first crack dam.

6. The display device according to claim 3, wherein: At least a portion of the touch buffer layer or at least a portion of the third encapsulation layer extends to the third boundary region, and The second crack dam also includes a side surface of the touch buffer layer or a side surface of the third encapsulation layer.

7. The display device according to claim 3, wherein: Some of the organic insulating material of the second encapsulation layer overflowing to the bonding region extends to a portion of the bonding region between the dam region and the groove and is accommodated on a portion of the first encapsulation layer overlapping the groove.

8. The display device according to claim 3, wherein: The substrate includes a main area including the display area and the non-display area and a sub-area protruding from one side of the main area, and The groove faces other sides of the edge of the main region except a side connected to the sub region.

9. The display device according to claim 3, wherein: The two or more inorganic insulating layers include: a first gate insulating layer, wherein the first gate insulating layer covers the first semiconductor layer on the buffer layer; a second gate insulating layer, wherein the second gate insulating layer covers the first gate conductive layer on the first gate insulating layer; a first interlayer insulating layer, wherein the first interlayer insulating layer covers the second gate conductive layer on the second gate insulating layer; a third gate insulating layer, the third gate insulating layer covering the second semiconductor layer on the first interlayer insulating layer; and A second interlayer insulating layer covers the third gate conductive layer on the third gate insulating layer.

10. The display device according to claim 9, wherein: The circuit layer further includes one or more planarization layers located on the second interlayer insulating layer and comprising an organic insulating material, The component layer includes: A plurality of anode electrodes, wherein the plurality of anode electrodes are respectively located in the plurality of emission regions; a pixel defining layer located in a non-emitting region between the plurality of emitting regions and covering an edge of each of the plurality of anode electrodes; a spacer layer, the spacer layer being located on a portion of the pixel defining layer; a plurality of light-emitting layers, wherein the plurality of light-emitting layers are respectively located on the plurality of anode electrodes; and a cathode electrode, the cathode electrode being located on the pixel defining layer, the spacer layer and the plurality of light emitting layers, wherein each of the at least one dam portion comprises two or more dam layers stacked sequentially, and Each of the two or more dam layers is the same layer as one of the one or more planarization layers, the pixel defining layer, and the spacer layer.

11. A method for manufacturing a display device, comprising: providing a substrate including a display area where a plurality of emission areas are arranged and a non-display area around the display area; as well as forming a circuit layer on the substrate, Wherein, the non-display area includes: a dam area spaced apart from the display area and surrounding the display area; and A bonding area, the bonding area is located between the edge of the substrate and the dam area, wherein forming the circuit layer includes: forming a barrier layer by stacking an inorganic insulating material on the substrate; forming a buffer layer by stacking an inorganic insulating material on the barrier layer; and forming a groove by partially removing the barrier layer and the buffer layer, The groove is located in a portion of the bonding area and is spaced apart from the dam area and the edge of the substrate.

12. The method for manufacturing a display device according to claim 11, wherein: The bonding region further includes a first boundary region in contact with the dam region and a second boundary region in contact with the edge of the substrate, Wherein, forming the circuit layer further comprises: Before forming the groove, forming a first semiconductor layer on the buffer layer; forming a first gate insulating layer covering the first semiconductor layer by stacking an inorganic insulating material on the buffer layer; forming a first gate conductive layer on the first gate insulating layer; forming a second gate insulating layer covering the first gate conductive layer by stacking an inorganic insulating material on the first gate insulating layer; forming a second gate conductive layer on the second gate insulating layer; forming a first interlayer insulating layer covering the second gate conductive layer by stacking an inorganic insulating material on the second gate insulating layer; forming a second semiconductor layer on the first interlayer insulating layer; forming a third gate insulating layer covering the second semiconductor layer by stacking an inorganic insulating material on the first interlayer insulating layer; forming a third gate conductive layer on the third gate insulating layer; forming a second interlayer insulating layer covering the third gate conductive layer by stacking an inorganic insulating material on the third gate insulating layer; and forming a first crack dam including side surfaces of the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer by partially removing the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, wherein, after forming the first crack dam, the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer extend to the first boundary region, and The first crack dam is spaced apart from the groove.

13. The method for manufacturing a display device according to claim 12, further comprising: After forming the circuit layer, forming a component layer on the circuit layer; forming a packaging layer on the component layer; as well as forming a touch sensor layer on the packaging layer, Wherein, forming the encapsulation layer comprises: forming a first encapsulation layer comprising an inorganic insulating material on the element layer; forming a second encapsulation layer including an organic insulating material on the first encapsulation layer; and forming a third encapsulation layer on the first encapsulation layer and covering the second encapsulation layer and comprising an inorganic insulating material, Wherein, forming the touch sensor layer comprises: forming a touch buffer layer by stacking an inorganic insulating material on the third encapsulation layer; forming a first touch conductive layer on the touch buffer layer; forming a touch interlayer insulating layer covering the first touch conductive layer by stacking an inorganic insulating material on the touch buffer layer; forming a second crack dam including a side surface of the touch interlayer insulating layer by partially removing the touch interlayer insulating layer; forming a second touch conductive layer on the touch interlayer insulating layer; and forming a touch planarization layer covering the second touch conductive layer by stacking an organic insulating material on the touch interlayer insulating layer, After the second crack dam is formed, the touch interlayer insulating layer extends to a third boundary region, and the third boundary region is a remaining region of the bonding region except the second boundary region.

14. The method for manufacturing a display device according to claim 13, wherein: The second crack dam is located between the edge of the substrate and the groove, and The touch interlayer insulating layer overlaps the groove.

15. The method for manufacturing a display device according to claim 13, wherein: The second crack dam is located between the groove and the first crack dam.

16. The method for manufacturing a display device according to claim 13, wherein: When forming the second crack dam, the touch buffer layer or the third encapsulation layer is partially removed, At least a portion of the touch buffer layer or at least a portion of the third encapsulation layer extends to the third boundary region, and The second crack dam also includes a side surface of the touch buffer layer or a side surface of the third encapsulation layer.

17. The method for manufacturing a display device according to claim 13, wherein: After the element layer is formed, at least one dam portion surrounding the display area is located in the dam area, forming the second encapsulation layer includes a process of dropping a liquid organic insulating material on the first encapsulation layer, a process of spreading the liquid organic insulating material into a region surrounded by the at least one dam, and a process of curing the liquid organic insulating material, and In the process of spreading the liquid organic insulating material, some of the liquid organic insulating material overflowing into the bonding area spreads into a portion of the bonding area between the dam area and the groove and is accommodated on a portion of the first encapsulation layer overlapping the groove.

18. The method for manufacturing a display device according to claim 13, wherein: When providing the substrate, the substrate includes a main area including the display area and the non-display area and a sub-area protruding from one side of the main area, and When the groove is formed, the groove faces the other sides of the edge of the main region except for the side connected to the sub region.

19. The method for manufacturing a display device according to claim 13, wherein: When forming the first crack dam, a plurality of first contact holes are also formed. When forming the groove, a plurality of second contact holes are also formed. Each of the plurality of first contact holes reaches one of the first semiconductor layer, the first gate conductive layer, and the second gate conductive layer, and Each of the plurality of second contact holes reaches one of the second semiconductor layer and the third gate conductive layer.

20. The method for manufacturing a display device according to claim 19, wherein: Forming the circuit layer further includes: After forming the groove, forming a first source-drain conductive layer on the second interlayer insulating layer; forming a first planarization layer covering the first source-drain conductive layer by stacking an organic insulating material on the second interlayer insulating layer; forming a second source-drain conductive layer on the first planarization layer; and forming a second planarization layer covering the second source-drain conductive layer by stacking an organic insulating material on the first planarization layer, Wherein, forming the component layer comprises: forming a plurality of anode electrodes in the plurality of emission regions; forming a pixel defining layer covering edges of the plurality of anode electrodes in a non-emitting region between the plurality of emitting regions, and forming a spacer layer on a portion of the pixel defining layer; forming a plurality of light emitting layers on the plurality of anode electrodes; and forming a cathode electrode on the pixel defining layer, the spacer layer and the plurality of light emitting layers, wherein each of the at least one dam portion comprises two or more dam layers stacked sequentially, and Each of the two or more dam layers is the same layer as one of the first planarization layer, the second planarization layer, the pixel defining layer, and the spacer layer.

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