Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes an inorganic insulating layer disposed on a substrate, a hydrogen supply layer disposed on the inorganic insulating layer, a pixel electrode contacting the hydrogen supply layer, and an interlayer receiving hydrogen ions from the hydrogen supply layer and disposed on the pixel electrode.

Description

Technical Field

[0001] Embodiments relate to a display device providing visual information and a method of manufacturing the display device. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has gradually emerged. Accordingly, the use of display devices (such as liquid crystal display devices, organic light emitting display devices, plasma display devices, and quantum dot light emitting display devices) is increasing.

[0003] A quantum dot light-emitting display device is a display device that uses quantum dots as light emitters. A quantum dot light-emitting display device has the advantages of high chromaticity and the ability to produce a variety of colors. Recently, there has been a need for a method of improving the light-emitting efficiency of a quantum dot light-emitting display device. Summary of the invention

[0004] Embodiments provide a display device with improved display quality.

[0005] Embodiments provide a method of manufacturing a display device.

[0006] A display device according to an embodiment may include an inorganic insulating layer disposed on a substrate, a hydrogen supply layer disposed on the inorganic insulating layer, a pixel electrode contacting the hydrogen supply layer; and an interlayer receiving hydrogen ions from the hydrogen supply layer and disposed on the pixel electrode.

[0007] In an embodiment, the display device may further include an organic insulating layer disposed on the inorganic insulating layer. The hydrogen supply layer may be disposed on the organic insulating layer.

[0008] In an embodiment, an upper surface of the hydrogen supply layer may contact the pixel electrode.

[0009] In an embodiment, the hydrogen supply layer may cover an upper surface of the organic insulating layer and a side surface of the organic insulating layer.

[0010] In an embodiment, the organic insulating layer may include a first opening penetrating the organic insulating layer, and the hydrogen supply layer may include a second opening overlapping the first opening in a plan view.

[0011] In an embodiment, the hydrogen supply layer may cover the organic insulating layer in the first opening.

[0012] In an embodiment, the display device may further include an organic insulating layer disposed on the inorganic insulating layer. The hydrogen supply layer may be disposed between the inorganic insulating layer and the organic insulating layer.

[0013] In an embodiment, the hydrogen supply layer may contact each of the inorganic insulating layer and the organic insulating layer.

[0014] In an embodiment, the organic insulating layer may include a first opening, and the hydrogen supply layer may include a second opening overlapping the first opening in a plan view.

[0015] In an embodiment, a portion of the hydrogen supply layer may contact the pixel electrode through the first opening.

[0016] In an embodiment, the display device may further include a common electrode disposed on the interlayer. The interlayer may include a light emitting layer and an electron auxiliary layer supplying electrons to the light emitting layer.

[0017] In an embodiment, the light emitting layer may include quantum dots, and the electron assisting layer may include a metal oxide.

[0018] In an embodiment, the electron assist layer may include at least one of zinc oxide and zinc manganese oxide.

[0019] In an embodiment, the hydrogen supply layer may include silicon nitride.

[0020] In an embodiment, the hydrogen supply layer may include silicon oxide.

[0021] In an embodiment, the hydrogen supply layer may include amorphous silicon.

[0022] A method of manufacturing a display device according to an embodiment may include forming an inorganic insulating layer on a substrate, forming a hydrogen supply layer on the inorganic insulating layer, forming a pixel electrode contacting the hydrogen supply layer on the hydrogen supply layer, and forming an interlayer receiving hydrogen ions from the hydrogen supply layer on the pixel electrode.

[0023] In an embodiment, the method may further include forming a preliminary organic insulating layer on the inorganic insulating layer, forming an organic insulating layer including a first opening by etching a portion of the preliminary organic insulating layer, forming a preliminary hydrogen supply layer on the organic insulating layer covering the organic insulating layer in the first opening, and forming a hydrogen supply layer including a second opening corresponding to the first opening by etching a portion of the preliminary hydrogen supply layer.

[0024] In an embodiment, the method may further include forming a preliminary hydrogen supply layer on the inorganic insulating layer, forming a preliminary organic insulating layer on the preliminary hydrogen supply layer, forming an organic insulating layer including a first opening by etching a portion of the preliminary organic insulating layer, and forming a hydrogen supply layer including a second opening corresponding to the first opening by etching a portion of the preliminary hydrogen supply layer.

[0025] In an embodiment, the method may further include performing a hydrogen plasma treatment on at least a portion of the hydrogen supply layer before forming the pixel electrode.

[0026] In a display device according to an embodiment of the present disclosure, a light-emitting layer included in the display device may include quantum dots, and accordingly, defects may be generated in a metal material included in an interlayer. In order to reduce defects generated in the metal material, a positive aging process may be performed in which a material including an acid is applied to the interlayer. Meanwhile, during the positive aging process, other side effects may be generated in the interlayer.

[0027] Accordingly, in order to reduce defects generated in the interlayer, the display device according to the present disclosure may include a hydrogen supply layer. Accordingly, hydrogen ions generated in the hydrogen supply layer can be supplied to the interlayer by diffusion. Therefore, hydrogen ions can be supplied to the metal material to reduce defects without the side effects of the positive aging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 A plan view for explaining a display device according to an embodiment of the present disclosure.

[0030] Figure 2 for Figure 1 Schematic diagram of an equivalent circuit of a first sub-pixel included in a display device in .

[0031] Figure 3 To explain along Figure 1 Schematic cross-sectional view of a display device according to an embodiment taken along line II'.

[0032] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 To explain the manufacturing Figure 1 Schematic cross-sectional view of a method for displaying a device in FIG.

[0033] Fig.15 To explain along Figure 1 Schematic cross-sectional view of a display device according to an embodiment taken along line II'.

[0034] Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 To explain the manufacturing Fig.15Schematic cross-sectional view of a method for displaying a device in FIG.

[0035] Fig.23 To explain along Figure 1 Schematic cross-sectional view of a display device according to an embodiment taken along line II'.

[0036] Fig.24 To explain along Figure 1 Schematic cross-sectional view of a display device according to an embodiment taken along line II'. DETAILED DESCRIPTION

[0037] Hereinafter, a display device and method according to an embodiment will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0038] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to another element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. Also, when an element is referred to as being "in contact" or "contacted" with another element, the element may be "electrically in contact" or "physically in contact" with the other element; or "indirectly in contact" or "directly in contact" with the other element.

[0039] As used herein, "about" or "approximately" is inclusive of the recited value and means within an acceptable range of deviation as determined for the particular value by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the recited value, or within ±30%, ±20%, ±10%, or ±5% of the recited value.

[0040] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0041] Spatially relative terms, such as "below," "beneath," "below," "above," "above," "high," and "side" (e.g., as in "sidewall"), etc., may be used herein for descriptive purposes and thereby describe the relationship of one element to another element as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is turned over, an element described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both orientations of above and below. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and, as such, the spatially relative descriptors used herein are interpreted accordingly.

[0042] The terms used in this article are used for the purpose of describing specific embodiments and are not intended to be limiting. As used in this article, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. Moreover, the terms "comprises", "comprising", "includes", and / or "including", when used in this specification, indicate the presence of the described features, integers, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0043] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the following group:...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B". In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a connecting sense or a separating sense, and may be understood to be equivalent to "and / or".

[0044] Unless otherwise defined or implied herein, all terms (including technical terms and scientific terms) used have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an ideal or overly formal sense unless clearly defined in the specification.

[0045] Figure 1 A plan view for explaining a display device DD according to an embodiment of the present disclosure.

[0046] refer to Figure 1 , the display device DD according to an embodiment of the present disclosure may include a display area DA and a non-display area NDA. The display area DA may be a region where an image is generated, and the non-display area NDA may be a region where an image is not generated.

[0047] At least one pixel PX may be disposed in the display area DA. The pixel PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 may emit a first light, the second sub-pixel SPX2 may emit a second light, and the third sub-pixel SPX3 may emit a third light. In an embodiment, the first light may be red light, the second light may be green light, and the third light may be blue light. However, the present disclosure is not limited thereto. For example, the first to third sub-pixels SPX1, SPX2, and SPX3 may emit yellow light, cyan light, and magenta light, respectively.

[0048] In a plan view, the first to third sub-pixels SPX1, SPX2, and SPX3 may be repeatedly arranged in a first direction DR1 and in a second direction DR2 intersecting the first direction DR1. For example, in the second direction DR2, the second sub-pixel SPX2 may be adjacent to the first sub-pixel SPX1. In the second direction DR2, the third sub-pixel SPX3 may be adjacent to the second sub-pixel SPX2.

[0049] The non-display area NDA may be adjacent to the display area DA. For example, the non-display area NDA may surround at least one side of the display area DA. A driver may be disposed in the non-display area NDA. The driver may supply a signal or voltage to the pixel PX. For example, the driver may include a data driver and a gate driver, etc.

[0050] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2. For example, the second direction DR2 may be perpendicular to the first direction DR1. The third direction DR3 may be perpendicular to the plane.

[0051] Figure 2 for Figure 1 Schematic diagram of an equivalent circuit of a first sub-pixel SPX1 included in a display device DD in FIG.

[0052] refer to Figure 2 , the first sub-pixel SPX1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor CAP, and a light emitting element EL.

[0053] The first transistor T1 may be connected between the first node N1 and the second node N2. The first transistor T1 may include a source electrode connected to the first node N1, a drain electrode connected to the second node N2, and a gate electrode connected to a third node N3.

[0054] The second transistor T2 may be connected between the first node N1 and the data line. The second transistor T2 may include a source electrode configured to receive the data voltage DV, a drain electrode connected to the first node N1, and a gate electrode configured to receive the first gate signal GS1.

[0055] The third transistor T3 may be connected between the second node N2 and the third node N3. The third transistor T3 may include a source electrode connected to the third node N3, a drain electrode connected to the second node N2, and a gate electrode configured to receive the first gate signal GS1.

[0056] The fourth transistor T4 may be connected between the initialization voltage line and the third node N3. The fourth transistor T4 may include a source electrode configured to receive the initialization voltage VINT, a drain electrode connected to the third node N3, and a gate electrode configured to receive the second gate signal GS2.

[0057] The fifth transistor T5 may be connected between a first power source configured to supply a high power voltage ELVDD and the first node N1. The fifth transistor T5 may include a source electrode configured to receive the high power voltage ELVDD, a drain electrode connected to the first node N1, and a gate electrode configured to receive the light control signal EM.

[0058] The sixth transistor T6 may be connected between the second node N2 and the fourth node N4. The sixth transistor T6 may include a source electrode connected to the second node N2, a drain electrode connected to the fourth node N4, and a gate electrode configured to receive the light control signal EM.

[0059] The seventh transistor T7 may be connected between the initialization voltage line and the fourth node N4. The seventh transistor T7 may include a source electrode configured to receive the initialization voltage VINT, a drain electrode connected to the fourth node N4, and a gate electrode configured to receive the second gate signal GS2.

[0060] The capacitor CAP may be connected between the first power source and the third node N3. The capacitor CAP may include a first capacitor electrode connected to the third node N3 and a second capacitor electrode configured to receive the high power source voltage ELVDD.

[0061] The light emitting element EL may be connected between the fourth node N4 and a second power source configured to supply a low power voltage ELVSS. The voltage level of the low power voltage ELVSS may be lower than the voltage level of the high power voltage ELVDD. The light emitting element EL may include a first electrode connected to the fourth node N4 and a second electrode configured to receive the low power voltage ELVSS.

[0062] In an embodiment, each of the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 may be a PMOS transistor. However, the present disclosure is not limited thereto, and in another embodiment, at least one of the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 may be an NMOS transistor.

[0063] Figure 2 It is explained that the first subpixel SPX1 includes seven transistors and one capacitor, however, the present disclosure is not limited thereto. For example, the first subpixel SPX1 may include two to six or eight or more transistors and two or more capacitors.

[0064] Each of the second subpixel SPX2 and the third subpixel SPX3 may have a circuit structure substantially identical to that of the first subpixel SPX1 .

[0065] Figure 3 To explain along Figure 1 Schematic cross-sectional view of a display device according to an embodiment taken along line II'.

[0066] refer to Figure 3 , the display device DD according to the embodiment of the present disclosure may include a substrate SUB, a bottom light blocking layer BML, a buffer layer 102, an active layer ACT, a first gate insulating layer 104, a gate electrode GE, a second gate insulating layer 106, a third gate insulating layer 108, a source electrode SE, a drain electrode DE, an organic insulating layer 120, a hydrogen supply layer 200, a pixel electrode PE, a pixel defining layer PDL, first to third hole auxiliary layers HTL1, HTL2 and HTL3, first to third light emitting layers EML1, EML2 and EML3, first to third electron auxiliary layers ETL1, ETL2 and ETL3, a common electrode CE, and an encapsulation layer TFE. The first to third light emitting layers EML1, EML2 and EML3 may include first to third quantum dots QD1, QD2 and QD3, respectively, and the first to third electron auxiliary layers ETL1, ETL2 and ETL3 may include first to third nanoparticles NP1, NP2 and NP3, respectively. The first to third light emitting layers EML1, EML2, and EML3 may correspond to Figure 1 The first to third sub-pixels SPX1, SPX2 and SPX3 in.

[0067] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may be a transparent resin substrate. Examples of transparent resin substrates may include polyimide substrates. For example, the substrate SUB may include a first organic layer, a first isolation layer, and a second organic layer, etc. In another embodiment, the substrate SUB may be a quartz substrate (e.g., a synthetic quartz substrate), a calcium fluoride substrate, or an alkali-free glass substrate, etc. These may be used alone or in combination with each other.

[0068] The bottom light blocking layer BML may be disposed on the substrate SUB. The bottom light blocking layer BML may block external light or light from a light emitting element (eg, Figure 2 The bottom light blocking layer BML may include a metal material. For example, the bottom light blocking layer BML may include silver (Ag), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), or neodymium (Nd). These may be used alone or in combination with each other.

[0069] The buffer layer 102 may be disposed on the bottom light blocking layer BML. The buffer layer 102 may prevent impurities from the substrate SUB from diffusing into the active layer ACT. The buffer layer 102 may include an inorganic insulating material. For example, the buffer layer 102 may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0070] The active layer ACT may be disposed on the buffer layer 102. The active layer ACT may be disposed to correspond to each of the first to third sub-pixels SPX1, SPX2, and SPX3. In a plan view, the active layer ACT may overlap with the bottom light blocking layer BML. Since the active layer ACT overlaps with the bottom light blocking layer BML, photocurrent may be prevented from being generated in the active layer ACT.

[0071] In an embodiment, the active layer ACT may include an oxide semiconductor, amorphous silicon, or polycrystalline silicon. For example, the oxide semiconductor may include zinc (Zn) oxide, indium zinc (In-Zn) oxide, gallium indium zinc (Ga-In-Zn) oxide, etc. These may be used alone or in combination with each other.

[0072] The active layer ACT may include a source region and a drain region doped with impurities, and a channel region disposed between the source region and the drain region.

[0073] The first gate insulating layer 104 may be disposed on the buffer layer 102. The first gate insulating layer 104 may cover the active layer ACT on the buffer layer 102. For example, along the contour of the active layer ACT, the first gate insulating layer 104 may have a substantially uniform thickness. In another embodiment, the first gate insulating layer 104 may fully cover the active layer ACT and may have a substantially flat upper surface without generating a step on the active layer ACT.

[0074] The first gate insulating layer 104 may include an inorganic insulating material. For example, the first gate insulating layer 104 may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0075] The gate electrode GE may be disposed on the first gate insulating layer 104. In a plan view, the gate electrode GE may overlap with the channel region of the active layer ACT. The gate electrode GE may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or copper (Cu), etc. These may be used alone or in combination with each other.

[0076] The second gate insulating layer 106 may be disposed on the first gate insulating layer 104. The second gate insulating layer 106 may cover the gate electrode GE. For example, along the contour of the gate electrode GE, the second gate insulating layer 106 may have a substantially uniform thickness. In another embodiment, the second gate insulating layer 106 may fully cover the gate electrode GE and may have a substantially flat upper surface without generating a step on the gate electrode GE.

[0077] The second gate insulating layer 106 may include an inorganic insulating material. For example, the second gate insulating layer 106 may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0078] The third gate insulating layer 108 may be disposed on the second gate insulating layer 106. The third gate insulating layer 108 may include an inorganic insulating material. For example, the third gate insulating layer 108 may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0079] The source electrode SE and the gate electrode GE may be disposed on the third gate insulating layer 108. Each of the source electrode SE and the gate electrode GE may be connected to the active layer ACT by penetrating the first gate insulating layer 104, the second gate insulating layer 106, and the third gate insulating layer 108. The source electrode SE and the gate electrode GE may be connected to the source region and the drain region, respectively. Figure 3 , but the source electrode SE and the gate electrode GE may be connected to the bottom light blocking layer BML by penetrating the first gate insulating layer 104 , the second gate insulating layer 106 , the third gate insulating layer 108 , the active layer ACT, and the buffer layer 102 .

[0080] The source electrode SE and the drain electrode DE may include metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive material, etc. These may be used alone or in combination with each other.

[0081] Accordingly, the active layer ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may form a transistor. The transistor may correspond to Figure 2 Any one of the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7.

[0082] In this specification, the inorganic insulating layer 100 may be defined as including a buffer layer 102 , a first gate insulating layer 104 , a second gate insulating layer 106 , and a third gate insulating layer 108 .

[0083] The organic insulating layer 120 may be disposed on the inorganic insulating layer 100. The organic insulating layer 120 may include an organic insulating material such as polyimide (PI).

[0084] The first opening OP1 may be defined in the organic insulating layer 120. The first opening OP1 may penetrate the organic insulating layer 120. For example, a portion of the drain electrode DE may be exposed through the first opening OP1 of the organic insulating layer 120. In another embodiment, a portion of the source electrode SE may be exposed through the first opening OP1.

[0085] The hydrogen supply layer 200 may be disposed on the organic insulating layer 120. The hydrogen supply layer 200 may supply hydrogen ions to the interlayer ML disposed on an upper portion of the hydrogen supply layer 200. For example, the hydrogen ions may diffuse from the hydrogen supply layer 200 to the interlayer ML.

[0086] In an embodiment, the hydrogen supply layer 200 may cover the upper and side surfaces of the organic insulation layer 120. For example, the hydrogen supply layer 200 may cover the contour of each of the upper and side surfaces of the organic insulation layer 120 in which the first opening OP1 is defined with a substantially uniform thickness.

[0087] The second opening OP2 may be defined in the hydrogen supply layer 200. In a plan view, the second opening OP2 may overlap with the first opening OP1. For example, the second opening OP2 may form one hole by being connected to the first opening OP1 in the third direction DR3. A portion of the transistor may be exposed through the first opening OP1 and the second opening OP2.

[0088] In an embodiment, the hydrogen supply layer 200 may include silicon nitride (SiN x ). From silicon nitride (SiN x ) may diffuse into the interlayer ML disposed on the upper portion of the hydrogen supply layer 200. Specifically, during the process of depositing the hydrogen supply layer 200, hydrogen gas may be used so that hydrogen may be coupled to the silicon nitride (SiN x ) on the surface of the hydrogen supply layer 200. Accordingly, the hydrogen supply layer 200 may generate hydrogen ions. In order to increase the amount of hydrogen ions generated in the hydrogen supply layer 200, the silicon nitride (SiN) may be treated with hydrogen plasma. x ) of the hydrogen supply layer 200.

[0089] In another embodiment, the hydrogen supply layer 200 may include amorphous silicon. Hydrogen ions may be generated from dangling bonds in the amorphous silicon. Accordingly, the hydrogen ions generated from the amorphous silicon may diffuse into the interlayer ML. Specifically, during the process of depositing the hydrogen supply layer 200, hydrogen gas may be used so that hydrogen may be coupled to the surface of the hydrogen supply layer 200 including amorphous silicon and hydrogen may form dangling bonds with the amorphous silicon. Accordingly, the hydrogen supply layer 200 may generate hydrogen ions. In order to increase the amount of hydrogen ions generated in the hydrogen supply layer 200, the hydrogen supply layer 200 including amorphous silicon may be treated with hydrogen plasma treatment.

[0090] In yet another embodiment, the hydrogen supply layer 200 may include silicon oxide (SiO x ). From silicon oxide (SiO x ) may diffuse into the interlayer ML disposed on the upper portion of the hydrogen supply layer 200. Specifically, during the process of depositing the hydrogen supply layer 200, hydrogen gas may be used so that hydrogen may be coupled to the silicon oxide (SiO x ) on the surface of the hydrogen supply layer 200. Accordingly, the hydrogen supply layer 200 may generate hydrogen ions. In order to increase the amount of hydrogen ions generated in the hydrogen supply layer 200, the silicon oxide (SiO x ) of the hydrogen supply layer 200.

[0091] The pixel electrode PE may be disposed on the hydrogen supply layer 200. For example, the pixel electrode PE may contact the hydrogen supply layer 200. In an embodiment, an upper surface of the hydrogen supply layer 200 in the third direction DR3 may contact the pixel electrode PE.

[0092] The pixel electrode PE may be arranged to correspond to Figure 1 The first to third sub-pixels SPX1, SPX2 and SPX3 in.

[0093] For example, the pixel electrode PE may contact the drain electrode DE through the first opening OP1 and the second opening OP2. In another embodiment, the pixel electrode PE may contact the source electrode SE through the first opening OP1 and the second opening OP2.

[0094] At least a portion of the pixel electrode PE may contact (eg, directly contact) the hydrogen supply layer 200. At least a portion of the upper surface of the pixel electrode PE may contact (eg, directly contact) the hole auxiliary layer HTL. As described above, the surface opposite to the upper surface of the pixel electrode PE may contact the hydrogen supply layer 200.

[0095] In an implementation, the pixel electrode PE may serve as an anode. The pixel electrode PE may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. These may be used alone or in combination with each other.

[0096] Each of the first to third hole auxiliary layers HTL1, HTL2 and HTL3 may be disposed on the pixel electrode PE. For example, each of the first to third hole auxiliary layers HTL1, HTL2 and HTL3 may include a hole injection layer and / or a hole transport layer. However, the present disclosure is not limited thereto. For example, each of the first to third hole auxiliary layers HTL1, HTL2 and HTL3 may further include a buffer layer and / or an electron blocking layer. The buffer layer may be used to increase the luminous efficiency by compensating the optical resonance distance depending on the wavelength of light emitted from the first to third light emitting layers EML1, EML2 and EML3. The electron blocking layer may be used to prevent the injection of electrons from the first to third electron auxiliary layers ETL1, ETL2 and ETL3. In the present specification, the hole auxiliary layer HTL may be at least one of the first to third hole auxiliary layers HTL1, HTL2 and HTL3.

[0097] Each of the first to third light-emitting layers EML1, EML2, and EML3 may be disposed on the first to third hole auxiliary layers HTL1, HTL2, and HTL3. The first to third light-emitting layers EML1, EML2, and EML3 may include first to third quantum dots QD1, QD2, and QD3, respectively. By adjusting the composition and / or size of the first to third quantum dots QD1, QD2, and QD3, the emission wavelengths of the first to third quantum dots QD1, QD2, and QD3 may be adjusted. In the present specification, the light-emitting layer EML may be at least one of the first to third light-emitting layers EML1, EML2, and EML3.

[0098] In one embodiment, each of the first to third quantum dots QD1, QD2 and QD3 may include a II-VI group compound, a III-V group compound, an IV-VI group compound, and a group IV element or a group IV compound, etc. These may be used alone or in combination with each other. For example, the II-VI group compound may include CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS and HgSe, etc. The III-V group compound may include GaN, GaP, GaAs, GaSb, AlN and AlP, etc. The IV-VI group compound may include SnS, SnSe, SnTe, PbS and PbSe, etc. The IV group element may include Si and Ge, etc. The IV group compound may include SiC and SiGe, etc.

[0099] Each of the first to third electron auxiliary layers ETL1, ETL2 and ETL3 may be disposed on the first to third light-emitting layers EML1, EML2 and EML3. Each of the first to third electron auxiliary layers ETL1, ETL2 and ETL3 may include an electron transport layer and / or an electron injection layer. However, the present disclosure is not limited thereto. For example, each of the first to third electron auxiliary layers ETL1, ETL2 and ETL3 may further include a hole blocking layer. The hole blocking layer may be used to prevent the injection of holes from the first to third hole auxiliary layers HTL1, HTL2 and HTL3. In the present specification, the electron auxiliary layer ETL may be at least one of the first to third electron auxiliary layers ETL1, ETL2 and ETL3.

[0100] In an embodiment, the first to third electron auxiliary layers ETL1, ETL2 and ETL3 may include first to third nanoparticles NP1, NP2 and NP3, respectively. In an embodiment, each of the first to third nanoparticles NP1, NP2 and NP3 may include a metal oxide. For example, each of the first to third nanoparticles NP1, NP2 and NP3 may include zinc oxide (ZnO) or zinc magnesium oxide (ZnMgO), etc. These may be used alone or in combination with each other.

[0101] The pixel defining layer PDL may be disposed on the pixel electrode PE. For example, an opening in which the first to third light emitting layers EML1, EML2, and EML3 are disposed may be formed in the pixel defining layer PDL. The pixel defining layer PDL may include an organic material and / or an inorganic material. For example, the pixel defining layer PDL may include a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, or an epoxy resin, etc. These may be used alone or in combination with each other.

[0102] The interlayer ML may include an electron assisting layer ETL, a light emitting layer EML, and a hole assisting layer HTL. The interlayer ML may receive hydrogen ions from the hydrogen supply layer 200.

[0103] The common electrode CE may be disposed on the first to third electron auxiliary layers ETL1, ETL2, and ETL3 and the pixel defining layer PDL. The common electrode CE may be continuously disposed throughout the first to third sub-pixels SPX1, SPX2, and SPX3. However, the present disclosure is not limited thereto, and in another embodiment, the common electrode CE may cover a portion of each of the first to third electron auxiliary layers ETL1, ETL2, and ETL3.

[0104] The common electrode CE may include metal, alloy, metal nitride, conductive metal oxide or transparent conductive material, etc. These may be used alone or in combination with each other. For example, the common electrode CE may serve as a cathode.

[0105] The encapsulation layer TFE may be disposed on the common electrode CE. The encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the inorganic encapsulation layer may include silicon oxide, silicon nitride, silicon oxynitride, etc., and the organic encapsulation layer may include a cured polymer (eg, polyacrylate).

[0106] Because the display device (e.g. Figure 1 The display device DD in FIG. 1 includes quantum dots in the light emitting layer EML, so defects may be generated in the metal material included in the interlayer ML (e.g., the electron auxiliary layer ETL included in the interlayer ML). In order to reduce the defects generated in the metal material, a positive aging process in which a material containing an acid is applied to the interlayer ML may be performed. During the positive aging process, other side effects may be generated in the interlayer ML.

[0107] Accordingly, in order to reduce defects generated in the interlayer ML, the display device DD according to an embodiment of the present disclosure may include a hydrogen supply layer 200. Since the display device DD includes the hydrogen supply layer 200, hydrogen ions generated in the hydrogen supply layer 200 may be supplied to the interlayer ML by diffusion. Hydrogen ions may be supplied to the metal material to reduce defects without the side effect of positive aging.

[0108] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 To explain the manufacturing Figure 1Schematic cross-sectional view of a method for displaying a display device DD in FIG. Figure 3 Those described are repeated descriptions.

[0109] refer to Figure 4 , the bottom light blocking layer BML, the buffer layer 102, the active layer ACT and the first gate insulating layer 104 may be formed on the substrate SUB in the order described.

[0110] refer to Figure 5 and Figure 6 , the gate electrode GE, the second gate insulating layer 106, and the third gate insulating layer 108 may be formed on the first gate insulating layer 104 in the order described. A portion of each of the first to third gate insulating layers 104, 106, and 108 that overlaps with the end of the active layer ACT may be removed by an etching process. For example, a through hole that penetrates a portion of each of the first to third gate insulating layers 104, 106, and 108 may be formed by an etching process. For example, in a plan view, the through hole may overlap with the source region and the drain region of the active layer ACT.

[0111] refer to Figure 7 , a source electrode SE and a drain electrode DE may be formed on the third gate insulating layer 108. The through hole may be filled with the source electrode SE and the drain electrode DE. For example, the source electrode SE may contact the source region through the through hole, and the drain electrode DE may contact the drain region through the through hole.

[0112] refer to Figure 8 , the preliminary organic insulating layer 120a may be formed on the inorganic insulating layer 100. For example, the preliminary organic insulating layer 120a may cover the third gate insulating layer 108. The upper portion of the preliminary organic insulating layer 120a may have a substantially flat surface. The preliminary organic insulating layer 120a and the organic insulating layer 120 (see, Figure 3 ) may include the same material. For example, the preliminary organic insulating layer 120a may be formed using an organic insulating material such as polyimide (PI).

[0113] refer to Fig. 9 , a portion of the preliminary organic insulating layer 120a may be removed by an etching process. For example, a portion of the preliminary organic insulating layer 120a may be etched to form an organic insulating layer 120 in which the first opening OP1 is defined. For example, a first opening OP1 may be defined in the organic insulating layer 120 in the thickness direction (eg, the third direction DR3 (see, Figure 3 )) is a first opening OP1 that penetrates a portion of the organic insulating layer 120. The first opening OP1 may be widened from a lower portion to an upper portion of the organic insulating layer 120. However, the present disclosure is not limited thereto, and the organic insulating layer 120 in which the first opening OP1 is defined may have various shapes.

[0114] The first opening OP1 can be used to separate the transistor and the interlayer ML (see, Figure 3 ) is electrically connected to the through hole. Accordingly, a portion of the drain electrode DE may be exposed through the first opening OP1. In another embodiment, a portion of the source electrode SE may be exposed through the first opening OP1.

[0115] refer to Fig.10 , the preliminary hydrogen supply layer 200a may be formed on the organic insulating layer 120. For example, the preliminary hydrogen supply layer 200a may cover the first opening OP1. For example, the preliminary hydrogen supply layer 200a may cover the drain electrode DE exposed through the first opening OP1.

[0116] The preliminary hydrogen supply layer 200a and the hydrogen supply layer 200 (see, Figure 3 ) may include the same material. For example, the preliminary hydrogen supply layer 200a may include an inorganic material. Along the contour of the organic insulating layer 120, the preliminary hydrogen supply layer 200a may have substantially the same thickness.

[0117] refer to Fig.11 , the preliminary hydrogen supply layer 200a may be removed by an etching process (see, Fig.10 ). A portion of the preliminary hydrogen supply layer 200a may be etched to form the hydrogen supply layer 200 in which the second opening OP2 is defined. For example, the hydrogen supply layer 200a may be defined in the thickness direction (eg, the third direction DR3 (see, Figure 3 )) has a second opening OP2 that penetrates a portion of the hydrogen supply layer 200.

[0118] A portion of the drain electrode DE may be exposed through the second opening OP2. In another embodiment, a portion of the source electrode SE may be exposed through the second opening OP2. The second opening OP2 may be a through hole overlapping the first opening OP1 to connect the transistor and the interlayer ML.

[0119] In an embodiment, the second opening OP2 may be positioned to correspond to the first opening OP1. For example, in a plan view, the second opening OP2 may overlap with the first opening OP1. The width of the second opening OP2 may be smaller than the width of the first opening OP1.

[0120] The second opening OP2 may have a constant width from the lower portion to the upper portion of the hydrogen supply layer 200. However, the present disclosure is not limited thereto, and the second opening OP2 may have various shapes to electrically connect the pixel electrode PE to the source electrode SE and the drain electrode DE.

[0121] refer to Fig.12, at least a portion of the hydrogen supply layer 200 may be treated with hydrogen plasma treatment. For example, the upper surface of the hydrogen supply layer 200 may be treated with hydrogen plasma treatment. Accordingly, the concentration of hydrogen ions on the upper surface of the hydrogen supply layer 200 may be relatively much increased compared to before the hydrogen plasma treatment. The hydrogen ions generated in the hydrogen supply layer 200 may be more easily directed toward the interlayer ML (see, Figure 3 However, the present disclosure is not limited to the hydrogen plasma treatment on the upper surface of the hydrogen supply layer 200.

[0122] refer to Fig.13 , the pixel electrode PE may be formed on the hydrogen supply layer 200. For example, the pixel electrode PE may fill the first opening OP1 and the second opening OP2. The pixel electrode PE may contact the drain electrode DE through the first opening OP1 and the second opening OP2. The pixel electrode PE may contact (eg, directly contact) the upper surface of the hydrogen supply layer 200.

[0123] refer to Fig.14 The pixel defining layer PDL, the interlayer ML and the common electrode CE may be formed on the pixel electrode PE. The encapsulation layer (eg, the encapsulation layer TFE (see, Figure 3 )) can be formed on the common electrode CE. Accordingly, a Figure 3 The structure shown in Figure 1 The display device DD in.

[0124] Fig.15 To explain along Figure 1 Schematic cross-sectional view of a display device DD according to an embodiment taken along line II'.

[0125] In the following, the references will be omitted or simplified. Figure 3 Those described are repeated descriptions.

[0126] refer to Fig.15 , the hydrogen supply layer 200' may be disposed between the inorganic insulating layer 100 and the organic insulating layer 120. For example, the hydrogen supply layer 200' may contact each of the inorganic insulating layer 100 and the organic insulating layer 120. For example, a lower surface of the hydrogen supply layer 200' may contact the third gate insulating layer 108. An upper surface of the hydrogen supply layer 200' may contact the organic insulating layer 120.

[0127] The second opening OP2 may be defined in the hydrogen supply layer 200'. In a plan view, the second opening OP2 may overlap with the first opening OP1. A width of the first opening OP1 may be greater than a width of the second opening OP2.

[0128] Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 To explain the manufacturing Fig.15 Schematic cross-sectional view of a method for displaying a display device DD in FIG.

[0129] refer to Fig.16 , a preliminary hydrogen supply layer 200a' may be formed on the inorganic insulating layer 100. For example, the preliminary hydrogen supply layer 200a' may cover each of the third gate insulating layer 108, the source electrode SE, and the drain electrode DE. For example, along the contour of each of the third gate insulating layer 108, the source electrode SE, and the drain electrode DE, the preliminary hydrogen supply layer 200a' may have a substantially uniform thickness.

[0130] refer to Fig.17 , at least a portion of the preliminary hydrogen supply layer 200a' may be treated with hydrogen plasma treatment. For example, the upper surface of the preliminary hydrogen supply layer 200a' may be treated with hydrogen plasma treatment. Accordingly, the concentration of hydrogen ions on the upper surface of the preliminary hydrogen supply layer 200a' may be relatively much increased compared to before the hydrogen plasma treatment.

[0131] refer to Fig.18 and Fig.19 , a preliminary organic insulating layer 120a may be formed on the preliminary hydrogen supply layer 200a'. A portion of the preliminary organic insulating layer 120a may be removed by an etching process. Accordingly, an organic insulating layer 120 in which a first opening OP1 is defined may be formed. A portion of the preliminary hydrogen supply layer 200a' may be exposed through the first opening OP1. In a plan view, a portion of the organic insulating layer 120 that is not removed by the etching process may overlap with the gate electrode GE.

[0132] refer to Fig. 20 , the preliminary hydrogen supply layer 200a' may be removed by an etching process (see, Fig.19 ) portion. Accordingly, a hydrogen supply layer 200' in which a second opening OP2 is defined may be formed. In a plan view, the second opening OP2 may overlap with the first opening OP1. The width of the first opening OP1 may be greater than the width of the second opening OP2. A portion of the drain electrode DE may be exposed through the first opening OP1 and the second opening OP2. In another embodiment, a portion of the source electrode SE may be exposed through the first opening OP1 and the second opening OP2.

[0133] refer to Fig.21 and Fig. 22, the pixel electrode PE may be formed on the organic insulating layer 120. The pixel electrode PE may contact each of the upper surface and the side surface of the organic insulating layer 120. The pixel electrode PE may contact the hydrogen supply layer 200' through the first opening OP1. The pixel electrode PE may contact a portion of the drain electrode DE through the second opening OP2. In another embodiment, the pixel electrode PE may contact a portion of the source electrode SE through the second opening OP2.

[0134] A hole auxiliary layer HTL, a light emitting layer EML, an electron auxiliary layer ETL, a pixel defining layer PDL, and a common electrode CE may be formed on the pixel electrode PE. An encapsulation layer (eg, an encapsulation layer TFE (see, Fig.15 )) can be formed on the common electrode CE. Accordingly, a Fig.15 The structure Figure 1 The display device DD in.

[0135] Fig.23 To explain along Figure 1 Schematic cross-sectional view of a display device DD according to an embodiment taken along line II'.

[0136] In addition to the electron auxiliary layer ETL and the hole auxiliary layer HTL, the reference Fig.23 The display device DD described is Figure 3 The display device DD is substantially the same as that of FIG. Figure 3 Those described are repeated descriptions.

[0137] refer to Fig.23 The electron auxiliary layer ETL may be disposed on the pixel electrode PE. The light emitting layer EML may be disposed on the electron auxiliary layer ETL. The hole auxiliary layer HTL may be disposed on the light emitting layer EML. In other words, the hole auxiliary layer HTL may be disposed on the upper portion of the electron auxiliary layer ETL. Fig.23 The distance between the hydrogen supply layer 200 and the electron auxiliary layer ETL is comparable Figure 3 The distance between the hydrogen supply layer 200 and the electron assisting layer ETL is small. Accordingly, hydrogen ions in the hydrogen supply layer 200 may be more easily diffused into the metal material included in the electron assisting layer ETL.

[0138] Fig.24 To explain along Figure 1 Schematic cross-sectional view of a display device DD according to an embodiment taken along line II'.

[0139] In addition to the electron auxiliary layer ETL and the hole auxiliary layer HTL, the reference Fig.24 The display device DD described is Fig.15 The display device DD is substantially the same as that of FIG. Fig.15Those described are repeated descriptions.

[0140] refer to Fig.24 The electron auxiliary layer ETL may be disposed on the pixel electrode PE. The light emitting layer EML may be disposed on the electron auxiliary layer ETL. The hole auxiliary layer HTL may be disposed on the light emitting layer EML. In other words, the hole auxiliary layer HTL may be disposed on the upper portion of the electron auxiliary layer ETL. Fig.24 The distance between the hydrogen supply layer 200' and the electron auxiliary layer ETL is comparable Fig.15 The distance between the hydrogen supply layer 200 ′ and the electron assisting layer ETL is small. Accordingly, hydrogen ions in the hydrogen supply layer 200 ′ may be more easily diffused into the metal material included in the electron assisting layer ETL.

[0141] The display device and the method of manufacturing the display device according to the embodiment may be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, or the like.

[0142] The above description is an example of the technical features of the present disclosure, and a person skilled in the art to which the present disclosure belongs will be able to make various modifications and variations. Therefore, the embodiments of the present disclosure described above may be implemented individually or in combination with each other.

[0143] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and should be interpreted as all technical spirits within the scope of equivalents are included in the scope of the present disclosure.

Claims

1. A display device, comprising: An inorganic insulating layer disposed on a substrate; a hydrogen supply layer disposed on the inorganic insulating layer; a pixel electrode contacting the hydrogen supply layer; as well as An interlayer receives hydrogen ions from the hydrogen supply layer and is disposed on the pixel electrode.

2. The display device according to claim 1, further comprising: An organic insulating layer is provided on the inorganic insulating layer, wherein the hydrogen supply layer is disposed on the organic insulating layer. 3 . The display device according to claim 2 , wherein an upper surface of the hydrogen supply layer contacts the pixel electrode. 4 . The display device according to claim 2 , wherein the hydrogen supply layer covers an upper surface of the organic insulating layer and a side surface of the organic insulating layer.

5. The display device according to claim 2, wherein: The organic insulating layer includes a first opening penetrating the organic insulating layer, The hydrogen supply layer includes a second opening overlapping the first opening in a plan view, and The hydrogen supply layer covers the organic insulating layer in the first opening.

6. The display device according to claim 1, further comprising: An organic insulating layer is provided on the inorganic insulating layer, The hydrogen supply layer is disposed between the inorganic insulating layer and the organic insulating layer.

7. The display device according to claim 1, further comprising: A common electrode is provided on the interlayer, wherein the interlayer comprises a light-emitting layer and an electron auxiliary layer for supplying electrons to the light-emitting layer, in: The light emitting layer includes quantum dots, and The electron assisting layer includes a metal oxide.

8. A method for manufacturing a display device, the method comprising: forming an inorganic insulating layer on a substrate; forming a hydrogen supply layer on the inorganic insulating layer; forming a pixel electrode on the hydrogen supply layer and contacting the hydrogen supply layer; as well as An interlayer receiving hydrogen ions from the hydrogen supply layer is formed on the pixel electrode.

9. The method according to claim 8, further comprising: forming a preliminary organic insulating layer on the inorganic insulating layer; forming an organic insulating layer including a first opening by etching a portion of the preliminary organic insulating layer; forming a preliminary hydrogen supply layer on the organic insulating layer and covering the organic insulating layer in the first opening; as well as The hydrogen supply layer including a second opening corresponding to the first opening is formed by etching a portion of the preliminary hydrogen supply layer.

10. The method according to claim 8, further comprising: forming a preliminary hydrogen supply layer on the inorganic insulating layer; forming a preliminary organic insulating layer on the preliminary hydrogen supply layer; forming an organic insulating layer including a first opening by etching a portion of the preliminary organic insulating layer; as well as The hydrogen supply layer including a second opening corresponding to the first opening is formed by etching a portion of the preliminary hydrogen supply layer.

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