Display device and display panel

Abstract

A display device according to an embodiment of the present disclosure may include: a substrate including an active area in which a plurality of sub-pixels are arranged, and a non-active area including a pad area extending in a column direction from the active area; a plurality of gate lines arranged in the active region and each extending in a row direction; a plurality of data lines arranged in the active area and each extending in a column direction; a plurality of pads disposed in the pad region; and a plurality of link lines electrically connecting the plurality of pads and the plurality of data lines. Each of the plurality of link lines may include a horizontal link line arranged in the active region and extending in a row direction and a vertical link line arranged in the active region and extending in a column direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0147160, filed on October 30, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device and a display panel. Background Art

[0004] The display panel of the display device may include an active area for displaying an image and an inactive area for not displaying an image. Various structures, circuits, and lines may be arranged in the inactive area (also referred to as a non-display area or a frame) of the display panel. Therefore, it is not easy to reduce the frame of the display panel. Specifically, since the link line for transmitting the data signal to the data line is arranged in the inactive area of ​​the display panel, it is not easy to reduce the frame. Summary of the invention

[0005] Embodiments of the present disclosure may provide a display panel and a display device having a data link structure for reducing a bezel.

[0006] Embodiments of the present disclosure may provide a display panel and a display device having a data link structure capable of reducing image abnormality caused by crosstalk between link lines and gate lines.

[0007] Embodiments of the present disclosure may provide a display panel and a display device having a data link structure capable of reducing resistance in a transmission path of a common driving voltage.

[0008] A display device according to an embodiment of the present disclosure may include: an active area, which is capable of displaying an image; an inactive area, which is located outside the active area and includes a pad area; a first pad, which is arranged in the pad area; a first data line, which is arranged in the active area and extends in a column direction; a first horizontal link line, which is arranged in the active area, extends in a row direction, and is electrically connected to the first data line; a first vertical link line, which is arranged in the active area, extends in the column direction, and electrically connects the first horizontal link line to the first pad; a second pad, which is arranged in the pad area; a second data line, which is arranged in the active area, extends in the row direction, and electrically connects the first horizontal link line to the first pad; A second data line is arranged in the active area and extends in a column direction; a second horizontal link line, which is arranged in the active area, extends in a row direction, and is electrically connected to the second data line; a second vertical link line, which is arranged in the active area, extends in a column direction, and electrically connects the second horizontal link line to a second pad; a first sub-pixel, which is connected to the first data line and emits light of a first color; a second sub-pixel, which is connected to the second data line and emits light of the first color; and two or more sub-pixel rows, which emit light of the first color and are arranged between the first horizontal link line and the second horizontal link line.

[0009] A display panel according to an embodiment of the present disclosure may include: an active area, which is capable of displaying an image; an inactive area, which is located outside the active area and includes a pad area; a first pad, which is arranged in the pad area; a first data line, which is arranged in the active area and extends in a column direction; a first horizontal link line, which is arranged in the active area, extends in a row direction, and is electrically connected to the first data line; a first vertical link line, which is arranged in the active area, extends in a column direction, and electrically connects the first horizontal link line to the first pad; a first gate line, which is arranged in the active area, extends in a column direction, and electrically connects the first horizontal link line to the first pad; and a first gate line. a polar line overlapping the first horizontal link line; a second pad, which is arranged in the pad area; a second data line, which is arranged in the active area and extends in the column direction; a second horizontal link line, which is arranged in the active area, extends in the row direction and is electrically connected to the second data line; a second vertical link line, which is arranged in the active area, extends in the column direction, and electrically connects the second horizontal link line to the second pad; a second gate line, which overlaps the second horizontal link line; and a third gate line, which is arranged between the first gate line and the second gate line and does not overlap with any of the horizontal link lines.

[0010] A display device according to an embodiment of the present disclosure may include: an active area, which is capable of displaying an image; an inactive area, which is located outside the active area and includes a pad area; a first pad, which is arranged in the pad area; a first data line, which is arranged in the active area and extends in the column direction; a first horizontal link line, which is arranged in the active area, extends in the row direction, and is electrically connected to the first data line; a first vertical link line, which is arranged in the active area, extends in the column direction, and electrically connects the first horizontal link line to the first pad; and a common drive voltage line, which is used to supply a common drive voltage to the common electrode of the light-emitting device of each sub-pixel.

[0011] According to an embodiment of the present disclosure, the display device may further include at least one of a horizontal metal line and a vertical metal line, wherein the horizontal metal line is configured to extend in a row direction, is located in a first metal layer, and is spaced apart from a first horizontal link line, and the vertical metal line is configured to extend in a column direction, is located in a second metal layer, and is spaced apart from a first vertical link line.

[0012] At least one of the horizontal metal line and the vertical metal line may be electrically floating or electrically connected to a common driving voltage line.

[0013] According to the embodiments of the present disclosure, a display panel and a display device having a data link structure for reducing a bezel may be provided.

[0014] According to the embodiments of the present disclosure, a display panel and a display device having a data link structure capable of reducing image abnormality caused by crosstalk between a link line and a gate line may be provided.

[0015] According to the embodiments of the present disclosure, a display panel and a display device having a data link structure capable of reducing resistance in a transmission path of a common driving voltage may be provided.

[0016] According to the embodiments of the present disclosure, it is possible to reduce the weight of a display panel and a display device by reducing a bezel through a data link structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0018] Figure 2 A display panel according to an embodiment of the present disclosure is shown.

[0019] Figure 3 A substrate of a display panel according to an embodiment of the present disclosure is shown.

[0020] Figure 4A data link structure in a display panel according to an embodiment of the present disclosure is shown.

[0021] Figure 5 A data link structure for reducing a bezel of a display panel according to an embodiment of the present disclosure is shown.

[0022] Figure 6 A data link structure for reducing a bezel of a display panel according to an embodiment of the present disclosure is shown in more detail.

[0023] Figure 7 A data link structure for alleviating the oblique line crosstalk phenomenon of a display panel according to an embodiment of the present disclosure is shown.

[0024] Figure 8 Another data link structure for alleviating the oblique line crosstalk phenomenon of a display panel according to an embodiment of the present disclosure is shown.

[0025] Fig. 9 Another data link structure for alleviating the oblique line crosstalk phenomenon of a display panel according to an embodiment of the present disclosure is shown.

[0026] Fig.10 Another data link structure for alleviating the oblique line crosstalk phenomenon of a display panel according to an embodiment of the present disclosure is shown.

[0027] Fig.11 Another data link structure for alleviating the oblique line crosstalk phenomenon of a display panel according to an embodiment of the present disclosure is shown.

[0028] Figures 12 to 15 is a cross-sectional view illustrating a data link structure of a display panel according to an embodiment of the present disclosure.

[0029] Fig.16 Show according to Figure 6 The tilted line crosstalk phenomenon of the data link structure.

[0030] Fig.17 Show according to Figures 7 to 11 The tilted line crosstalk phenomenon of the data link structure. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. When assigning reference numerals to the components of the various drawings, even if the same components are shown on different drawings, the components may be assigned the same reference numerals. When it is determined that the disclosed subject matter is unclear, the details of known technologies or functions may be skipped. As used herein, when a component "includes", "has" another component or is "composed of" another component, the component may add other components unless the component "only" includes, has, or is "composed of" the other component. As used herein, the singular forms "a", "an" are also intended to include plural forms, unless the context clearly indicates otherwise.

[0032] References such as "first," "second," "A," "B," "(a)," and "(b)" may be used to describe components of the present disclosure. These references are provided only to distinguish one component from another, and the nature, order, or number of the components is not limited by these references.

[0033] When describing the positional relationship between components, when two or more components are described as being "connected," "combined," or "linked," the two or more components may be directly "connected," "combined," or "linked," or another component may be inserted. Here, another component may be included in one or more of the two or more components that are "connected," "combined," or "linked" to each other.

[0034] When such terms as “after,” “next,” “subsequently,” and “before” are used to describe a time-flow relationship associated with components, methods of operation, and methods of manufacture, they may include non-sequential relationships unless the terms “immediately” or “directly” are used.

[0035] When a component is represented by a value or its corresponding information (eg, a level), the value or the corresponding information may be interpreted as including tolerances that may occur due to various factors (eg, process factors, internal or external influences, or noise).

[0036] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0037] Figure 1 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0038] Reference Figure 1 The display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit is a circuit for driving the display panel 110 and may include a data driving circuit 120, a gate driving circuit 130, and a display controller 140.

[0039] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111 .

[0040] The substrate 111 of the display panel 110 may include an active area AA capable of displaying an image and a non-active area NA located outside the active area AA. A plurality of sub-pixels SP for image display may be disposed in the active area AA. The non-active area NA may include a pad area PA extending from the active area AA in a first direction (e.g., a column direction or a row direction).

[0041] In the display panel 110 according to an embodiment of the present disclosure, the non-active area NA may be very small. In this specification, the non-active area NA may also be referred to as a "border". For example, the non-active area NA may include a first non-active area located outside the active area AA in the first direction, a second non-active area located outside the active area AA in the second direction, a third non-active area located outside the active area AA in a direction opposite to the first direction, and a fourth non-active area located outside the active area AA in a direction opposite to the second direction. In the first to fourth non-active areas, the first non-active area may include a pad area connected or combined with a driving circuit. In the first to fourth non-active areas, the second to fourth non-active areas not including the pad area may have a very small size.

[0042] For another example, the boundary area between the active area AA and the non-active area NA may be curved so that the non-active area NA may be located below the active area. In this case, when the user views the display device 100 from the front, there may be little or no non-active area NA visible to the user.

[0043] Various types of signal lines for driving the plurality of sub-pixels SP may be disposed on the substrate 111 of the display panel 110 .

[0044] The display device 100 according to the embodiment of the present disclosure may be a liquid crystal display device, etc., or may be a self-luminous display device in which the display panel 110 emits light itself. When the display device 100 according to the embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light emitting device.

[0045] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting device is implemented as an organic light-emitting diode (OLED). For another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting device is implemented as an inorganic-based light-emitting diode. For another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which the light-emitting device is implemented by a quantum dot, which is a semiconductor crystal that emits light by itself.

[0046] The structure of each of the plurality of subpixels SP may vary according to the type of the display device 100. For example, if the display device 100 is a self-luminous display device having self-luminous subpixels SP, each subpixel SP may include a self-luminous light emitting device, one or more transistors, and one or more capacitors.

[0047] For example, the various types of signal lines may include a plurality of data lines DL supplying data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL for transmitting gate signals (also referred to as scan signals).

[0048] For example, a plurality of data lines DL and a plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend in a first direction. Each of the plurality of gate lines GL may be arranged to extend in a second direction. Here, the first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be a row direction, and the second direction may be a column direction. Hereinafter, for ease of explanation, a case where each of the plurality of data lines DL is arranged in a column direction, and each of the plurality of gate lines GL is arranged in a row direction will be exemplified.

[0049] The data driving circuit 120 is a circuit for driving the plurality of data lines DL, and may output data signals to the plurality of data lines DL.

[0050] The data driving circuit 120 may receive image data DATA in a digital form from the display controller 140 and convert the received image data into analog data signals to output to the plurality of data lines DL.

[0051] For example, the data driving circuit 120 can be connected to the display panel 110 using a tape automated packaging (TAB) method, or can be connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or can be implemented and connected to the display panel 110 using a chip on film (COF) method.

[0052] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. The data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to more than two of the four sides of the display panel 110, depending on a driving method, a panel design method, etc.

[0053] The data driving circuit 120 may be connected to the outside of the active area AA of the display panel 110 , but alternatively, the data driving circuit 120 may be disposed in the active area AA of the display panel 110 .

[0054] The gate driving circuit 130 is a circuit for driving the plurality of gate lines GL, and may output gate signals to the plurality of gate lines GL.

[0055] The gate driving circuit 130 may receive a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage and various gate driving control signals GCS, and may generate and supply gate signals to a plurality of gate lines GL.

[0056] In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 130 may be built in the display panel 110 in a gate-in-panel (GIP) type. If the gate driving circuit 130 is a gate-in-panel type, the gate driving circuit 130 may be formed on a substrate of the display panel 110 during a manufacturing process of the display panel 110.

[0057] For example, the gate driving circuit 130 may be disposed in the non-active area NA of the display panel 110 .

[0058] As another example, the gate driving circuit 130 may be disposed in the active area AA of the display panel 110. In this case, as an example, the gate driving circuit 130 may be disposed in a first partial area (e.g., a left area or a right area) within the active area AA. As another example, the gate driving circuit 130 may be disposed in a first partial area (e.g., a left area or a right area within the active area AA) and a second partial area (e.g., a right area or a left area within the active area AA) within the active area AA.

[0059] In the present disclosure, the gate driving circuit 130 built into or embedded in the display panel 110 may also be referred to as an “in-panel gate circuit”.

[0060] The display controller 140 may be a device for controlling the data driving circuit 120 and the gate driving circuit 130 , and may control a driving timing of a plurality of data lines DL and a driving timing of a plurality of gate lines GL.

[0061] The display controller 140 may supply the data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120 , and may supply the gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130 .

[0062] The display controller 140 may receive input image data from the host system 150 and supply image data DATA to the data driving circuit 120 based on the input image data.

[0063] The display controller 140 may be implemented as a separate component from the data driving circuit 120 , or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0064] The display controller 140 may be a timing controller used in typical display technologies, or may be a control device capable of further performing other control functions including a timing controller, or may be a control device different from a timing controller, or may be a control device other than a timing controller, or may be a circuit within a control device. The display controller 140 may be implemented by various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0065] The display controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, or the like.

[0066] The display controller 140 may send and receive signals to and from the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI) interface, or a serial peripheral interface (SPI).

[0067] In order to provide not only an image display function but also a touch sensing function, the display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit for detecting a touch generated by a touch object such as a finger or a pen or detecting a touch position by sensing the touch sensor.

[0068] The touch sensing circuit may include a touch driving circuit for driving and sensing the touch sensor to generate and output touch sensing data, and a touch controller for detecting occurrence of a touch or detecting a touch position using the touch sensing data.

[0069] The touch sensor may include a plurality of touch electrodes and may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes with a touch driving circuit.

[0070] The touch sensor may exist outside the display panel 110 in the form of a touch panel, or may exist inside the display panel 110. If the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor may be referred to as an external type. If the touch sensor is an external type, the touch panel and the display panel 110 may be manufactured separately and combined during the assembly process. The external touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0071] If the touch sensor exists inside the display panel 110 , the touch sensor may be formed on a substrate together with signal lines and electrodes related to display driving during a manufacturing process of the display panel 110 .

[0072] The touch driving circuit may supply a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0073] The touch sensing circuit may perform touch sensing using a self-capacitance sensing method or a mutual capacitance sensing method.

[0074] If the touch sensing circuit uses a self-capacitance sensing method to perform touch sensing, the touch sensing circuit may perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self-capacitance sensing method, each of the plurality of touch electrodes may be used as a driving touch electrode and a sensing touch electrode. The touch drive circuit may drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0075] If the touch sensing circuit uses a mutual capacitance sensing method to perform touch sensing, the touch sensing circuit may perform touch sensing based on the capacitance between the touch electrodes. According to the mutual capacitance sensing method, a plurality of touch electrodes may be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit may drive the driving touch electrodes and sense the sensing touch electrodes.

[0076] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate devices or as one device. In addition, the touch driving circuit and the data driving circuit 120 may be implemented as separate devices or as one device.

[0077] The display device 100 may further include a power supply circuit that supplies various types of power to the display driving circuit and / or the touch sensing circuit.

[0078] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smart phone or a tablet, or a display or a television of various sizes, but is not limited thereto and may be a display of various types and sizes capable of displaying information or images.

[0079] The display device 100 according to an embodiment of the present disclosure may further include electronic devices such as a camera (eg, an image sensor) and a detection sensor. For example, the detection sensor may be a sensor for detecting an object or a human body by receiving light such as infrared, ultrasonic or ultraviolet rays.

[0080] Figure 2 A display panel 110 according to an embodiment of the present disclosure is shown.

[0081] Reference Figure 2 , the display panel 110 may include a substrate 111 provided with a plurality of sub-pixels SP and an encapsulation layer 200 on the substrate 111. Here, the encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation part.

[0082] Reference Figure 2 , when the display device 100 according to an embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light emitting device ED and a sub-pixel circuit SPC for driving the light emitting device ED.

[0083] Reference Figure 2 , the sub-pixel circuit SPC may include a plurality of pixel driving transistors and at least one capacitor for driving the light emitting device ED. In the present disclosure, the sub-pixel circuit SPC may drive the light emitting device ED by supplying a driving current to the light emitting device ED at a predetermined time. The light emitting device ED may be driven by the driving current and emit light.

[0084] The plurality of pixel driving transistors may include a driving transistor DT for driving the light emitting device ED and a scanning transistor ST which is turned on or off according to a scanning signal SC.

[0085] The driving transistor DT may supply a driving current to the light emitting device ED.

[0086] The scan transistor ST may be configured to control an electrical state of a corresponding node in the sub-pixel circuit SPC, or to control a state or operation of the drive transistor DT.

[0087] The at least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during a frame.

[0088] To drive the subpixel SP, a data signal VDATA as an image signal and a scan signal SC as a gate signal may be applied to the subpixel SP. In addition, a common pixel driving voltage including a first driving voltage VDD and a second driving voltage VSS may be applied to the subpixel SP to drive the subpixel SP.

[0089] The light emitting device ED may include an anode AND, a light emitting device intermediate layer EL, and a cathode CAT. The light emitting device intermediate layer EL may be a layer disposed between the anode AND and the cathode CAT.

[0090] In the case where the light emitting device ED is an organic light emitting device, the light emitting device intermediate layer EL may include a light emitting layer EML and a common layer EL_COM. The common layer EL_COM may include a first common layer COM1 between the anode AND and the light emitting layer EML and a second common layer COM2 between the light emitting layer EML and the cathode. The light emitting layer EML may be disposed in each sub-pixel SP. In contrast, the first common layer COM1 and the second common layer COM2 may be disposed together across a plurality of sub-pixels SP. The light emitting layer EML may be disposed in each light emitting region, and the first common layer COM1 and the second common layer COM2 may be disposed together across a plurality of light emitting regions and non-light emitting regions.

[0091] For example, the first common layer COM1 may include a hole injection layer HIL and a hole transport layer HTL, and the second common layer COM2 may include an electron transport layer ETL and an electron injection layer EIL. The hole injection layer may inject holes from the anode AND into the hole transport layer, the hole transport layer may transport holes to the light emitting layer EML, the electron injection layer may inject electrons from the cathode CAT into the electron transport layer, and the electron transport layer may transport electrons to the light emitting layer EML.

[0092] For example, the cathode CAT may be electrically connected to a second driving voltage line VSSL. A second driving voltage VSS as a common pixel driving voltage type may be applied to the cathode CAT through the second driving voltage line VSSL. The anode AND may be electrically connected to a first node N1 of a driving transistor DT of each sub-pixel SP. In the present disclosure, the second driving voltage VSS may also be referred to as a base voltage VSS, and the second driving voltage line VSSL may also be referred to as a base voltage line VSSL.

[0093] For example, the anode AND may be a pixel electrode provided in each sub-pixel SP, and the cathode CAT may be a common electrode provided in a plurality of sub-pixels SP. For another example, the cathode CAT may be a pixel electrode provided in each sub-pixel SP, and the anode AND may be a common electrode provided in a plurality of sub-pixels SP. Hereinafter, for ease of explanation, it is assumed that the anode AND is a pixel electrode and the cathode CAT is a common electrode.

[0094] Each light emitting device ED may be composed of an overlapping portion of an anode AND, a light emitting device intermediate layer EL, and a cathode CAT. A predetermined light emitting region may be formed by each light emitting device ED. For example, the light emitting region of each light emitting device ED may include an overlapping region of the anode AND, the light emitting device intermediate layer EL, and the cathode CAT.

[0095] For example, the light emitting device ED may be an organic light emitting diode (OLED), an inorganic light emitting diode or a quantum dot light emitting device. For example, in the case where the light emitting device ED is an organic light emitting diode OLED, the light emitting device intermediate layer EL in the light emitting device ED may include an organic light emitting device intermediate layer EL including an organic material.

[0096] The driving transistor DT may be a driving transistor for supplying a driving current to the light emitting device ED. The driving transistor DT may be connected between the first driving voltage line VDDL and the light emitting device ED.

[0097] The driving transistor DT may include a first node N1 electrically connected to the light emitting device ED, a second node N2 to which the data signal VDATA is applied, and a third node N3 to which the driving voltage VDD from the first driving voltage line VDDL is applied.

[0098] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of explanation, a case in which the second node N2 in the driving transistor DT is a gate node, the first node N1 is a source node, and the third node N3 is a drain node will be described.

[0099] exist Figure 2 The scan transistor ST included in the illustrated sub-pixel circuit SPC may be a switching transistor for transmitting the data signal VDATA, which is an image signal, to the second node N2, which is a gate node of the driving transistor DT.

[0100] The scanning transistor ST may be controlled to be on-off by a scanning signal SC as a gate signal applied through a scanning line SCL (as a type of gate line GL), and may control the electrical connection between the second node N2 of the driving transistor DT and the data line DL. The drain or source of the scanning transistor ST may be electrically connected to the data line DL, and the source or drain of the scanning transistor ST may be electrically connected to the second node N2 of the driving transistor DT. The gate of the scanning transistor ST may be electrically connected to the scanning line SCL.

[0101] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DT.

[0102] The storage capacitor Cst may be an external capacitor intentionally designed outside the driving transistor DT, rather than a parasitic capacitor (eg, Cgs, Cgd) that is an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DT.

[0103] Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0104] The display panel 110 may have a top emission structure or a bottom emission structure.

[0105] If the display panel 110 has a top emission structure, at least a portion of the sub-pixel circuit SPC may overlap at least a portion of the light emitting device ED in the vertical direction. Alternatively, if the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC may not overlap with the light emitting device ED in the vertical direction.

[0106] like Figure 2 As shown, the sub-pixel circuit SPC may have a 2T-1C structure including two transistors T1 and T2 and one capacitor Cst. In some cases, depending on this, the sub-pixel circuit SPC may also include one or more transistors or one or more capacitors.

[0107] For example, the sub-pixel circuit SPC may have an 8T-1C structure including eight transistors and a single capacitor. For another example, the sub-pixel circuit SPC may have a 6T-2C structure including six transistors and two capacitors. For another example, the sub-pixel circuit SPC may have a 7T-1C structure including seven transistors and one capacitor.

[0108] According to the structure of the sub-pixel circuit SPC, the type and number of gate signals and / or gate lines supplied to the sub-pixels SP may be changed.

[0109] Furthermore, according to the structure of the sub-pixel circuit SPC, the type and amount of the common pixel driving voltage supplied to the sub-pixels SP may be changed.

[0110] Since the circuit elements within each subpixel SP (specifically, the light emitting device ED implemented as an organic light emitting diode (OLED) including organic materials) are susceptible to external moisture or oxygen, the encapsulation layer 200 can be disposed on the display panel 110 to prevent oxygen from penetrating into the circuit elements (specifically, the light emitting device ED).

[0111] The encapsulation layer 200 may be configured in various shapes to prevent the light emitting device ED from contacting moisture or oxygen. For example, the encapsulation layer 200 may have a structure in which an inorganic layer and an organic layer are stacked. The encapsulation layer 200 may include a first inorganic layer on the light emitting device ED, an organic layer on the first inorganic layer, and a second inorganic layer on the organic layer.

[0112] Figure 3 A substrate 111 of a display panel 110 according to an embodiment of the present disclosure is shown.

[0113] Reference Figure 3 , the substrate 111 of the display panel 110 according to an embodiment of the present disclosure may include an active area AA capable of displaying an image and a non-active area NA not displaying an image.

[0114] Reference Figure 3 , the non-active region NA may include a first non-active region NA1, a second non-active region NA2, a third non-active region NA3, and a fourth non-active region NA4.

[0115] The first non-active area NA1 may extend from the active area AA in the first direction. The second non-active area NA2 may extend from the active area AA in the second direction. The third non-active area NA3 may extend from the active area AA in the third direction. The fourth non-active area NA4 may extend from the active area AA in the fourth direction.

[0116] For example, the first direction and the third direction may be column directions and opposite directions. The second direction and the fourth direction may be row directions and opposite directions. For another example, the first direction and the third direction may be row directions and opposite directions. The second direction and the fourth direction may be column directions and opposite directions. Hereinafter, for ease of explanation, an example will be given in which the first direction and the third direction are column directions and opposite directions, and the second direction and the fourth direction are row directions and opposite directions.

[0117] For example, the column direction may be the direction in which the data lines DL extend, and the row direction may be the direction in which the gate lines GL extend. For another example, the column direction may be the direction in which the gate lines GL extend, and the row direction may be the direction in which the data lines DL extend. Hereinafter, for ease of explanation, an example will be given in which the column direction is the direction in which the data lines DL extend, and the row direction is the direction in which the gate lines GL extend.

[0118] Reference Figure 3 The first non-active area NA1 may include a pad area PA provided with a plurality of pads, wherein at least one driving circuit or printed circuit board is electrically connected to the plurality of pads. For example, a plurality of data lines DL, a first common driving voltage line VDDL, and a second common driving voltage line VSSL may be electrically connected to the plurality of pads.

[0119] Reference Figure 3 , the first non-active area NA1 may further include a bending area BA. In this case, the substrate 111 may be a flexible substrate. In some cases, the first non-active area NA1 may not include the bending area BA.

[0120] Reference Figure 3 The display panel 110 may further include a ground line disposed in the non-active area NA of the substrate 111. The ground line may be disposed from one point of the pad area PA to different points of the pad area PA via the second non-active area NA2, the third non-active area NA3, and the fourth non-active area NA4.

[0121] Reference Figure 3 In the display panel 110 according to an embodiment of the present disclosure, the encapsulation layer 200 may have a structure in which an inorganic layer and an organic layer are stacked. In this case, the edge of the encapsulation layer 200 may be regarded as the edge of the organic layer. The encapsulation layer 200 may extend from the active area AA to a portion of the non-active area NA.

[0122] Reference Figure 3 In order to prevent the organic layer included in the encapsulation layer 200 from overflowing, the display panel 110 according to an embodiment of the present disclosure may include at least one dam portion or at least one stopper located further outside the organic layer included in the encapsulation layer 200 .

[0123] Figure 4 A data link structure in the display panel 110 according to an embodiment of the present disclosure is shown.

[0124] Reference Figure 4 , the display panel 110 according to an embodiment of the present disclosure may include a plurality of data lines DL for supplying a data voltage VDATA and a plurality of pads PD disposed in the pad area PA and electrically connected to the data driving circuit 120 .

[0125] Reference Figure 4 , the display panel 110 according to an embodiment of the present disclosure may include a data link structure for electrically connecting a plurality of data lines DL and a plurality of pads PD. The data link structure according to an embodiment of the present disclosure may include a plurality of link lines LINK.

[0126] Reference Figure 4 , the plurality of link lines LINK may be disposed in the non-active area NA. That is, the plurality of link lines LINK may be disposed in the first non-active area NA1 including the pad area PA.

[0127] Reference Figure 4 , the first non-active area NA1 may further include a link area LA in addition to the pad area PA and the bending area BA.

[0128] For example, each of the plurality of link lines LINK may be arranged to cross the pad area PA, the bending area BA, and the link area LA. Each of the plurality of link lines LINK may include a first end electrically connected to the pad PD disposed in the pad area PA and a second end electrically connected to the data line DL disposed in the active area AA. A wiring portion between both ends (i.e., the first end and the second end) of each of the plurality of link lines LINK may be arranged to cross the bending area BA and the link area LA.

[0129] For example, each of the plurality of link lines LINK may include one line or more than two lines. Each of the plurality of link lines LINK may be disposed on one metal layer or more than two metal layers.

[0130] Reference Figure 4 , the bending area BA may be bent during a manufacturing process of the display panel 110. Therefore, when a user views the display device 100 from the front, the bending area BA and the pad area PA may not be visible from the front.

[0131] However, when the user views the display device 100 from the front, the link area LA may be recognized as a bezel even if it is covered by the housing. Therefore, in order to achieve a narrow bezel, the area of ​​the link area LA may need to be reduced.

[0132] Reference Figure 4 , since all of the plurality of link lines LINK in the link area LA in the first non-active area NA1 need to be electrically connected to the plurality of data lines DL, the area of ​​the link area LA may increase.

[0133] In particular, when the length of the pad area PA in the second direction (e.g., the row direction) is shorter than the length of the active area AA in the second direction (e.g., the row direction), each of the plurality of link lines LINK in the left area LBZ and the right area RBZ within the link area LA needs to extend in a diagonal direction and be electrically connected to the plurality of data lines DL. Therefore, the length of the link area LA in the first direction (e.g., the column direction) may increase.

[0134] Therefore, if Figure 4As shown, if the display panel 110 has a data link structure in which a plurality of link lines LINK are disposed in the first non-active area NA1, the area of ​​the link area LA within the first non-active area NA1 may increase. Therefore, when a user views the display device 100 from the front, the link area LA may be recognized as a large frame.

[0135] Therefore, in order to achieve a narrow frame, a data link structure capable of reducing the area of ​​the link area LA may be required. Therefore, an embodiment of the present disclosure proposes a data link structure capable of achieving a narrow frame.

[0136] Hereinafter, a data link structure capable of realizing a narrow bezel according to an embodiment of the present disclosure will be described.

[0137] Figure 5 A data link structure for reducing a bezel of the display panel 110 according to an embodiment of the present disclosure is shown.

[0138] Reference Figure 5 , the non-active area NA may include a first non-active area NA1 extending from the active area AA in the column direction. The first non-active area NA1 may include a pad area PA and a link area LA extending from the active area AA in the column direction.

[0139] The display panel 110 according to an embodiment of the present disclosure may include a data link structure capable of supplying a data voltage VDATA to a plurality of sub-pixels SP arranged in the active area AA and reducing a bezel.

[0140] Reference Figure 5 , the data link structure for reducing the bezel according to an embodiment of the present disclosure may include a plurality of link lines LINK electrically connecting the plurality of data lines DL with the plurality of pads PD.

[0141] A plurality of data lines DL may be disposed in the active area AA, and each may extend in a column direction and may be connected to a plurality of sub-pixels SP disposed in the active area AA.

[0142] A plurality of pads PD may be disposed in the pad area PA included in the first non-active area NA1.

[0143] The plurality of link lines LINK may electrically connect the plurality of pads PD disposed in the pad area PA included in the first non-active area NA1 and the plurality of data lines DL disposed in the active area AA.

[0144] Reference Figure 5 , each of the plurality of link lines LINK included in the data link structure for a narrow bezel according to an embodiment of the present disclosure may include a portion LIA disposed in the active area AA.

[0145] Based on the data link structure for reducing the border according to the embodiment of the present disclosure, the plurality of link lines LINK and the plurality of data lines DL may be electrically connected within the active area AA. That is, in the data link structure for reducing the border according to the embodiment of the present disclosure, the connection point CNT_DL between the plurality of link lines LINK and the plurality of data lines DL may be located in the active area AA.

[0146] Therefore, each of the multiple link lines LINK does not need to extend in the diagonal direction in the left area and the right area within the link area LA, and each of the multiple link lines LINK can temporarily pass through the link area LA along the column direction and enter the active area AA, and can be connected to the data line DL in the active area AA.

[0147] like Figure 5 As shown, since the display panel 110 according to an embodiment of the present disclosure has a data link structure for reducing the frame, the length of the link area LA in the column direction can become very short or can be zero, and therefore, the first non-active area NA1 visible to the user from the front can become very small.

[0148] Reference Figure 5 In the data link structure for reducing the bezel according to an embodiment of the present disclosure, each of the plurality of link lines LINK may include an active area link line LIA disposed in the active area AA.

[0149] Reference Figure 5 The active area link lines LIA may include horizontal link lines HLIA located in the active area AA and extending in a row direction (ie, a horizontal direction) and vertical link lines VLIA located in the active area AA and extending in a column direction (ie, a vertical direction).

[0150] Reference Figure 5 , the vertical link line VLIA may electrically connect the pad PD and the horizontal link line HLIA, and the horizontal link line HLIA may electrically connect the vertical link line VLIA and the data line DL.

[0151] Reference Figure 5 The horizontal link line HLIA and the vertical link line VLIA may be electrically connected at the link line connection hole CNT_LIA. The horizontal link line HLIA and the data line DL may be electrically connected at the data line connection hole CNT_DL.

[0152] Reference Figure 5 , each of the plurality of link lines LINK may further include a non-active area link line LIN disposed in a first non-active area NA1 included in the non-active area NA.

[0153] The non-active area link line LIN may be formed integrally with the vertical link line VLIA. Alternatively, the non-active area link line LIN may be a line or wiring electrically connected to the vertical link line VLIA but disposed on a different metal layer from the vertical link line VLIA. Alternatively, the non-active area link line LIN may include a line electrically connected to the vertical link line VLIA but disposed on a different metal layer from the vertical link line VLIA.

[0154] Meanwhile, when the display panel 110 according to the embodiment of the present disclosure has Figure 5 In the data link structure for reducing the frame shown, the horizontal link line HLIA included in each of the plurality of link lines LINK may be parallel to the plurality of gate lines GL disposed in the active area AA and each extending in a row direction (ie, a horizontal direction).

[0155] In addition, when the display panel 110 according to the embodiment of the present disclosure has Figure 5 In the data link structure for reducing the frame as shown, the horizontal link line HLIA included in each of the plurality of link lines LINK may overlap with at least one gate line GL in a vertical direction.

[0156] Reference Figure 5 , among the plurality of vertical link lines VLIA, the length of the vertical link line VLIA electrically connected to the data line DL located further inside may be shorter. Among the plurality of vertical link lines VLIA, the length of the vertical link line VLIA electrically connected to the data line DL located further outside may be longer. The length of the vertical link line VLIA electrically connected to the data line DL located further inside may be shorter than the length of the vertical link line VLIA electrically connected to the data line DL located further outside.

[0157] Reference Figure 5 , among the plurality of horizontal link lines HLIA, the length of the horizontal link line HLIA electrically connected to the data line DL located further inside may be shorter. Among the plurality of horizontal link lines HLIA, the length of the horizontal link line HLIA electrically connected to the data line DL located further outside may be longer. The length of the horizontal link line HLIA electrically connected to the data line DL located further inside may be shorter than the length of the horizontal link line HLIA electrically connected to the data line DL located further outside.

[0158] Reference Figure 5, among the plurality of horizontal link lines HLIA, the length of the horizontal link line HLIA adjacent to the pad area PA may be shorter. Among the plurality of horizontal link lines HLIA, the length of the horizontal link line HLIA set farther from the pad area PA may be longer. The length of the horizontal link line HLIA adjacent to the pad area PA may be shorter than the length of the horizontal link line HLIA set farther from the pad area PA.

[0159] Reference Figure 5 , the first link line LINK1 may include a first active area link line LIA1 and a first non-active area link line LIN1. The first active area link line LIA1 may include a first horizontal link line HLIA1 and a first vertical link line VLIA1.

[0160] Reference Figure 5 The second link line LINK2 may include a second active area link line LIA2 and a second non-active area link line LIN2. The second active area link line LIA2 may include a second horizontal link line HLIA2 and a second vertical link line VLIA2.

[0161] Reference Figure 5 Among the first vertical link lines VLIA1 and the second vertical link lines VLIA2, the first vertical link line VLIA1 electrically connected to the outer first data line DL1 of the first data line DL1 and the second data line DL2 may be longer than the second vertical link line VLIA2.

[0162] Reference Figure 5 In the first and second horizontal link lines HLIA1 and HLIA2 , the first horizontal link line HLIA1 electrically connected to the outer first data line DL1 of the first and second data lines DL1 and DL2 may be longer than the second horizontal link line HLIA2 .

[0163] Reference Figure 5 Since the length of the first horizontal link line HLA1 is longer than that of the second horizontal link line HLIA2, a first area where the first horizontal link line HLIA1 overlaps with at least one gate line GL may be larger than a second area where the second horizontal link line HLIA2 overlaps with at least one gate line GL.

[0164] According to the above structure, Figure 5 As shown, the point CNT_DL where the data line DL is connected to the horizontal link line HLIA may form two first inclined lines SLT_DL. In addition, the point CNT_LIA where the vertical link line VLIA is connected to the horizontal link line HLIA may form two second inclined lines SLT_LIA.

[0165] like Figure 5 As shown, two triangles may be formed by two first inclined lines SLT_DL and two second inclined lines SLT_LIA. In each of the two triangles, one of the three sides may be a horizontal side parallel to the horizontal link line HLIA, and the vertex facing the horizontal side may be located at or near a boundary point between the active area AA and the first non-active area NA1.

[0166] Reference Figure 5 , the active area AA may include a central area Ac, a first area A1 on one side of the central area Ac, and a second area A2 on the other side of the central area Ac.

[0167] Reference Figure 5 , the data lines DL disposed in the first area A1 and the second area A2 may be connected to the non-active area link line LIN through the active area link line LIA.

[0168] Reference Figure 5 Alternatively, at least one data line DL disposed in the central area Ac may be directly connected to the non-active area link line LIN instead of being connected to the non-active area link line LIN via the active area link line LIA.

[0169] As described above, when the display panel 110 according to the embodiment of the present disclosure has Figure 5 In the data link structure shown for reducing the border, the horizontal link line HLIA included in each of the multiple link lines LINK can be parallel to the multiple gate lines GL arranged in the active area AA and each extending in the row direction (i.e., horizontal direction), and the horizontal link line HLIA included in each of the multiple link lines LINK can overlap with at least one gate line in the vertical direction.

[0170] Therefore, the horizontal link line HLIA included in each of the plurality of link lines LINK may form a parasitic capacitance with at least one gate line GL. That is, the horizontal link line HLIA included in each of the plurality of link lines LINK may be capacitively connected to at least one gate line GL.

[0171] Therefore, the change of the electrical state of at least one gate line GL may also affect the electrical state of the data line DL connected to the horizontal link line HLIA overlapping with the at least one gate line GL. Figure 5 In the data link structure shown for reducing the frame, crosstalk may occur between the gate line GL and the horizontal link line HLIA.

[0172] That is, the gate signal (eg, Figure 2 The voltage level variation of the scan signal SC in the gate line GL may generate noise in the data signal VDATA transmitted to the data line DL through the horizontal link line HLIA overlapping at least one gate line GL. Here, the noise generated in the data signal VDATA may have the form of an undesirable peak voltage.

[0173] Since the display panel 110 according to the embodiment of the present disclosure has Figure 5 The data link structure shown for reducing the frame has almost no link area LA visible from the front, so that the frame can be significantly reduced, but crosstalk may occur between the gate line GL and the horizontal link line HLIA.

[0174] The crosstalk between the gate line GL and the horizontal link line HLIA may cause image abnormalities at or near the left and right first inclined lines SLT_DL formed by the point CNT_DL connecting the data line DL and the horizontal link line HLIA. In an embodiment of the present disclosure, the image abnormalities in the oblique direction occurring near the two first inclined lines SLT_DL may be referred to as "oblique line crosstalk". Here, the image abnormalities may include dark lines and / or bright lines appearing in the form of diagonal lines.

[0175] Hereinafter, a data link structure for reducing the bezel will be described in more detail.

[0176] Figure 6 The data link structure for reducing the frame of the display panel 110 according to an embodiment of the present disclosure is shown in more detail. Figure 5 .

[0177] Reference Figure 6 , the plurality of sub-pixels SP disposed on the display panel 110 may include a plurality of first color sub-pixels SP_G emitting light of a first color, a plurality of second color sub-pixels SP_R emitting light of a second color, and a plurality of third color sub-pixels SP_B emitting light of a third color.

[0178] exist Figure 6 In FIG. 1 , a plurality of first color sub-pixels SP_G, a plurality of second color sub-pixels SP_R, and a plurality of third color sub-pixels SP_B may represent a light emitting region or an emission region. Figure 6 In the figure, a plurality of first color sub-pixels SP_G, a plurality of second color sub-pixels SP_R, and a plurality of third color sub-pixels SP_B may represent a light-emitting device ED. In the following figures, examples are given of cases where a plurality of first color sub-pixels SP_G, a plurality of second color sub-pixels SP_R, and a plurality of third color sub-pixels SP_B may correspond to a light-emitting device or a light-emitting region formed by the light-emitting device ED.

[0179] Reference Figure 6 , two first color sub-pixels SP_G, one second color sub-pixel SP_R, and one third color sub-pixel SP_B may form one unit pixel UP. That is, the display panel 110 may include a plurality of unit pixels UP, and each of the plurality of unit pixels UP may include two first color sub-pixels SP_G, one second color sub-pixel SP_R, and one third color sub-pixel SP_B.

[0180] Reference Figure 6 , each of the plurality of unit pixels UP may have a diamond shape.

[0181] Reference Figure 6 , a plurality of first color sub-pixels SP_G may be arranged in a row direction (eg, a horizontal direction). A plurality of second color sub-pixels SP_R and a plurality of third color sub-pixels SP_B may be alternately arranged one by one in the row direction (eg, a horizontal direction).

[0182] Reference Figure 6 The plurality of data lines DL may include a plurality of first color data lines DL_G1, DL_G2, DL_G3, and DL_G4 for supplying data voltages to first color sub-pixels SP_G arranged in a column direction (e.g., a vertical direction), and a plurality of integrated data lines DL_RB1, DL_RB2, and DL_RB3 for alternately supplying data voltages to second color sub-pixels SP_R and third color sub-pixels SP_B alternately arranged in a column direction (e.g., a vertical direction).

[0183] Reference Figure 6 , a plurality of first color data lines DL_G1 , DL_G2 , DL_G3 , and DL_G4 and a plurality of integrated data lines DL_RB1 , DL_RB2 , and DL_RB3 may be alternately arranged one by one in a row direction (eg, a horizontal direction).

[0184] Reference Figure 6 , a plurality of gate lines GL may be arranged in a row direction (eg, a horizontal direction). For example, the plurality of gate lines GL may overlap with a plurality of first color sub-pixels SP_G.

[0185] Reference Figure 6 , the data link structure of the display panel 110 according to an embodiment of the present disclosure may include vertical link lines VLIA_G1, VLIA_G2, VLIA_G3, VLIA_G4, VLIA_RB1, VLIA_RB2 and VLIA_RB3 and horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2 and HLIA_RB3.

[0186] Reference Figure 6 Each of the vertical link lines VLIA_G1, VLIA_G2, VLIA_G3, VLIA_G4, VLIA_RB1, VLIA_RB2, and VLIA_RB3 may be arranged to extend in a column direction (e.g., a vertical direction). Each of the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2, and HLIA_RB3 may be arranged to extend in a row direction (e.g., a horizontal direction).

[0187] Reference Figure 6 , the vertical link lines VLIA_G1, VLIA_G2, VLIA_G3, VLIA_G4, VLIA_RB1, VLIA_RB2 and VLIA_RB3 may electrically connect the non-active area link line LIN disposed in the first non-active area NA1 with the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2 and HLIA_RB3 disposed in the active area AA.

[0188] Reference Figure 6 , the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HUA_RB1, HLIA_RB2 and HLIA_RB3 can electrically connect the vertical link lines VLIA_G1, VLIA_G2, VLIA_G3, VLIA_RB1, VLIA_RB2 and VLIA_RB3 and the data lines DL_G1, DL_G2, DL_G3, DL_G4, DL_RB1, DL_RB2 and DL_RB3.

[0189] Reference Figure 6 , horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2, and HLIA_RB3 may be set for one or two pixel rows. That is, one horizontal link line may be arranged to correspond to one or two pixel rows.

[0190] Reference Figure 6 Each of the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2, and HLIA_RB3 may be arranged to correspond to one gate line GL. That is, a corresponding horizontal link line may exist in each of the plurality of gate lines GL.

[0191] Reference Figure 6The link line connection holes CNT_LIA that electrically connect the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2, and HLIA_RB3 with the vertical link lines VLIA_G1, VLIA_G2, VLIA_G3, VLIA_G4, VLIA_RB1, VLIA_RB2, and VLIA_RB3 may form second inclined lines SLT_LIA.

[0192] Reference Figure 6 The data line connection holes CNT_DL in which the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HUA_G4, HLIA_RB1, HLIA_RB2, and HLIA_RB3 are electrically connected to the data lines DL_G1, DL_G2, DL_G3, DL_G4, DL_RB1, DL_RB2, and DL_RB3 may form a first inclined line SLT_DL.

[0193] As described above, the crosstalk between the gate line GL and the horizontal link line HLIA may cause abnormal image phenomena at or near the first inclined line SLT_DL formed by the data line connection hole CNT_DL connecting the data line DL and the horizontal link line HLIA. For example, due to the "inclined line crosstalk" occurring near the first inclined line SLT_DL, inclined dark lines and / or bright lines may appear as image abnormalities.

[0194] Therefore, the display device 100 and the display panel 110 according to the embodiment of the present disclosure may include a data link structure capable of alleviating oblique line crosstalk. Hereinafter, the data link structure for alleviating oblique line crosstalk according to the embodiment of the present disclosure will be described. Figure 6 Description of the same content.

[0195] Figure 7 and Figure 8 The data link structure for alleviating the oblique line crosstalk phenomenon of the display panel 110 according to an embodiment of the present disclosure is shown. Figure 5 .

[0196] Reference Figure 7 and Figure 8 , the plurality of sub-pixels SP disposed on the display panel 110 may include a plurality of first color sub-pixels SP_G emitting light of a first color, a plurality of second color sub-pixels SP_R emitting light of a second color, and a plurality of third color sub-pixels SP_B emitting light of a third color. For example, the first color light may be green light, the second color light may be red light, and the third color light may be blue light.

[0197] exist Figure 7and Figure 8 In FIG. 1 , a plurality of first color sub-pixels SP_G, a plurality of second color sub-pixels SP_R, and a plurality of third color sub-pixels SP_B may represent a light emitting region or an emission region. Figure 7 , a plurality of first color sub-pixels SP_G, a plurality of second color sub-pixels SP_R, and a plurality of third color sub-pixels SP_B may represent light emitting devices ED.

[0198] Reference Figure 7 and Figure 8 , two first color sub-pixels SP_G, one second color sub-pixel SP_R, and one third color sub-pixel SP_B may constitute one unit pixel. In other words, the display panel 110 may include a plurality of unit pixels UP, and each of the plurality of unit pixels UP may include two first color sub-pixels SP_G, one second color sub-pixel SP_R, and one third color sub-pixel SP_B.

[0199] Reference Figure 7 and Figure 8 , each of the plurality of unit pixels UP may have a diamond shape.

[0200] Reference Figure 7 and Figure 8 , a plurality of first color sub-pixels SP_G may be arranged in a row direction (eg, a horizontal direction). A plurality of second color sub-pixels SP_R and a plurality of third color sub-pixels SP_B may be alternately arranged one by one in the row direction (eg, a horizontal direction).

[0201] Reference Figure 7 and Figure 8 The multiple data lines DL may include a plurality of first color data lines DL_G1, DL_G2, DL_G3 and DL_G4 for supplying data voltages to first color sub-pixels SP_G arranged in a column direction (e.g., a vertical direction), and a plurality of integrated data lines DL_RB1, DL_RB2 and DL_RB3 for alternately supplying data voltages to second color sub-pixels SP_R and third color sub-pixels SP_B arranged in a column direction (e.g., a vertical direction).

[0202] Reference Figure 7 and Figure 8 , a plurality of first color data lines DL_G1 , DL_G2 , DL_G3 , and DL_G4 and a plurality of integrated data lines DL_RB1 , DL_RB2 , and DL_RB3 may be alternately arranged one by one in a row direction (eg, a horizontal direction).

[0203] Reference Figure 7 and Figure 8, a plurality of gate lines GL may be arranged in a row direction (eg, a horizontal direction). For example, the plurality of gate lines GL may overlap with a plurality of first color sub-pixels SP_G. Each of the plurality of gate lines GL may be arranged to correspond to one unit pixel UP. Figure 7 , the data link structure of the display panel 110 according to an embodiment of the present disclosure may include vertical link lines VLIA_G1, VLIA_G2, VLIA_G3, VLIA_G4, VLIA_RB1, VLIA_RB2 and VLIA_RB3 and horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2 and HLIA_RB3.

[0204] Reference Figure 7 and Figure 8 , each of the vertical link lines VLIA_G1, VLIA_G2, VLIA_G3, VLIA_G4, VUA_RB1, VLIA_RB2, and VLIA_RB3 may be arranged to extend in a column direction (e.g., a vertical direction). Each of the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2, and HLIA_RB3 may be arranged to extend in a row direction (e.g., a horizontal direction).

[0205] Reference Figure 7 and Figure 8 , the vertical link lines VLIA_G1, VLIA_G2, VLIA_G3, VLIA_G4, VLIA_RB1, VLIA_RB2 and VLIA_RB3 may electrically connect the non-active area link line LIN disposed in the first non-active area NA1 with the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2 and HLIA_RB3 disposed in the active area AA.

[0206] Reference Figure 7 and Figure 8 , the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2 and HLIA_RB3 can electrically connect the vertical link lines VLIA_G1, VLIA_G2, VLIA_G3, VLIA_RB1, VLIA_RB2 and VLIA_RB3 with the data lines DL_G1, DL_G2, DL_G3, DL_G4, DL_RB1, DL_RB2 and DL_RB3.

[0207] Reference Figure 7 and Figure 8 , when the display panel 110 according to an embodiment of the present disclosure has a data link structure, the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2, and HLIA_RB3 may not be arranged for each pixel row. That is, there may be no horizontal link line corresponding to at least one of the plurality of pixel rows, and there may be horizontal link lines corresponding to only some of the plurality of pixel rows.

[0208] Reference Figure 7 and Figure 8 , each of the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, HLIA_G4, HLIA_RB1, HLIA_RB2, and HLIA_RB3 may be set to correspond to one gate line GL. However, a plurality of gate lines GL ( Figure 7 GLc and GLd in Figure 8 At least one of GLc and GLe) in may not have a corresponding horizontal link line.

[0209] According to an embodiment of the present disclosure, the display panel 110 of the display device 100 may include: a substrate 111 including an active area AA capable of displaying an image and a non-active area NA located outside the active area AA and including a pad area PA, a plurality of data lines DL arranged in the active area AA and each extending in a column direction, a plurality of gate lines GL arranged in the active area AA and each extending in a row direction, and a plurality of link lines LINK electrically connecting a plurality of pads PD arranged in the pad area PA with the plurality of data lines DL.

[0210] Each of the plurality of link lines LINK may include a horizontal link line HLIA extending in a row direction and a vertical link line VLIA extending in a column direction.

[0211] The horizontal link line HLIA included in each of the plurality of link lines LINK may be disposed in the active area AA, and at least a portion of the vertical link line VLIA included in each of the plurality of link lines LINK may be disposed in the active area AA.

[0212] Reference Figure 7 and Figure 8 , the plurality of link lines LINK may include a first link line LINK_G1 electrically connected to a first data line DL_G1 among the plurality of data lines DL and a second link line LINK_G2 electrically connected to a second data line DL_G2 among the plurality of data lines DL different from the first data line DL_G1 .

[0213] Reference Figure 7 and Figure 8 , the first link line LINK_G1 may include a first line LIA_G1 disposed in the active area AA and a second line LIN_G1 disposed in the first non-active area NA1. The first line LIA_G1 may include a first vertical link line VLIA_G1 and a first horizontal link line HLIA_G1. The second link line LINK_G2 may include a third line LIA_G2 disposed in the active area AA and a fourth line LIN_G2 disposed in the first non-active area NA1. The third line LIA_G2 may include a second vertical link line VLIA_G2 and a second horizontal link line HLIA_G2.

[0214] Reference Figure 7 and Figure 8 The plurality of sub-pixels SP may include a plurality of first color sub-pixels SP_G emitting light of a first color among the plurality of colors. A light emitting region of each of the plurality of first color sub-pixels SP_G may be disposed in a plurality of first color sub-pixel rows G_SPL (ie, G_SPL1 to G_SPL1_3).

[0215] Reference Figure 7 and Figure 8 , the first horizontal link line HLIA_G1 may correspond to one first color sub-pixel row G_SPL1 among the plurality of first color sub-pixel rows G_SPL1 to G_SPL1_3. In addition, the second horizontal link line HLIA_G2 may correspond to another first color sub-pixel row G_SPL5 among the plurality of first color sub-pixel rows G_SPL1 to G_SPL13.

[0216] Reference Figure 7 and Figure 8 , the plurality of first color sub-pixel rows G_SPL1 to G_SPL1_3 may include two or more additional first color sub-pixel rows G_SPL2 , G_SPL3 , and G_SPL4 disposed between one first color sub-pixel row G_SPL1 and another first color sub-pixel row G_SPL5 .

[0217] The active area AA may include a central area Ac, a first area A1, and a second area A2, and the first area A1 may be located on one side of the central area Ac in the row direction, and the second area A2 may be located on the other side of the central area Ac in the row direction (see Figure 5 ).

[0218] Both the first data line DL_G1 and the second data line DL_G2 may be arranged in the first area A1 or the second area A2 located at one side of the central area Ac.

[0219] Reference Figure 7 and Figure 8, the first vertical link line VLIA_G1 may be electrically connected to the first pad PD of the plurality of pads PD, and the first horizontal link line HLIA_G1 may electrically connect the first vertical link line VLIA_G1 with the first data line DL_G1.

[0220] Reference Figure 7 and Figure 8 , the second vertical link line VLIA_G2 may be electrically connected to the second pad PD of the plurality of pads PD, and the second horizontal link line HLIA_G2 may electrically connect the second vertical link line VLIA_G2 with the second data line DL_G2.

[0221] Reference Figure 7 and Figure 8 , the first data line DL_G1 may supply the first data voltage to one first color sub-pixel SP_G among the first color sub-pixels SP_G included in one first color sub-pixel row G_SPL1 .

[0222] Reference Figure 7 and Figure 8 , the second data line DL_G2 may supply the second data voltage to one of the first color sub-pixels SP_G included in another first color sub-pixel row G_SPL5.

[0223] Reference Figure 7 and Figure 8 , the plurality of gate lines GL may include at least one first gate line GLa corresponding to the first horizontal link line HLIA_G1 and at least one second gate line GLb corresponding to the second horizontal link line HLIA_G2 .

[0224] Reference Figure 7 and Figure 8 , at least a portion of the first horizontal link line HLIA_G1 may overlap with at least one first gate line GLa, and at least a portion of the second horizontal link line HLIA_G2 may overlap with at least one second gate line GLb.

[0225] Reference Figure 7 and Figure 8 , the length of the first horizontal link wire HLIA_G1 may be shorter than the length of the second horizontal link wire HLIA_G2, and the length of the first vertical link wire VLIA_G1 may be shorter than the length of the second vertical link wire VLIA_G2.

[0226] The plurality of sub-pixels SP may further include a plurality of second color sub-pixels SP_R emitting light of a second color among the plurality of color lights and a plurality of third color sub-pixels SP_B emitting light of a third color among the plurality of color lights.

[0227] The plurality of second color sub-pixels SP_R may include at least one second color sub-pixel SP_R disposed between one first color sub-pixel row G_SPL1 and another first color sub-pixel row G_SPL5 .

[0228] The plurality of third color sub-pixels SP_B may include at least one third color sub-pixel SP_B disposed between one first color sub-pixel row G_SPL1 and another first color sub-pixel row G_SPL5 .

[0229] At least one second color sub-pixel SP_R and at least one third color sub-pixel SP_B may be arranged adjacent to each other in a column direction (or a row direction).

[0230] The plurality of data lines DL may include a third data line DL_RB1 for alternately supplying a data voltage to at least one second color sub-pixel SP_R and at least one third color sub-pixel SP_B.

[0231] The plurality of link lines LINK may further include a third link line LINK_RB1 electrically connected to the third data line DL_RB1. The third link line LINK_RB1 may include a fifth line LIA_RB1 disposed in the active area AA and a sixth line LIN_RB1 disposed in the first non-active area NA1. The fifth line LIA_RB1 may include a third vertical link line VLIA_RB1 extending in a vertical direction and a third horizontal link line HLIA_RB1 extending in a horizontal direction.

[0232] The third vertical link line VLIA_RB1 may be electrically connected to a third pad PD among the plurality of pads PD, and the third horizontal link line HLIA_RB_1 may electrically connect the third vertical link line VLIA_RB_1 with the third data line DL_RB1 .

[0233] Reference Figure 7 and Figure 8 , the third horizontal link line HLIA_RB1 may be disposed between the first horizontal link line HLIA_G1 and the second horizontal link line HLIA_G2 .

[0234] Reference Figure 7 , the third horizontal link line HLIA_RB1 may be disposed closer to the first horizontal link line HLIA_G1 of the first horizontal link line HLIA_G1 and the second horizontal link line HLIA_G2.

[0235] Reference Figure 8 , the third horizontal link line HLIA_RB1 may be disposed closer to the second horizontal link line HLIA_G2 of the first horizontal link line HLIA_G1 and the second horizontal link line HLIA_G2.

[0236] The plurality of sub-pixels SP may include a plurality of unit pixels UP, and each of the plurality of unit pixels UP may include two first color sub-pixels SP_G, one second color sub-pixel SP_R, and one third color sub-pixel SP_B.

[0237] In the two first color sub-pixels SP_G, the one second color sub-pixel SP_R, and the one third color sub-pixel SP_B, at least one of the horizontal link line HLIA and the gate line GL may be disposed under the two first color sub-pixels SP_G.

[0238] Among the two first color sub-pixels SP_G, the one second color sub-pixel SP_R, and the one third color sub-pixel SP_B, the two first color sub-pixels SP_G may overlap with at least one of the horizontal link line HLIA and the gate line GL.

[0239] Reference Figure 7 and Figure 8 , the horizontal link lines HLIA_G1, HLIA_G2, HLIA_G3, and HLIA_G4 connected to the data lines DL_G1, DL_G2, DL_G3, and DL_G4 for supplying data voltages to the first color subpixels SP_G may be separated by a predetermined distance L. For example, the first horizontal link line HLIA_G1 and the second horizontal link line HLIA_G2 may be spaced apart by a predetermined distance L.

[0240] Reference Figure 7 and Figure 8 The predetermined distance L may be greater than twice the spacing between two adjacent first color subpixel rows G_SPL1 to G_SPL1_3. Here, the spacing between two adjacent first color subpixel rows G_SPL may correspond to the spacing K between two adjacent gate lines GL.

[0241] Reference Figure 7 and Figure 8 , a distance L between the first horizontal link line HLIA_G1 and the second horizontal link line HLIA_G2 may be greater than twice a distance K between two adjacent gate lines GL (ie, L>2*K).

[0242] Reference Figure 7 and Figure 8 , the third horizontal link line HLIA_RB1 can be set at any position between the first horizontal link line HLIA_G1 and the second horizontal link line HLIA_G2.

[0243] Reference Figure 7 and Figure 8According to an embodiment of the present disclosure, the display panel 110 may include: an active area AA capable of displaying an image, a non-active area NA located outside the active area AA and including a pad area PA, a first pad PD arranged in the pad area PA, a first data line DL_G1 arranged in the active area AA and extending in a column direction, a first horizontal link line HLIA_G1 arranged in the active area AA, extending in a row direction and electrically connected to the first data line DL_G1, and a first vertical link line VLIA_G1 arranged in the active area AA, extending in a column direction and electrically connecting the first horizontal link line HLIA_G1 to the first pad PD.

[0244] Reference Figure 7 and Figure 8 According to an embodiment of the present disclosure, the display panel 110 may further include: a second pad PD arranged in the pad area PA, a second data line DL_G2 arranged in the active area AA and extending in the column direction, a second horizontal link line HLIA_G2 arranged in the active area AA, extending in the row direction and electrically connected to the second data line DL_G2, and a second vertical link line VLIA_G2 arranged in the active area AA, extending in the column direction and electrically connecting the second horizontal link line HLIA_G2 to the second pad PD.

[0245] Reference Figure 7 and Figure 8 According to an embodiment of the present disclosure, the display panel 110 may further include: a first subpixel SP_G connected to the first data line DL_G1 and emitting light of the first color, a second subpixel SP_G connected to the second data line DL_G2 and emitting light of the first color, and two or more third subpixels SP_G connected to the first data line DL_G1 and arranged between the first horizontal link line HLIA_G1 and the second horizontal link line HLIA_G2, emitting light of the first color.

[0246] Reference Figure 7 and Figure 8 The display panel 110 according to an embodiment of the present disclosure may further include two or more fourth sub-pixels SP_G that are connected to the second data line DL_G2 and disposed between the first horizontal link line HLIA_G1 and the second horizontal link line HLIA_G2 and emit light of the first color.

[0247] Reference Figure 7 and Figure 8According to an embodiment of the present disclosure, the display panel 110 may further include: a third pad PD arranged in the pad area PA, a third data line DL_RB1 arranged in the active area AA and extending in the column direction, a third horizontal link line HLIA_RB1 arranged in the active area AA, extending in the row direction and electrically connected to the third data line DL_RB1, and a third vertical link line VLIA_RB1 arranged in the active area AA, extending in the column direction and electrically connecting the third horizontal link line HLIA_RB1 to the third pad PD.

[0248] Subpixels SP_R and SP_B connected to the third data line DL_RB1 may emit second color light (eg, red light or blue light) different from the first color light, and the third horizontal link line HLIA_RB1 may be disposed between the first and second horizontal link lines HLIA_G1 and HLIA_G2 .

[0249] Reference Figure 7 and Figure 8 , the display panel 110 according to an embodiment of the present disclosure may further include at least one first gate line GLa corresponding to the first horizontal link line HLIA_G1 and at least one second gate line GLb corresponding to the second horizontal link line HLIA_G2 .

[0250] Reference Figure 7 and Figure 8 , at least a portion of the first horizontal link line HLIA_G1 may overlap with at least one first gate line GLa, and at least a portion of the second horizontal link line HLIA_G2 may overlap with at least one second gate line GLb.

[0251] The active area AA may include a central area Ac, a first area A1, and a second area A2 adjacent to each other in a row direction. The first area A1 may be located at one side of the central area Ac. The second area A2 may be located at the other side of the central area Ac.

[0252] Both the first data line DL_G1 and the second data line DL_G2 may be located in the first area A1 or the second area A2. That is, both the first data line DL_G1 and the second data line DL_G2 may be located in the first area A1. Both the first data line DL_G1 and the second data line DL_G2 may be located in the second area A2.

[0253] Reference Figure 7 and Figure 8According to an embodiment of the present disclosure, the display panel 110 may include: an active area AA capable of displaying an image, a non-active area NA located outside the active area AA and including a pad area PA, a first pad PD arranged in the pad area PA, a first data line DL_G1 arranged in the active area AA and extending in a column direction, a first horizontal link line HLIA_G1 arranged in the active area AA, extending in a row direction and electrically connected to the first data line DL_G1, and a first vertical link line VLIA_G1 arranged in the active area AA, extending in a column direction and electrically connecting the first horizontal link line HLIA_G1 to the first pad PD.

[0254] Reference Figure 7 and Figure 8 According to an embodiment of the present disclosure, the display panel 110 may further include: a first gate line GLa arranged to overlap with the first horizontal link line HLIA_G1, a second pad PD arranged in the pad area PA, a second data line DL_G2 arranged in the active area AA and extending in the column direction, a second horizontal link line HLIA_G2 arranged in the active area AA, extending in the row direction and electrically connected to the second data line DL_G2, a second vertical link line VLIA_G2 arranged in the active area AA, extending in the column direction and electrically connecting the second horizontal link line HLIA_G2 to the second pad PD, and a second gate line GLb arranged to overlap with the second horizontal link line HLIA_G2.

[0255] Reference Figure 7 and 8 According to an embodiment of the present disclosure, the display panel 110 may further include an intermediate gate line ( Figure 7 GLc and GLd in Figure 8 GLc and GLe in ).

[0256] Reference Figure 7 and Figure 8 The display panel 110 according to the embodiment of the present disclosure may further include: a third pad PD disposed in the pad region, a third data line DL_RB1 disposed in the active region and extending in the column direction, a third horizontal link line HLIA_RB1 disposed in the active region, extending in the row direction and electrically connected to the third data line DL_RB1, a third vertical link line VLIA_RB1 disposed in the active region, extending in the column direction and electrically connecting the third horizontal link line HLIA_RB1 to the third pad PD, and a third gate line ( Figure 7 In GLe, Figure 8 GLd in.

[0257] Reference Figure 7 and Figure 8 , in the display panel 110 according to an embodiment of the present disclosure, the third horizontal link line HLIA_RB1 may be disposed between the first horizontal link line HLIA_G1 and the second horizontal link line HLIA_G2 .

[0258] Reference Figure 7 and Figure 8 , the third gate line ( Figure 7 In GLe, Figure 8 The gate line GLd) may be disposed between the first gate line GLa and the second gate line GLb.

[0259] Fig. 9 1 shows another data link structure for alleviating the oblique line crosstalk phenomenon of the display panel 110 according to an embodiment of the present disclosure. Fig.10 1 shows another data link structure for alleviating the oblique line crosstalk phenomenon of the display panel 110 according to an embodiment of the present disclosure. Fig.11 Another data link structure for alleviating the oblique line crosstalk phenomenon of the display panel 110 according to an embodiment of the present disclosure is shown. Fig.10 and Fig.11 It is shown in detail Fig. 9 However, hereinafter, description of the same contents as previously described may be omitted.

[0260] Reference Fig.10 and Fig.11 , the display panel 110 according to an embodiment of the present disclosure may include gate driving panel circuits GIPC1 and GIPC2 disposed in a non-active area NA which is an area outside the active area AA.

[0261] Reference Fig.10 and Fig.11 The gate driving panel circuits GIPC1 and GIPC2 may be circuits for outputting the scan signal SC to the gate line GL as the scan line SCL, and may be a gate in panel (GIP) type gate driving circuit 130.

[0262] Reference Figures 9 to 11 According to an embodiment of the present disclosure, the display panel 110 may further include a horizontal metal line NC_HLIA, which is arranged to extend in the row direction in the same manner as the first horizontal link line HLIA_G1, is located in the first metal layer in the same manner as the first horizontal link line HLIA_G1, and is spaced apart from the first horizontal link line HLIA_G1.

[0263] Reference Figures 9 to 11, the horizontal metal line NC_HLIA and the first horizontal link line HLIA_G1 may be metals formed together by patterning in the first metal layer. Even if the horizontal metal line NC_HLIA and the first horizontal link line HLIA_G1 are formed together in the first metal layer, they may be electrically separated.

[0264] Reference Figure 10 to Figure 11 , the horizontal metal line NC_HLIA may be electrically floating or electrically connected to a common driving voltage line (eg, VSSL).

[0265] Even though the horizontal metal line NC_HLIA and the first horizontal link line HLIA_G1 are formed together in the first metal layer, they may have different voltage states.

[0266] A data signal (ie, data voltage) is applied to the first horizontal link line HLIA_G1, but the horizontal metal line NC_HLIA may be in a floating state with no voltage or signal applied thereto, or may be in a state with a signal (or voltage) completely different from the data signal (or data voltage) applied thereto.

[0267] When a signal (or voltage) completely different from the data signal (or data voltage) is applied to the horizontal metal line NC_HLIA, for example, a signal that can change according to an image or a driving state (e.g., a data signal, a gate signal, etc.) is not applied to the horizontal metal line NC_HLIA, and a common driving voltage that does not change according to the image or the driving state may be applied to the horizontal metal line NC_HLIA.

[0268] For example, the common driving voltage may include a first common driving voltage VDD and a second common driving voltage VSS. In this case, the display panel 110 may include common driving voltage lines VDDL and VSSL for supplying the common driving voltage.

[0269] For example, Figure 10 to Figure 11 As shown, the second common driving voltage VSS may be applied to the horizontal metal line NC_HLIA. In this case, the display panel 110 may further include a second common driving voltage line VSSL for supplying the second common driving voltage VSS to the cathode electrode CAT corresponding to the common electrode.

[0270] When the horizontal metal line NC_HLIA is electrically connected to the second common driving voltage line VSSL for transmitting the second common driving voltage VSS, the connection position between the horizontal metal line NC_HLIA and the second common driving voltage line VSSL may be as follows: Fig.10 As shown, it is located in the non-active area NA, or it can be as shown Fig.11 The illustration is in the active area AA.

[0271] Reference Fig.10 , the horizontal metal line NC_HLIA may be electrically connected to the second common driving voltage line VSSL disposed in the non-active area NA through the external common voltage contact hole CNT_VSS_NA located in the non-active area NA. That is, the horizontal metal line NC_HLIA may be electrically connected to the second common driving voltage line VSSL in the non-active area NA.

[0272] Reference Fig.11 , the horizontal metal line NC_HLIA may be electrically connected to the second common driving voltage line VSSL disposed in the non-active area NA through the inner common voltage contact hole CNT_VSS_AA located in the active area AA. That is, the horizontal metal line NC_HLIA may be electrically connected to the second common driving voltage line VSSL in the active area AA.

[0273] In this case, if Fig.11 As shown, the horizontal metal line NC_HLIA may be electrically connected to the second common driving voltage line VSSL disposed in the non-active area NA through an external common voltage contact hole CNT_VSS_NA located in the non-active area NA.

[0274] Reference Figures 9 to 11 According to an embodiment of the present disclosure, the display panel 110 may further include a vertical metal line NC_VLIA, which is configured to extend in a column direction (e.g., a vertical direction) in the same manner as the first vertical link line VLIA_G1, is located in the second metal layer in the same manner as the first vertical link line VLIA_G1, and is spaced apart from the first vertical link line VLIA_G1.

[0275] Reference Figures 9 to 11 , the vertical metal line NC_VLIA may be configured in the same manner as the horizontal metal line NC_HLIA described above. However, the vertical metal line NC_VLIA may be disposed on a second metal layer different from the first metal layer on which the horizontal metal line NC_HLIA is disposed. Here, the second metal layer may be located on the first metal layer.

[0276] Reference Figures 9 to 11 , the vertical metal line NC_VLIA may be electrically connected to the second common driving voltage line VSSL in the same manner as the horizontal metal line NC_HLIA.

[0277] Reference Figures 9 to 11 , the vertical metal line NC_VLIA may be electrically floating, or may be electrically connected to the common driving voltage line VSSL.

[0278] Even though the vertical metal line NC_VLIA and the first vertical link line VLIA_G1 are formed together in the second metal layer, they may have different voltage states.

[0279] The data signal (or data voltage) is applied to the first vertical link line VLIA_G1 , but the vertical metal line NC_VLIA may be in a floating state where no voltage or signal is applied, or may be in a state where a signal (or voltage) completely different from the data signal (or data voltage) is applied.

[0280] When a signal (or voltage) completely different from the data signal (or data voltage) is applied to the vertical metal line NC_VLIA, for example, a signal (e.g., a data signal, a gate signal) that can change according to an image or a driving state may not be applied to the vertical metal line NC_VLIA, and a common driving voltage that does not change according to an image or a driving state may be applied to the vertical metal line NC_VLIA.

[0281] For example, the common driving voltage may include a first common driving voltage VDD and a second common driving voltage VSS. In this case, the display panel 110 may include common driving voltage lines VDDL and VSSL for supplying the common driving voltage.

[0282] For example, Figure 10 to Figure 11 As shown, the second common driving voltage VSS may be applied to the vertical metal line NC_VLIA. In this case, the display panel 110 may further include a second common driving voltage line VSSL for supplying the second common driving voltage VSS to the cathode CAT corresponding to the common electrode of the light emitting device ED constituting each of the plurality of sub-pixels SP.

[0283] If the vertical metal line NC_VLIA is electrically connected to a second common driving voltage line VSSL for transmitting a second common driving voltage VSS, the connection position between the vertical metal line NC_VLIA and the second common driving voltage line VSSL may be as follows: Fig.10 As shown, it is located in the non-active area NA, or it can be as shown Fig.11 The illustration is in the active area AA.

[0284] Reference Fig.10 , the vertical metal line NC_VLIA may be electrically connected to the second common driving voltage line VSSL disposed in the non-active area NA through the external common voltage contact hole CNT_VSS_NA located in the non-active area NA. That is, the vertical metal line NC_VLIA may be electrically connected to the second common driving voltage line VSSL in the non-active area NA.

[0285] Reference Fig.11, the vertical metal line NC_VLIA may be electrically connected to the second common driving voltage line VSSL disposed in the non-active area NA through the inner common voltage contact hole CNT_VSS_AA located in the active area AA. That is, the vertical metal line NC_VLIA may be electrically connected to the second common driving voltage line VSSL in the active area AA.

[0286] In this case, if Fig.11 As shown, the vertical metal line NC_VLIA may be electrically connected to the second common driving voltage line VSSL disposed in the non-active area NA through an external common voltage contact hole CNT_VSS_NA located in the non-active area NA.

[0287] like Figures 9 to 11 As shown, when the data link structure is formed, the remaining metal (e.g., horizontal metal line, vertical metal line) can be electrically connected to the second common driving voltage line VSSL, thereby reducing the resistance of the second common driving voltage line VSSL. In other words, the resistance on the transmission path of the second common driving voltage VSS can be reduced.

[0288] Figures 12 to 15 is a cross-sectional view illustrating a data link structure of the display panel 110 according to an embodiment of the present disclosure. Fig.12 yes Fig.10 A cross-sectional view of region AA′ in FIG. Fig.13 yes Fig.10 A cross-sectional view of region BB′ in FIG. Fig.14 yes Fig.10 A cross-sectional view of region CC′ in FIG. Fig.15 yes Fig.11 Cross-sectional view of the contact area CA in FIG.

[0289] Reference Figures 12 to 15 , the display panel 110 according to an embodiment of the present disclosure may include a first metal layer ML1 and a second metal layer ML2 to form a data link structure. An insulating layer 1270 may be disposed between the first metal layer ML1 and the second metal layer ML2.

[0290] Reference Figures 12 to 15 , the display panel 110 may include a first buffer layer 1210 on the substrate 111 , a first gate insulating film 1220 on the first buffer layer 1210 , and a first interlayer insulating film 1230 on the first gate insulating film 1220 .

[0291] Reference Figures 12 to 15 , the display panel 110 may include a second buffer layer 1240 on the first interlayer insulating film 1230 , a second gate insulating film 1250 on the second buffer layer 1240 , and a second interlayer insulating film 1260 on the second gate insulating film 1250 .

[0292] Reference Figures 12 to 15 , the first semiconductor material layer may be disposed above or below the first gate insulating film 1220. The second semiconductor material layer may be disposed above or below the second gate insulating film 1250. Here, the first semiconductor material disposed in the first semiconductor material layer and the second semiconductor material disposed in the second semiconductor material layer may be different from each other. For example, the first semiconductor material may be a polycrystalline silicon semiconductor material, and the second semiconductor material may be an oxide semiconductor material. For example, the polycrystalline silicon semiconductor material may be low temperature polycrystalline silicon (LTPS).

[0293] Reference Figures 12 to 15 , the display panel 110 may include a first metal layer ML1 on the second interlayer insulating film 1260 , a first planarization layer 1270 on the first metal layer ML1 , a second metal layer ML2 on the first planarization layer 1270 , and a second planarization layer 1280 on the second metal layer ML2 .

[0294] Reference Figures 12 to 15 The first metal layer ML1 may be a metal layer on which lines extending in a row direction (eg, a horizontal direction) are disposed, and the second metal layer ML2 may be a metal layer on which lines extending in a column direction (eg, a vertical direction) are disposed.

[0295] Reference Figures 12 to 15 , the first metal layer ML1 may be a metal layer on which lines parallel to the gate line GL are disposed, and the second metal layer ML2 may be a metal layer on which lines parallel to the data line DL are disposed.

[0296] Reference Figures 12 to 15 , the first metal layer ML1 may be a metal layer provided with horizontal link lines (e.g., HLIA_RB1, HLIA_G2) and horizontal metal lines NC_HLIA. The second metal layer ML2 may be a metal layer provided with data lines (e.g., DL_RB1), vertical link lines (e.g., VLIA_RB1, VLIA_G2) and vertical metal lines NC_VLIA. The second metal layer ML2 may be a metal layer on which a second common driving voltage line VSSL is further provided.

[0297] Reference Figures 12 to 15 , the horizontal link line HLIA (e.g., HLIA_RB1 and HLIA_G2) included in each of the plurality of link lines LINK may be located in a first metal layer ML1 on a layer where a plurality of gate lines GL are disposed, and the vertical link line VLIA (e.g., VLIA_RB1 and VLIA_G2) included in each of the plurality of link lines LINK may be located in a second metal layer ML2 on the first metal layer ML1.

[0298] Reference Fig.12 , in the active area AA, the third vertical link line VLIA_RB1 may be electrically connected to the third horizontal link line HLIA_RB1 through the link line connection hole CNT_LIA which is a contact hole of the first planarization layer 1270 .

[0299] Reference Fig.12 , in the active area AA, the third data line DL_RB1 may be electrically connected to the third horizontal link line HLIA_RB1 through the data line connection hole CNT_DL which is a contact hole of the first planarization layer 1270 .

[0300] Reference Fig.12 , the third vertical link line VLIA_RB1 and the third data line DL_RB1 may be disposed in the second metal layer ML2 , and the third horizontal link line HLIA_RB1 may be disposed in the first metal layer ML1 .

[0301] Reference Fig.12 , the data voltage VDATA may be supplied to the sub-pixels SP_R and SP_B connected to the third data line DL_RB1 through the third vertical link line VLIA_RB1 , the third horizontal link line HLIA_RB1 , and the third data line DL_RB1 .

[0302] Reference Fig.12 , the third vertical link line VLIA_RB1 and the third horizontal link line HLIA_RB1 may be disposed in the active area AA.

[0303] Reference Fig.13 , in the active area AA, the second vertical link line VLIA_G2 may be electrically connected to the second horizontal link line HLIA_G2 through the link line connection hole CNT_LIA which is a contact hole of the first planarization layer 1270 .

[0304] Reference Fig.13 , the second vertical link line VLIA_G2 and the second horizontal link line HLIA_G2 may be disposed in the active area AA.

[0305] Reference Fig.13 , in the non-active area NA, the second common driving voltage line VSSL may be electrically connected to the horizontal metal line NC_HLIA through the outer common voltage contact hole CNT_VSS_NA which is a contact hole of the first planarization layer 1270 .

[0306] Reference Fig.13 , the second vertical link line VLIA_G2 and the second common driving voltage line VSSL may be disposed in the second metal layer ML2 , and the second horizontal link line HLIA_G2 and the horizontal metal line NC_HLIA may be disposed in the first metal layer ML1 .

[0307] Reference Fig.14 , in the non-active area NA, the second common driving voltage line VSSL may be electrically connected to the horizontal metal line NC_HLIA through the outer common voltage contact hole CNT_VSS_NA which is a contact hole of the first planarization layer 1270 .

[0308] Reference Fig.14 , the horizontal metal line NC_HLIA may extend to the active area AA.

[0309] Reference Fig.14 , the horizontal metal line NC_HLIA may intersect and overlap with the data line VLIA_G2 extending in a column direction (eg, a vertical direction).

[0310] Reference Fig.15 , in the active area AA, the vertical metal line NC_VLIA may be electrically connected to the horizontal metal line NC_HLIA through the external common voltage contact hole CNT_VSS_AA which is a contact hole of the first planarization layer 1270 .

[0311] Reference Fig.15 , at least one of the vertical metal line NC_VLIA and the horizontal metal line NC_HLIA may be electrically connected to the second common driving voltage line VSSL disposed in the non-active area NA.

[0312] Reference Fig.15 , the vertical metal line NC_VLIA may be disposed in the second metal layer ML2 , and the horizontal metal line NC_HLIA may be disposed in the first metal layer ML1 .

[0313] Fig.16 Show according to Figure 6 The tilted line crosstalk phenomenon of the data link structure.

[0314] Reference Fig.16 , as in Figure 6 In the data link structure of , when the horizontal link line HLIA connected to the vertical link line VLIA is arranged for one or two pixel rows, a dark point DP and a bright point BP may appear for each unit pixel at or near the inclined line SLT_DL. Here, one pixel row may include unit pixels PU arranged in the row direction.

[0315] Reference Fig.16 , one or two pixel rows may correspond to one gate line GL. That is, each horizontal link line HLIA may correspond to one gate line GL.

[0316] Reference Fig.16, each horizontal link line HLIA may overlap with the gate line GL. Therefore, a dark dot DP and a bright dot BP may be generated at the moment when the voltage level of the scan signal SC applied to the gate line GL changes. For example, when the voltage level of the scan signal SC rises, a dark dot DP may appear. When the voltage level of the scan signal SC drops, a bright dot BP may appear.

[0317] Reference Fig.16 , when the display panel 110 has Figure 6 When the data link structure is formed, the horizontal link line HLIA has a narrow first gap L1. Here, the first gap L1 may correspond to a gap or spacing between two adjacent pixel rows, a gap or spacing between the first pixel row and the third pixel row, or a gap or spacing between two adjacent gate lines GL, or a gap or spacing between the first gate line GL and the third gate line GL.

[0318] As described above, if the display panel 110 has Figure 6 In the data link structure, the horizontal link line HLIA has a narrow first gap L1, so that for each or two pixel rows, dark dots DP and bright dots BP may appear along the inclined line SLT_DL. Therefore, the user can very clearly identify the dark dots DP and bright dots BP generated along the inclined line SLT_DL. Therefore, the user can easily identify serious image defects.

[0319] Fig.17 Show according to Figures 7 to 11 The tilted line crosstalk phenomenon of the data link structure.

[0320] Reference Fig.17 , as in Figures 7 to 11 In the data link structure of , if a horizontal link line HLIA connected to a vertical link line VLIA is arranged for each of more than three pixel rows, a dark point DP and a bright point BP may be generated for each unit pixel at or near the inclined line SLT_DL. Here, one pixel row may include unit pixels PU arranged in the row direction.

[0321] Reference Fig.17 More than three pixel rows may correspond to more than three gate lines GL. That is, each horizontal link line HLIA may correspond to one gate line GL.

[0322] Reference Fig.17 , some of the gate lines GL may overlap with the horizontal link line HLIA, and some of the gate lines GL do not overlap with the horizontal link line HLIA.

[0323] Reference Fig.17At the moment when the voltage level of the scanning signal SC applied to the gate line GL changes, a dark spot DP and a bright spot BP may be generated at a position corresponding to the gate line GL overlapping the horizontal link line HLIA. For example, when the voltage level of the scanning signal SC rises, a dark spot DP may appear. When the voltage level of the scanning signal SC drops, a bright spot BP may appear.

[0324] However, at the time when the voltage level of the scan signal SC applied to the gate line GL is changed, the dark dot DP and the bright dot BP do not appear at the position corresponding to the gate line GL which does not overlap with the horizontal link line HLIA.

[0325] Therefore, refer to Fig.17 , if the display panel 110 has Figures 7 to 11 The horizontal link line HLIA has a second gap L2 wider than the first gap L1. Here, the second gap L2 may be wider than the first gap L1 by at least the gap P between two adjacent pixel rows (ie, L2≥L1+P).

[0326] Therefore, if the display panel 110 has Figures 7 to 11 The second gap L2 of the horizontal link line HLIA is Figure 6 The narrow first gap L1 in the data link structure of FIG. 1 is wide, so that for each of more than three pixel rows, dark dots DP and bright dots BP may appear sporadically along the inclined line SLT_DL. Therefore, the dark dots DP and bright dots BP generated along the inclined line SLT_DL may not be easily recognized by the user.

[0327] The embodiments of the present disclosure described above are briefly described as follows.

[0328] According to an embodiment of the present disclosure, a display device may include: an active area capable of displaying an image, an inactive area located outside the active area and including a pad area, a first pad arranged in the pad area, a first data line arranged in the active area and extending in a column direction, a first horizontal link line arranged in the active area, extending in a row direction and electrically connected to the first data line, a first vertical link line arranged in the active area, extending in a column direction and electrically connecting the first horizontal link line to the first pad, a second pad arranged in the pad area, a second data line arranged in the active area and extending in a column direction, a second horizontal link line arranged in the active area, extending in a row direction and electrically connected to the second data line, a second vertical link line arranged in the active area, extending in a column direction and electrically connecting the second horizontal link line to the second pad, a first sub-pixel connected to the first data line and emitting light of a first color, a second sub-pixel connected to the second data line and emitting light of the first color, and two or more sub-pixel rows that emit light of the first color and are arranged between the first horizontal link line and the second horizontal link line.

[0329] The active area may include a central area, a first area, and a second area adjacent to each other in a row direction, the first area may be located on one side of the central area, and the second area may be located on the other side of the central area. Both the first data line and the second data line may be located in one of the first area and the second area.

[0330] The display device according to an embodiment of the present disclosure may further include at least one first gate line corresponding to the first horizontal link line and at least one second gate line corresponding to the second horizontal link line.

[0331] At least a portion of the first horizontal link line may overlap with at least one first gate line, and at least a portion of the second horizontal link line may overlap with at least one second gate line.

[0332] The length of the first horizontal link line may be shorter than the length of the second horizontal link line, and the length of the first vertical link line may be shorter than the length of the second vertical link line.

[0333] The display device according to an embodiment of the present disclosure may also include a plurality of third sub-pixels emitting light of a second color or a third color different from light of the first color, a third data line for supplying a data voltage to the third sub-pixels, a third pad arranged in the pad area, a third horizontal link line arranged in the active area, extending in the row direction and electrically connected to the third data line, and a third vertical link line arranged in the active area, extending in the column direction and electrically connecting the third data line to the third pad.

[0334] The third horizontal link line may be disposed between the first horizontal link line and the second horizontal link line.

[0335] The third horizontal link line may be disposed closer to the first horizontal link line of the first horizontal link line and the second horizontal link line or may be disposed closer to the second horizontal link line of the first horizontal link line and the second horizontal link line.

[0336] The first and second horizontal link lines may be located in a first metal layer on a layer where the gate line is disposed, and the first and second vertical link lines may be located in a second metal layer on the first metal layer.

[0337] The display device according to an embodiment of the present disclosure may also include a common driving voltage line for supplying a common driving voltage to a common electrode of a light-emitting device in each of the first sub-pixel and the second sub-pixel, and a horizontal metal line that is arranged to extend in a row direction, is located in the first metal layer, and is spaced apart from the first horizontal link line.

[0338] The horizontal metal lines may be electrically floating or electrically connected to a common driving voltage line.

[0339] The horizontal metal line may be electrically connected to the common driving voltage line in the inactive region, or may be electrically connected to the common driving voltage line in the active region.

[0340] The display device according to an embodiment of the present disclosure may also include a common driving voltage line for supplying a common driving voltage to a common electrode of a light-emitting device in each of the first sub-pixel and the second sub-pixel, and a vertical metal line arranged to extend in a column direction, located in the second metal layer, and spaced apart from the first vertical link line.

[0341] The vertical metal lines may be electrically floating or electrically connected to a common driving voltage line.

[0342] The vertical metal line may be electrically connected to the common driving voltage line in the inactive region, or may be electrically connected to the common driving voltage line in the active region.

[0343] The display device according to the embodiment of the present disclosure may further include a third gate line disposed between the first horizontal link line and the second horizontal link line.

[0344] In the display device according to the embodiment of the present disclosure, there may be no horizontal link line overlapping the third gate line.

[0345] According to an embodiment of the present disclosure, a display panel may include: an active area capable of displaying an image, an inactive area located outside the active area and including a pad area, a first pad arranged in the pad area, a first data line arranged in the active area and extending in a column direction, a first horizontal link line arranged in the active area, extending in a row direction and electrically connected to the first data line, a first vertical link line arranged in the active area, extending in a column direction and electrically connecting the first horizontal link line to the first pad, a first gate line overlapping the first horizontal link line, a second pad arranged in the pad area, a second data line arranged in the active area and extending in a column direction, a second horizontal link line arranged in the active area, extending in a row direction and electrically connecting the second data line, a second vertical link line arranged in the active area, extending in a column direction and electrically connecting the second horizontal link line to the second pad, a second gate line overlapping the second horizontal link line, and a third gate line arranged between the first gate line and the second gate line and not overlapping with any of the horizontal link lines.

[0346] The display panel according to an embodiment of the present disclosure may further include a common driving voltage line for supplying a common driving voltage to a common electrode of a light-emitting device of each sub-pixel, and a horizontal metal line arranged to extend in a row direction in the first metal layer and spaced apart from the first horizontal link line.

[0347] The horizontal metal lines may be electrically floating or electrically connected to a common driving voltage line.

[0348] The display panel according to an embodiment of the present disclosure may further include a common driving voltage line for supplying a common driving voltage to a common electrode of a light-emitting device of each sub-pixel, and a vertical metal line arranged to extend in a column direction, located in the second metal layer, and spaced apart from the first vertical link line.

[0349] The vertical metal lines may be electrically floating or electrically connected to a common driving voltage line.

[0350] According to an embodiment of the present disclosure, a display device may include: an active area capable of displaying an image, an inactive area located outside the active area and including a pad area, a first pad arranged in the pad area, a first data line arranged in the active area and extending in a column direction, a first horizontal link line arranged in the active area, extending in a row direction and electrically connected to the first data line, a first vertical link line arranged in the active area, extending in a column direction and electrically connecting the first horizontal link line to the first pad, and a common driving voltage line for supplying a common driving voltage to a common electrode of a light-emitting device of each sub-pixel.

[0351] According to an embodiment of the present disclosure, the display device may further include: at least one of a horizontal metal line arranged to extend in a row direction, located in a first metal layer and spaced apart from a first horizontal link line, and a vertical metal line arranged to extend in a column direction, located in a second metal layer and spaced apart from a first vertical link line.

[0352] The horizontal metal lines are electrically floating or electrically connected to a common driving voltage line, and the vertical metal lines are electrically floating or electrically connected to a common driving voltage line.

[0353] According to an embodiment of the present disclosure, the display device may further include: a first gate line overlapping with the first horizontal link line, a second pad arranged in the pad area, a second data line arranged in the active area and extending in the column direction, a second horizontal link line arranged in the active area, extending in the row direction and electrically connected to the second data line, a second vertical link line arranged in the active area, extending in the column direction and electrically connecting the second horizontal link line to the second pad, a second gate line overlapping with the second horizontal link line, and a third gate line arranged between the first gate line and the second gate line and not overlapping with any of the horizontal link lines.

[0354] According to the embodiments of the present disclosure, a display panel and a display device having a data link structure for reducing a bezel may be provided.

[0355] According to the embodiments of the present disclosure, a display panel and a display device having a data link structure capable of reducing image abnormality caused by crosstalk between a link line and a gate line may be provided.

[0356] According to the embodiments of the present disclosure, a display panel and a display device having a data link structure capable of reducing impedance in a transmission path of a common driving voltage may be provided.

[0357] According to an embodiment of the present disclosure, the weight of a display panel and a display device may be reduced by reducing a bezel through a data link structure.

[0358] The above description and accompanying drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. In addition, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiments shown.

Claims

1. A display device, comprising: an active area, the active area being capable of displaying an image; a non-active region, the non-active region being located outside the active region and including a pad region; a first pad, the first pad being disposed in the pad region; a first data line disposed in the active area and extending in a column direction; a first horizontal link line disposed in the active region, extending in a row direction, and electrically connected to the first data line; a first vertical link line, which is disposed in the active region, extends in the column direction, and electrically connects the first horizontal link line and the first pad; a second pad, the second pad being disposed in the pad region; a second data line disposed in the active region and extending in the column direction; a second horizontal link line disposed in the active region, extending in the row direction, and electrically connected to the second data line; a second vertical link line, the second vertical link line being disposed in the active region, extending in the column direction, and electrically connecting the second horizontal link line and the second pad; a first sub-pixel connected to the first data line and emitting light of a first color; a second sub-pixel connected to the second data line and emitting light of the first color; as well as Two or more sub-pixel rows emit light of the first color and are disposed between the first horizontal link line and the second horizontal link line.

2. The display device according to claim 1, wherein: The active region includes a central region, a first region, and a second region adjacent to each other in the row direction, wherein the first area is located on one side of the central area, and the second area is located on the other side of the central area, and The first data line and the second data line are both located in one of the first area and the second area.

3. The display device according to claim 1, further comprising: at least one first gate line, the at least one first gate line corresponding to the first horizontal link line; as well as at least one second gate line, the at least one second gate line corresponding to the second horizontal link line, Wherein, at least a portion of the first horizontal link line overlaps with the at least one first gate line, and at least a portion of the second horizontal link line overlaps with the at least one second gate line.

4. The display device according to claim 1, wherein: The length of the first horizontal link line is shorter than the length of the second horizontal link line, and the length of the first vertical link line is shorter than the length of the second vertical link line.

5. The display device according to claim 1, further comprising: a plurality of third sub-pixels emitting light of a second color or light of a third color different from the light of the first color; a third data line, the third data line being used to supply a data voltage to the third sub-pixel; a third pad, the third pad being arranged in the pad region; a third horizontal link line disposed in the active region, extending in the row direction, and electrically connected to the third data line; as well as a third vertical link line, the third vertical link line being disposed in the active region, extending in the column direction, and electrically connecting the third data line and the third pad, Wherein, the third horizontal link line is arranged between the first horizontal link line and the second horizontal link line.

6. The display device according to claim 5, wherein: The third horizontal link line is disposed closer to the first horizontal link line of the first horizontal link line and the second horizontal link line.

7. The display device according to claim 5, wherein: The third horizontal link line is disposed closer to the second horizontal link line of the first horizontal link line and the second horizontal link line.

8. The display device according to claim 1, wherein: The first horizontal link line and the second horizontal link line are located in a first metal layer on a layer where a gate line is disposed, and The first vertical link line and the second vertical link line are located in a second metal layer on the first metal layer.

9. The display device according to claim 1, further comprising: a common driving voltage line for supplying a common driving voltage to a common electrode of the light emitting device of each of the first sub-pixel and the second sub-pixel; as well as a horizontal metal line arranged to extend in the row direction, located in the first metal layer, and spaced apart from the first horizontal link line, Wherein, the horizontal metal line is electrically floating or electrically connected to the common driving voltage line.

10. The display device according to claim 9, wherein: The horizontal metal line is electrically connected to the common driving voltage line in the inactive region.

11. The display device according to claim 9, wherein: The horizontal metal line is electrically connected to the common driving voltage line in the active region.

12. The display device according to claim 1, further comprising: a common driving voltage line for supplying a common driving voltage to a common electrode of the light emitting device of each of the first sub-pixel and the second sub-pixel; as well as a vertical metal line, the vertical metal line being arranged to extend in the column direction, being located in the second metal layer, and being spaced apart from the first vertical link line, Wherein, the vertical metal line is electrically floating or electrically connected to the common driving voltage line.

13. The display device according to claim 12, wherein: The vertical metal line is electrically connected to the common driving voltage line in the inactive region.

14. The display device according to claim 12, wherein: The vertical metal line is electrically connected to the common driving voltage line in the active region.

15. The display device according to claim 1, wherein: Also includes: a third gate line, the third gate line being disposed between the first horizontal link line and the second horizontal link line, Wherein, the horizontal link lines do not overlap with the third gate lines.

16. A display panel, comprising: an active area, the active area being capable of displaying an image; a non-active region, the non-active region being located outside the active region and including a pad region; a first pad, the first pad being disposed in the pad region; a first data line disposed in the active area and extending in a column direction; a first horizontal link line disposed in the active region, extending in a row direction, and electrically connected to the first data line; a first vertical link line, which is disposed in the active region, extends in the column direction, and electrically connects the first horizontal link line and the first pad; a first gate line, the first gate line overlapping the first horizontal link line; a second pad, the second pad being disposed in the pad region; a second data line disposed in the active region and extending in the column direction; a second horizontal link line disposed in the active region, extending in the row direction, and electrically connected to the second data line; a second vertical link line, the second vertical link line being disposed in the active region, extending in the column direction, and electrically connecting the second horizontal link line and the second pad; a second gate line, the second gate line overlapping the second horizontal link line; as well as A third gate line is disposed between the first gate line and the second gate line and does not overlap with any horizontal link line.

17. The display panel according to claim 16, further comprising: a common driving voltage line for supplying a common driving voltage to a common electrode of a light emitting device of each sub-pixel; as well as a horizontal metal line arranged to extend in the row direction, located in the first metal layer, and spaced apart from the first horizontal link line, Wherein, the horizontal metal line is electrically floating or electrically connected to the common driving voltage line.

18. The display panel according to claim 16, further comprising: a common driving voltage line for supplying a common driving voltage to a common electrode of a light emitting device of each sub-pixel; as well as a vertical metal line, the vertical metal line being arranged to extend in the column direction, being located in the second metal layer, and being spaced apart from the first vertical link line, Wherein, the vertical metal line is electrically floating or electrically connected to the common driving voltage line.

19. The display panel according to claim 1, further comprising: A non-active area link line is disposed in the non-active area and is integrally formed with or electrically connected to one or both of the first vertical link line and the second vertical link line.

20. A display device, comprising: an active area, the active area being capable of displaying an image; a non-active region, the non-active region being located outside the active region and including a pad region; a first pad, the first pad being disposed in the pad region; a first data line disposed in the active area and extending in a column direction; a first horizontal link line disposed in the active region, extending in a row direction, and electrically connected to the first data line; a first vertical link line, which is disposed in the active region, extends in the column direction, and electrically connects the first horizontal link line and the first pad; as well as a common driving voltage line for supplying a common driving voltage to a common electrode of a light emitting device of each sub-pixel, Wherein, the display device further includes at least one of the following items: a horizontal metal line arranged to extend in the row direction, located in the first metal layer, and spaced apart from the first horizontal link line, wherein the horizontal metal line is electrically floating or electrically connected to the common driving voltage line; and A vertical metal line is arranged to extend in the column direction, is located in the second metal layer, and is spaced apart from the first vertical link line, wherein the vertical metal line is electrically floating or electrically connected to the common driving voltage line.

21. The display device according to claim 20, further comprising: a first gate line, the first gate line overlapping the first horizontal link line; a second pad, the second pad being disposed in the pad region; a second data line disposed in the active region and extending in the column direction; a second horizontal link line disposed in the active region, extending in the row direction, and electrically connected to the second data line; a second vertical link line, which is disposed in the active region, extends in the column direction, and electrically connects the second horizontal link line and the second pad; a second gate line, the second gate line overlapping the second horizontal link line; as well as A third gate line is disposed between the first gate line and the second gate line and does not overlap with any horizontal link line.

Images