Display device

Abstract

A display device is provided. A display device according to one or more embodiments of the present disclosure includes a plurality of unit pixel regions arranged in a first direction and a second direction and in which a first thin film transistor and a second thin film transistor are positioned, a valley portion, and a cover layer, and a valley portion at a boundary of the unit pixel region, extending in the first direction, at least partially extending in the second direction, and penetrating at least some of the plurality of insulating layers, a capping layer positioned to overlap the valley portion and positioned to cover an inner sidewall of the valley portion, the capping layer is located on a portion of the valley portion adjacent to a semiconductor region of one of the unit pixel regions where the second active layer is located and between the second active layer and the organic insulating material in the valley portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0147099 filed in the Korean Intellectual Property Office on October 30, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of the present disclosure relate to a display device. Background Art

[0004] As the information society develops, the demand for display devices for displaying images increases and diversifies. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. In such a flat panel display device, since each of the pixels of the display panel includes a light emitting element that can emit light by itself, the light emitting display device can display an image without a backlight unit that provides light to the display panel.

[0005] The display device may also include pixels emitting predetermined light, scan lines, data lines and power lines for driving the pixels, a scan driver outputting scan signals to the scan lines, and a display driver outputting data voltages to the data lines. The above information disclosed in this background technology section is only for enhancing understanding of the background of the present invention, and therefore it may contain information that does not form the prior art. Summary of the invention

[0006] According to some embodiments of the present disclosure, a display device capable of preventing damage to a circuit element caused by an external impact and preventing degradation of the circuit element is provided.

[0007] However, aspects of the present disclosure are not limited to the aspects described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0008] According to some embodiments of the present disclosure, a display device is provided, the display device including a plurality of unit pixel regions, a valley portion and a covering layer, the plurality of unit pixel regions being arranged in a first direction and in a second direction intersecting the first direction and having first and second thin film transistors positioned therein, each of the first thin film transistors including a first active layer, and each of the second thin film transistors including a second active layer at a different layer from the first active layer and including an oxide semiconductor, the valley portion extending at a boundary of the unit pixel region, in the first direction, at least partially extending in the second direction and penetrating at least some of a plurality of insulating layers overlapping with the first and second thin film transistors, at least a portion of the valley portion overlapping with the second active layer in a horizontal direction, the covering layer being positioned to overlap with the valley portion and to cover an inner sidewall of the valley portion, the covering layer being on a portion of the valley portion adjacent to a semiconductor region of one of the unit pixel regions in which the second active layer is positioned and between the second active layer and an organic insulating material in the valley portion.

[0009] In one or more embodiments, the shortest distance between the capping layer and the second active layer may be about 10 μm or less.

[0010] In one or more embodiments, the capping layer may include SiN x 、SiO x and SiO x N y At least one of .

[0011] In one or more embodiments, the display device may further include a plurality of lines electrically connected to at least one of the first and second thin film transistors and extending in the first direction or the second direction, wherein at least a portion of the valley portion overlaps any one of the lines.

[0012] In one or more embodiments, a depth of a portion of the valley portion that does not overlap with the wires may be greater than a depth of at least a portion of the valley portion that overlaps with any of the wires.

[0013] In one or more embodiments, the covering layer may include a first covering pattern on an inner sidewall of the valley portion, and a second covering pattern that is not connected to the first covering pattern and is positioned on a line overlapping the valley portion.

[0014] In one or more embodiments, the valley portion may be configured to extend in the first direction and the second direction to surround the unit pixel region, and the cover layer may include a portion overlapping the valley portion and extending in the first direction and the second direction.

[0015] In one or more embodiments, the second active layer may be adjacent to a portion of the valley portion extending in the second direction, and the capping layer may be on the portion of the valley portion extending in the second direction.

[0016] In one or more embodiments, a width of the capping layer measured in the second direction may be substantially the same as a width of the semiconductor region measured in the second direction.

[0017] In one or more embodiments, the portion of the cover layer extending in the first direction may be positioned on the portion of the valley portion extending in the first direction, and the cover layer may not be positioned on at least a portion of the portion of the valley portion extending in the first direction.

[0018] In one or more embodiments, the cover layer may be configured to extend in the first direction and the second direction to surround the unit pixel region.

[0019] In one or more embodiments, the valley portion may include a portion extending in a first direction, and a portion protruding in a second direction from the portion extending in the first direction and positioned at a boundary of the unit pixel area, and the valley portion and the covering layer may not be positioned between semiconductor regions of the unit pixel areas arranged in the first direction.

[0020] In one or more embodiments, the display device may further include a gate electrode on the second active layer, and a step pattern positioned at the same layer as the gate electrode and overlapping a portion of the valley portion extending in the second direction. The capping layer may be on and in direct contact with the step pattern.

[0021] In one or more embodiments, a portion of the valley portion on the step pattern has a smaller depth than other portions, and the capping layer on the step pattern may not overlap with the second active layer in a horizontal direction.

[0022] According to some embodiments of the present disclosure, a display device is provided, the display device including a plurality of unit pixel regions and a valley portion, the plurality of unit pixel regions are arranged in a first direction and a second direction intersecting the first direction and wherein a first thin film transistor and a second thin film transistor are positioned, each of the first thin film transistors includes a first active layer, and each of the second thin film transistors includes a second active layer at a different layer from the first active layer and including an oxide semiconductor, the valley portion extends in the first direction at a boundary of the unit pixel region, at least partially extends in the second direction, and penetrates at least some of a plurality of insulating layers overlapping the first thin film transistor and the second thin film transistor. The second active layer is adjacent to one side of the unit pixel region, and on one side of the unit pixel region adjacent to the semiconductor region where the second active layer is positioned, the valley portion is formed so as not to penetrate a gate insulating layer covering the second active layer.

[0023] In one or more embodiments, the valley portion may include a portion extending in the first direction, and a portion protruding in the second direction from the portion extending in the first direction and positioned at a boundary of the unit pixel region.

[0024] In one or more embodiments, the valley portion may not be formed between the semiconductor regions of the unit pixel regions arranged in the first direction.

[0025] In one or more embodiments, the display device may further include a gate electrode overlapping the second active layer, and a step pattern positioned at the same layer as the gate electrode and overlapping a portion of the valley portion extending in the second direction. The valley portion may be configured to extend in the first direction and the second direction to surround the unit pixel area.

[0026] In one or more embodiments, a portion of the valley portion positioned on the step pattern may have a smaller depth than other portions.

[0027] In one or more embodiments, the step pattern may be positioned on the gate insulating layer covering the second active layer. The valley portion may not penetrate the gate insulating layer overlapping the step pattern.

[0028] The display device according to some embodiments may include a valley portion surrounding an area where a pixel circuit is arranged, and a covering layer covering an inner sidewall of the valley portion. The valley portion may absorb external impact, and the covering layer may prevent gas generated from the organic insulating material from moving to adjacent circuit elements. Accordingly, the display device may prevent or substantially reduce damage to the circuit element due to external impact and degradation of the circuit element due to gas.

[0029] In addition, when the display device has flexible characteristics, cracks that may be formed in a plurality of insulating layers disposed on a substrate when the substrate is folded may be prevented by the valley portion.

[0030] The effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 shows a perspective view of a display device according to some embodiments of the present disclosure;

[0033] Figure 2 Some embodiments of the present disclosure are shown Figure 1 A plan view of a display device;

[0034] Figure 3 The following diagram shows some embodiments of the present disclosure. Figure 2 A cross-sectional view taken along line A-A';

[0035] Figure 4 shows a plan view of a display panel according to some embodiments of the present disclosure;

[0036] Figure 5 shows a pixel circuit diagram of a sub-pixel according to some embodiments of the present disclosure;

[0037] Figure 6 shows a pixel circuit diagram of a sub-pixel according to some embodiments of the present disclosure;

[0038] Figure 7 A plan view showing an arrangement of a plurality of pixel circuits arranged in a display area of ​​a display device according to some embodiments of the present disclosure;

[0039] Figure 8 The arrangement according to some embodiments of the present disclosure is shown in Figure 7 A plan view of a pixel circuit in a unit pixel area;

[0040] Fig. 9 The following diagram shows some embodiments of the present disclosure. Figure 8 A cross-sectional view taken along line IX-IX';

[0041] Fig.10 shows a plan view illustrating an arrangement of a unit pixel region and a semiconductor layer region of a display device according to some embodiments of the present disclosure;

[0042] Fig.11 The following diagram shows some embodiments of the present disclosure. Fig.10 A cross-sectional view taken along line XI-XI';

[0043] Fig.12 The following diagram shows some embodiments of the present disclosure. Fig.10 A cross-sectional view taken along line XII-XII';

[0044] Fig.13 shows a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure;

[0045] Fig.14 The following diagram shows some embodiments of the present disclosure. Fig.13 A cross-sectional view taken along line A1-A1';

[0046] Fig.15 shows a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure;

[0047] Fig.16shows a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure;

[0048] Fig.17 The following diagram shows some embodiments of the present disclosure. Fig.16 A cross-sectional view taken along line A2-A2';

[0049] Fig.18 shows a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure;

[0050] Fig.19 The following diagram shows some embodiments of the present disclosure. Fig.18 A cross-sectional view taken along line A3-A3';

[0051] Fig. 20 shows a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure;

[0052] Fig.21 The following diagram shows some embodiments of the present disclosure. Fig. 20 A cross-sectional view taken along line A4-A4';

[0053] Fig. 22 shows a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure; and

[0054] Fig.23 The following diagram shows some embodiments of the present disclosure. Fig. 22 A cross-sectional view taken along line A5-A5'. DETAILED DESCRIPTION

[0055] Hereinafter, the present disclosure will now be described more fully with reference to the accompanying drawings in which embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0056] It will also be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0057] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure.

[0059] Reference Figure 1 The display device 10 is a device that displays moving images or still images, and can be used as a display screen for various suitable products such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-thin mobile PCs (UMPCs).

[0060] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, some embodiments in which the display device 10 is an organic light-emitting display device have been described, but the type of the display device 10 is not limited thereto.

[0061] In some embodiments, the display device 10 may be formed to be flat. For example, the display device 10 may be formed to be substantially flat on a plane defined by the first direction DR1 and the second direction DR2, and may have a preset thickness (or height) in the third direction DR3. In another embodiment, the display device 10 may include a bent portion in at least a portion thereof including an edge region or the like. In addition, the display device 10 may be flexibly formed to be bent, curved, folded, or curled.

[0062] In some embodiments, the first direction DR1 may be a longitudinal direction, a column direction, or a vertical direction, and the second direction DR2 is a direction crossing the first direction DR1 and may be, for example, a transverse direction, a row direction, or a horizontal direction based on the image display surface of the display device 10. The third direction DR3 may be a thickness direction or a height direction of the display device 10.

[0063] The display device 10 may include a display panel 100 , a driver 200 , and a circuit board 300 .

[0064] The display panel 100 may include a main area MA including a display area DA displaying an image, and a sub area SBA positioned on one side of the main area MA.

[0065] The main area MA may include a display area DA and a non-display area NA positioned around the display area DA. The display area DA may be positioned at the center of the main area MA and may occupy most of the main area MA. The non-display area NA may be positioned at an edge of the main area MA and may contact the sub-area SBA.

[0066] The display area DA is a region where pixels (eg, Figure 4 The display area DA may be a region where pixels PX are displayed, and may be a region where images are displayed by the pixels PX. In some embodiments, the display area DA may also be provided with a sensing pattern (e.g., a touch electrode) for sensing a touch input, etc., and may include a sensing region for sensing a touch input through the sensing pattern.

[0067] In some embodiments, the display area DA may be formed in a substantially rectangular shape including long sides in the first direction DR1 and short sides in the second direction DR2 in a plan view. Corner portions where the long sides and short sides of the display area DA intersect may be rounded or right-angled. The shape of the display area DA may be variously changed in an appropriate manner according to the embodiment. For example, the display area DA may also be formed in other polygonal shapes, circular shapes, elliptical shapes, or the like other than the rectangular shape.

[0068] The non-display area NA may be positioned immediately around the display area DA. The non-display area NA may surround the display area DA. The embedded circuit may be arranged in the non-display area NA (i.e., positioned in or located in the non-display area NA). For example, an embedded circuit including a scan driving circuit and the like may be arranged in the non-display area NA positioned on one side (e.g., the left side or the right side) or both sides of the display area DA.

[0069] The sub-region SBA may be positioned on one side of the main region MA. For example, the sub-region SBA may be a region protruding from one side of the main region MA in the first direction DR1. As an example, the sub-region SBA may protrude from the lower end of the main region MA in the first direction DR1. In some embodiments, the sub-region SBA may have a width smaller than that of the main region MA. For example, based on the second direction DR2, the sub-region SBA may have a width smaller than that of the main region MA.

[0070] Lines and pads may be arranged in the sub-area SBA. For example, lines and pads connected to pixels and / or embedded circuits positioned in the main area MA and the driver 200 and / or circuit board 300 positioned in the sub-area SBA may be arranged in the sub-area SBA. When describing the embodiments, the term "connection" may include the meaning of electrical connection and / or physical connection.

[0071] In some embodiments, the driver 200 (eg, a display driving circuit) may be mounted in the sub-area SBA. The circuit board 300 may be disposed on a portion of the sub-area SBA.

[0072] The driver 200 may include a data driving circuit for driving pixels. In some embodiments, the driver 200 may be formed as an integrated circuit (IC) and arranged in the sub-area SBA. In another embodiment, the driver 200 may be arranged on a circuit board 300 located on the sub-area SBA, or on another circuit board connected to the display panel 100 through the circuit board 300.

[0073] The circuit board 300 may be arranged on a portion of the sub-area SBA. For example, the circuit board 300 may be bonded to a pad positioned at a portion (e.g., a lower edge) of the sub-area SBA, and may supply or transmit a source voltage and a driving signal for driving the display panel 100 to the display panel 100. For example, the circuit board 300 may supply input image data (e.g., digital image data), a driving signal including a timing signal, and a driving voltage to the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as a chip on film (COF), but is not limited thereto.

[0074] Figure 2 is a diagram showing some embodiments of the present disclosure Figure 1 A plan view of a display device. Figure 3 According to some embodiments of the present disclosure Figure 2 A cross-sectional view taken along line AA'.

[0075] Figure 1 shows a state in which the display device 10 is not bent but straightened, and Figure 2 and Figure 3 A state in which the display device 10 is bent in the sub-area SBA is shown. Figure 1 shows a state in which the sub-area SBA is stretched parallel to the main area MA, and Figure 2 and Figure 3 A state in which a part of the sub-area SBA is bent is shown.

[0076] Reference Figure 2 and Figure 3, the display panel 100 may include a substrate 110 including a main area MA and a sub-area SBA, a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140 sequentially arranged on the substrate 110. The circuit layer 120 may be positioned in the main area MA and the sub-area SBA on the substrate 110. The light emitting element layer 130 and the encapsulation layer 140 may be positioned on portions of the substrate 110 and the circuit layer 120. For example, the light emitting element layer 130 and the encapsulation layer 140 may be positioned in the main area MA.

[0077] In some embodiments, the display device 10 may further include additional components disposed on the display panel 100. For example, the display device 10 may further include at least one of a sensor layer (e.g., a touch sensor layer), a polarizing layer, a color filter layer, and a protective layer (e.g., a window) disposed on the encapsulation layer 140. Each of the sensor layer, the polarizing layer, the color filter layer, and the protective layer may be manufactured integrally with the display panel 100, or may be manufactured separately from the display panel 100 and attached to the display panel 100 via an adhesive layer or the like.

[0078] The substrate 110 may include an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide or other insulating materials. The substrate 110 may be a flexible substrate that is deformable (e.g., bent, folded, and curled). In some embodiments, the substrate 110 may include an insulating material such as glass.

[0079] The circuit layer 120 may include pixel circuits and lines. For example, the circuit layer 120 may include circuit elements (e.g., pixel transistors and capacitors) constituting the pixel circuits of each of the pixels and lines connected to the pixels. In some embodiments, the circuit layer 120 may also include circuit elements constituting embedded circuits (such as scan drive circuits) and lines connected to the embedded circuits.

[0080] The light emitting element layer 130 may include light emitting elements arranged in the emission regions of the pixels. For example, each of the pixels may include at least one light emitting element and a pixel circuit connected to the light emitting element. Each of the pixels may be positioned in a corresponding pixel region including an emission region in which the light emitting element is arranged and a pixel circuit region in which the pixel circuit is arranged. The emission region and the pixel circuit region of each pixel may overlap each other, but are not limited thereto.

[0081] In describing some embodiments, the circuit layer 120 and the light emitting element layer 130 have been described separately, but the embodiments are not limited thereto. For example, the circuit layer 120 and the light emitting element layer 130 may be integrated with each other.

[0082] The encapsulation layer 140 may cover the light emitting element layer 130 and extend to the non-display area NA to contact the circuit layer 120. In some embodiments, the encapsulation layer 140 may have a multilayer structure including at least two inorganic encapsulation films overlapping each other and at least one organic encapsulation film interposed therebetween.

[0083] In some embodiments, the display panel 100 may be bent in the bending area BA. The bending area BA may be a portion of the sub area SBA and may be spaced apart from the main area MA.

[0084] The substrate 110 and the circuit layer 120 may be bent in the bending area BA corresponding to a partial section of the sub-area SBA. Accordingly, a bezel area recognized as the non-display area NA by a user may be reduced or minimized.

[0085] Figure 4 is a plan view showing a display panel according to some embodiments. Figure 4 A state in which the display panel 100 is not bent but straightened is shown.

[0086] Reference Figure 4 , the display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NA, and the sub-area SBA may include a bank area BNKA, a driving circuit mounting area ICA, a pad area PA, and the like.

[0087] The display area DA may be an area where a plurality of pixels PX (hereinafter also referred to as unit pixels PX) are arranged. The pixels PX and lines (or parts of the lines) connected to the pixels PX may be arranged in the display area DA.

[0088] The pixels PX may be provided in the circuit layer 120 and the light emitting element layer 130 of the display panel 100. As an example, each pixel PX may include a pixel circuit including circuit elements arranged in the circuit layer 120 (eg, Figure 5 or Figure 6 The pixel circuit PCA) and the light emitting elements (eg, Figure 5 or Figure 6 light-emitting element EL).

[0089] The pixel PX may include at least two sub-pixels SPX emitting light of different colors. For example, the pixel PX may include a first color sub-pixel SPX1 emitting light of a first color (e.g., red light), a second color sub-pixel SPX2 emitting light of a second color (e.g., green light), and a third color sub-pixel SPX3 emitting light of a third color (e.g., blue light).

[0090] At least one first color sub-pixel SPX1, at least one second color sub-pixel SPX2, and at least one third color sub-pixel SPX3 adjacent to each other may constitute one unit pixel PX. For example, one first color sub-pixel SPX1, two second color sub-pixels SPX2, and one third color sub-pixel SPX3 adjacent to each other may constitute one unit pixel PX. Each unit pixel PX may emit light of various appropriate colors including white light by mixing the colors of light emitted from the sub-pixels SPX1, SPX2, and SPX3 constituting each unit pixel PX with each other. In some embodiments, the first color sub-pixel SPX1 and the third color sub-pixel SPX3 may be alternately arranged in the first direction DR1 and / or the second direction DR2, and the second color sub-pixel SPX2 may be continuously and / or sequentially arranged in the first direction DR1. The types, shapes, arrangement structures, etc. of the sub-pixels SPX1, SPX2, and SPX3 may be variously changed in an appropriate manner according to some embodiments. In addition, the type, number, ratio, arrangement structure, etc. of the sub-pixels SPX1, SPX2 and SPX3 constituting each unit pixel PX may also be variously changed in an appropriate manner according to some embodiments.

[0091] The encapsulation layer 140 may be disposed on the pixel PX. For example, the encapsulation layer 140 may be provided at least in the display area DA to cover the pixel PX, and a portion of the encapsulation layer 140 may extend to the non-display area NA.

[0092] The wire may be provided in the circuit layer 120 and may be positioned in the display area DA and the non-display area NA. In addition, the wire may also be positioned in the sub-area SBA. For example, the wire may extend from the sub-area SBA through the non-display area NA to the display area DA.

[0093] The non-display area NA may be positioned around the display area DA. For example, the non-display area NA may be an edge area of ​​the main area MA positioned outside the display area DA.

[0094] The non-display area NA may include a dam area DAMA spaced apart from the display area DA, a first non-display area NA1 positioned between the display area DA and the dam area DAMA, and a second non-display area NA2 positioned outside the dam area DAMA. The dam area DAMA may be an area where a dam surrounding the display area DA is arranged. The second non-display area NA2 may include an inorganic encapsulation area IEA (also referred to as a "bonding area") where inorganic encapsulation films of the encapsulation layer 140 are bonded to each other.

[0095] The sub-area SBA may include a bank area BNKA, a driving circuit mounting area ICA, and a pad area PA sequentially arranged on one side of the main area MA. Lines (or parts of lines), banks, and pads PD may be arranged in the sub-area SBA. At least some of the lines may extend to the main area MA to be connected to the pixels PX.

[0096] The bank area BNKA may be an area where a bank including at least one organic film is arranged. In some embodiments, the bank area BNKA may include a curved area BA. For example, the bank area BNKA may include a curved area BA spaced apart from the main area MA, and a first edge area BEA1 and a second edge area BEA2 respectively positioned on both sides of the curved area BA in the first direction DR1. The bank may be provided in the curved area BA and its surrounding areas (e.g., the first edge area BEA1 and the second edge area BEA2 of the bank area BNKA) to cover a line passing through the curved area BA. The display panel 100 may be bent in the curved area BA so that a portion of the sub-area SBA may be positioned behind the main area MA.

[0097] The driving circuit mounting area ICA may be an area where the driver 200 is arranged. Pads for connecting at least some lines to the driver 200 may be arranged in the driving circuit mounting area ICA. For example, input pads for connecting the driver 200 to specific pads (e.g., data input pads) of the pad area PA and output pads for connecting the driver 200 to the pixels PX may be arranged in the driving circuit mounting area ICA.

[0098] In some embodiments, the driver 200 may not be disposed on the display panel 100. In this case, the display panel 100 may not include the driving circuit mounting area ICA, and only wires may be disposed in an area between the bank area BNKA and the pad area PA.

[0099] The pad area PA may be an area where pads PD for connecting the display panel 100 and / or the driver 200 to the circuit board 300, etc. are arranged. The circuit board 300 may be arranged on the pad area PA or bonded to the pad area PA.

[0100] A plurality of pads PD including power pads and signal pads connected to the pixels PX, the driver 200, the embedded circuit, etc. may be arranged in the pad area PA. A source voltage for driving the pixels PX, the driver 200, the embedded circuit, etc. may be supplied to the power pads. A driving signal and / or image data for driving the pixels PX, the driver 200, the embedded circuit, etc. may be supplied to the signal pads. According to some embodiments, the type, position, arrangement order, number, etc. of the pads PD may be variously changed in an appropriate manner.

[0101] Figure 5is a pixel circuit diagram of a sub-pixel according to some embodiments of the present disclosure. Figure 6 is a pixel circuit diagram of a sub-pixel according to some embodiments of the present disclosure.

[0102] Figure 5 and Figure 6 Various embodiments related to the pixel circuit PCA and the lines connected to the pixel circuit PCA are shown. The configuration of the pixel circuit PCA and the type and number of lines connected to the pixel circuit PCA may be variously changed in an appropriate manner according to the embodiment.

[0103] exist Figure 5 In some embodiments, each pixel circuit PCA includes a first transistor T1 to a seventh transistor T7. Figure 5 The scan lines SL connected to the sub-pixel SPX may include a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fourth scan line SL4. Figure 5 The power lines PL connected to the sub-pixel SPX may include a first pixel power line VDL, a second pixel power line VSL, a first initialization power line VIL, and a second initialization power line VAIL. Figure 5 The sub-pixel SPX may be connected to the emission control line ECL.

[0104] exist Figure 6 In some embodiments, each pixel circuit PCA includes a first transistor T1 to an eighth transistor T8. Figure 6 The scan lines SL connected to the sub-pixel SPX may include a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fifth scan line SL5. Figure 6 The power lines PL connected to the sub-pixel SPX may include a first pixel power line VDL, a second pixel power line VSL, a first initialization power line VIL, a second initialization power line VAIL, and a bias power line VOBL. Figure 6 The sub-pixel SPX may be connected to the emission control line ECL.

[0105] Reference Figure 5 , the sub-pixel SPX may include a light emitting unit EMU including at least one light emitting element EL and a pixel circuit PCA (also referred to as a “pixel driving unit”) connected to the light emitting unit EMU.

[0106] The light emitting element EL may be connected between a second pixel power supply line VSL to which a second pixel source voltage ELVSS is applied and the pixel circuit PCA. In some embodiments, the second pixel source voltage ELVSS may be a low potential pixel driving voltage. The light emitting element EL may be a light source of the sub-pixel SPX and may emit light by receiving a driving current supplied from the pixel circuit PCA.

[0107] The light emitting element EL may be an organic light emitting diode, but is not limited thereto. For example, the light emitting element EL may be an inorganic light emitting element, a quantum dot light emitting element, or other types of light emitting elements.

[0108] The pixel circuit PCA can control the light emission timing and brightness of the light emitting element EL by controlling the driving current supplied to the light emitting element EL. The pixel circuit PCA may include at least one pixel transistor T and a capacitor Cst. In some embodiments, the pixel circuit PCA may include a pixel transistor T including a first transistor T1 to a seventh transistor T7.

[0109] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode electrically connected to the first pixel power line VDL through a fifth transistor T5, and a second electrode electrically connected to the light emitting unit EMU through a sixth transistor T6. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode. The first transistor T1 may control a source-drain current (hereinafter referred to as a "driving current") flowing between the first electrode and the second electrode according to a voltage applied to the gate electrode (e.g., a voltage of the first node N1 corresponding to a voltage of a data signal). For example, the first transistor T1 may be a driving transistor of the sub-pixel SPX.

[0110] The second transistor T2 may include a gate electrode connected to the first scan line SL1, a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the first transistor T1. The second transistor T2 may be turned on by a first scan signal supplied to the first scan line SL1 to electrically connect the first electrode of the first transistor T1 and the data line DL to each other. When the second transistor T2 is turned on, the voltage of the data signal supplied to the data line DL may be applied to the first electrode of the first transistor T1.

[0111] The third transistor T3 may include a gate electrode connected to the second scan line SL2, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the gate electrode (or the first node N1) of the first transistor T1. The third transistor T3 may be turned on by a second scan signal supplied to the second scan line SL2 to electrically connect the gate electrode and the second electrode of the first transistor T1 to each other. When the third transistor T3 is turned on, the first transistor T1 may be driven as a diode.

[0112] The fourth transistor T4 may include a gate electrode connected to the third scan line SL3, a first electrode connected to the gate electrode of the first transistor T1, and a second electrode connected to the first initialization power line VIL. The fourth transistor T4 may be turned on by the third scan signal supplied to the third scan line SL3 to electrically connect the gate electrode of the first transistor T1 and the first initialization power line VIL to each other. When the fourth transistor T4 is turned on, the first initialization voltage VINT (e.g., gate initialization voltage) of the first initialization power line VIL may be applied to the gate electrode of the first transistor T1.

[0113] The fifth transistor T5 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a first pixel power line VDL, and a second electrode connected to a first electrode of the first transistor T1. The fifth transistor T5 may be turned on by an emission control signal supplied to the emission control line ECL to electrically connect the first electrode of the first transistor T1 and the first pixel power line VDL to which the first pixel source voltage ELVDD is applied to each other. When the fifth transistor T5 is turned on, the first pixel source voltage ELVDD may be applied to the first electrode of the first transistor T1. In some embodiments, the first pixel source voltage ELVDD may be a high potential pixel driving voltage.

[0114] The sixth transistor T6 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a second electrode of the first transistor T1, and a second electrode connected to the light emitting element EL. The sixth transistor T6 may be turned on by an emission control signal supplied to the emission control line ECL to electrically connect the first transistor T1 and the light emitting element EL to each other. When both the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current having a magnitude corresponding to a voltage of the gate electrode of the first transistor T1 may flow to the light emitting element EL.

[0115] The seventh transistor T7 may include a gate electrode connected to the fourth scan line SL4, a first electrode connected to the anode of the light emitting element EL, and a second electrode connected to the second initialization power line VAIL. The seventh transistor T7 may be turned on by a fourth scan signal supplied to the fourth scan line SL4 to electrically connect the anode of the light emitting element EL and the second initialization power line VAIL to each other. The fourth scan signal may be a signal that is the same as or different from the first scan signal. When the seventh transistor T7 is turned on, a second initialization voltage VAINT (e.g., an anode initialization voltage) of the second initialization power line VAIL may be applied to the anode of the light emitting element EL.

[0116] The capacitor Cst may be connected between the gate electrode of the first transistor T1 and the first pixel power line VDL. The capacitor Cst may be charged with a voltage corresponding to a voltage of a data signal applied to the gate electrode of the first transistor T1.

[0117] The active layer (e.g., a semiconductor pattern including a channel region) of each of the pixel transistors T (e.g., the first transistor T1 to the seventh transistor T7) may include one semiconductor material among polycrystalline silicon, amorphous silicon, and an oxide semiconductor. In some embodiments, some of the pixel transistors T may be formed as transistors of a different conductivity type from other pixel transistors T. In addition, some of the pixel transistors T may include semiconductor materials of a different type from other pixel transistors T.

[0118] For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed as P-type transistors (e.g., P-type metal oxide semiconductor field effect transistors (MOSFETs)) including corresponding active layers made of polysilicon, and the third transistor T3 and the fourth transistor T4 may be formed as N-type transistors (e.g., N-type MOSFETs) including corresponding active layers made of oxide semiconductors. In some embodiments, transistors including corresponding active layers made of polysilicon and transistors including corresponding active layers made of oxide semiconductors may be arranged at different layers within the circuit layer 120.

[0119] In addition to reference Figure 5 In addition, refer to Figure 6 , the pixel circuit PCA may further include an eighth transistor T8. The eighth transistor T8 may include a gate electrode connected to the fifth scan line SL5, a first electrode connected to the bias power line VOBL, and a second electrode connected to the first electrode of the first transistor T1. The eighth transistor T8 may be turned on by the fifth scan signal supplied to the fifth scan line SL5 to electrically connect the first electrode of the first transistor T1 and the bias power line VOBL to each other. When the eighth transistor T8 is turned on, the bias voltage VOBS supplied to the bias power line VOBL may be applied to the first electrode of the first transistor T1. In some embodiments, the bias voltage VOBS may have a voltage level suitable for compensating for the hysteresis characteristic of the first transistor T1. When the eighth transistor T8 is turned on, the first electrode of the first transistor T1 may be initialized to the bias voltage VOBS.

[0120] exist Figure 6 In some embodiments, the gate electrode of the seventh transistor T7 may be connected to the fifth scan line SL5. Accordingly, the seventh transistor T7 may be turned on by the fifth scan signal supplied to the fifth scan line SL5 to connect the anode of the light emitting element EL to the second initialization power line VAIL.

[0121] Figure 7 is a plan view of an arrangement of a plurality of pixel circuits arranged in a display area of ​​a display device according to some embodiments of the present disclosure. Figure 8 According to some embodiments of the present disclosure, Figure 7A plan view of a pixel circuit in a unit pixel area.

[0122] Reference Figure 7 and Figure 8 , the display device 10 may include a plurality of pixel circuits PXC arranged in the display area DA: PXC1, PXC2, PXC3, and PXC4. Each of the plurality of pixel circuits PXC may be electrically connected to the sub-pixels SPX1, SPX2, and SPX3 (see, for example, Figure 4 ) in the pixel circuit PXC. An electrical signal for allowing the light emitting element EL to emit light may be applied to a plurality of circuit elements included in the pixel circuit PXC.

[0123] A plurality of pixel circuits PXC may be arranged in the first direction DR1 and the second direction DR2. For example, two pixel circuits PXC adjacent to each other in the second direction DR2 may constitute one unit pixel region UPX: UPX1, UPX2, UPX3, or UPX4. The unit pixel regions UPX: UPX1, UPX2, UPX3, and UPX4 may be arranged in the first direction DR1 and the second direction DR2. The first pixel circuit PXC1 and the second pixel circuit PXC2 adjacent to each other in the second direction DR2 may constitute one first unit pixel region UPX1. The third pixel circuit PXC3 and the fourth pixel circuit PXC4 adjacent to each other in the second direction DR2 may constitute one second unit pixel region UPX2. The first unit pixel region UPX1 and the second unit pixel region UPX2 may be arranged in the first direction DR1. The third unit pixel region UPX3 and the fourth unit pixel region UPX4 may also each include two pixel circuits adjacent to each other in the second direction DR2, and may be arranged in the first direction DR1. The first unit pixel region UPX1 may be arranged in the second direction DR2 with the third unit pixel region UPX3. The second unit pixel region UPX2 may be aligned with the fourth unit pixel region UPX4 in the second direction DR2.

[0124] The plurality of lines, conductive patterns, and semiconductor layers constituting the pixel circuit may include the same or substantially the same pattern repeated based on one unit pixel region UPX instead of the pixel circuit. For example, the arrangement structure of the lines, conductive patterns, and semiconductor layers in the first unit pixel region UPX1 may be the same or substantially the same as the arrangement structure of the lines, conductive patterns, and semiconductor layers in the second unit pixel region UPX2, the third unit pixel region UPX3, and the fourth unit pixel region UPX4. The first pixel circuit PXC1 and the second pixel circuit PXC2 may each have a structure in which the arrangement of the conductive patterns and semiconductor layers is symmetrical or substantially symmetrical to each other, and the patterns of the conductive patterns and semiconductor layers constituting the two pixel circuits PXC1 and PXC2 may be repeatedly arranged throughout the entire display area DA.

[0125] According to some embodiments, the display device 10 may include a valley portion VA arranged to surround a unit pixel region UPX. The valley portion VA may surround one unit pixel region UPX, and may surround a plurality of unit pixel regions UPX throughout the entire display area DA. The valley portion VA may be arranged at a boundary of a plurality of unit pixel regions UPX arranged in the first direction DR1 and the second direction DR2. The valley portion VA may be arranged to extend in the first direction DR1 and the second direction DR2, and two pixel circuits PXC may be arranged in a region surrounded by the valley portion VA when portions of the valley portion VA extending in the first direction DR1 and the second direction DR2 intersect each other. A plurality of unit pixel regions UPX may be arranged to be spaced apart from each other across the valley portion VA, and may be isolated in a region surrounded by the valley portion VA.

[0126] The valley portion VA may be formed to penetrate an interlayer insulating layer disposed between a plurality of conductive layers and semiconductor layers constituting the pixel circuit PXC. The valley portion VA may prevent an external impact applied to the display device 10 from being transmitted to elements of the pixel circuit. In addition, the display device 10 may prevent cracks that may be formed in a plurality of insulating layers when the display device 10 including the flexible substrate 110 is folded by including the valley portion VA surrounding an area where the pixel circuit PXC is disposed.

[0127] Fig. 9 According to some embodiments of the present disclosure Figure 8 A cross-sectional view taken along line IX-IX'. Fig. 9 A cross section of a portion of the display area DA corresponding to an area where one unit pixel area UPX is located is schematically shown. Fig. 9 A cross section crossing a portion of the first pixel circuit PXC1 and the second pixel circuit PXC2 adjacent to each other in the second direction DR2 is shown.

[0128] Reference Fig. 9 , the display panel 100 may include a substrate 110 and a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140 disposed on the substrate 110. The circuit layer 120, the light emitting element layer 130, and the encapsulation layer 140 may be sequentially disposed or stacked on the substrate 110 along the third direction DR3.

[0129] The substrate 110 may be made of a material having a flexible property so as to be able to be bent, folded, or rolled. The substrate 110 may be made of an insulating material such as a polymer resin. As an example, the substrate 110 may be made of polyimide.

[0130] The circuit layer 120 may include pixel circuits PXC and lines. For example, the circuit layer 120 may include circuit elements (e.g., pixel transistors T and capacitors Cst) constituting the pixel circuits PXC of each of the sub-pixels SPX and lines (e.g., various power lines and signal lines including power lines PL, scan lines SL, emission control lines ECL, and data lines DL) electrically connected to the sub-pixels SPX.

[0131] Fig. 9 The first thin film transistor TFT1 (also referred to as "first pixel transistor"), the second thin film transistor TFT2 (also referred to as "second pixel transistor"), and the capacitor Cst included in the pixel circuit PXC of each sub-pixel SPX are shown among the elements that can be provided in the circuit layer 120. The first thin film transistor TFT1 may be a representative of a first type transistor (e.g., a P-type transistor) including a first semiconductor material (e.g., polysilicon) among the pixel transistors T constituting each pixel circuit PXC. For example, the first thin film transistor TFT1 may be one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. Fig. 9 In the embodiment, one transistor (eg, a first connection electrode CNE1 and a second connection electrode CNE2) among the first type transistors is connected to the light emitting element EL through at least one connection electrode (eg, a first connection electrode CNE1 and a second connection electrode CNE2). Figure 5 or Figure 6 The sixth transistor T6 of the pixel transistor T is shown as the first thin film transistor TFT1. The second thin film transistor TFT2 may be a representative of a second type transistor (e.g., an N-type transistor) including a second semiconductor material (e.g., an oxide semiconductor) among the pixel transistors T. For example, the second thin film transistor TFT2 may be one of the third transistor T3 and the fourth transistor T4.

[0132] The cross-section of the subpixel SPX may be variously changed in an appropriate manner according to the type, structure, etc. of the corresponding subpixel SPX and the display panel 100 including the corresponding pixel PX. For example, the position, formation order, etc. of the first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may be changed according to the embodiment.

[0133] The circuit layer 120 may include semiconductor layers and conductive layers for forming circuit elements, lines, etc., and insulating films arranged between and / or around the conductive layers and the semiconductor layers. For example, the circuit layer 120 may include a first semiconductor layer SCL1 (e.g., a polysilicon semiconductor layer), a first insulating layer 123 (e.g., a first gate insulating layer), a first conductive layer CDL1 (e.g., a first gate conductive layer), a second insulating layer 124 (e.g., a second gate insulating layer), a second conductive layer CDL2 (e.g., a second gate conductive layer), a third insulating layer 125 (e.g., a first interlayer insulating layer), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 126 (e.g., a third gate insulating layer), a third conductive layer CDL3 (e.g., a third gate conductive layer), a fifth insulating layer 127 (e.g., a second interlayer insulating layer), a fourth conductive layer CDL4 (e.g., a first source-drain conductive layer), and a sixth insulating layer 128 (e.g., a first through-hole layer or a first planarization layer) sequentially arranged on the substrate 110 in the third direction DR3. In some embodiments, the circuit layer 120 may further include a fifth conductive layer CDL5 (e.g., a second source-drain conductive layer) and a seventh insulating layer 129 (e.g., a second via layer or a second planarization layer) sequentially disposed on the sixth insulating layer 128. In some embodiments, the circuit layer 120 may further include a bottom conductive layer BCDL disposed between the substrate 110 and the first semiconductor layer SCL1, a barrier layer 121 disposed between the substrate 110 and the bottom conductive layer BCDL, and a buffer layer 122 disposed between the bottom conductive layer BCDL and the first semiconductor layer SCL1.

[0134] The barrier layer 121 may be disposed on the substrate 110. The barrier layer 121 may protect the elements disposed in the circuit layer 120 and the light emitting element layer 130 from moisture penetrating through the substrate 110 which may be susceptible to moisture penetration. The barrier layer 121 may include at least one inorganic film including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating material). According to the embodiment, the material of the barrier layer 121 may be variously changed in an appropriate manner.

[0135] The bottom conductive layer BCDL may be disposed on the barrier layer 121. The bottom conductive layer BCDL may include a bottom metal layer BML overlapping an active layer (eg, a first active layer ACT1 and / or a second active layer ACT2) of at least one pixel transistor T and / or at least one wire (or a portion of at least one wire). Fig. 92 has shown that the bottom metal layer BML is arranged to overlap only the first active layer ACT1 of the first thin film transistor TFT1 and the capacitor electrodes CAE1 and CAE2 of the capacitor Cst, but the present disclosure is not limited thereto. For example, the bottom metal layer BML may also be patterned in an appropriate size and / or shape as needed and arranged only in a portion of the pixel circuit PXC or may be arranged throughout the entire pixel circuit PXC. As an example, the bottom metal layer BML may also be arranged only in a portion of the pixel area to overlap with the first active layer ACT1 of the first thin film transistor TFT1 and the capacitor electrodes CAE1 and CAE2 of the capacitor Cst. Figure 5 and Figure 6 In some embodiments, the bottom metal layer BML may also be used as a light blocking pattern, a back gate electrode of at least one pixel transistor T, and the like.

[0136] The buffer layer 122 may be disposed on the bottom conductive layer BCDL to cover the bottom conductive layer BCDL. The buffer layer 122 may include at least one inorganic film including an inorganic insulating material.

[0137] The first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may be arranged on one surface of the substrate 110 including the buffer layer 122. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2. In some embodiments, the second thin film transistor TFT2 may include a back gate electrode BG. The capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2.

[0138] The first semiconductor layer SCL1 may be disposed on the buffer layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first thin film transistor TFT1. For example, the first semiconductor layer SCL1 may include a first active layer ACT1 of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8.

[0139] The first active layer ACT1 may be provided at the first semiconductor layer SCL1 and may include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 may include a first channel region CH1, a first source region S1, and a first drain region D1. The first channel region CH1 may overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 may be arranged on one side of the first channel region CH1, and the first drain region D1 may be arranged on the other side of the first channel region CH1. The first source region S1 and the first drain region D1 may be regions formed to have conductivity by doping a semiconductor used to form the first active layer ACT1 with ions or impurities. In some embodiments, the first source region S1 may be a source electrode of the first thin film transistor TFT1. In another embodiment, the first thin film transistor TFT1 may include a separate source electrode connected to the first source region S1. In some embodiments, the first drain region D1 may be a drain electrode of the first thin film transistor TFT1. In another embodiment, the first thin film transistor TFT1 may include a separate drain electrode connected to the first drain region D1.

[0140] The first insulating layer 123 may be disposed on the first semiconductor layer SCL1. The first insulating layer 123 may cover the first semiconductor layer SCL1.

[0141] The first conductive layer CDL1 may be disposed on the first insulating layer 123. The first conductive layer CDL1 may include a first gate electrode G1 of the first thin film transistor TFT1. The first gate electrode G1 may be disposed to overlap a portion of the first active layer ACT1 (e.g., the first channel region CH1). In some embodiments, the first conductive layer CDL1 may further include at least one line (or a portion of at least one line), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode. As an example, the first conductive layer CDL1 may further include a first capacitor electrode CAE1 of a capacitor Cst.

[0142] In some embodiments, the first capacitor electrode CAE1 may be integrally formed with a gate electrode of at least one first thin film transistor TFT1. Figure 5 and Figure 6 As an example, the first capacitor electrode CAE1 and the gate electrode of the first transistor T1 may be formed as one conductive pattern, and the second capacitor electrode CAE2 may be arranged to overlap the conductive pattern.

[0143] The second insulating layer 124 may be disposed on the first conductive layer CDL1. The second insulating layer 124 may cover the first conductive layer CDL1.

[0144] The second conductive layer CDL2 may be arranged on the second insulating layer 124. The second conductive layer CDL2 may include one electrode of the capacitor Cst, for example, the second capacitor electrode CAE2. In some embodiments, the second conductive layer CDL2 may also include at least one electrode, at least one line (or a portion of at least one line) and / or a conductive pattern (for example, a bridge pattern). For example, the second conductive layer CDL2 may also include a back gate electrode BG connected to the second gate electrode G2 of the second thin film transistor TFT2.

[0145] The third insulating layer 125 may be disposed on the second conductive layer CDL2. The third insulating layer 125 may cover the second conductive layer CDL2.

[0146] The second semiconductor layer SCL2 may be disposed on the third insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second thin film transistor TFT2. For example, the second semiconductor layer SCL2 may include a second active layer ACT2 of each of the third transistor T3 and the fourth transistor T4.

[0147] The second active layer ACT2 may be provided at the second semiconductor layer SCL2 and may include a second semiconductor material (e.g., an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)), etc.

[0148] The second active layer ACT2 may include a second channel region CH2, a second source region S2, and a second drain region D2. The second channel region CH2 may overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 may be arranged on one side of the second channel region CH2, and the second drain region D2 may be arranged on the other side of the second channel region CH2. The second source region S2 and the second drain region D2 may be regions having conductivity by doping a semiconductor used to form the second active layer ACT2 with ions or impurities. In some embodiments, the second source region S2 may be a source electrode of the second thin film transistor TFT2. In another embodiment, the second thin film transistor TFT2 may include a separate source electrode connected to the second source region S2. In some embodiments, the second drain region D2 may be a drain electrode of the second thin film transistor TFT2. In another embodiment, the second thin film transistor TFT2 may include a separate drain electrode connected to the second drain region D2.

[0149] The fourth insulating layer 126 may be disposed on the second semiconductor layer SCL2. The fourth insulating layer 126 may cover the second semiconductor layer SCL2.

[0150] The third conductive layer CDL3 may be disposed on the fourth insulating layer 126. The third conductive layer CDL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may be disposed to overlap a portion of the second active layer ACT2 (e.g., the second channel region CH2). In some embodiments, the third conductive layer CDL3 may further include at least one line (or a portion of at least one line), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0151] In some embodiments, the corresponding electrodes, conductive patterns and / or wires provided at the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may each include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, alloys thereof or other conductive materials), and may each have a single-layer or multi-layer structure. For example, the corresponding electrodes, conductive patterns and / or wires provided at the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may each include molybdenum (Mo) or other metal materials. At least two of the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include the same or substantially the same material, or include different materials. The material of each of the bottom conductive layer BCDL, the first conductive layer CDL1 , the second conductive layer CDL2 , and the third conductive layer CDL3 is not limited and may be variously changed in an appropriate manner according to various embodiments.

[0152] The fifth insulating layer 127 may be disposed on the third conductive layer CDL3. The fifth insulating layer 127 may cover the third conductive layer CDL3.

[0153] In some embodiments, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may be inorganic insulating films each including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials), and each may have a single-layer or multi-layer structure. At least two of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may include the same or substantially the same material, or include different materials. The material of each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may be variously changed in an appropriate manner according to the embodiment.

[0154] The fourth conductive layer CDL4 may be disposed on the fifth insulating layer 127. The fourth conductive layer CDL4 may include a first connection electrode CNE1 (or a drain electrode of the first thin film transistor TFT1), a first bridge electrode BE1 (or a source electrode of the second thin film transistor TFT2), and a second bridge electrode BE2 (or a drain electrode of the second thin film transistor TFT2). The first connection electrode CNE1 may be provided at the fourth conductive layer CDL4 and connected to the first drain region D1 of the first active layer ACT1 through a first contact hole CT1 penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The first bridge electrode BE1 may be provided at the fourth conductive layer CDL4 and connected to the second source region S2 of the second active layer ACT2 through a second contact hole CT2 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. The second bridge electrode BE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third contact hole CT3 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. In some embodiments, the fourth conductive layer CDL4 may further include at least one line (or a portion of at least one line) and / or a conductive pattern (e.g., a bridge pattern). As an example, the fourth conductive layer CDL4 may include a power line PL (e.g., a bridge pattern) provided inside and / or outside the display area DA. Figure 5 or Figure 6 A portion of the first pixel power line VDL and / or the second pixel power line VSL).

[0155] The valley portion VA may be formed to penetrate at least some of the plurality of insulating layers disposed on the barrier layer 121. For example, the valley portion VA may penetrate at least some of the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The valley portion VA may penetrate at least some of the plurality of insulating layers overlapping the first thin film transistor TFT1 and the second thin film transistor TFT2. When the valley portion VA is formed to penetrate the buffer layer 122 and all of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127, the valley portion VA may have a maximum depth. The valley portion VA may be formed not to penetrate the semiconductor layers SCL1 and SCL2 and the conductive layers CDL1, CDL2, and CDL3 disposed between the buffer layer 122 and the fifth insulating layer 127. The valley portion VA formed in a portion of the valley portion VA overlapping the semiconductor layers SCL1 and SCL2 and the conductive layers CDL1, CDL2, CDL3, and CDL4 may have a small depth. Fig. 9, a portion of the valley portion VA penetrating the buffer layer 122 and all of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 is shown. However, the valley portion VA may overlap with at least one of the semiconductor layers SCL1 and SCL2 and the conductive layers CDL1, CDL2, and CDL3 depending on a position, and in this case, the depth of the valley portion VA may become smaller.

[0156] According to some embodiments, the display device 10 may include a cover layer CPL disposed at the valley portion VA. The cover layer CPL may be disposed to overlap the valley portion VA, and at least a portion of the cover layer CPL may be disposed on the fifth insulating layer 127. For example, the cover layer CPL may be disposed on an inner sidewall of the valley portion VA and an upper surface of a lower layer exposed by the valley portion VA. Fig. 9 The capping layer CPL shown in FIG. 1 may be disposed to cover the inner sidewall of the valley portion VA and to be in direct contact with each of the barrier layer 121 and the fifth insulating layer 127 .

[0157] Fig.10 is a plan view illustrating the arrangement of a unit pixel region and a semiconductor layer region of a display device according to some embodiments of the present disclosure. Fig.11 According to some embodiments of the present disclosure Fig.10 A cross-sectional view taken along line XI-XI'. Fig.10 The second semiconductor layer SCL2 of the two pixel circuits PXC1 and PXC2 is shown (see for example Fig. 9 )A planar arrangement of the semiconductor region ACTA arranged in the unit pixel region UPX and an arrangement of the valley portion VA and the cover layer CPL.

[0158] Apart from Fig. 9 In addition, refer to Fig.10 and Fig.11 , the cover layer CPL may be arranged to overlap the valley portion VA. The cover layer CPL may be arranged to extend in the first direction DR1 and the second direction DR2, and may be arranged to surround the unit pixel region UPX. The arrangement of the cover layer CPL in a plan view may be substantially the same as the arrangement of the valley portion VA described above.

[0159] In some embodiments, the capping layer CPL may be formed to include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) or the like. For example, the cover layer CPL may be formed of SiN x Single layer film, SiN x / SiO x Double layer film or SiNx / SiO x / SiN x In some embodiments, like the fourth conductive layer CDL4, the cover layer CPL may include a conductive material such as a metal. In this case, the cover layer CPL may be formed in the same process as the fourth conductive layer CDL4. The cover layer CPL may include the above-mentioned material and cover the inner sidewall of the valley portion VA.

[0160] The second active layer ACT2 of the second thin film transistor TFT2 included in the first pixel circuit PXC1 and the second pixel circuit PXC2 may be formed as a second semiconductor layer SCL2 including an oxide semiconductor. In the unit pixel region UPX, the second semiconductor layer SCL2 may be arranged at Fig.10 The second semiconductor layer SCL2 of the first pixel circuit PXC1 and the second semiconductor layer SCL2 of the second pixel circuit PXC2 may each be arranged in the semiconductor region ACTA. The second semiconductor layer SCL2 may be arranged slightly adjacent to the lower side of the unit pixel region UPX, the lower side being one side of the unit pixel region UPX in the first direction DR1 relative to the center of the unit pixel region UPX. The valley portion VA and a portion of the cover layer CPL extending in the second direction DR2 on the lower side of the unit pixel region UPX may be arranged adjacent to the semiconductor region ACTA.

[0161] The valley portion VA may protect the circuit elements from external impact applied to the display device 10. The valley portion VA may be formed by a process of etching the lower insulating layer after forming the fourth conductive layer CDL4, and may then be filled with the sixth insulating layer 128 to be described later. Before the sixth insulating layer 128 fills the valley portion VA, the cover layer CPL may cover the inner sidewall of the valley portion VA, and may prevent degradation of adjacent circuit elements caused by gas when the sixth insulating layer 128 is formed. Specifically, the second thin film transistor TFT2 may include a second active layer ACT2 including an oxide semiconductor. The sixth insulating layer 128 may include an organic insulating material. The cover layer CPL may prevent gas generated in the sixth insulating layer 128 from moving to the second active layer ACT2. The display device 10 may improve (e.g., increase) impact resistance by including the valley portion VA, and may prevent degradation of circuit elements that may occur when the valley portion VA is formed by the cover layer CPL.

[0162] The capping layer CPL may cover at least a portion of the inner sidewall of the valley portion VA, and may be arranged from the lower surface of the valley portion VA or the upper surface of the barrier layer 121 exposed in the valley portion VA to a preset height. In some embodiments, the capping layer CPL may be arranged so that at least a portion of the inner sidewall of the valley portion VA covered by it overlaps at least the second semiconductor layer SCL2 in a direction horizontal to the upper surface of the substrate 110. For example, the capping layer CPL may cover the lower surface and the inner sidewall of the valley portion VA, and may be arranged at least to a height at which the second semiconductor layer SCL2 is arranged. That is, the valley portion VA may be formed to penetrate each of the second insulating layer 124 arranged under the second semiconductor layer SCL2 and the third insulating layer 125 arranged on the second insulating layer 124. The capping layer CPL may contact the second insulating layer 124 and the third insulating layer 125 on the inner sidewall of the valley portion VA. The capping layer CPL may be disposed between the second semiconductor layer SCL2 and the organic insulating material disposed in the valley portion VA to prevent gas from moving from the organic insulating material to the second semiconductor layer SCL2 and prevent or substantially reduce degradation of the second semiconductor layer SCL2 .

[0163] According to some embodiments, the shortest distance DC between the second active layer ACT2 including an oxide semiconductor and the cover layer CPL may be about 10 μm or less. When the valley portion VA is formed in a region within about 10 μm from the second active layer ACT2, gas generated from the organic material filling the valley portion VA may cause degradation of the second semiconductor layer SCL2. In order to prevent or substantially reduce degradation of the second semiconductor layer SCL2, the inner sidewall of the valley portion VA formed in the region within about 10 μm from the second active layer ACT2 may be covered by the cover layer CPL, and the shortest distance DC between the second active layer ACT2 and the cover layer CPL may be about 10 μm or less.

[0164] exist Fig.10 and Fig.11 , the cover layer CPL is shown to be arranged along the valley portion VA, but the present disclosure is not limited thereto. The cover layer CPL may also be arranged only in the region of the valley portion VA adjacent to the semiconductor region ACTA to prevent degradation of the second semiconductor layer SCL2. In some embodiments, the valley portion VA is not formed within a preset distance from the semiconductor region ACTA, thereby preventing degradation of the second semiconductor layer SCL2. This will be described with reference to other embodiments.

[0165] Fig.12 According to some embodiments of the present disclosure Fig.10 A cross-sectional view taken along line XII-XII'. Fig.12 A cross section of a portion of the valley portion VA taken along the first direction DR1 is shown.

[0166] Reference Fig.12 , the valley portion VA of the display device 10 may have a non-constant depth, and the cover layer CPL may be discontinuously arranged in the valley portion VA. The valley portion VA may be formed to penetrate a plurality of layers from the buffer layer 122 to the fifth insulating layer 127, but may not penetrate the semiconductor layer or the conductive layer. The valley portion VA may be formed to surround the unit pixel region UPX. In a portion of the valley portion VA overlapping with a plurality of conductive layers or semiconductor layers outside the unit pixel region UPX, the valley portion VA may not penetrate the plurality of conductive layers or semiconductor layers, and the depth of the valley portion VA may become smaller.

[0167] For example, Fig.12 As shown in , the patterns of the bottom conductive layer BCDL and the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 may be partially positioned inside the valley portion VA. The valley portion VA having the largest depth may be formed in a portion of the valley portion VA where no pattern is arranged, and the depth of the valley portion VA may become smaller in an area where the valley portion VA overlaps with the bottom conductive layer BCDL and the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3. In the valley portion VA, the patterns of the insulating layers 123, 124, 125, and 126 that the valley portion VA does not penetrate may remain under the patterns or lines of the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3.

[0168] The pattern may be a plurality of lines arranged on the bottom conductive layer BCDL and the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3. The pattern may be connected to the pixel circuit PXC or may be a conductive pattern electrically connected to the thin film transistors TFT1 and TFT2. For example, the pattern may be a reference Figure 5 and Figure 6 Described are multiple scan lines SL, data lines DL, emission control lines ECL, power lines PL, etc.

[0169] The cover layer CPL may include a first cover pattern CP1 arranged on the inner sidewall of the valley portion VA, a second cover pattern CP2 arranged on the upper surface of the barrier layer 121, and a third cover pattern CP3, a fourth cover pattern CP4, and a fifth cover pattern CP5 arranged on patterns of the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 respectively overlapping the valley portion VA. The cover layer CPL may include a plurality of cover patterns CP1, CP2, CP3, CP4, and CP5 spaced apart from each other in the valley portion VA. The display device 10 may include a valley portion VA whose depths are different from each other depending on the arrangement of the plurality of conductive layers CDL1, CDL2, and CDL3, the bottom conductive layer BCDL, and the semiconductor layers SCL1 and SCL2, and may include a cover layer CPL arranged along the valley portion VA but not continuously. In some embodiments in which the covering layer CPL is formed along the valley portion VA and is formed to cover the inner side wall of the valley portion VA, a portion of the covering layer CPL (e.g., CP1) may be arranged on the inner side wall of the valley portion VA, and other portions of the covering layer CPL may remain on the barrier layer 121 (e.g., CP2) or may remain on the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 (e.g., CP3, CP4, and CP5).

[0170] Refer again Fig.11 , the sixth insulating layer 128 may be disposed on the fourth conductive layer CDL4. The sixth insulating layer 128 may cover the fourth conductive layer CDL4. In addition, the sixth insulating layer 128 may fill the inside of the valley portion VA and may be directly disposed on the cover layer CPL.

[0171] The fifth conductive layer CDL5 may be disposed on the sixth insulating layer 128. The fifth conductive layer CDL5 may include a second connection electrode CNE2. The second connection electrode CNE2 may be provided at the fifth conductive layer CDL5 and connected to the first connection electrode CNE1 through a fourth contact hole CT4 (or a first through hole) penetrating the sixth insulating layer 128. In some embodiments, the fifth conductive layer CDL5 may further include at least one line (or a portion of at least one line) and / or a conductive pattern (e.g., a bridge pattern). As an example, the fifth conductive layer CDL5 may include a portion of a power line PL (e.g., a first pixel power line VDL and / or a second pixel power line VSL) provided inside and / or outside the display area DA.

[0172] In some embodiments, the corresponding electrodes, conductive patterns and / or wires provided at the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may each include a conductive material (for example, at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, alloys thereof or other conductive materials), and may each have a single-layer or multi-layer structure. For example, the corresponding electrodes, conductive patterns and / or wires provided at the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may each be formed as a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include the same or substantially the same material, or include different materials. The material of each of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be variously changed in an appropriate manner according to the embodiment.

[0173] The seventh insulating layer 129 may be disposed on the fifth conductive layer CDL5. The seventh insulating layer 129 may cover the fifth conductive layer CDL5.

[0174] In some embodiments, the sixth insulating layer 128 and the seventh insulating layer 129 may be an organic insulating film including an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or other organic insulating material) to flatten the circuit layer 120, and each may have a single-layer or multi-layer structure. The sixth insulating layer 128 and the seventh insulating layer 129 may include the same or substantially the same material, or include different materials. The material of each of the sixth insulating layer 128 and the seventh insulating layer 129 may be variously changed in an appropriate manner according to the embodiment.

[0175] The light emitting element layer 130 may include a pixel defining film 131 that separates the emission area EA of the pixel PX and the corresponding light emitting element EL positioned in the corresponding emission area EA. In some embodiments, the light emitting element layer 130 may further include a spacer 132 disposed on a portion of the pixel defining film 131 .

[0176] Each light emitting element EL may include a first connection electrode CNE1, a second connection electrode CNE2, etc. connected to a light emitting element included in a corresponding sub-pixel SPX (see, for example, Figure 5 or Figure 6) in the embodiment of the present invention, the first electrode ET1 (e.g., an anode) of at least one pixel transistor T (e.g., a first thin film transistor TFT1) in the light emitting element EL and the light emitting layer EML. Each light emitting element EL may include a second electrode ET2 (e.g., a cathode) sequentially arranged on the first electrode ET1. In some embodiments, the light emitting element EL may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) between the first electrode ET1 and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) between the light emitting layer EML and the second electrode ET2.

[0177] The first electrode ET1 of the light emitting element EL may include a conductive material and may be disposed on the circuit layer 120. For example, the first electrode ET1 may be disposed on the seventh insulating layer 129 to correspond to each emission area EA. The first electrode ET1 may be connected to the second connection electrode CNE2 through a fifth contact hole CT5 (or a second through hole) penetrating the seventh insulating layer 129.

[0178] In some embodiments, the first electrode ET1 may include a metal material having a high reflectivity. For example, the first electrode ET1 may have a single-layer structure of Mo, Ti, Cu, or Al, or a single-layer structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), etc. (for example, ITO / Mg, ITO / MgF 2 , ITO / Ag, ITO / Ag / ITO, etc.).

[0179] The light-emitting layer EML of the light-emitting element EL may include a polymer material or a low-molecular material. In some embodiments, each sub-pixel SPX may have a corresponding light-emitting layer EML, and the light-emitting layer EML of each sub-pixel SPX may emit visible light of a color corresponding to the corresponding sub-pixel SPX. In another embodiment, the light-emitting layer EML may be a common layer shared by sub-pixels SPX of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light to be emitted from the corresponding sub-pixel SPX may be arranged in the emission area EA of at least some of the sub-pixels SPX.

[0180] The second electrode ET2 of the light emitting element EL may include a conductive material and may be connected to a second pixel power supply line VSL. In some embodiments, the second electrode ET2 may be a common layer formed throughout the entire display area DA in a form in which it covers the light emitting layer EML and the pixel defining film 131. In some embodiments, the second electrode ET2 may be made of a transparent conductive material (TCM) (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)) that allows light to pass (e.g., pass through). When the second electrode ET2 is made of a semi-transmissive conductive material, an improvement (e.g., increase) in light emission efficiency due to the microcavity effect can be expected.

[0181] The pixel defining film 131 may have an opening corresponding to the corresponding emission area EA and surround the emission area EA. For example, the pixel defining film 131 may be formed to cover the edge of the first electrode ET1 of the light emitting element EL, and may include an opening exposing other portions of the first electrode ET1. The region where the exposed first electrode ET1 and the light emitting layer EML overlap each other (or a region including such a region) may be defined as the emission area EA of each pixel PX.

[0182] In some embodiments, the pixel defining film 131 may include at least one organic film including an organic insulating material. For example, the pixel defining film 131 may include polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), or other organic insulating materials.

[0183] The spacer 132 may be arranged on a portion of the pixel defining film 131. The spacer 132 may include at least one organic film including an organic insulating material. The spacer 132 may include a material that is the same or substantially the same as the pixel defining film 131, or include a material that is different from the material of the pixel defining film 131. In some embodiments, the pixel defining film 131 and the spacer 132 may be sequentially formed by corresponding mask processes. In another embodiment, the pixel defining film 131 and the spacer 132 may be formed simultaneously using a halftone mask. In this case, the pixel defining film 131 and the spacer 132 may be regarded as a single insulating film that is integrated with each other. The organic insulating material constituting the spacer 132 is not particularly limited, and various changes may be made in appropriate manners according to the embodiments.

[0184] The encapsulation layer 140 may be formed in the main area MA (see, for example, Figure 1 ) is arranged on the light emitting element layer 130. For example, the encapsulation layer 140 may be arranged in the display area DA (see, for example Figure 1 ) and non-display area NA (see e.g. Figure 1) to cover the light emitting element layer 130. The encapsulation layer 140 may block or reduce the penetration of oxygen or moisture into the light emitting element layer 130, and mitigate (eg, prevent) electrical or physical impacts to the circuit layer 120 and the light emitting element layer 130.

[0185] In some embodiments, the encapsulation layer 140 may include a first inorganic encapsulation film 141, an organic encapsulation film 142, and a second inorganic encapsulation film 143 sequentially disposed on the light emitting element layer 130. The first inorganic encapsulation film 141 and the second inorganic encapsulation film 143 may each include an inorganic material, and the organic encapsulation film 142 may include an organic material.

[0186] The display device 10 according to some embodiments may include a valley portion VA surrounding an area where a plurality of pixel circuits PXC are arranged, and a cover layer CPL covering an inner sidewall of the valley portion VA. The valley portion VA of the display device 10 may prevent an external impact applied to the display device 10 from damaging circuit elements. In addition, when the display device 10 has a flexible characteristic, cracks that may be formed in a plurality of insulating layers arranged on the substrate 110 when the substrate 110 is folded may be prevented by the valley portion VA. In addition, by including the cover layer CPL arranged on the inner sidewall of the valley portion VA, degradation of the oxide semiconductor due to gas generated from an organic material filling the valley portion VA may be prevented or reduced.

[0187] Hereinafter, various embodiments of the display device 10 will be described with reference to other drawings.

[0188] Fig.13 is a plan view illustrating a unit pixel region and a valley portion of a display device according to some embodiments of the present disclosure. Fig.14 According to some embodiments of the present disclosure Fig.13 A cross-sectional view taken along line A1-A1'.

[0189] Reference Fig.13 and Fig.14In a display device 10_1 according to another embodiment, the cover layer CPL_1 may be arranged only around the semiconductor region ACTA. The cover layer CPL_1 may be arranged to overlap with the valley portion VA, but may not be arranged throughout the entire valley portion VA, and may be arranged to correspond to the periphery of the semiconductor region ACTA where the second semiconductor layer SCL2 including an oxide semiconductor is arranged. For example, the cover layer CPL_1 may be arranged to overlap with a portion of the valley portion VA that is arranged on the lower side of the semiconductor region ACTA and extends in the second direction DR2. In addition, in the portion of the valley portion VA that extends in the first direction DR1, the cover layer CPL_1 may be arranged only on a portion adjacent to the semiconductor region ACTA (i.e., on the lower side relative to the center of the unit pixel region UPX). A plurality of unit pixel regions UPX may be repeatedly arranged in the first direction DR1 and the second direction DR2, and accordingly, the semiconductor region ACTA may also be repeatedly arranged in the first direction DR1 and the second direction DR2 throughout the entire display area DA. The cover layer CPL_1 arranged throughout the entire display area DA may be arranged in a pattern not connected to and spaced apart from each other, and an exposed area without the cover layer CPL_1 may be formed in a partial area of ​​a portion of the valley portion VA extending in the first direction DR1.

[0190] As described above, the cover layer CPL_1 may prevent the gas generated from the organic insulating material of the sixth insulating layer 128 arranged in the valley portion VA from moving to the second semiconductor layer SCL2 including an oxide semiconductor. The cover layer CPL_1 may be arranged in an area within about 10 μm of the second active layer ACT2 of the second semiconductor layer SCL2 to prevent degradation of the second active layer ACT2 due to the movement of the gas. Accordingly, the cover layer CPL_1 may not be arranged in an area of ​​about 10 μm or more from the second active layer ACT2. According to another embodiment, the cover layer CPL_1 may be selectively arranged only on a portion of the valley portion VA adjacent to the second semiconductor layer SCL2. For example, the cover layer CPL_1 may be arranged only in a partial area of ​​the valley portion VA to correspond to the semiconductor region ACTA arranged adjacent to the lower side of the unit pixel region UPX.

[0191] Fig.15 is a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure.

[0192] Reference Fig.15, in the display device 10_2 according to still another embodiment, the cover layer CPL_2 may be arranged only in the region of the valley portion VA closest to the semiconductor region ACTA. For example, the cover layer CPL_2 may have a width that is the same as or substantially the same as a width of the semiconductor region ACTA measured in the second direction DR2, and may be arranged on a portion of the valley portion VA extending in the second direction DR2. When the shortest distance DC between the second active layer ACT2 of the semiconductor region ACTA and the portion of the valley portion VA extending in the second direction DR2 (see, for example Fig.10 ) is less than about 10 μm, the cover layer CPL_2 may be arranged to correspond only to the corresponding area. The cover layer CPL_2 may be arranged in a form in which patterns having a preset width in the second direction DR2 are spaced apart from each other and are repeatedly arranged in the first direction DR1 and the second direction DR2 throughout the entire display area DA.

[0193] Fig.16 is a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure. Fig.17 According to some embodiments of the present disclosure Fig.16 A cross-sectional view taken along line A2-A2'.

[0194] Reference Fig.16 and Fig.17 In a display device 10_3 according to still another embodiment, a valley portion VA_3 may be formed in a region that is not closest to the semiconductor region ACTA. The valley portion VA_3 may be arranged throughout the entire display area DA in a linear shape in which it extends in the first direction DR1, and may have a shape in which it has a protruding portion that partially protrudes to both sides in the second direction DR2. The region NVA in which the valley portion VA_3 is not formed may be arranged between portions of the valley portion VA_3 that protrude in the second direction DR2. The region NVA in which the valley portion VA_3 is not formed may be positioned between the unit pixel regions UPX arranged in the first direction DR1 or between the semiconductor regions ACTA of the unit pixel regions UPX arranged in the first direction DR1.

[0195] The cover layer CPL_3 may be formed to overlap the valley portion VA_3 , and like the valley portion VA_3 , the cover layer CPL_3 may be arranged in a linear shape throughout the entire display area DA in which it extends in the first direction DR1 , and may have a shape in which it has a protruding portion partially protruding to both sides in the second direction DR2 .

[0196] Since the valley portion VA_3 is selectively not formed in the region adjacent to the semiconductor region ACTA, degradation of the second active layer ACT2 of the second semiconductor layer SCL2 due to movement of gas generated from the organic insulating material of the sixth insulating layer 128 disposed in the valley portion VA_3 may be prevented or reduced.

[0197] Fig.18 is a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure. Fig.19 According to some embodiments of the present disclosure Fig.18 A cross-sectional view taken along line A3-A3'.

[0198] Reference Fig.18 and Fig.19 , the display device 10_4 according to some embodiments may include a step pattern GSL_4 overlapping the valley portion VA_4. The step pattern GSL_4 may be arranged at the same layer as the layer of the third conductive layer CDL3 arranged above the second semiconductor layer SCL2. The step pattern GSL_4 may be arranged on the fourth insulating layer 126 and in a region adjacent to the semiconductor region ACTA. For example, the step pattern GSL_4 may be arranged on the lower side of the unit pixel region UPX and may be arranged to be spaced apart from the semiconductor region ACTA in the first direction DR1 and overlap with a portion of the valley portion VA_4 extending in the second direction DR2.

[0199] The valley portion VA_4 may penetrate the buffer layer 122 and the plurality of insulating layers 123, 124, 125, 126, and 127, but may not penetrate the conductive layers CDL1, CDL2, and CDL3 or the semiconductor layers SCL1 and SCL2. In the process of forming the valley portion VA_4, the conductive layers CDL1, CDL2, and CDL3 or the semiconductor layers SCL1 and SCL2 may be used as an etching stop layer. In the region where the step pattern GSL_4 is arranged, the valley portion VA_4 may not penetrate the step pattern GSL_4, and the region of the valley portion VA_4 overlapping with the step pattern GSL_4 may have a smaller depth than other portions. The valley portion VA_4 may include a first portion VAP1 that does not overlap with the step pattern GSL_4 and penetrates up to the buffer layer 122, and a second portion VAP2 that overlaps with the step pattern GSL_4 and does not penetrate the step pattern GSL_4 and a layer arranged below the step pattern GSL_4. The first portion VAP1 of the valley portion VA_4 may have a depth greater than a depth of the second portion VAP2 of the valley portion VA_4 .

[0200] The cover layer CPL_4 may be arranged to correspond to the valley portion VA_4, and may be arranged on the step pattern GSL_4. The portion of the cover layer CPL_4 arranged on the step pattern GSL_4 may be in direct contact with the upper surface of the step pattern GSL_4. The portion of the cover layer CPL_4 arranged in the first portion VAP1 of the valley portion VA_4 may be in direct contact with the barrier layer 121. The portion of the cover layer CPL_4 arranged in the second portion VAP2 of the valley portion VA_4 may be in direct contact with the step pattern GSL_4.

[0201] The step pattern GSL_4 may be arranged at the same layer as the layer of the third conductive layer CDL3 arranged above the second semiconductor layer SCL2, and a portion of the valley portion VA_4 overlapping with the step pattern GSL_4 may penetrate the fifth insulating layer 127 but may not penetrate the fourth insulating layer 126. That is, the portion of the valley portion VA_4 overlapping with the step pattern GSL_4 does not overlap with the second active layer ACT2 of the second semiconductor layer SCL2 in a horizontal direction. The step pattern GSL_4 may be arranged in a region adjacent to the semiconductor region ACTA or the second active layer ACT2 of the second semiconductor layer SCL2, and accordingly, the valley portion VA_4 may not be formed in a region horizontal to the second active layer ACT2 of the second semiconductor layer SCL2. The display device 10_4 may include the step pattern GSL_4 so that a partial region of the valley portion VA_4 may be selectively formed with a small depth, and degradation of the second active layer ACT2 of the second semiconductor layer SCL2 due to movement of gas generated from the organic insulating material may be prevented or reduced.

[0202] If the valley portion VA_4 and the second semiconductor layer SCL2 of the semiconductor area ACTA may be separated from each other by the step pattern GSL_4 and movement of gas generated from the organic insulating material may be prevented by the step pattern GSL_4 , the capping layer CPL may be omitted.

[0203] Fig. 20 is a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure. Fig.21 According to some embodiments of the present disclosure Fig. 20 A cross-sectional view taken along line A4-A4'.

[0204] Reference Fig. 20 and Fig.21, the display device 10_5 according to some embodiments may include a step pattern GSL_5 overlapping with the valley portion VA_5. The step pattern GSL_5 may be arranged adjacent to the second semiconductor layer SCL2 of the semiconductor region ACTA, and the area of ​​the valley portion VA_5 overlapping with the step pattern GSL_5 may have a smaller depth than other portions. The valley portion VA_5 may include a first portion VAP1 that does not overlap with the step pattern GSL_5 and penetrates up to the buffer layer 122. The valley portion VA_5 may include a second portion VAP2 that overlaps with the step pattern GSL_5 and does not penetrate the step pattern GSL_5 and a layer arranged below the step pattern GSL_5. The first portion VAP1 of the valley portion VA_5 may have a depth greater than the depth of the second portion VAP2 of the valley portion VA_5. Accordingly, the second active layer ACT2 of the second semiconductor layer SCL2 may not overlap with the valley portion VA_5 in the horizontal direction, and even if the cover layer CPL is omitted in the display device 10_5, degradation due to gas generated from the organic insulating material may be prevented or reduced. These embodiments are similar to Fig.18 and Fig.19 Some embodiments differ in that the cover layer CPL is omitted.

[0205] Fig. 22 is a plan view illustrating a unit pixel region and a valley portion of a display device according to some other embodiments of the present disclosure. Fig.23 According to some embodiments of the present disclosure Fig. 22 A cross-sectional view taken along line A5-A5'.

[0206] Reference Fig. 22 and Fig.23 In the display device 10_6 according to still another embodiment, a valley portion VA_6 may be formed in a region that is not closest to the semiconductor region ACTA. The valley portion VA_6 may be arranged in a linear shape throughout the entire display area DA in which it extends in the first direction DR1, and may have a shape in which it has a protruding portion partially protruding to both sides in the second direction DR2.

[0207] Since the valley portion VA_6 is selectively not formed in the region adjacent to the semiconductor region ACTA, even if the cover layer CPL is omitted in the display device 10_6, degradation of the second active layer ACT2 of the second semiconductor layer SCL2 caused by movement of gas generated from the organic insulating material of the sixth insulating layer 128 disposed in the valley portion VA_6 can be prevented or reduced. Fig.16 and Fig.17 Some embodiments differ in that the cover layer CPL is omitted.

Claims

1. A display device, comprising: a plurality of unit pixel regions, the plurality of unit pixel regions being arranged in a first direction and in a second direction intersecting the first direction and having first and second thin film transistors positioned in the plurality of unit pixel regions, each of the first thin film transistors including a first active layer, and each of the second thin film transistors including a second active layer located at a different layer from the first active layer and including an oxide semiconductor; a valley portion, the valley portion being located at a boundary of the unit pixel region, extending in the first direction, at least partially extending in the second direction, and penetrating at least some of the plurality of insulating layers overlapping the first thin film transistor and the second thin film transistor, at least a portion of the valley portion overlapping the second active layer in a horizontal direction; as well as a covering layer positioned to overlap the valley portion and to cover an inner sidewall of the valley portion, the covering layer being located on a portion of the valley portion adjacent to a semiconductor region of one of the plurality of unit pixel regions where the second active layer is located, and being located between the second active layer and the organic insulating material in the valley portion.

2. The display device according to claim 1, wherein: The shortest distance between the capping layer and the second active layer is 10 μm or less.

3. The display device according to claim 1, wherein: The capping layer includes SiN x 、SiO x and SiO x N y At least one of .

4. The display device according to claim 1, further comprising: a plurality of lines electrically connected to at least one of the first thin film transistor and the second thin film transistor and extending in the first direction or the second direction, wherein at least a portion of the valley portion overlaps with any one of the plurality of lines.

5. The display device according to claim 4, wherein: A depth of a portion of the valley portion that does not overlap the line is greater than a depth of the at least a portion of the valley portion that overlaps the any one of the plurality of lines.

6. The display device according to claim 5, wherein: The covering layer includes a first covering pattern located on the inner sidewall of the valley portion and a second covering pattern that is not connected to the first covering pattern and is located on the line overlapping the valley portion.

7. The display device according to claim 1, wherein: The valley portion is configured to extend in the first direction and the second direction to surround the unit pixel region, and The cover layer includes a portion overlapping the valley portion and extending in the first direction and the second direction.

8. The display device according to claim 7, wherein: the second active layer is adjacent to a portion of the valley portion extending in the second direction, and Wherein, the covering layer is located on the portion of the valley portion extending in the second direction.

9. The display device according to claim 8, wherein: A width of the capping layer measured in the second direction is the same as a width of the semiconductor region measured in the second direction.

10. The display device according to claim 8, wherein: The portion of the cover layer extending in the first direction is positioned on the portion of the valley portion extending in the first direction, and wherein the cover layer is not positioned on at least a portion of the portion of the valley portion extending in the first direction.

11. The display device according to claim 7, wherein: The cover layer is configured to extend in the first direction and the second direction to surround the unit pixel region.

12. The display device according to claim 1, wherein: The valley portion includes a portion extending in the first direction and a portion protruding in the second direction from the portion extending in the first direction and positioned at the boundary of the unit pixel region, and The valley portion and the cover layer are not positioned between the semiconductor regions of the unit pixel regions arranged in the first direction.

13. The display device according to claim 1, further comprising: a gate electrode, wherein the gate electrode is located on the second active layer; as well as a step pattern positioned at the same layer as the gate electrode and overlapping a portion of the valley portion extending in the second direction, Wherein, the covering layer is located on the step pattern and directly contacts the step pattern.

14. The display device according to claim 13, wherein: A portion of the valley portion on the step pattern has a smaller depth than other portions, and The capping layer on the step pattern does not overlap the second active layer in the horizontal direction.

15. A display device, comprising: a plurality of unit pixel regions, the plurality of unit pixel regions being arranged in a first direction and in a second direction intersecting the first direction and having first and second thin film transistors positioned in the plurality of unit pixel regions, each of the first thin film transistors including a first active layer, and each of the second thin film transistors including a second active layer located at a different layer from the first active layer and including an oxide semiconductor; as well as a valley portion, the valley portion being located at a boundary of the unit pixel region, extending in the first direction, at least partially extending in the second direction, and penetrating at least some of the plurality of insulating layers overlapping the first thin film transistor and the second thin film transistor, The second active layer is adjacent to one side of the unit pixel region, and on the side of the unit pixel region adjacent to the semiconductor region where the second active layer is located, the valley portion is formed so as not to penetrate the gate insulating layer covering the second active layer.

16. The display device according to claim 15, wherein: The valley portion includes a portion extending in the first direction and a portion protruding in the second direction from the portion extending in the first direction and positioned at the boundary of the unit pixel region.

17. The display device according to claim 16, wherein: The valley portion is not formed between the semiconductor regions of the unit pixel regions arranged in the first direction.

18. The display device according to claim 15, further comprising: a gate electrode, the gate electrode overlapping the second active layer; as well as a step pattern positioned at the same layer as the gate electrode and overlapping a portion of the valley portion extending in the second direction, The valley portion is configured to extend in the first direction and the second direction to surround the unit pixel region.

19. The display device according to claim 18, wherein: A portion of the valley portion positioned on the step pattern has a smaller depth than other portions.

20. The display device according to claim 18, wherein: The step pattern is positioned on the gate insulating layer covering the second active layer, and The valley portion does not penetrate the gate insulating layer overlapping the step pattern.

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