Display device

Abstract

A display device includes: a substrate including a display area and a peripheral area adjacent to the display area; a plurality of light emitting diodes arranged in the display area; a first inorganic encapsulation layer disposed on the plurality of light emitting diodes; an organic encapsulation layer disposed on the first inorganic encapsulation layer; a plurality of inorganic patterns disposed on the organic encapsulation layer and spaced apart from each other; and a touch electrode disposed on the organic encapsulation layer and defining a plurality of electrode holes respectively overlapping the plurality of light emitting diodes in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0145080 filed on October 26, 2023 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] Mobile electronic devices include display devices for providing visual information such as images or videos to users. With the development of display devices, various display devices having excellent characteristics such as thinness, light weight, and low power consumption have been introduced. With the miniaturization of components for driving display devices, the proportion of display devices in electronic devices has gradually increased, and display devices having a structure that is bendable or foldable to have a certain angle have also been developed. Summary of the invention

[0005] The display device may include a display panel configured to display an image. The display panel may include a region that can be bent in a back direction of the display panel, and stress may be concentrated on the bent region.

[0006] Embodiments include a display device in which reliability is improved by preventing or reducing damage caused by concentration of stress.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of embodiments of the disclosure.

[0008] According to an embodiment, a display device may include: a substrate including a display area and a peripheral area adjacent to the display area; a plurality of light emitting diodes arranged in the display area; a first inorganic encapsulation layer disposed on the plurality of light emitting diodes; an organic encapsulation layer disposed on the first inorganic encapsulation layer; a plurality of inorganic patterns disposed on the organic encapsulation layer and spaced apart from each other; and a touch electrode disposed on the organic encapsulation layer and defining a plurality of electrode holes respectively overlapping the plurality of light emitting diodes in a plan view.

[0009] Each of the plurality of inorganic patterns may cover one of the plurality of light emitting diodes in a plan view, and the plurality of inorganic patterns may be respectively arranged within the plurality of electrode holes in a plan view.

[0010] Each of the plurality of inorganic patterns may cover two or more of the plurality of light emitting diodes in a plan view, and each of the plurality of inorganic patterns may overlap two or more of the plurality of electrode holes in a plan view.

[0011] The first opening may be defined between the plurality of inorganic patterns, and the first opening may overlap at least a portion of the touch electrode in a plan view.

[0012] A portion of the touch electrode overlapping the first opening in a plan view may be in direct contact with the organic encapsulation layer, and a remaining portion of the touch electrode may be disposed on the plurality of inorganic patterns.

[0013] The plurality of inorganic patterns may include a first inorganic layer and a second inorganic layer.

[0014] The display device may further include a first inorganic layer disposed on the plurality of inorganic patterns and covering the first opening, wherein the touch electrode may be disposed on the first inorganic layer.

[0015] The display device may further include an organic layer disposed on the plurality of inorganic patterns and filling the first opening, wherein the touch electrode may be disposed on the organic layer.

[0016] Each of the plurality of light emitting diodes may include a pixel electrode, an opposing electrode, and an emission layer disposed between the pixel electrode and the opposing electrode. The display device may further include a pixel defining layer and a metal dam layer disposed on the pixel defining layer, the pixel defining layer defining a plurality of pixel openings exposing a plurality of central portions of the plurality of pixel electrodes, the metal dam layer including a first sub-metal layer and a second sub-metal layer on the first sub-metal layer, and the metal dam layer defining a plurality of openings overlapping the plurality of pixel openings in a plan view. The second sub-metal layer may include an end protruding from a side surface of the first sub-metal layer toward a center direction of each of the plurality of pixel openings.

[0017] The opposite electrode may directly contact a side surface of the first sub-metal layer.

[0018] The first inorganic encapsulation layer may be in direct contact with a bottom surface of the terminal and a side surface of the first sub-metal layer.

[0019] In a plan view, a width of each of the plurality of inorganic patterns may be greater than a width of a plurality of pixel openings among the plurality of pixel openings overlapping the plurality of inorganic patterns.

[0020] The display device may further include a common voltage line arranged in the peripheral area, and a second inorganic encapsulation layer disposed on the organic encapsulation layer and overlapping the common voltage line in a plan view. The second inorganic encapsulation layer may define a second opening extending in a direction parallel to an edge of the substrate.

[0021] In a plan view, the second opening may overlap the organic encapsulation layer.

[0022] The second opening may surround at least a portion of the display area in a plan view.

[0023] According to an embodiment, a display device may include: a substrate including a display area and a peripheral area adjacent to the display area; a plurality of light emitting diodes arranged in the display area; a first inorganic encapsulation layer disposed on the plurality of light emitting diodes and extending to the peripheral area; an organic encapsulation layer disposed on the first inorganic encapsulation layer; and a second inorganic encapsulation layer disposed on the organic encapsulation layer and defining a first opening in the peripheral area.

[0024] In a plan view, the first opening may overlap the organic encapsulation layer.

[0025] The display device may further include: a common voltage line arranged in the peripheral area and surrounding at least a portion of the display area in a plan view; an organic insulating layer arranged between the substrate and the plurality of light emitting diodes, and the organic insulating layer overlaps with a boundary of the common voltage line at one side in a plan view by extending from the display area to the peripheral area; and a dam overlapping with a boundary of the common voltage line at another side in a plan view.

[0026] The first opening may be disposed closer to the display region than one end of the organic insulating layer.

[0027] The peripheral region may be curved with a curvature in a back direction of the substrate.

[0028] Other aspects, features, and advantages may become apparent from the accompanying drawings, claims, and detailed description of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features and advantages of the embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a perspective view schematically showing a display device according to an embodiment;

[0031] Figure 2A is along Figure 1 A schematic cross-sectional view of the display device taken along line AA';

[0032] Figure 2B is along Figure 1 A schematic cross-sectional view of the display device taken along line BB';

[0033] Figure 2C is along Figure 1 A schematic cross-sectional view of the display device taken along line CC';

[0034] Figure 3 is a plan view of a display panel included in a display device according to an embodiment;

[0035] Figure 4A is a schematic diagram of an equivalent circuit of a pixel included in a display device according to an embodiment;

[0036] Figure 4B is a schematic diagram of an equivalent circuit of a pixel included in a display device according to an embodiment;

[0037] Figure 5A According to the embodiment Figure 3 A plan view of a portion of a region G of a display panel;

[0038] Figure 5B According to the embodiment Figure 3 A plan view of a portion of a region G of a display panel;

[0039] Figure 5C yes Figure 5B An enlarged plan view of the area H shown in FIG.

[0040] Fig. 6A is a plan view of a portion of a display panel according to an embodiment;

[0041] Figure 6B yes Fig. 6A A schematic cross-sectional view of a display panel;

[0042] Figure 6C yes Fig. 6A A schematic cross-sectional view of a display panel;

[0043] Fig. 7A is a plan view of a portion of a display panel according to an embodiment;

[0044] Figure 7B yes Fig. 7A A schematic cross-sectional view of a display panel;

[0045] Figure 7C yes Fig. 7A A schematic cross-sectional view of a display panel;

[0046] Fig. 8A is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0047] Figure 8B is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0048] Fig.9A is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0049] Fig. 9B is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0050] Fig.10 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0051] Fig.11 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0052] Fig.12 is along Figure 3 A schematic cross-sectional view of the display panel taken along line EE'; and

[0053] Fig.13 is a plan view of a display panel included in a display device according to an embodiment. DETAILED DESCRIPTION

[0054] The present disclosure may have various modifications and various embodiments, and specific embodiments are shown in the drawings and described in detail in the detailed description. With reference to the embodiments described in detail with reference to the drawings, the effects and features of the present disclosure and the methods for implementing the same will become apparent. However, the present disclosure is not limited to the embodiments described below and may be implemented in various forms.

[0055] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, and in the following description with reference to the accompanying drawings, the same reference numerals denote the same elements and redundant descriptions thereof will be omitted.

[0056] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0057] In this specification, an expression used in the singular includes an expression in the plural unless it has an apparently different meaning in the context.

[0058] In the present specification, it will also be understood that the terms “include” and / or “comprises” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0059] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without an intermediate element. In addition, when an element is referred to as being "in contact with" or "in contact with" another element, etc., the element may be "electrically in contact with" or "physically in contact with" the other element, or "indirectly in contact with" or "directly in contact with" the other element.

[0060] In the specification and claims, for the purpose of its interpretation and explanation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B". In the specification and claims, for the purpose of its interpretation and explanation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction and a disjunction sense and may be understood to be equivalent to "and / or".

[0061] In this specification, the x-direction, y-direction, and z-direction are not limited to directions on three axes on a rectangular coordinate system, but can be broadly interpreted as including three axes. For example, the x-direction, y-direction, and z-direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0062] When a certain embodiment can be implemented differently, a specific processing order can be performed in an order different from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described order.

[0063] In the drawings, the size of components may be exaggerated or reduced for convenience of description. In other words, since the size and thickness of components in the drawings are arbitrarily shown for convenience of explanation, the present disclosure is not necessarily limited thereto.

[0064] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formalized meaning.

[0065] Figure 1 is a perspective view schematically showing a display device 1 according to the embodiment. Figure 2A is along Figure 1 Schematic cross-sectional view of the display device 1 taken along line AA′. Figure 2B is along Figure 1 A schematic cross-sectional view of the display device 1 taken along line BB′. Figure 2C is along Figure 1 A schematic cross-sectional view of the display device 1 taken along line CC′.

[0066] Reference Figure 1 as well as FIG. 2A to FIG. 2C , the display device 1 can display an image. The display device 1 may include an edge extending in a first direction and an edge extending in a second direction. The first direction and the second direction may intersect each other. For example, the first direction and the second direction may form an acute angle. For example, the first direction and the second direction may form an obtuse angle or a right angle. Hereinafter, an embodiment in which the first direction and the second direction form a right angle will be described. For example, the first direction may be an x ​​direction or a -x direction, and the second direction may be a y direction or a -y direction.

[0067] According to an embodiment, a corner CN where an edge in a first direction (eg, x direction or −x direction) and an edge in a second direction (eg, y direction or −y direction) meet may have a specific curvature.

[0068] The display device 1 may include a cover window 20 and a display panel 10. The cover window 20 may protect the display panel 10. According to an embodiment, the cover window 20 may be disposed on the display panel 10. According to an embodiment, the cover window 20 may be a flexible window. The cover window 20 may protect the display panel 10 by being easily bent in response to an external force without causing cracks, etc. The cover window 20 may include glass, sapphire, or plastic. The cover window 20 may include, for example, ultra-thin glass or colorless polyimide.

[0069] The display panel 10 may be disposed under the cover window 20. The display panel 10 and the cover window 20 may be connected to each other by using a transparent adhesive member such as an optically clear adhesive film.

[0070] The display panel 10 may display an image. The display panel 10 may include a substrate 100 and pixels PX. The display panel 10 may include a display area DA and a peripheral area PA adjacent to the display area DA. The display area DA may include a central area CA, a first area A1, a second area A2, a corner area CNA, and a middle area MA. The central area CA, the first area A1, the second area A2, the corner area CNA, the middle area MA, and the peripheral area PA as the display area DA may be defined on the substrate 100 of the display panel 10. In other words, the substrate 100 may include the central area CA, the first area A1, the second area A2, the corner area CNA, the middle area MA, and the peripheral area PA adjacent to the display area DA as the display area DA.

[0071] The central area CA may be a flat area. The display panel 10 may be bent in the first area A1. The first area A1 may be adjacent to the central area CA in a first direction (e.g., the x direction or the -x direction). The first area A1 may be defined as an area bent from the central area CA in a cross section (e.g., the xz cross section) in a first direction (e.g., the x direction or the -x direction). The first area A1 may extend in a second direction (e.g., the y direction or the -y direction) and not bend in a cross section (e.g., the yz cross section) in the second direction (e.g., the y direction or the -y direction). The first area A1 may be an area bent around an axis extending in the second direction (e.g., the y direction or the -y direction).

[0072] Figure 2A It is shown that the first area A1 is bent while extending in the x direction from the central area CA, and the first area A1 is bent while extending in the -x direction from the central area CA and has the same curvature, but the present disclosure is not limited thereto, and according to another embodiment, the first area A1 may be bent while extending in the x direction from the central area CA, and the first area A1 may be bent while extending in the -x direction from the central area CA and have a different curvature.

[0073] The display panel 10 may be bent in the second area A2. The second area A2 may be adjacent to the central area CA in a second direction (e.g., y direction or -y direction). The second area A2 may be defined as an area bent from the central area CA in a cross section (e.g., yz cross section) in a second direction (e.g., y direction or -y direction). The second area A2 may extend in a first direction (e.g., x direction or -x direction). The second area A2 may not be bent in a cross section (e.g., xz cross section) in a first direction (e.g., x direction or -x direction). The second area A2 may be an area bent around an axis extending in a first direction (e.g., x direction or -x direction). Figure 2BIt is shown that the second area A2 is bent while extending in the y direction from the central area CA, and the second area A2 is bent while extending in the -y direction from the central area CA and has the same curvature, but the present disclosure is not limited to this, and according to another embodiment, the second area A2 may be bent while extending in the y direction from the central area CA, and the second area A2 may be bent while extending in the -y direction from the central area CA and have a different curvature.

[0074] The display panel 10 may be bent in the corner area CNA. The corner area CNA may be an area arranged at the corner CN. According to an embodiment, the corner area CNA may be an area where an edge of the display device 1 in a first direction (e.g., the x direction or the -x direction) meets an edge of the display device 1 in a second direction (e.g., the y direction or the -y direction). In the case where the first area A1 is bent while extending in the first direction (e.g., the x direction or the -x direction) and the second area A2 is bent while extending in the second direction (e.g., the y direction or the -y direction), at least a portion of the corner area CNA may be bent while extending in the first direction (e.g., the x direction or the -x direction) and bent while extending in the second direction (e.g., the y direction or the -y direction). In other words, at least a portion of the corner area CNA may be a multi-curvature area in which multiple curvatures in multiple directions overlap each other. According to an embodiment, the display device 1 may have multiple corner areas CNAs.

[0075] The middle area MA may be provided between the central area CA and the corner area CNA. The middle area MA may be located between the first area A1 and the corner area CNA. The middle area MA may be located between the second area A2 and the corner area CNA. According to an embodiment, the middle area MA may be curved. A driving circuit configured to provide an electrical signal to the pixel PX and / or a power supply wiring configured to provide power may be arranged in the middle area MA, and the pixel PX arranged in the middle area MA may overlap with the driving circuit and / or the power supply wiring.

[0076] The peripheral area PA may be arranged outside the central area CA. According to an embodiment, the peripheral area PA may be arranged outside the first area A1. The peripheral area PA may extend from the first area A1. According to an embodiment, the peripheral area PA extending from the first area A1 may be bent around an axis extending in a second direction (e.g., y direction or -y direction). According to an embodiment, the peripheral area PA may be arranged outside the second area A2. The peripheral area PA may extend from the second area A2. According to an embodiment, the peripheral area PA extending from the second area A2 may be bent around an axis extending in a first direction (e.g., x direction or -x direction). The pixel PX may not be arranged in the peripheral area PA. Therefore, the peripheral area PA may be a non-display area that does not display an image. A drive circuit configured to provide an electrical signal to the pixel PX and / or a power supply wiring configured to provide power may be arranged in the peripheral area PA.

[0077] Reference Figure 2A , the first area A1, the middle area MA, and a portion of the corner area CNA may be curved with a first radius of curvature R1. Figure 2B , the second area A2, the middle area MA, and another portion of the corner area CNA may be curved with a second radius of curvature R2. Figure 2C , another portion of the middle area MA and the corner area CNA may be curved at a third curvature radius R3.

[0078] The pixel PX may be disposed on the substrate 100. According to an embodiment, the pixel PX may include a light emitting diode and a pixel circuit electrically connected to the light emitting diode. The display device may include a plurality of pixels PX, and the pixel PX may display an image by emitting light.

[0079] According to an embodiment, the pixels PX may be arranged in the central area CA, the first area A1, the second area A2, the corner area CNA, and the middle area MA as the display area DA. The display device 1 may be configured to display images in the central area CA, the first area A1, the second area A2, the corner area CNA, and the middle area MA. Therefore, the proportion of the display area DA as the area where the display device 1 displays images may be increased. In addition, the display device 1 may display images at the corner CN, and thus the aesthetic feeling may be enhanced.

[0080] Figure 3 is a plan view of a display panel 10 included in a display device according to an embodiment. Figure 3 is a plan view showing a state where the display panel 10 is not bent.

[0081] Reference Figure 3, the display panel 10 may display an image. The display panel 10 may include a substrate 100, a pixel PX, and a driving circuit DC. The substrate 100 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA may include a central area CA, a first area A1, a second area A2, a corner area CNA, and an intermediate area MA. The central area CA may be a flat area. According to an embodiment, the display panel 10 may provide most of the image in the central area CA.

[0082] The first area A1 may extend from the central area CA in a first direction (eg, x direction or −x direction). According to an embodiment, the first area A1 may be disposed between the central area CA and the peripheral area PA.

[0083] The second area A2 may extend from the central area CA in the second direction (eg, the y direction or the −y direction). According to an embodiment, the second area A2 may be disposed between the central area CA and the peripheral area PA.

[0084] The corner area CNA may be an area arranged at the corner CN of the display panel 10. According to an embodiment, the corner area CNA may be an area where an edge of the display panel 10 in a first direction (e.g., x direction or -x direction) meets an edge of the display panel 10 in a second direction (e.g., y direction or -y direction).

[0085] The middle area MA may be provided between the central area CA and the corner area CNA. According to an embodiment, the middle area MA may be arranged between the first area A1 and the corner area CNA, and between the second area A2 and the corner area CNA. A driving circuit DC configured to provide an electrical signal to the pixel PX and / or a power supply wiring configured to provide power may be arranged in the middle area MA. The pixel PX arranged in the middle area MA may overlap with the driving circuit DC and / or the power supply wiring.

[0086] The peripheral area PA may be arranged outside the central area CA. The pixels PX may not be arranged in the peripheral area PA. Therefore, the peripheral area PA may be a non-display area where no image is displayed. A driving circuit DC configured to provide an electrical signal to the pixel PX and / or a power supply wiring configured to provide power may be arranged in the peripheral area PA. The peripheral area PA may include a first adjacent area AA1, a second adjacent area AA2, a third adjacent area AA3, a bending area BA, and a pad area PADA.

[0087] The first adjacent area AA1 may be arranged outside the first area A1. In other words, the first area A1 may be arranged between the first adjacent area AA1 and the central area CA. According to an embodiment, the first adjacent area AA1 may extend from the first area A1 in a first direction (e.g., x direction or -x direction). According to an embodiment, the drive circuit DC and / or the power supply wiring may be arranged in the first adjacent area AA1.

[0088] The second adjacent area AA2 and the third adjacent area AA3 may be arranged outside the second area A2. In other words, the second area A2 may be provided between the second adjacent area AA2 and the central area CA. In addition, the second area A2 may be provided between the third adjacent area AA3 and the central area CA. According to an embodiment, the second adjacent area AA2 and the third adjacent area AA3 may extend from the second area A2 in a second direction (e.g., a y direction or a -y direction).

[0089] The bending area BA may be arranged outside the third adjacent area AA3. In the bending area BA, the display panel 10 may be bent in the back direction of the substrate 100, and the pad area PADA may be located on the back surface of the display panel 10 opposite to the top surface displaying the image. Therefore, the area of ​​the peripheral area PA displayed to the user may be reduced.

[0090] The pad area PADA may be arranged outside the bending area BA. A pad (not shown) may be arranged in the pad area PADA. The display panel 10 may be configured to receive an electrical signal and / or a power voltage through the pad.

[0091] At least one of the first area A1, the second area A2, the corner area CNA, and the middle area MA may be bent. For example, a portion of the corner area CNA and the first area A1 may be bent in a cross section (e.g., xz cross section) in a first direction (e.g., x direction or -x direction). The first adjacent area AA1 extending from the first area A1 may be bent in a cross section (e.g., xz cross section) in a first direction (e.g., x direction or -x direction). Another portion of the corner area CNA and the second area A2 may be bent in a cross section (e.g., yz cross section) in a second direction (e.g., y direction or -y direction). The second adjacent area AA2 or the third adjacent area AA3 extending from the second area A2 may be bent in a cross section (e.g., yz cross section) in a second direction (e.g., y direction or -y direction). Another portion of the corner area CNA may be bent in a cross section (e.g., xz cross section) in a first direction (e.g., x direction or -x direction), and bent in a cross section (e.g., yz cross section) in a second direction (e.g., y direction or -y direction).

[0092] The pixel PX and the driving circuit DC may be provided on the substrate 100. The pixel PX may be arranged in at least one of the central area CA, the first area A1, the second area A2, the corner area CNA, and the middle area MA. According to an embodiment, the pixel PX may include a display element. According to an embodiment, the display element may be an organic light emitting diode including an organic emission layer. According to another embodiment, the display element may be an inorganic light emitting diode including an inorganic emission layer. The size of the light emitting diode may be micrometer-scale or nanometer-scale. According to an embodiment, the display element may be a quantum dot light emitting diode including a quantum dot emission layer.

[0093] Each pixel PX can be configured to emit light of various colors by using a display element. In this specification, a pixel PX can be the smallest unit for realizing an image, and can be an emission area of ​​a display element. In the case of using a light-emitting diode as a display element, the emission area can be defined by an opening of a pixel defining layer.

[0094] Each pixel PX may include a pixel circuit electrically connected to a display element. The drive circuit DC may provide a signal to the pixel circuit of the pixel PX. According to an embodiment, the drive circuit DC may be a scan drive circuit configured to provide a scan signal to the pixel PX through a scan line SL. According to another embodiment, the drive circuit DC may be an emission control drive circuit configured to provide an emission control signal to each pixel PX through an emission control line. According to another embodiment, the drive circuit DC may be a data drive circuit configured to provide a data signal to each pixel PX through a data line DL. According to an embodiment, the data drive circuit may be arranged in the third adjacent area AA3 or the pad area PADA. According to another embodiment, the data drive circuit may be arranged on a circuit board connected by a pad.

[0095] Figure 4A and Figure 4B is a schematic diagram of an equivalent circuit of a pixel included in a display device according to an embodiment.

[0096] Reference Figure 4A , the pixel may include a light emitting diode ED as a display element and a pixel circuit PC electrically connected to the light emitting diode ED. The pixel circuit PC may include a driving transistor T1, a switching transistor T2, and a storage capacitor Cst. According to an embodiment, the light emitting diode ED may be configured to emit red light, green light, or blue light, or to emit red light, green light, blue light, or white light.

[0097] The switching transistor T2 may be connected to the scan line SL and the data line DL, and may be configured to transfer a data signal input from the data line DL to the driving transistor T1 according to a scan signal input from the scan line SL.

[0098] The storage capacitor Cst may be connected to the switching transistor T2 and the driving voltage line PL, and may be configured to store a voltage corresponding to a difference between a voltage received from the switching transistor T2 and the first power voltage ELVDD supplied from the driving voltage line PL.

[0099] The driving transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may be configured to control a driving current flowing from the driving voltage line PL to the light emitting diode ED in response to the value of the voltage stored in the storage capacitor Cst. The light emitting diode ED may emit light of brightness according to the driving current. The opposite electrode of the light emitting diode ED may receive the second power voltage ELVSS.

[0100] Figure 4A It is shown that the pixel circuit PC includes two transistors and one storage capacitor, but the present invention is not limited thereto, and in another embodiment, the pixel circuit PC may include more than two transistors.

[0101] Reference Figure 4B , the pixel circuit PC may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6 and a second initialization transistor T7.

[0102] The drain electrode of the driving transistor T1 may be electrically connected to the light emitting diode ED through the emission control transistor T6. The driving transistor T1 may supply a driving current to the light emitting diode ED by receiving the data signal Dm according to the switching operation of the switching transistor T2.

[0103] A gate electrode of the switching transistor T2 may be connected to the scan line SL, and a source electrode of the switching transistor T2 may be connected to the data line DL. A drain electrode of the switching transistor T2 may be connected to the source electrode of the driving transistor T1 and to the driving voltage line PL through the operation control transistor T5.

[0104] The switching transistor T2 may be turned on according to the scan signal Sn received through the scan line SL to perform a switching operation of transmitting the data signal Dm transmitted to the data line DL to the source electrode of the driving transistor T1 .

[0105] The gate electrode of the compensation transistor T3 may be connected to the scan line SL. The source electrode of the compensation transistor T3 may be connected to the drain electrode of the drive transistor T1, and connected to the pixel electrode (e.g., anode) of the light emitting diode ED through the emission control transistor T6. The drain electrode of the compensation transistor T3 may be connected to the electrode of the storage capacitor Cst, the source electrode of the first initialization transistor T4, and the gate electrode of the drive transistor T1. The compensation transistor T3 may be turned on according to the scan signal Sn received through the scan line SL, thereby diode-connecting the drive transistor T1.

[0106] The gate electrode of the first initialization transistor T4 may be connected to the previous scan line SL-1. The drain electrode of the first initialization transistor T4 may be connected to the initialization voltage line VL. The source electrode of the first initialization transistor T4 may be connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation transistor T3, and the gate electrode of the driving transistor T1. The first initialization transistor T4 may be turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1 to transmit the initialization voltage Vint to the gate electrode of the driving transistor T1, thereby performing an initialization operation of initializing the voltage of the gate electrode of the driving transistor T1.

[0107] A gate electrode of the operation control transistor T5 may be connected to the emission control line EL. A source electrode of the operation control transistor T5 may be connected to the driving voltage line PL. A drain electrode of the operation control transistor T5 may be connected to the source electrode of the driving transistor T1 and the drain electrode of the switching transistor T2.

[0108] The gate electrode of the emission control transistor T6 may be connected to the emission control line EL. The source electrode of the emission control transistor T6 may be connected to the drain electrode of the driving transistor T1 and the source electrode of the compensation transistor T3. The drain electrode of the emission control transistor T6 may be electrically connected to the pixel electrode of the light emitting diode ED. The operation control transistor T5 and the emission control transistor T6 may be turned on at the same time according to the emission control signal En received through the emission control line EL, so that the driving current may flow to the light emitting diode ED.

[0109] The gate electrode of the second initialization transistor T7 may be connected to the previous scan line SL-1. The source electrode of the second initialization transistor T7 may be connected to the pixel electrode of the light emitting diode ED. The drain electrode of the second initialization transistor T7 may be connected to the initialization voltage line VL. The second initialization transistor T7 may be turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1 to initialize the pixel electrode of the light emitting diode ED.

[0110] Figure 4BIt is shown that both the first initialization transistor T4 and the second initialization transistor T7 are connected to the previous scan line SL-1, but the present invention is not limited thereto, and according to another embodiment, the first initialization transistor T4 and the second initialization transistor T7 may be connected to the previous scan line SL-1 and the next scan line (not shown), respectively, and the first initialization transistor T4 and the second initialization transistor T7 may be operated according to the previous scan signal Sn-1 and the next scan signal, respectively.

[0111] also, Figure 4B It is shown that both the first initialization transistor T4 and the second initialization transistor T7 are connected to the initialization voltage line VL, but the present invention is not limited thereto, and according to another embodiment, the first initialization transistor T4 and the second initialization transistor T7 may be connected to different initialization voltage lines. For example, the first initialization transistor T4 may be connected to a first initialization voltage line configured to transmit a first initialization voltage, and the second initialization transistor T7 may be connected to a second initialization voltage line configured to transmit a second initialization voltage. The first initialization voltage and the second initialization voltage may be different from each other.

[0112] One electrode of the storage capacitor Cst may be connected to the driving voltage line PL. The other electrode of the storage capacitor Cst may be simultaneously connected to the gate electrode of the driving transistor T1, the drain electrode of the compensation transistor T3, and the source electrode of the first initialization transistor T4.

[0113] An opposite electrode (eg, cathode) of the light emitting diode ED may receive the second power voltage ELVSS. The light emitting diode ED may emit light by receiving a driving current from the driving transistor T1.

[0114] According to an embodiment, some of the transistors T1 to T7 may be n-channel transistors, and the remaining transistors of the transistors T1 to T7 may be p-channel transistors. According to an embodiment, the compensation transistor T3 and the first initialization transistor T4 may be n-channel transistors, and the remaining transistors T1, T2, T5, T6 and T7 may be p-channel transistors.

[0115] A transistor including a silicon semiconductor layer has high electron mobility and excellent reliability. Therefore, the driving transistor T1 directly affecting the brightness of the organic light emitting diode (OLED) may include a silicon semiconductor layer, thereby realizing a high-resolution display device.

[0116] The transistor including the oxide semiconductor layer has a low off current and is low frequency operable. Therefore, at least one of the remaining transistors T2 to T7 excluding the driving transistor T1 may include an oxide semiconductor layer, thereby reducing power consumption of the display device.

[0117] Figure 5Aand Figure 5B According to the embodiments Figure 3 A plan view of a portion of a region G of the display panel 10, and Figure 5C yes Figure 5B An enlarged plan view of the area H shown in FIG. Figure 5A The first touch conductive layer MTL1 of the display panel 10 is schematically shown, and Figure 5B The second touch conductive layer MTL2 of the display panel 10 is schematically shown.

[0118] Reference Figure 5A and Figure 5B , the display panel 10 may include a first touch conductive layer MTL1 forming a touch sensor and a second touch conductive layer MTL2 on the first touch conductive layer MTL1. At least one insulating layer may be disposed between the first touch conductive layer MTL1 and the second touch conductive layer MTL2.

[0119] Each of the first touch conductive layer MTL1 and the second touch conductive layer MTL2 may have a single-layer structure or a stacked multilayer structure. The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al) or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO)). The transparent conductive layer may include a conductive polymer (such as poly (3,4-ethylenedioxythiophene) (PEDOT)), a metal nanowire or graphene.

[0120] The conductive layer having a multi-layer structure may have a three-layer structure of, for example, Ti / Al / Ti. The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0121] Each of the first touch conductive layer MTL1 and the second touch conductive layer MTL2 may include a plurality of conductive patterns. For example, the first touch conductive layer MTL1 may include the second connection electrode CTE2, and the second touch conductive layer MTL2 may include body portions of the driving electrode TE and the sensing electrode RE.

[0122] The driving electrodes TE may extend in a first direction (e.g., x direction or -x direction) and be spaced apart from each other in a second direction (e.g., y direction or -y direction). The driving electrode TE may include a body portion and a first connection electrode CTE1 connecting body portions adjacent to each other in the first direction (e.g., x direction or -x direction). According to an embodiment, the first connection electrode CTE1 and the body portion of the driving electrode TE may be formed integrally with each other.

[0123] The sensing electrode RE may include a second connection electrode CTE2 disposed in the first touch conductive layer MTL1 and a body portion disposed in the second touch conductive layer MTL2. The second connection electrode CTE2 may be connected to the body portions of the sensing electrodes RE adjacent in the second direction (eg, y direction or -y direction) through a contact hole CNT.

[0124] In a plan view, the first connection electrode CTE1 and the second connection electrode CTE2 may be arranged to cross each other. At least one insulating layer may be provided between the first connection electrode CTE1 and the second connection electrode CTE2, and thus, the first connection electrode CTE1 and the second connection electrode CTE2 overlapping each other in a plan view may form a type of capacitor. The touch sensor may sense an external input through a change in capacitance of such a capacitor.

[0125] The driving electrode TE and the sensing electrode RE may have a grid (or grid or lattice) pattern in a plan view. The grid pattern may be formed by grid lines extending in a third direction and a fourth direction respectively intersecting the first direction (x direction) and the second direction (y direction) intersecting each other. Therefore, the driving electrode TE and the sensing electrode RE may include a plurality of electrode holes.

[0126] Reference Figure 5A and Figure 5B , the second connection electrode CTE2 may be included in the first touch conductive layer MTL1, and body portions of the driving electrode TE and the sensing electrode RE may be included in the second touch conductive layer MTL2, but the present disclosure is not limited thereto.

[0127] According to another embodiment, the first touch conductive layer MTL1 may include a main body portion of the driving electrode TE and the sensing electrode RE, and the second touch conductive layer MTL2 may include the second connection electrode CTE2. According to another embodiment, various modifications are possible, for example, the first touch conductive layer MTL1 may include the driving electrode TE, and the second touch conductive layer MTL2 may include the sensing electrode RE.

[0128] Reference Figure 5C , the display panel 10 (for example, see Figure 3 ) may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1 may include a light emitting diode that emits red light. The second pixel PX2 may include a light emitting diode that emits green light. The third pixel PX3 may include a light emitting diode that emits blue light. Figure 5C , the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 may each indicate an emission area EA of a light emitting diode included in each pixel.

[0129] exist Figure 5CIn the embodiment, the first pixel PX1, the second pixel PX2 and the third pixel PX3 may be The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be arranged in another pattern, such as stripes or Arrangement.

[0130] The emission area EA of the light emitting diode may be defined by the pixel opening 209OP defined by the pixel defining layer 209. The non-emission area NEA may overlap with the pixel defining layer 209 in a plan view and may be arranged between adjacent emission areas EA. The area of ​​the emission area EA may be different for each pixel. Therefore, the areas of the pixel opening 209OP defined by the pixel defining layer 209 may also be different from each other. For example, in a plan view, the emission area EA of the first pixel PX1 may be larger than the emission area EA of the second pixel PX2 and smaller than the emission area EA of the third pixel PX3. However, the present disclosure is not limited thereto.

[0131] The driving electrodes TE may have a first direction (x direction (see FIG. Figure 5A and Figure 5B )) and the second direction (y direction (see Figure 5A and Figure 5B )) The grid lines of the driving electrode TE may define a plurality of electrode holes TEH. In other words, the driving electrode TE may define the electrode holes TEH. In a plan view, the electrode holes TEH may overlap with a plurality of light emitting diodes, respectively. In a plan view, the grid lines of the driving electrode TE may overlap with the non-emitting area NEA.

[0132] It has been described based on the driving electrode TE Figure 5C , but a similar or identical structure may be applied to the sensing electrode RE (see Figure 5B ), the first connection electrode CTE1 (see Figure 5B ) and the second connection electrode CTE2 (see Figure 5A ).

[0133] Fig. 6A is a display panel 10 according to an embodiment (for example, see Figure 6B ), and Figure 6B and Figure 6C yes Fig. 6A Schematic cross-sectional view of a display panel 10 . Figure 6B is along Fig. 6A Schematic cross-sectional view of the display panel 10 taken along line II′. Figure 6C 2 is a schematic cross-sectional view of a region in which the second touch electrode TE2 is arranged to describe the arrangement of the first touch conductive layer MTL1.

[0134] Reference Fig. 6A , the display panel 10 may include a plurality of inorganic patterns IP spaced apart from each other. The inorganic pattern IP may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0135] The plurality of inorganic patterns IP may respectively cover the plurality of emission areas EA of the plurality of light emitting diodes. In a plan view, the emission areas EA of the light emitting diodes may be located within corresponding inorganic patterns IP.

[0136] The inorganic patterns IP may be spaced apart from each other and define a first opening IOP between the inorganic patterns IP. The first opening IOP may have a shape in a plan view approximately corresponding to the shape of the pixel defining layer 209. In a plan view, the first opening IOP may overlap a portion of the pixel defining layer 209 and not overlap the pixel opening 209OP.

[0137] In a plan view, a plurality of inorganic patterns IP may be respectively located in a plurality of electrode holes TEH. In other words, the inorganic pattern IP may be spaced apart from the grid lines of the driving electrode TE. In a plan view, the first opening IOP may have a shape approximately corresponding to the shape of the driving electrode TE. In a plan view, the first opening IOP may overlap the driving electrode TE.

[0138] Reference Figure 6B and Figure 6C , the pixel circuit layer 200, the first light emitting diode ED1 and the second light emitting diode ED2, the encapsulation layer 300, and the touch sensor layer 400 may be sequentially stacked on the display area DA of the substrate 100. The first pixel circuit PC1 and the second pixel circuit PC2 electrically connected to the first light emitting diode ED1 and the second light emitting diode ED2, respectively, may be arranged in the pixel circuit layer 200.

[0139] The substrate 100 may include an insulating material such as glass, quartz, or a polymer resin, etc. The substrate 100 may be a rigid substrate or a flexible substrate that can be bent, folded, or rolled.

[0140] The buffer layer 201 may be disposed on the substrate 100 to reduce or prevent impurities, moisture, or external air from penetrating from the lower portion of the substrate 100 and to provide a flat surface to the semiconductor layer Act. The buffer layer 201 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic and inorganic composite, and may have a single-layer structure or a multi-layer structure including an inorganic material and an organic material.

[0141] A barrier layer 101 configured to prevent external air penetration may also be provided between the substrate 100 and the buffer layer 201. The barrier layer 101 and the buffer layer 201 may each be a single layer or a multilayer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0142] A first pixel circuit PC1 and a second pixel circuit PC2 including a thin film transistor TFT and a storage capacitor Cst may be disposed on the buffer layer 201. The first pixel circuit PC1 and the second pixel circuit PC2 may have the same or similar structure. Hereinafter, the first pixel circuit PC1 will be described.

[0143] The thin film transistor TFT may correspond to the reference Figure 4A The driving transistor T1 is described. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a drain electrode DE, and a source electrode SE.

[0144] The semiconductor layer Act may be disposed on the buffer layer 201 and may include polycrystalline silicon. According to another embodiment, the semiconductor layer Act may include amorphous silicon. According to another embodiment, the semiconductor layer Act may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer Act may include a channel region, and a source region and a drain region doped with impurities. The source region and the drain region may be arranged on both sides of the channel region.

[0145] The first gate insulating layer 203 may be provided to cover the semiconductor layer Act. The first gate insulating layer 203 may include an inorganic insulating material (such as silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x )). Zinc oxide (ZnO x ) can be ZnO or ZnO 2 The first gate insulating layer 203 may be a single layer or multiple layers including the above-mentioned inorganic insulating material.

[0146] The gate electrode GE may be disposed on the first gate insulating layer 203 and overlap the semiconductor layer Act in a plan view. The gate electrode GE may include a metal material such as Mo, Al, Cu, or Ti and may be a single layer or multiple layers. For example, the gate electrode GE may be a single layer of Mo.

[0147] The second gate insulating layer 204 may be provided to cover the gate electrode GE. The second gate insulating layer 204 may include an inorganic insulating material (such as SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 or ZnO x ). ZnO x Can be ZnO or ZnO 2 The second gate insulating layer 204 may be a single layer or multiple layers including the above-mentioned inorganic insulating material.

[0148] The second electrode CE2 of the storage capacitor Cst may be disposed on the second gate insulating layer 204. In a plan view, the second electrode CE2 may overlap the gate electrode GE. In a plan view, the gate electrode GE and the second electrode CE2 may overlap each other, and the second gate insulating layer 204 may be interposed between the gate electrode GE and the second electrode CE2, thereby forming the storage capacitor Cst. In other words, the gate electrode GE may serve as the first electrode CE1 of the storage capacitor Cst.

[0149] The second electrode CE2 may include a metal material such as Mo, Al, Cu, or Ti, and may be a single layer or a multi-layer.

[0150] An interlayer insulating layer 205 may be provided to cover the second electrode CE2. The interlayer insulating layer 205 may be a single layer or a multilayer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0151] The source electrode SE and the drain electrode DE may be disposed on the interlayer insulating layer 205. The source electrode SE and the drain electrode DE may include a metal material such as Mo, Al, Cu, or Ti, and the source electrode SE and the drain electrode DE may be a single layer or a multilayer. For example, the source electrode SE and the drain electrode DE may have a multilayer structure of a Ti layer, an Al layer, and a Ti layer. According to another embodiment, the source electrode SE or the drain electrode DE may be omitted.

[0152] The planarization insulating layer 207 may be provided to cover the source electrode SE and the drain electrode DE. The planarization insulating layer 207 may provide a flat base surface for the first light emitting diode ED1 and the second light emitting diode ED2 disposed on the planarization insulating layer 207.

[0153] The planarization insulating layer 207 may include an organic material or an inorganic material, and may have a single-layer structure or a multi-layer structure. The planarization insulating layer 207 may include benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aromatic ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, or a vinyl alcohol polymer. The planarization insulating layer 207 may include an inorganic insulating material (such as SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 or ZnO x ). ZnO x Can be ZnO or ZnO 2 When the planarization insulating layer 207 is formed, in order to provide a flat top surface after the layer is formed, mechanical polishing may be performed on the top surface of the layer.

[0154] The first light emitting diode ED1 and the second light emitting diode ED2 may be disposed on the planarization insulating layer 207. The first light emitting diode ED1 may be electrically connected to the first pixel circuit PC1, and the second light emitting diode ED2 may be electrically connected to the second pixel circuit PC2. The first light emitting diode ED1 may include a first pixel electrode 210a, an intermediate layer 220, and an opposing electrode 230, and the second light emitting diode ED2 may include a second pixel electrode 210b, an intermediate layer 220, and an opposing electrode 230. The first light emitting diode ED1 and the second light emitting diode ED2 may have substantially the same or similar structures. Hereinafter, the first light emitting diode ED1 will be described.

[0155] The planarization insulating layer 207 may include a through hole for exposing one of the source electrode SE and the drain electrode DE of the thin film transistor TFT, and the first pixel electrode 210a may contact the source electrode SE or the drain electrode DE through the through hole to be electrically connected to the thin film transistor TFT of the first pixel circuit PC1.

[0156] Figure 6BThe embodiment in which the planarization insulating layer 207 has a single-layer structure is schematically shown, but the present disclosure is not limited thereto, and according to an embodiment, the planarization insulating layer 207 may have a multi-layer structure in which a plurality of organic material layers are stacked on each other. The connection electrode may be arranged between the organic material layers, and the first pixel electrode 210a may be in contact with the source electrode SE or the drain electrode DE through the connection electrode to be electrically connected to the first pixel circuit PC1.

[0157] The first pixel electrode 210a and the second pixel electrode 210b may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The first pixel electrode 210a and the second pixel electrode 210b may include a reflective film including Ag, Mg, Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), Cr, or a compound thereof. For example, the first pixel electrode 210a and the second pixel electrode 210b may have a reflective film including ITO, IZO, ZnO, or In 2 O 3 The film is disposed on / under the reflective film, and the first pixel electrode 210 a and the second pixel electrode 210 b may have a stack structure of ITO / Ag / ITO.

[0158] The pixel defining layer 209 may include a first pixel opening 209OP1 and a second pixel opening 209OP2, the first pixel opening 209OP1 and the second pixel opening 209OP2 respectively cover the edges of the first pixel electrode 210a and the second pixel electrode 210b on the planarization insulating layer 207, and the first pixel opening 209OP1 and the second pixel opening 209OP2 respectively expose the central portions of the first pixel electrode 210a and the second pixel electrode 210b. The emission area EA (i.e., the size and shape of the pixel) of the first light emitting diode ED1 may be defined by the first pixel opening 209OP1, and the emission area EA (i.e., the size and shape of the pixel) of the second light emitting diode ED2 may be defined by the second pixel opening 209OP2.

[0159] The pixel defining layer 209 can increase the distance between the opposing electrode 230 and the edge of each of the first pixel electrode 210a and the second pixel electrode 210b, thereby preventing arcing from occurring at the edge of each of the first pixel electrode 210a and the second pixel electrode 210b. The pixel defining layer 209 can be formed by a method such as spin coating using an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, HMDSO, or phenolic resin.

[0160] The pixel defining layer 209 may be formed in black. The pixel defining layer 209 may include a light blocking material and be provided in black. The light blocking material may include a resin or paste containing carbon black, carbon nanotubes or a black dye, metal particles (such as Ni, Al, Mo or an alloy thereof), metal oxide particles (e.g., chromium oxide) or metal nitride particles (e.g., chromium nitride). In the case where the pixel defining layer 209 includes a light blocking material, external light reflection caused by a metal structure arranged at a lower portion of the pixel defining layer 209 may be reduced.

[0161] The intermediate layer 220 may be provided between the opposing electrode 230 and the first pixel electrode 210a and the second pixel electrode 210b. The intermediate layer 220 may include a first emission layer 222a formed to correspond to the first pixel electrode 210a, and a second emission layer 222b formed to correspond to the second pixel electrode 210b. For example, the first emission layer 222a may be arranged in the first pixel opening 209OP1, and the second emission layer 222b may be arranged in the second pixel opening 209OP2.

[0162] The first emission layer 222a and the second emission layer 222b may include a high molecular weight material or a low molecular weight material, and emit red light, green light, blue light, or white light.

[0163] The first functional layer 221 and the second functional layer 223 may be disposed under and / or on each of the first emission layer 222a and the second emission layer 222b. According to an embodiment, unlike the first emission layer 222a and the second emission layer 222b patterned for each pixel, the first functional layer 221 and the second functional layer 223 may be integrally provided throughout the display area DA.

[0164] The first functional layer 221 may be a single layer or a multilayer. For example, in the case where the first functional layer 221 is formed of a high molecular weight material, the first functional layer 221 may be a hole transport layer having a single layer structure, and may include poly (3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). In the case where the first functional layer 221 is formed of a low molecular weight material, the first functional layer 221 may include a hole injection layer and a hole transport layer.

[0165] The second functional layer 223 may be optional. For example, in the case where the first functional layer 221 and the emission layer 222 are formed of a high molecular weight material, the second functional layer 223 may be formed. The second functional layer 223 may be a single layer or a multilayer. The second functional layer 223 may include an electron transport layer and / or an electron injection layer. According to an embodiment, at least one of the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be omitted.

[0166] The opposing electrode 230 may include a conductive material having a relatively low work function. For example, the opposing electrode 230 may include a (semi) transparent layer including Ag, Mg, Al, Ni, Cr, Li, Ca or an alloy thereof. The opposing electrode 230 may also include a conductive material including ITO, IZO, ZnO or In on the (semi) transparent layer of such a material. 2 O 3 According to an embodiment, the opposite electrode 230 may include Ag and Mg.

[0167] According to an embodiment, a coating layer (not shown) may be further provided on the opposite electrode 230. The coating layer may improve the luminous efficiency of the first light emitting diode ED1 according to the principle of constructive interference. The coating layer may be an organic coating layer including an organic material, an inorganic coating layer including an inorganic material, or a composite coating layer including an organic material and an inorganic material.

[0168] The encapsulation layer 300 may be disposed on the first light emitting diode ED1 and the second light emitting diode ED2. According to an embodiment, the encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation layer 300 may include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0169] The first inorganic encapsulation layer 310 may be disposed on the opposite electrode 230. The first inorganic encapsulation layer 310 may be a single layer or a multilayer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. According to an embodiment, the first inorganic encapsulation layer 310 may include a silicon nitride layer. The silicon nitride layer has a dense structure, and therefore, in the case where the first inorganic encapsulation layer 310 includes a silicon nitride layer, the first light emitting diode ED1 and the second light emitting diode ED2 may be sufficiently prevented from being damaged due to a manufacturing process performed after forming the first light emitting diode ED1 and the second light emitting diode ED2. The first inorganic encapsulation layer 310 may be formed by chemical vapor deposition.

[0170] The organic encapsulating layer 320 may be disposed on the first inorganic encapsulating layer 310. The organic encapsulating layer 320 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, HMDSO, acrylic resin, or a combination thereof.

[0171] The second inorganic encapsulating layer 330 may be disposed on the organic encapsulating layer 320. The second inorganic encapsulating layer 330 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The second inorganic encapsulating layer 330 may be formed by chemical vapor deposition.

[0172] The second inorganic encapsulation layer 330 may form an inorganic pattern IP covering each of the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2. Figure 6B As schematically shown in FIG. 1 , the inorganic pattern IP may be formed as a double layer of the second inorganic encapsulation layer 330 (first inorganic layer) and the first touch insulating layer 410 (second inorganic layer) described later. According to another embodiment, the inorganic pattern IP may be formed as a single layer of the second inorganic encapsulation layer 330.

[0173] The touch sensor layer 400 may have a multi-layer structure. The touch sensor layer 400 may include a sensing electrode RE (see Figure 5B ), a sensing signal line connected to the sensing electrode RE, a driving electrode TE (see Figure 5B ), a driving signal line connected to the driving electrode TE, and at least one insulating layer. The touch sensor included in the touch sensor layer 400 may sense an external input through, for example, capacitance.

[0174] The touch sensor layer 400 may include a first touch insulating layer 410 , a first touch conductive layer MTL1 , a second touch insulating layer 420 , a second touch conductive layer MTL2 , and a third touch insulating layer 430 .

[0175] The first touch insulating layer 410 may be disposed on the encapsulation layer 300 (e.g., directly disposed on the encapsulation layer 300). The first touch insulating layer 410 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The first touch insulating layer 410 may be a layer formed throughout the substrate 100 to cover the second inorganic encapsulation layer 330 in the peripheral area PA (see FIG. Figure 1 ) in the outer boundary, thereby enhancing the adhesion of the second inorganic encapsulation layer 330.

[0176] As described above, the first touch insulating layer 410 may form an inorganic pattern IP covering each of the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2. The width (or area) of the inorganic pattern IP may be greater than the width (or area) of the corresponding emission area EA. For example, the boundary of the inorganic pattern IP corresponding to the emission area EA of the first light emitting diode ED1 may be spaced apart from the boundary of the first pixel opening 209OP1 by a first distance d1. The first distance d1 may be about 2 μm.

[0177] The first opening IOP may be defined between adjacent inorganic patterns IP. The first opening IOP may be an opening that penetrates the first touch insulating layer 410 and the second inorganic encapsulation layer 330. The first opening area OPA in which the first opening IOP is arranged may overlap with the non-emission area NEA in a plan view. In other words, in a plan view, the first opening IOP may not overlap with the first pixel opening 209OP1 and the second pixel opening 209OP2.

[0178] In the case where a portion (e.g., an edge region) of the display panel 10 is bent in the back direction of the substrate 100 to have a certain curvature, when stress is concentrated on some regions, the light emitting diode may be damaged. According to an embodiment, the inorganic layer (e.g., the second inorganic encapsulation layer 330 and the first touch insulating layer 410) on the organic encapsulation layer 320 is patterned to form inorganic patterns IP spaced apart from each other, and thus, the elongation of the top surface of the display panel 10 can be increased, thereby reducing or preventing stress from being concentrated on a region. Therefore, the reliability of the display panel 10 can be improved.

[0179] According to an embodiment, the inorganic pattern IP may be formed only in a portion (eg, an edge region) of the display panel 10. In other words, in a flat region (eg, a central region CA, see FIG. Figure 1 ), the second inorganic encapsulation layer 330 and / or the first touch insulation layer 410 may not be patterned but may be integrally formed.

[0180] According to another embodiment, the inorganic pattern IP may extend over the display area DA (see FIG. Figure 1 )form.

[0181] The first touch conductive layer MTL1 and the second touch conductive layer MTL2 may be disposed on the first touch insulating layer 410. The second touch insulating layer 420 may be disposed between the first touch conductive layer MTL1 and the second touch conductive layer MTL2.

[0182] Each of the first touch conductive layer MTL1 and the second touch conductive layer MTL2 may have a single-layer structure or a stacked multi-layer structure. The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include Mo, Ag, Ti, Cu, Al or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide (such as ITO, IZO, ZnO or ITZO). The transparent conductive layer may include a conductive polymer (such as PEDOT), a metal nanowire or graphene.

[0183] The first touch conductive layer MTL1 may include a plurality of conductive patterns. The second touch conductive layer MTL2 may include a plurality of conductive patterns. In this regard, Figure 6B and Figure 6C The first touch conductive layer MTL1 including the second touch electrode TE2 and the second touch conductive layer MTL2 including the first touch electrode TE1 are schematically illustrated.

[0184] Each of the first touch electrode TE1 and the second touch electrode TE2 may be a driving electrode, a sensing electrode, or a connecting electrode forming a touch sensor. Figure 6B The first touch electrode TE1 may correspond to Fig. 6A The driving electrode TE, and Figure 7C The second touch electrode TE2 may correspond to the second connection electrode CTE2 (see Figure 5A ), but the present disclosure is not limited thereto. The touch electrodes included in the first touch conductive layer MTL1 and the second touch conductive layer MTL2 may be variously designed.

[0185] like Figure 6C As shown in , the second touch electrode TE2 included in the first touch conductive layer MTL1 may be disposed in the first opening IOP. Therefore, at least a portion of the second touch electrode TE2 may directly contact the organic encapsulation layer 320.

[0186] Each of the first touch electrode TE1 and the second touch electrode TE2 may have a mesh structure so that light emitted from the light emitting diode is transmitted. For example, the first touch electrode TE1 and the second touch electrode TE2 may define an electrode hole TEH that overlaps with the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2, respectively, in a plan view (see FIG. Fig. 6A ). In a plan view, a mesh line of each of the first touch electrode TE1 and the second touch electrode TE2 may overlap the non-emission area NEA.

[0187] In a plan view, the inorganic pattern IP may be arranged within the corresponding electrode hole TEH. For example, a boundary of the inorganic pattern IP may be spaced apart from a boundary of a grid line defining the electrode hole TEH by a second distance d2. The second distance d2 may be about 2.5 μm.

[0188] Figure 6B and Figure 6CAn embodiment in which the inorganic pattern IP includes a first inorganic layer (e.g., a second inorganic encapsulation layer 330) and a second inorganic layer (e.g., a first touch insulating layer 410) is schematically shown, but the present disclosure is not limited thereto. According to an embodiment, the inorganic pattern IP may be a single layer including only the second inorganic encapsulation layer 330, and the first touch insulating layer 410 may be omitted. According to another embodiment, the first touch insulating layer 410 may be disposed on the inorganic pattern IP and arranged throughout the display area DA to cover the inorganic pattern IP and the first opening IOP between the inorganic pattern IP. In the case where the first touch insulating layer 410 is not patterned, the second touch electrode TE2 may be disposed on the top surface of the first touch insulating layer 410 covering the bottom surface of the first opening IOP.

[0189] The second touch insulating layer 420 may be disposed on the first touch conductive layer MTL1. The second touch insulating layer 420 may provide a flat substrate surface by filling the first opening IOP. The second touch insulating layer 420 may include an organic material. For example, the second touch insulating layer 420 may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin.

[0190] The third touch insulating layer 430 may be disposed on the second touch conductive layer MTL2. The third touch insulating layer 430 may have a single layer structure or a multi-layer structure. The third touch insulating layer 430 may include an organic material, an inorganic material, or a composite material. According to an embodiment, the third touch insulating layer 430 may be omitted.

[0191] Fig. 7A is a display panel 10 according to an embodiment (for example, see Figure 7B ), and Figure 7B and Figure 7C yes Fig. 7A Schematic cross-sectional view of a display panel 10 . Figure 7B is along Fig. 7A Schematic cross-sectional view of the display panel 10 taken along line JJ′.

[0192] 7A to 7C Similar to FIG. 6A to FIG. 6C , but is different therefrom in that: in a plan view, one inorganic pattern IP overlaps with a plurality of emission areas EA of a plurality of light emitting diodes. Hereinafter, the difference will be described.

[0193] Reference Fig. 7A , the display panel 10 may include inorganic patterns IP spaced apart from each other. The inorganic patterns IP may each cover the emission areas EA of two or more light emitting diodes. In this regard, Fig. 7AAn embodiment in which one inorganic pattern IP overlaps the emission areas EA of four light emitting diodes in a plan view is schematically illustrated.

[0194] The inorganic patterns IP may be spaced apart from each other and define a first opening IOP between the inorganic patterns IP. The first opening IOP may overlap a portion of the pixel defining layer 209 in a plan view and not overlap the pixel opening 2090P.

[0195] The plurality of inorganic patterns IP may each overlap two or more electrode holes TEH in a plan view. Thus, the inorganic pattern IP may overlap a portion of the driving electrode TE located between the corresponding electrode holes TEH in a plan view. A portion of the driving electrode TE may be disposed on the inorganic pattern IP, and the remaining portion of the driving electrode TE may be arranged in the first opening IOP.

[0196] Reference Figure 7B and Figure 7C , the inorganic pattern IP may be disposed on the organic encapsulation layer 320. According to an embodiment, the inorganic pattern IP may be provided as a double layer of the second inorganic encapsulation layer 330 and the first touch insulation layer 410. According to another embodiment, the inorganic pattern IP may be provided as a single layer of the second inorganic encapsulation layer 330.

[0197] The first opening IOP penetrating the second inorganic encapsulation layer 330 and the first touch insulating layer 410 may be formed in the non-emission area NEA between the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2. Based on the first light emitting diode ED1, the first opening IOP may not be formed in the non-emission area NEA located in the opposite direction to the second light emitting diode ED2. Based on the second light emitting diode ED2, the first opening IOP may not be formed in the non-emission area NEA located in the opposite direction to the first light emitting diode ED1.

[0198] The first touch conductive layer MTL1 may include the second touch electrode TE2, and the second touch conductive layer MTL2 may include the first touch electrode TE1. Figure 7B The first touch electrode TE1 may correspond to Fig. 7A The driving electrode TE is TE, but the present disclosure is not limited thereto.

[0199] A portion of the second touch electrode TE2 disposed in the first opening area OPA may be disposed inside the first opening IOP. A portion of the second touch electrode TE2 may directly contact the organic encapsulation layer 320 in the first opening IOP. The remaining portion of the second touch electrode TE2 may be disposed on the inorganic pattern IP.

[0200] The second touch insulating layer 420 may be disposed on the first touch conductive layer MTL1 . The second touch insulating layer 420 may provide a flat base surface by filling the first openings IOP. The first touch electrodes TE1 may be disposed on the second touch insulating layer 420 .

[0201] Fig. 8A and Figure 8B Each is a display panel 10 according to an embodiment (for example, see Figure 7B ) is a schematic cross-sectional view of a portion of ). Fig. 8A and Figure 8B yes Figure 7B A modified embodiment of the display panel 10, and Fig. 8A and Figure 8B Schematically shows the corresponding Figure 7C The area of ​​K.

[0202] Reference Fig. 8A , the inorganic pattern IP may be disposed on the organic encapsulation layer 320 and may be provided as a single layer of the second inorganic encapsulation layer 330. The inorganic patterns IP may be spaced apart from each other with the first open area OPA between the inorganic patterns IP, and adjacent inorganic patterns IP may define a first opening IOP penetrating the second inorganic encapsulation layer 330.

[0203] The touch sensor layer 400 may be disposed on the second inorganic encapsulation layer 330. The touch sensor layer 400 may include a first touch insulating layer 410, a first touch conductive layer MTL1, a second touch insulating layer 420, a second touch conductive layer MTL2 (see FIG. Figure 7B ) and a third touch insulation layer 430.

[0204] The first touch insulating layer 410 may be disposed on the inorganic pattern IP. The first touch insulating layer 410 may be integrally disposed to cover the substrate 100 (see Figure 7C ). The first touch insulating layer 410 may cover the first opening IOP.

[0205] The first touch conductive layer MTL1 may include a second touch electrode TE2. The second touch electrode TE2 may have a hole for defining an electrode hole TEH (see FIG. Fig. 7A ). At least a portion of the second touch electrode TE2 may be arranged in the first opening area OPA. In other words, at least a portion of the second touch electrode TE2 may overlap with the first opening IOP in a plan view, and may be disposed on the first touch insulating layer 410 within the first opening IOP.

[0206] The second touch insulating layer 420 may be disposed on the first touch insulating layer 410. The second touch insulating layer 420 may provide a flat base surface to the second touch conductive layer MTL2 by filling the step difference caused by the first opening IOP. The third touch insulating layer 430 may be disposed on the second touch insulating layer 420. According to an embodiment, the third touch insulating layer 430 may be omitted.

[0207] Reference Figure 8B , the inorganic pattern IP may be disposed on the organic encapsulation layer 320, and may be provided as a double layer of the second inorganic encapsulation layer 330 and the first touch insulating layer 410. The inorganic patterns IP may be spaced apart from each other with the first opening area OPA between the inorganic patterns IP, and adjacent inorganic patterns IP may define a first opening IOP penetrating the second inorganic encapsulation layer 330 and the first touch insulating layer 410.

[0208] The organic layer 440 may be disposed between the first touch insulating layer 410 and the second touch insulating layer 420. The organic layer 440 may provide a flat base surface to the first touch conductive layer MTL1 by filling the step difference caused by the first opening IOP. The organic layer 440 may include an organic material. For example, the organic layer 440 may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin.

[0209] The first touch conductive layer MTL1 may be disposed on the organic layer 440. The first touch conductive layer MTL1 may include a second touch electrode TE2. The second touch electrode TE2 may have a hole for defining an electrode THE (see FIG. 4 ). Fig. 7A ). At least a portion of the second touch electrode TE2 may be arranged in the first opening area OPA. In other words, in a plan view, at least a portion of the second touch electrode TE2 may overlap with the first opening IOP. The second touch electrode TE2 may be disposed on the organic layer 440.

[0210] The second touch insulation layer 420 may be disposed on the first touch insulation layer 410. The third touch insulation layer 430 may be disposed on the second touch insulation layer 420. According to an embodiment, the third touch insulation layer 430 may be omitted.

[0211] Fig.9A and Fig. 9B Each is a schematic cross-sectional view of a portion of a display panel 10 according to an embodiment. Fig.9A and Fig. 9B and Figure 6B Similar, but different from it in that it forms an organic pattern OPT instead of Figure 6B Inorganic pattern IP.

[0212] Reference Fig.9A , the pixel circuit layer 200, the first light emitting diode ED1 and the second light emitting diode ED2, the encapsulation layer 300 and the touch sensor layer 400 may be sequentially stacked on the display area DA of the substrate 100. The first pixel circuit PC1 and the second pixel circuit PC2 electrically connected to the first light emitting diode ED1 and the second light emitting diode ED2 may be arranged in the pixel circuit layer 200.

[0213] The encapsulation layer 300 may be disposed on the first light emitting diode ED1 and the second light emitting diode ED2. According to an embodiment, the encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation layer 300 may include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0214] The first inorganic encapsulating layer 310 may be disposed on the opposite electrode 230. The first inorganic encapsulating layer 310 may be a single layer or a multilayer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0215] The organic encapsulation layer 320 may be disposed on the first inorganic encapsulation layer 310, and may form an organic pattern OPT covering each of the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2. The organic pattern OPT may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, HMDSO, acrylic resin, or a combination thereof.

[0216] The width (or area) of the organic pattern OPT may be greater than the width (or area) of the corresponding emission area EA. For example, the organic pattern OPT corresponding to the emission area EA of the first light-emitting diode ED1 may be embedded in the first pixel opening OP1 and partially overlap the pixel defining layer 209 in a plan view. Similarly, the organic pattern OPT corresponding to the emission area EA of the second light-emitting diode ED2 may be embedded in the second pixel opening OP2 and partially overlap the pixel defining layer 209 in a plan view.

[0217] The second inorganic encapsulating layer 330 may be disposed on the organic encapsulating layer 320. The second inorganic encapsulating layer 330 may be continuously formed to cover the entire surface of the display area DA. The second inorganic encapsulating layer 330 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0218] The touch sensor layer 400 may be disposed on the encapsulation layer 300. The touch sensor layer 400 may include a first touch insulating layer 410, a first touch conductive layer MTL1, a second touch insulating layer 420, a second touch conductive layer MTL2, and a third touch insulating layer 430.

[0219] The first touch insulating layer 410 may be disposed on the encapsulation layer 300 (e.g., directly disposed on the encapsulation layer 300). The first touch insulating layer 410 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The first touch insulating layer 410 may be continuously formed to cover the entire surface of the display area DA.

[0220] The contact area CTA may be defined between the organic patterns OPT spaced apart from each other. The contact area CTA may be an area where the second inorganic encapsulation layer 330 and the first touch insulating layer 410 are in direct contact with each other to form an inorganic contact. In the case where the second inorganic encapsulation layer 330 and the first touch insulating layer 410 are in direct contact with each other and form an inorganic contact, even in the case where a portion of the inorganic layer is broken, etc., a path through which impurities (such as dust) or moisture penetrates to adjacent pixels does not expand.

[0221] The first touch conductive layer MTL1 may include a second touch electrode TE2. The second touch electrode TE2 may not overlap with the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2 in a plan view. The second touch electrode TE2 may not overlap with the organic pattern OPT in a plan view and may be arranged in a region between the organic patterns OPT.

[0222] The second touch insulating layer 420 may be disposed on the first touch conductive layer MTL1. The second touch insulating layer 420 may include an organic material. The second touch conductive layer MTL2 may be disposed on the second touch insulating layer 420. The second touch conductive layer MTL2 may include a first touch electrode TE1. In a plan view, the first touch electrode TE1 may not overlap with the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2. The first touch electrode TE1 may not overlap with the organic pattern OPT in a plan view, and may be arranged in a region between the organic patterns OPT. Each of the first touch conductive layer MTL1 and the second touch conductive layer MTL2 may have a single-layer structure or a stacked multi-layer structure.

[0223] The third touch insulating layer 430 may be disposed on the second touch conductive layer MTL2. The third touch insulating layer 430 may have a single layer structure or a multi-layer structure. The third touch insulating layer 430 may include an organic material, an inorganic material, or a composite material. According to an embodiment, the third touch insulating layer 430 may be omitted.

[0224] Reference Fig. 9B , the organic encapsulation layer 320 may be disposed on the first inorganic encapsulation layer 310, and may form an organic pattern OPT that simultaneously covers the emission areas EA of two or more light emitting diodes. For example, in a plan view, one organic pattern OPT may overlap the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2.

[0225] The touch sensor layer 400 may be disposed on the encapsulation layer 300. The touch sensor layer 400 may include a first touch insulating layer 410, a first touch conductive layer MTL1, a second touch insulating layer 420, a second touch conductive layer MTL2, and a third touch insulating layer 430.

[0226] The first touch insulating layer 410 may be disposed on the encapsulation layer 300 (e.g., directly disposed on the encapsulation layer 300). The first touch insulating layer 410 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The first touch insulating layer 410 may be continuously formed to cover the entire surface of the display area DA.

[0227] The contact area CTA may be defined between the organic patterns OPT spaced apart from each other. The contact area CTA may be an area where the second inorganic encapsulation layer 330 and the first touch insulating layer 410 are in direct contact with each other to form an inorganic contact. In the case where the second inorganic encapsulation layer 330 and the first touch insulating layer 410 are in direct contact with each other and form an inorganic contact, even in the case where a portion of the inorganic layer is broken, etc., a path through which impurities (such as dust) or moisture penetrates to adjacent pixels does not expand.

[0228] In the case where a portion (e.g., an edge region) of the display panel 10 is bent in the back direction of the substrate 100 to have a certain curvature, when stress is concentrated on some regions, the light emitting diode may be damaged. According to an embodiment, the organic patterns OPT spaced apart from each other may be formed by patterning the organic encapsulation layer 320, and thus, the elongation of the top surface of the display panel 10 may be increased, thereby reducing or preventing stress from being concentrated on a region. Therefore, the reliability of the display panel 10 may be improved.

[0229] According to an embodiment, the organic pattern OPT may be formed only in a portion (eg, an edge region) of the display panel 10. In other words, in a flat region (eg, a central region CA, see FIG. Figure 1 ), the organic encapsulation layer 320 may not be patterned but may be integrally formed.

[0230] According to another embodiment, the organic pattern OPT may extend over the display area DA (see FIG. Figure 1)form.

[0231] Fig.10 and Fig.11 is a schematic cross-sectional view of a portion of a display panel 10 according to an embodiment. Fig.10 and Figure 6B Similar and Fig.11 and Fig.9A Similar, but Fig.10 and Fig.11 and Figure 6B and Fig.9A The difference is that the pixel defining layer PDL defining the emission area EA of the light emitting diode may include an inorganic material, and the metal bank layer BNL may be further disposed on the pixel defining layer PDL. Hereinafter, the difference will be described.

[0232] Reference Fig.10 , the pixel circuit layer 200, the first light emitting diode ED1 and the second light emitting diode ED2, the encapsulation layer 300 and the touch sensor layer 400 may be sequentially stacked on the display area DA of the substrate 100. The first pixel circuit PC1 and the second pixel circuit PC2 electrically connected to the first light emitting diode ED1 and the second light emitting diode ED2 may be arranged in the pixel circuit layer 200.

[0233] The first light emitting diode ED1 and the second light emitting diode ED2 may be disposed on the planarization insulating layer 207 of the pixel circuit layer 200. The first light emitting diode ED1 may be electrically connected to the first pixel circuit PC1, and the second light emitting diode ED2 may be electrically connected to the second pixel circuit PC2. The first light emitting diode ED1 may include a first pixel electrode 210a, a first intermediate layer 220a, and a first opposing electrode 230a, and the second light emitting diode ED2 may include a second pixel electrode 210b, a second intermediate layer 220b, and a second opposing electrode 230b. The first light emitting diode ED1 and the second light emitting diode ED2 may have substantially the same or similar structures. Hereinafter, the first light emitting diode ED1 will be described.

[0234] The first pixel electrode 210a and the second pixel electrode 210b may be disposed on the planarization insulating layer 207. The first pixel electrode 210a may be electrically connected to the first pixel circuit PC1, and the second pixel electrode 210b may be electrically connected to the second pixel circuit PC2.

[0235] The first intermediate layer 220a and the second intermediate layer 220b may each include an emission layer that emits color light. The emission layer may include a high molecular weight or low molecular weight organic material. The first intermediate layer 220a and the second intermediate layer 220b may each include a first functional layer disposed below the emission layer and a second functional layer disposed on the emission layer. The first functional layer may include a hole transport layer and / or a hole injection layer. The second functional layer may include an electron transport layer and / or an electron injection layer.

[0236] The first relative electrode 230a and the second relative electrode 230b may include a conductive material having a low work function. For example, the first relative electrode 230a and the second relative electrode 230b may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca or an alloy thereof. The first relative electrode 230a and the second relative electrode 230b may also include a (semi) transparent layer including ITO, IZO, ZnO or In on the (semi) transparent layer including the above materials. 2 O 3 layer.

[0237] The pixel defining layer PDL may be disposed on the planarization insulating layer 207 and cover an edge of each of the first pixel electrode 210a and the second pixel electrode 210b. The pixel defining layer PDL may include a first pixel opening OP1 exposing a portion of the first pixel electrode 210a and a second pixel opening OP2 exposing a portion of the second pixel electrode 210b. The first pixel opening OP1 may define an emission area EA of the first light emitting diode ED1, and the second pixel opening OP2 may define an emission area EA of the second light emitting diode ED2.

[0238] The pixel defining layer PDL may include an inorganic insulating material (such as silicon oxide, silicon nitride and / or silicon oxynitride) and have a single-layer structure or a multi-layer structure. The pixel defining layer PDL may increase the distance between the edge of the first pixel electrode 210a and the first opposing electrode 230a, and the distance between the edge of the second pixel electrode 210b and the second opposing electrode 230b, thereby preventing an arc therebetween.

[0239] The remaining sacrificial layer may be disposed between the pixel defining layer PDL and the first and second pixel electrodes 210a and 210b. The remaining sacrificial layer may be a portion of the sacrificial layer for preventing surfaces of the first and second pixel electrodes 210a and 210b from being damaged during a process.

[0240] The metal bank layer BNL may be disposed on the pixel defining layer PDL. The metal bank layer BNL may include a first sub-metal layer SM1 and a second sub-metal layer SM2. The first sub-metal layer SM1 and the second sub-metal layer SM2 may include different metals. According to an embodiment, the first sub-metal layer SM1 may include Al or Mo, and the second sub-metal layer SM2 may include Ti or tantalum (Ta).

[0241] The first sub-metal layer SM1 may define a first dam opening that overlaps the first pixel opening OP1 and the second pixel opening OP2, respectively, in a plan view, and the second sub-metal layer SM2 may define a second dam opening that overlaps the first pixel opening OP1 and the second pixel opening OP2, respectively, in a plan view. The width (or area) of the first dam opening defined in the first sub-metal layer SM1 may be greater than the width (or area) defined in the second sub-metal layer SM2. In other words, an undercut structure may be formed in which the second sub-metal layer SM2 protrudes due to a portion of the first sub-metal layer SM1 located below the second sub-metal layer SM2 being removed. Therefore, the second sub-metal layer SM2 may include a first terminal PT1 that protrudes from the side surface of the first sub-metal layer SM1 toward the center of the first pixel opening OP1, and a second terminal PT2 that protrudes from the side surface of the first sub-metal layer SM1 toward the center of the second pixel opening OP2.

[0242] The dummy stack may be disposed on the top surface of the second sub-metal layer SM2. The first dummy stack located in the region adjacent to the first light-emitting diode ED1 may include a dummy layer. For example, the dummy layer of the first dummy stack may include the same material as the first intermediate layer 220a and the first relative electrode 230a, respectively. The second dummy stack located in the region adjacent to the second light-emitting diode ED2 may include a dummy layer. For example, the dummy layer of the second dummy stack may include the same material as the second intermediate layer 220b and the second relative electrode 230b, respectively.

[0243] The first relative electrode 230a may be in direct contact with the side surface of the first sub-metal layer SM1 in the first pixel opening OP1. The second relative electrode 230b may be in direct contact with the side surface of the first sub-metal layer SM1 in the second pixel opening OP2. The metal bank layer BNL may be electrically connected to a voltage line configured to transmit a common power voltage, and the first relative electrode 230a and the second relative electrode 230b may receive a second power voltage.

[0244] The encapsulation layer 300 may be disposed on the first light emitting diode ED1 and the second light emitting diode ED2. The encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation layer 300 may include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0245] The first inorganic encapsulation layer 310 may be disposed on the first relative electrode 230a and the second relative electrode 230b. The first inorganic encapsulation layer 310 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride. The first inorganic encapsulation layer 310 has a relatively high step coverage, and therefore may be in direct contact with the side surface of the first sub-metal layer SM1 and the bottom surface of the first terminal PT1, at which the first intermediate layer 220a and the first relative electrode 230a are not formed due to the first terminal PT1. Similarly, the first inorganic encapsulation layer 310 may be in direct contact with the side surface of the first sub-metal layer SM1 and the bottom surface of the second terminal PT2, at which the second intermediate layer 220b and the second relative electrode 230b are not formed. Therefore, the first inorganic encapsulation layer 310 may seal each of the first light-emitting diode ED1 and the second light-emitting diode ED2.

[0246] The organic encapsulating layer 320 may be disposed on the first inorganic encapsulating layer 310. The organic encapsulating layer 320 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, HMDSO, acrylic resin, or a combination thereof.

[0247] The second inorganic encapsulating layer 330 may be disposed on the organic encapsulating layer 320. The second inorganic encapsulating layer 330 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The second inorganic encapsulating layer 330 may be formed by chemical vapor deposition.

[0248] The second inorganic encapsulation layer 330 may form an inorganic pattern IP covering each of the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2. Fig.10 The inorganic pattern IP is schematically shown as a double layer of the second inorganic encapsulation layer 330 (first inorganic layer) and the first touch insulating layer 410 (second inorganic layer). However, the present disclosure is not limited thereto, and according to another embodiment, the inorganic pattern IP may be formed as a single layer of the second inorganic encapsulation layer 330.

[0249] The touch sensor layer 400 may have a multi-layer structure. The touch sensor layer 400 may include sensing electrodes, sensing signal lines connected to the sensing electrodes, driving electrodes, driving signal lines connected to the driving electrodes, and at least one insulating layer. The touch sensor included in the touch sensor layer 400 may sense external inputs through, for example, capacitance.

[0250] The touch sensor layer 400 may include a first touch insulating layer 410 , a first touch conductive layer MTL1 , a second touch insulating layer 420 , a second touch conductive layer MTL2 , and a third touch insulating layer 430 .

[0251] The first touch insulating layer 410 may be disposed on (eg, directly on) the encapsulation layer 300. The first touch insulating layer 410 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0252] The first touch insulating layer 410 may form an inorganic pattern IP covering each of the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2. The width (or area) of the inorganic pattern IP may be greater than the width (or area) of the corresponding emission area EA. According to another embodiment, the inorganic pattern IP may cover the emission area EA of two or more light emitting diodes.

[0253] The first opening IOP may be defined between adjacent inorganic patterns IP. The first opening IOP may be an opening that penetrates the first touch insulating layer 410 and the second inorganic encapsulation layer 330. The first opening area OPA where the first opening IOP is arranged may overlap with the non-emission area NEA in a plan view. In other words, in a plan view, the first opening IOP may not overlap with the first pixel opening 209OP1 and the second pixel opening 209OP2.

[0254] In the case where a portion (e.g., an edge region) of the display panel 10 is bent in the back direction of the substrate 100 to have a certain curvature, when stress is concentrated on some regions, the light emitting diode may be damaged. According to an embodiment, the inorganic layer (e.g., the second inorganic encapsulation layer 330 and the first touch insulating layer 410) on the organic encapsulation layer 320 may be patterned to form inorganic patterns IP spaced apart from each other, and thus, the elongation of the top surface of the display panel 10 may be increased, thereby reducing or preventing stress from being concentrated on some regions. Therefore, the reliability of the display panel 10 may be improved.

[0255] According to an embodiment, the inorganic pattern IP may be formed only in a portion (eg, an edge region) of the display panel 10. In other words, in a flat region (eg, a central region CA, see FIG. Figure 1), the second inorganic encapsulation layer 330 and / or the first touch insulation layer 410 may not be patterned but may be integrally formed.

[0256] According to another embodiment, the inorganic pattern IP may extend over the display area DA (see FIG. Figure 1 )form.

[0257] The first touch conductive layer MTL1 may be disposed on the first touch insulating layer 410. The first touch conductive layer MTL1 may include a plurality of patterns. The second touch electrode TE2 included in the first touch conductive layer MTL1 may be arranged in the first opening IOP. Therefore, at least a portion of the second touch electrode TE2 may directly contact the organic encapsulation layer 320.

[0258] Fig.10 An embodiment in which the inorganic pattern IP includes a first inorganic layer (e.g., a second inorganic encapsulation layer 330) and a second inorganic layer (e.g., a first touch insulating layer 410) is schematically shown, but the present disclosure is not limited thereto. According to an embodiment, the inorganic pattern IP may be a single layer including only the second inorganic encapsulation layer 330, and the first touch insulating layer 410 may be omitted. According to another embodiment, the first touch insulating layer 410 may be disposed on the inorganic pattern IP and cover the inorganic pattern IP and the first opening IOP between the inorganic pattern IP. In the case where the first touch insulating layer 410 is not patterned, as shown in FIG. Fig. 8A As described above, the second touch electrode TE2 may be disposed on the first touch insulating layer 410 covering the bottom surface of the first opening IOP. Figure 8B As described above, the touch sensor layer 400 may further include an organic layer 440 filling the first opening IOP between the first touch insulating layer 410 and the second touch insulating layer 420 .

[0259] The second touch insulating layer 420 may be disposed on the first touch conductive layer MTL1. The second touch insulating layer 420 may provide a flat substrate surface by filling the first opening IOP. The second touch insulating layer 420 may include an organic material. The second touch conductive layer MTL2 may be disposed on the second touch insulating layer 420. The second touch conductive layer MTL2 may include a first touch electrode TE1.

[0260] The third touch insulating layer 430 may be disposed on the second touch conductive layer MTL2. The third touch insulating layer 430 may have a single layer structure or a multi-layer structure. The third touch insulating layer 430 may include an organic material, an inorganic material, or a composite material. According to an embodiment, the third touch insulating layer 430 may be omitted.

[0261] Reference Fig.11, the encapsulation layer 300 may be disposed on the first light emitting diode ED1 and the second light emitting diode ED2. According to an embodiment, the encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation layer 300 may include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0262] The first inorganic encapsulating layer 310 may be disposed on the first and second opposing electrodes 230a and 230b. The first inorganic encapsulating layer 310 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0263] The organic encapsulation layer 320 may be disposed on the first inorganic encapsulation layer 310 , and an organic pattern OPT covering each of the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2 may be formed. Fig.11 The organic pattern OPT is schematically illustrated as overlapping one emission area EA in a plan view, but the present disclosure is not limited thereto. According to another embodiment, one organic pattern OPT may overlap the emission areas EA of two or more light emitting diodes in a plan view.

[0264] The width (or area) of the organic pattern OPT may be greater than the width (or area) of the corresponding emission area EA. For example, the organic pattern OPT corresponding to the emission area EA of the first light-emitting diode ED1 may be embedded in the first pixel opening OP1 and partially overlap the pixel defining layer PDL and the metal bank layer BNL in a plan view. Similarly, the organic pattern OPT corresponding to the emission area EA of the second light-emitting diode ED2 may be embedded in the second pixel opening OP2 and partially overlap the pixel defining layer PDL and the metal bank layer BNL in a plan view.

[0265] The second inorganic encapsulating layer 330 may be disposed on the organic encapsulating layer 320. The second inorganic encapsulating layer 330 may be continuously formed to cover the entire surface of the display area DA. The second inorganic encapsulating layer 330 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0266] The touch sensor layer 400 may be disposed on the encapsulation layer 300. The touch sensor layer 400 may include a first touch insulating layer 410, a first touch conductive layer MTL1, a second touch insulating layer 420, a second touch conductive layer MTL2, and a third touch insulating layer 430.

[0267] The first touch insulating layer 410 may be disposed on the encapsulation layer 300 (e.g., directly disposed on the encapsulation layer 300). The first touch insulating layer 410 may be a single layer or multiple layers including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The first touch insulating layer 410 may be continuously formed to cover the entire surface of the display area DA.

[0268] Between the organic patterns OPT spaced apart from each other, the second inorganic encapsulation layer 330 and the first touch insulating layer 410 may form an inorganic contact by directly contacting each other. Therefore, even if a portion of the inorganic layer is broken, etc., a path through which impurities (such as dust) or moisture penetrates to adjacent pixels may not be expanded.

[0269] The first touch conductive layer MTL1 may include a second touch electrode TE2. In a plan view, the second touch electrode TE2 may not overlap with the emission area EA of the first light emitting diode ED1 and the emission area EA of the second light emitting diode ED2. The second touch electrode TE2 may not overlap with the organic pattern OPT in a plan view and may be arranged in a region between the organic patterns OPT.

[0270] The second touch insulating layer 420 may be disposed on the first touch conductive layer MTL1. The second touch insulating layer 420 may include an organic material. The second touch conductive layer MTL2 may be disposed on the second touch insulating layer 420. The second touch conductive layer MTL2 may include a first touch electrode TE1. Each of the first touch conductive layer MTL1 and the second touch conductive layer MTL2 may have a single-layer structure or a stacked multi-layer structure.

[0271] The third touch insulating layer 430 may be disposed on the second touch conductive layer MTL2. The third touch insulating layer 430 may have a single layer structure or a multi-layer structure. The third touch insulating layer 430 may include an organic material, an inorganic material, or a composite material. According to an embodiment, the third touch insulating layer 430 may be omitted.

[0272] Fig.12 is along Figure 3 Schematic cross-sectional view of the display panel 10 taken along line EE′.

[0273] Reference Fig.12, the barrier layer 101, and the inorganic insulating layer and the organic insulating layer constituting the pixel circuit layer 200 may be disposed on the substrate 100. The inorganic insulating layer may include a buffer layer 201, a first gate insulating layer 203, a second gate insulating layer 204, and an interlayer insulating layer 205, but the present disclosure is not limited thereto, and according to the embodiment, some of them may be omitted or another layer may be added. The organic insulating layer may include a planarizing insulating layer 207, a first organic insulating layer 208, and a second organic insulating layer 211. The planarizing insulating layer 207 may be a first planarizing insulating layer, the first organic insulating layer 208 may be a second planarizing insulating layer, and the second organic insulating layer 211 may be a third planarizing insulating layer. Some of the planarizing insulating layer 207, the first organic insulating layer 208, and the second organic insulating layer 211 may be omitted, or another organic insulating layer may be added. The pixel defining layer 209 may be disposed on the second organic insulating layer 211.

[0274] The buffer layer 201, the first gate insulating layer 203, the second gate insulating layer 204, and the interlayer insulating layer 205 may be arranged on the entire surface of the substrate 100. The planarization insulating layer 207, the first organic insulating layer 208, the second organic insulating layer 211, and the pixel defining layer 209 may extend from the display area DA and cover a portion of the peripheral area PA. Among the end portions of the planarization insulating layer 207, the first organic insulating layer 208, the second organic insulating layer 211, and the pixel defining layer 209, the end portion farthest from the display area DA may be defined as the end portion OE of the organic insulating layer.

[0275] The common voltage line VSSL may be disposed on the interlayer insulating layer 205. The common voltage line VSSL may be arranged adjacent to an edge of the substrate 100 and have a ring shape with one side opened to surround at least a portion of the display area DA in a plan view.

[0276] The common voltage line VSSL may include one or more metal wirings. For example, the common voltage line VSSL may include a first metal wiring 610, a second metal wiring 620, a third metal wiring 630, and a fourth metal wiring 640 that overlap each other. The first metal wiring 610, the electrode, and the wiring arranged between the interlayer insulating layer 205 and the planarizing insulating layer 207 may include the same material. The second metal wiring 620, the electrode, and the wiring arranged between the planarizing insulating layer 207 and the first organic insulating layer 208 may include the same material. The third metal wiring 630, the electrode, and the wiring arranged between the first organic insulating layer 208 and the second organic insulating layer 211 may include the same material. The fourth metal wiring 640 and the pixel electrode of the light emitting diode may include the same material. One or more of the first metal wiring 610, the second metal wiring 620, the third metal wiring 630, and the fourth metal wiring 640 may be omitted.

[0277] In a plan view, the inner boundary of the common voltage line VSSL (e.g., in a direction toward the display area DA) may overlap with the organic insulating layer. For example, the inner boundary of the first metal wiring 610 may be arranged between the interlayer insulating layer 205 and the planarizing insulating layer 207, the inner boundary of the second metal wiring 620 may be arranged between the planarizing insulating layer 207 and the first organic insulating layer 208, the inner boundary of the third metal wiring 630 may be arranged between the first organic insulating layer 208 and the second organic insulating layer 211, and the inner boundary of the fourth metal wiring 640 may be arranged between the second organic insulating layer 211 and the pixel defining layer 209.

[0278] Pixel defining layer 209 may include an opening for exposing a portion of fourth metal wiring 640. Opposite electrode 230 may directly contact fourth metal wiring 640 through the opening of pixel defining layer 209. In other words, opposite electrode 230 may be electrically connected to common voltage line VSSL.

[0279] In a plan view, the second dam DAM2 may overlap an outer boundary (eg, a direction in an edge of the substrate 100) of the common voltage line VSSL. The first dam DAM1 may be spaced apart from the second dam DAM2 on the common voltage line VSSL. The first dam DAM1 and the second dam DAM2 may include a plurality of organic layers.

[0280] One or more sub-dams may be provided on the common voltage line VSSL. Fig.12 The first sub-dam SDAM1 and the second sub-dam SDAM2 disposed on the common voltage line VSSL are schematically shown. The first sub-dam SDAM1 and the second sub-dam SDAM2 may include a plurality of organic layers.

[0281] The first dam DAM1, the second dam DAM2, the first sub-dam SDAM1, and the second sub-dam SDAM2 may be a configuration of the organic encapsulation layer 320 for controlling the encapsulation layer 300. For example, since the organic encapsulation layer 320 may not reach the top surface of the second dam DAM2, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may directly contact the top surface of the second dam DAM2. Therefore, a path through which impurities (such as dust) or moisture penetrates from the outside of the substrate 100 to the display area DA through the organic encapsulation layer 320 may be prevented or reduced.

[0282] The encapsulation layer 300 may be arranged to cover the opposite electrode 230, the common voltage line VSSL, the first dam DAM1, the second dam DAM2, the first sub-dam SDAM1, and the second sub-dam SDAM2. The encapsulation layer 300 may include at least one inorganic encapsulation layer and one organic encapsulation layer. According to an embodiment, the encapsulation layer 300 may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0283] The first inorganic encapsulation layer 310 may cover the entire surface of the substrate 100. The organic encapsulation layer 320 may extend from the display area DA to the first dam DAM1 or the second dam DAM2. As described above, the first dam DAM1, the second dam DAM2, the first sub-dam SDAM1, and the second sub-dam SDAM2 may control the flow of the organic encapsulation layer 320.

[0284] The second inorganic encapsulation layer 330 may be disposed on the organic encapsulation layer 320. The second inorganic encapsulation layer 330 may be divided into an outer portion and an inner portion, and the second opening area OPAs are between the outer portion and the inner portion. The second inorganic encapsulation layer 330 may include a second opening IOPs extending in a direction parallel to the edge of the substrate 100 and overlapping the second opening area OPAs. The second opening IOPs may be arranged in the peripheral area PA and overlap with the organic encapsulation layer 320 in a plan view. In other words, in a plan view, the second opening IOPs may be located on the inner side (e.g., in a direction toward the display area DA) of the first dam DAM1 and the second dam DAM2. In a plan view, the second opening IOPs may have a ring shape and surround at least a portion of the display area DA along the edge of the substrate 100. According to an embodiment, the second opening IOPs may be positioned closer to the display area DA than the end portion OE of the organic insulating layer.

[0285] Fig.12 It is schematically shown that one second opening IOPs is arranged in the second opening areas OPAs, but the present disclosure is not limited thereto. According to another embodiment, a plurality of second openings IOPs may be arranged in the second opening areas OPAs. Each second opening IOPs may have a ring shape in a plan view and surround at least a portion of the display area DA.

[0286] The peripheral area PA of the display panel 10 may be bent in the back direction of the substrate 100 to have a specific curvature. When stress is concentrated on some areas, the light emitting diode may be damaged. According to an embodiment, the second opening IOPs may be formed in the second inorganic encapsulation layer 330 to prevent or reduce the generation of cracks in the stress concentrated area.

[0287] Fig.13is a plan view of a display panel 10 included in a display device according to an embodiment.

[0288] Reference Fig.13 , the display panel 10 may include a substrate 100. The substrate 100 may include a display area DA and a peripheral area PA adjacent to the display area DA.

[0289] The display area DA may include a central area CA, a first area A1, a second area A2, a corner area CNA, and a middle area MA. The central area CA may be a flat area. According to an embodiment, the display panel 10 may provide most of an image in the central area CA.

[0290] The peripheral area PA may include a first adjacent area AA1, a second adjacent area AA2, a third adjacent area AA3, a bending area BA, and a pad area PADA. Therefore, the peripheral area PA may be a non-display area where an image is not displayed.

[0291] According to an embodiment, the second opening IOPs may surround the central area CA, the first area A1, and the second area A2 in a plan view. Fig.13 As shown in FIG. 1 , the second openings IOPs may be arranged in the first adjacent area AA1, the second adjacent area AA2, the third adjacent area AA3, and the middle area MA, and may have a closed loop shape surrounding the central area CA, the first area A1, and the second area A2 in a plan view.

[0292] According to another embodiment, the second openings IOPs may be arranged in each of the first adjacent area AA1 , the second adjacent area AA2 , and the third adjacent area AA3 along the edge of the substrate 100 .

[0293] The display panel 10 may further include a reference FIG. 6A to FIG. 8B , Fig.10 and Fig.11 Describe the first opening IOP.

[0294] According to an embodiment, the second inorganic encapsulation layer 330 (see Figure 6B ) may not be patterned in the central area CA which is a flat area in the display area DA, but may be integrally formed to cover the entire surface of the central area CA. The inorganic patterns IP (see FIG. 1 ) spaced apart from each other may be patterned in the central area CA which is a flat area in the display area DA, but may be integrally formed to cover the entire surface of the central area CA. Figure 6B ) may be arranged only in some areas of the first area A1, the second area A2, the corner area CNA, and the middle area MA in the display area DA, where stress is concentrated. In other words, the second inorganic encapsulation layer 330 (see Figure 6B) may be patterned only in some areas of the first area A1, the second area A2, the corner area CNA, and the middle area MA to define the first opening IOP (see Figure 6B ).

[0295] According to another embodiment, the inorganic pattern IP (see Figure 6B ) may be arranged throughout the display area DA. In other words, the second inorganic encapsulation layer 330 (see Figure 6B ) may be patterned throughout the display area DA to define a first opening IOP (see Figure 6B ).

[0296] According to the embodiment, by including inorganic patterns spaced apart from each other, the elongation of the display panel can be increased. Therefore, damage caused by stress concentration on a portion of the display panel can be prevented or reduced, and thus, a display device with enhanced reliability can be provided. The scope of the present disclosure is not limited by this effect.

[0297] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0298] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and should be interpreted as all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, wherein: The display device comprises: A substrate, comprising a display area and a peripheral area adjacent to the display area; A plurality of light emitting diodes are arranged in the display area; A first inorganic encapsulation layer is disposed on the plurality of light emitting diodes; an organic encapsulation layer, disposed on the first inorganic encapsulation layer; a plurality of inorganic patterns disposed on the organic encapsulation layer and spaced apart from each other; and A touch electrode is disposed on the organic encapsulation layer and defines a plurality of electrode holes respectively overlapping the plurality of light emitting diodes in a plan view.

2. The display device according to claim 1, wherein: Each of the plurality of inorganic patterns covers at least one of the plurality of light emitting diodes in a plan view, and In a plan view, the plurality of inorganic patterns overlap at least one of the plurality of electrode holes.

3. The display device according to claim 1, wherein: A first opening is defined between the plurality of inorganic patterns, and In a plan view, the first opening overlaps at least a portion of the touch electrode.

4. The display device according to claim 3, wherein: A portion of the touch electrode overlapping the first opening in a plan view is in direct contact with the organic encapsulation layer, and The remaining portions of the touch electrodes are disposed on the plurality of inorganic patterns.

5. The display device according to claim 3, wherein: The display device further includes: A first inorganic layer or an organic layer is disposed on the plurality of inorganic patterns and covers the first opening. Wherein, the touch electrode is arranged on the first inorganic layer or the organic layer.

6. The display device according to claim 1, wherein: Each of the plurality of light emitting diodes includes a pixel electrode, an opposing electrode, and an emission layer disposed between the pixel electrode and the opposing electrode. The display device further includes: a pixel defining layer defining a plurality of pixel openings exposing a plurality of central portions of a plurality of the pixel electrodes; and a metal embankment layer disposed on the pixel defining layer, comprising a first sub-metal layer and a second sub-metal layer on the first sub-metal layer, wherein the metal embankment layer defines a plurality of openings overlapping the plurality of pixel openings in a plan view, and The second sub-metal layer includes an end protruding from a side surface of the first sub-metal layer toward a center direction of each of the plurality of pixel openings.

7. The display device according to claim 6, wherein: The counter electrode is in direct contact with a portion of the side surface of the first sub-metal layer, The first inorganic encapsulation layer is in direct contact with a bottom surface of the terminal and a remaining portion of the side surface of the first sub-metal layer.

8. A display device, wherein: The display device comprises: A substrate, comprising a display area and a peripheral area adjacent to the display area; A plurality of light emitting diodes are arranged in the display area; a first inorganic encapsulation layer, disposed on the plurality of light emitting diodes and extending to the peripheral region; an organic encapsulation layer, disposed on the first inorganic encapsulation layer; and a second inorganic encapsulation layer disposed on the organic encapsulation layer and defining a first opening in the peripheral region, Wherein, in a plan view, the first opening overlaps with the organic encapsulation layer.

9. The display device according to claim 8, wherein: The display device further includes: a common voltage line arranged in the peripheral area and surrounding at least a portion of the display area in a plan view; an organic insulating layer disposed between the substrate and the plurality of light emitting diodes, and overlapping a boundary of the common voltage line at one side in a plan view by extending from the display area to the peripheral area; and a dam overlapping a boundary of the common voltage line at the other side in a plan view, Wherein, the first opening is arranged closer to the display area than one end of the organic insulating layer.

10. The display device according to claim 8, wherein: The peripheral region is bent with a curvature in a back direction of the substrate.

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