Display device and head mounted display device including the same

Abstract

A display device and a head-mounted display device including the same are provided. The display device includes a first single crystal semiconductor substrate, a first transistor over the first single crystal semiconductor substrate, and a second single crystal semiconductor substrate over the first single crystal semiconductor substrate, a second single crystal semiconductor substrate having an area larger than that of the first single crystal semiconductor substrate in a plan view and including a display region in which a light emitting element is positioned and a non-display region located around the display region in the plan view, the second single crystal semiconductor substrate defining a first through-hole, a second through-hole, and a third through-hole, a first via is defined in the display area and has a first conductive via electrically connected to the light emitting element, a second via is defined in the display area and has a second conductive via electrically connected to the first transistor, and a third via is defined in the non-display area and has a third conductive via therein.

Description

Technical Field

[0001] The present disclosure relates to a display device and a head-mounted display device including the display device. Background Art

[0002] A head mounted display device (HMD) is an image display device that is worn on the user's head in the form of glasses or a helmet to form a focus at a close distance in front of the user's eyes. The head mounted display device can realize virtual reality (VR) or augmented reality (AR).

[0003] The head-mounted display device enlarges the image displayed on the small display device by using a plurality of lenses, and displays the enlarged image. Therefore, the display device applied to the head-mounted display device can appropriately provide a high-resolution image, for example, an image with a resolution of 3000PPI (pixels per inch) or more. For this reason, an organic light-emitting diode on silicon (OLEDoS), which is a small organic light-emitting display device with high resolution, is used as a display device applied to the head-mounted display device. OLEDoS is an image display device in which an organic light-emitting diode (OLED) is positioned on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is positioned. Summary of the invention

[0004] Aspects of the present disclosure provide a micro display device including a plurality of different single-crystal semiconductor substrates, and a head-mounted display device including the micro display device.

[0005] Aspects of the present disclosure also provide a micro display device having circuit elements respectively positioned on different single crystal semiconductor substrates, and a head-mounted display device including the micro display device.

[0006] However, the aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0007] According to one or more embodiments of the present disclosure, a display device includes a first single crystal semiconductor substrate, a first transistor located above the first single crystal semiconductor substrate, and a second single crystal semiconductor substrate, wherein the second single crystal semiconductor substrate is located above the first single crystal semiconductor substrate, has an area larger than that of the first single crystal semiconductor substrate in a plan view, and includes a display region in which a light emitting element is positioned and a non-display region located around the display region in a plan view, wherein the second single crystal semiconductor substrate defines a first through hole, a second through hole, and a third through hole, the first through hole being defined in the display region and having a first conductive via electrically connected to the light emitting element, the second through hole being defined in the display region and having a second conductive via electrically connected to the first transistor, and the third through hole being defined in the non-display region and having a third conductive via therein.

[0008] The display device may also include a pixel circuit portion located above the first single crystal semiconductor substrate and including some of the first transistors, a signal driver located above the first single crystal semiconductor substrate and including other of the first transistors, and a second transistor located above the second single crystal semiconductor substrate.

[0009] One of the light emitting elements may be electrically connected to one of the first transistors of the pixel circuit portion through a first conductive via, wherein one of the second transistors is electrically connected to one of the first transistors of the pixel circuit portion through a second conductive via.

[0010] The display device may further include a signal line positioned across the display region and the non-display region on the second single crystalline semiconductor substrate and connected to a third conductive via in the non-display region.

[0011] The signal line may be electrically connected to the second transistor in the display area, and may be electrically connected to the signal driver through a third conductive via.

[0012] A minimum line width of the first transistor may be smaller than a minimum line width of the second transistor.

[0013] The number of the first through holes may be equal to the number of the second through holes.

[0014] The number of each of the first through-holes and the second through-holes may be greater than the number of the third through-holes.

[0015] The first through hole may overlap the light emitting element in a thickness direction.

[0016] Some of the first through-holes or the second through-holes may not overlap with the first single crystal semiconductor substrate.

[0017] The third through hole may not overlap with the first single crystal semiconductor substrate.

[0018] The display device may further include a connection wiring layer including a connection line electrically connected to one of the first conductive via, the second conductive via, and the third conductive via and located between the first single crystal semiconductor substrate and a light emitting element layer including the light emitting element.

[0019] The connection wiring layer may be located between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate.

[0020] The connection wiring layer may be located between the second single crystal semiconductor substrate and the light emitting element layer.

[0021] The display device may further include a passivation layer surrounding the first single crystalline semiconductor substrate and partially contacting the second single crystalline semiconductor substrate.

[0022] According to one or more embodiments of the present disclosure, a display device includes a first single crystal semiconductor substrate, a first transistor located above the first single crystal semiconductor substrate, a second single crystal semiconductor substrate located above the first single crystal semiconductor substrate, a second transistor located above the second single crystal semiconductor substrate, at least one signal line electrically connected to the second transistor, a light emitting element layer located above the second single crystal semiconductor substrate and including a light emitting element, and a connection wiring layer located between the light emitting element layer and the first single crystal semiconductor substrate and including a first connection line and a second connection line, the first connection line being connected to a first conductive via located in a first through hole penetrating the second single crystal semiconductor substrate and being electrically connected to one of the second transistors and one of the first transistors, and the second connection line being connected to a second conductive via located in a second through hole penetrating the second single crystal semiconductor substrate and being electrically connected to one of the at least one signal line.

[0023] The connection wiring layer may further include a third connection line connected to a third conductive via located in a third through hole penetrating the second single crystal semiconductor substrate, wherein the third connection line is electrically connected to one of the light emitting elements and one of the first transistors.

[0024] The signal line may be electrically connected to one of the first transistors located above the first single crystal semiconductor substrate through the second conductive via and the second connection line.

[0025] An area of ​​the first single crystal semiconductor substrate in a plan view may be smaller than an area of ​​the second single crystal semiconductor substrate in a plan view.

[0026] According to one or more embodiments of the present disclosure, a head-mounted display device includes a frame mounted on a user's body and corresponding to a left eye and a right eye, a display device located in the frame, and a lens located above the display device, wherein the display device includes a first single crystal semiconductor substrate, a first transistor located above the first single crystal semiconductor substrate, a second single crystal semiconductor substrate located above the first single crystal semiconductor substrate, a second transistor located above the second single crystal semiconductor substrate, at least one signal line electrically connected to the second transistor, a light emitting element layer located above the second single crystal semiconductor substrate and including a light emitting element, and a connection wiring layer located between the light emitting element layer and the first single crystal semiconductor substrate and including a first connection line and a second connection line, the first connection line being connected to a first conductive via located in a first through hole penetrating the second single crystal semiconductor substrate and being electrically connected to the second transistor and the first transistor, and the second connection line being connected to a second conductive via located in a second through hole penetrating the second single crystal semiconductor substrate and being electrically connected to one of the at least one signal line.

[0027] The display device according to one or more embodiments may include two different single crystalline semiconductor substrates, and a manufacturing process of the single crystalline semiconductor substrate positioned on the lower portion can produce a large number of products per unit wafer substrate, thereby improving manufacturing yield.

[0028] In addition, in a display device according to one or more embodiments, circuit elements constituting a pixel circuit can be respectively positioned on two different single crystal semiconductor substrates, thereby alleviating high integration density on a single crystal semiconductor substrate with a small area and reducing parasitic capacitance that may be formed between adjacent circuit elements.

[0029] However, aspects according to embodiments of the present disclosure are not limited to the above aspects, and various other aspects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is an exploded perspective view of a display device according to one or more embodiments;

[0032] Figure 2 It is shown Figure 1 A plan view of an example of a drive unit shown in FIG.

[0033] Figure 3 It is shown Figure 1 A plan view of an example of a display portion shown in ;

[0034] Figure 4 is a block diagram showing a display device according to one or more embodiments;

[0035] Figure 5 is an equivalent circuit diagram of a pixel according to one or more embodiments;

[0036] Figure 6 is an enlarged plan view of a portion of a driving portion in a display device according to one or more embodiments;

[0037] Figure 7 is an enlarged plan view showing a part of a display portion in a display device according to one or more embodiments;

[0038] Figure 8 is a diagram schematically showing a connection between a driving section and a display section in a display device according to one or more embodiments;

[0039] Fig. 9 is a schematic cross-sectional view of a display device according to one or more embodiments;

[0040] Fig.10 is a schematic cross-sectional view of a driving portion according to one or more embodiments;

[0041] Fig.11 is a plan view showing a layout of pixels positioned in a display area of ​​a display section according to one or more embodiments;

[0042] Fig.12 is a cross-sectional view showing a portion of a display area and a portion of a non-display area in a display portion according to one or more embodiments;

[0043] Fig.13 and Fig.14 is a plan view showing a layout of a display area of ​​a display portion according to one or more other embodiments;

[0044] Fig.15 is an equivalent circuit diagram of a sub-pixel of a display device according to one or more other embodiments;

[0045] Fig.16 is a schematic cross-sectional view of a display device according to one or more other embodiments;

[0046] Fig.17 is a perspective view showing a head mounted display device according to one or more embodiments;

[0047] Fig.18 It is shown Fig.17 An exploded perspective view of an example of a head mounted display device; and

[0048] Fig.19 is a perspective view showing a head mounted display device according to one or more embodiments. DETAILED DESCRIPTION

[0049] By referring to the detailed description and drawings of the embodiments, various aspects of some embodiments of the present disclosure and methods for realizing these aspects can be more easily understood. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey various aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or unnecessary processes, elements and techniques for fully understanding various aspects of the present disclosure for those of ordinary skill in the art can be omitted. Unless otherwise stated, the same reference numerals, characters or combinations thereof represent the same elements throughout the drawings and written descriptions, and therefore their repeated descriptions can be omitted.

[0050] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "may not" when describing one or more embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and alternatives within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various technical interlocks and drives are possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0051] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0052] Various embodiments are described herein with reference to schematic cross-sectional illustrations as embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations caused by, for example, manufacturing techniques and / or tolerances are expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but include deviations in shapes caused by, for example, manufacturing.

[0053] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0054] Spatial relative terms, such as "below", "below", "lower", "lower side", "below", "above", "upper side", etc., can be used in this article for the convenience of explanation, to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. It should be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to also cover the different orientations of the device in use or in operation. For example, if the device in the figure is turned over, the element described as "below", "below" or "below" other elements or features will be subsequently oriented to "above" other elements or features. Therefore, the example terms "below" and "below" can cover both the orientations of above and below. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this indicates that the first part is arranged at the upper side or lower side of the second part, without being limited to its upper side based on the direction of gravity.

[0055] In addition, the phrase "in a plan view" means when observing the object portion from above, and the phrase "in a schematic cross-sectional view" means when observing the schematic cross-section taken by vertically cutting the object portion from the side. The term "overlap" or "overlapping" means that the first object may be located above or below the second object or on the side of the second object, and vice versa. Additionally, the term "overlap" may include stacking, facing or facing, extending on ..., covering or partially covering, or any other suitable term that will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include the meaning of any other suitable corresponding words such as "separated from ... "or "set aside ... "or "offset from ... "and any other suitable corresponding words that will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, although still facing each other, the first object and the second object may be understood to be indirectly opposite to each other.

[0056] It should be understood that when an element, layer, region, or component is referred to as being "formed on," "located on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component can be directly formed on, located on, connected to, or directly coupled to another element, layer, region, or component, or indirectly formed on, located on, connected to, or indirectly coupled to another element, layer, region, or component such that there may be one or more intervening elements, layers, regions, or components. Additionally, this may collectively mean direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it can be directly electrically connected or coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, capacitors, and / or the like. When describing embodiments, unless explicitly described as being directly connected, a connected statement indicates an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or is located on another component without intermediate components.

[0057] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the situation that the part is "directly" located "below" another part, but also includes the situation that there is another part between the part and the other part. At the same time, other expressions such as "between...", "directly between..." or "adjacent to" and "directly adjacent to" that describe the relationship between parts can be interpreted similarly. It should be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0058] For the purposes of this disclosure, expressions such as "at least one of..." or "any of..." or "one or more of...", when following a list of elements, modify the entire list of elements, rather than modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X; only Y; only Z; any combination of two or more of X, Y, and Z, such as XYZ, XY, and YZ; or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements, rather than modifying the individual elements in the list.

[0059] It should be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, area, region, layer, section or part from another element, member, component, area, region, layer, section or part. Therefore, the first element, component, area, layer or section described below can be referred to as the second element, component, area, layer or section without departing from the scope of this disclosure. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish different categories or sets of elements. For the sake of brevity, the terms "first", "second", etc. can respectively represent "first category (or first set)", "second category (or second set)", etc.

[0060] In the example, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted as a broader meaning. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0061] The terms used herein are for the purpose of describing the embodiments only and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "a" and "an" as used herein are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It should also be understood that the terms "comprise", "comprising", "have", "having", "include" and "including" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0062] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as terms of approximation rather than as terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. Taking into account the errors associated with the measurement and the measurement of a specific amount (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the stated values ​​and mean within an acceptable deviation range for a specific value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure".

[0063] In some embodiments, well-known structures and devices are described in the accompanying drawings in relation to one or more functional blocks (e.g., block diagrams), units and / or modules to avoid making various embodiments unnecessary obscurity. It will be understood by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and optionally, blocks, units and / or modules implemented by microprocessors or other similar hardware can be driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform functions different from those of the dedicated hardware. In addition, in some embodiments, blocks, units and / or modules can be physically separated into two or more separate blocks, units and / or modules that interact with each other without departing from the scope of this disclosure. Additionally, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0064] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having the same meaning as they have in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0065] Figure 1 is an exploded perspective view of a display device according to one or more embodiments.

[0066] Reference Figure 1 , the display device 10 according to one or more embodiments is a device for displaying a moving image or a still image. The display device 10 according to one or more embodiments may be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), or the like. For example, the display device 10 may be applied as a display portion of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 may be applied to a smart watch, a watch phone, a head mounted display device (HMD) for realizing virtual reality and augmented reality, and the like.

[0067] The display device 10 according to one or more embodiments may include a driving part 100, a display part 200, and a circuit board 300. The display device 10 may further include a passivation layer 900 positioned around the driving part 100 (eg, in a plan view).

[0068] The driving part 100 may have a planar shape similar to a quadrilateral shape. For example, the driving part 100 may have a planar shape similar to a square having one side in the first direction DR1 and another side in the second direction DR2 intersecting the first direction DR1. In the driving part 100, a corner where one side in the first direction DR1 and another side in the second direction DR2 intersect may be a right angle or rounded with a curvature (e.g., a predetermined curvature). The planar shape of the driving part 100 is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the driving part 100, but is not limited thereto.

[0069] The display unit 200 may be positioned on the driving unit 100. Figure 1 , the display portion 200 and the driving portion 100 are shown as being spaced apart from each other, but this is merely an example in which they are separated for the purpose of illustrating the driving portion 100. In the display device 10, the driving portion 100 and the display portion 200 may be joined to each other. The display portion 200 may have a shape or contour substantially similar to that of the driving portion 100. For example, the display portion 200 may have a planar shape similar to a square having one side in a first direction DR1 and another side in a second direction DR2 intersecting the first direction DR1. The planar shape of the display portion 200 is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0070] According to one or more embodiments, in the display device 10, the area of ​​the display unit 200 in the plan view may be larger than the area of ​​the driving unit 100 in the plan view. The display device 10 may include a driving unit 100 and a display unit 200 having different substrates, and they may have different areas. The elements formed in the driving unit 100 and the elements formed in the display unit 200 may be different, and these elements may be formed separately on different substrates. The display device 10 may be manufactured by forming a plurality of elements having different sizes, line widths, and manufacturing processes on different substrates, and then joining them. The display device 10 may have aspects in which product performance and manufacturing yield can be improved. A description thereof will be given later with reference to other drawings.

[0071] The circuit board 300 may be electrically connected to a plurality of pads in the pad region of the display portion 200 by using a conductive adhesive such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 1 100, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be positioned on the bottom surface of the driving part 100. The other end of the circuit board 300 may be connected to a plurality of pads in the pad area of ​​the display part 200 by using a conductive adhesive.

[0072] In one or more embodiments, the display device 10 may further include a heat dissipation layer overlapping the driving portion 100 and the display portion 200 in the third direction DR3. The heat dissipation layer may be positioned on the bottom surface of the driving portion 100 and may dissipate heat generated from the driving portion 100 and the display portion 200. The heat dissipation layer may include graphite having high thermal conductivity or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al).

[0073] The passivation layer 900 may be positioned on the bottom surface of the display part 200 while surrounding the driving part 100. The passivation layer 900 may reduce a step due to an area difference between the driving part 100 and the display part 200, and may also protect the driving part 100 and the display part 200.

[0074] Figure 2 It is shown Figure 1 A plan view of an example of a drive portion shown in FIG. Figure 3 It is shown Figure 1 A plan view of an example of a display portion shown in FIG. Figure 4 is a block diagram illustrating a display device according to one or more embodiments.

[0075] Reference Figures 2 to 4 The driving unit 100 of the display device 10 may include driving circuit elements of the display device 10. The driving unit 100 may include a first single crystal semiconductor substrate 110 and a driving circuit unit 400, a gate driver 600, a data driver 700, and a pixel circuit unit 800 formed on the first single crystal semiconductor substrate 110.

[0076] The first single crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Transistors of the driving circuit elements may be formed on the first single crystal semiconductor substrate 110. A plurality of transistors may be electrically connected to each other to form a driving circuit portion 400, a gate driver 600, a data driver 700, and a pixel circuit portion 800.

[0077] The accompanying drawings show that the pixel circuit unit 800 is generally positioned at the center of the driving unit 100, the gate driver 600 is positioned on the right side thereof, and the data driver 700 and the driving circuit unit 400 are positioned below the pixel circuit unit 800. However, the present disclosure is not limited thereto. In the driving unit 100, the positions of the driving circuit unit 400, the gate driver 600, the data driver 700, and the pixel circuit unit 800 may be changed in various ways according to the design structure of the plurality of circuit elements formed on the first single crystal semiconductor substrate 110.

[0078] The driving circuit unit 400 may include a timing control circuit 410 and a power supply circuit 420. In addition, the driving circuit unit 400 may also include various circuits involved in driving the display device 10, such as a gamma circuit and a logic circuit. The driving circuit unit 400 may include a plurality of transistors formed on the first single crystal semiconductor substrate 110. The transistors may be formed by a semiconductor process. For example, the plurality of transistors may be formed as complementary metal oxide semiconductor (CMOS) transistors.

[0079] The timing control circuit 410 may receive digital video data DATA and a timing signal input from the outside. The timing control circuit 410 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display unit 200 according to the timing signal. The timing control circuit 410 may output the scan timing control signal SCS to the scan driver 610 of the gate driver 600, and may output the emission timing control signal ECS to the emission driver 620 of the gate driver 600. The timing control circuit 410 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0080] The power supply circuit 420 may generate a plurality of panel driving voltages according to a power supply voltage from the outside. For example, the power supply circuit 420 may generate a first driving voltage VSS and a second driving voltage VDD to supply them to the pixel circuit portion 800. Figure 5 A description of the first driving voltage VSS and the second driving voltage VDD is provided.

[0081] The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 410 may be supplied to the pixel circuit portion 800. The first driving voltage VSS and the second driving voltage VDD of the power supply circuit 420 may also be supplied to the pixel circuit portion 800. The driving portion 100 may be bonded to the bottom surface of the display portion 200, and the driving circuit portion 400 of the driving portion 100 may be electrically connected to the display portion 200.

[0082] The gate driver 600 may include a scan driver 610 and an emission driver 620. The scan driver 610 includes a plurality of scan transistors formed on a first single crystal semiconductor substrate 110, and the emission driver 620 includes a plurality of emission transistors formed on the first single crystal semiconductor substrate 110. The plurality of scan transistors and the plurality of emission transistors may be formed by a semiconductor process. For example, the plurality of scan transistors and the plurality of emission transistors may be formed as CMOS transistors.

[0083] The scan driver 610 may include a first scan signal output part 611 and a second scan signal output part 612. Each of the first scan signal output part 611 and the second scan signal output part 612 may receive a scan timing control signal SCS from the timing control circuit 410. The first scan signal output part 611 may generate write scan signals according to the scan timing control signal SCS of the timing control circuit 410, and may sequentially output them to the first scan lines GWL. The second scan signal output part 612 may generate bias scan signals according to the scan timing control signal SCS, and may sequentially output them to the second scan lines GBL.

[0084] The emission driver 620 may receive the emission timing control signal ECS from the timing control circuit 410. The emission driver 620 may generate emission control signals in response to the emission timing control signal ECS, and may sequentially output them to the emission control lines EL.

[0085] The data driver 700 includes a plurality of data transistors formed on the first single crystal semiconductor substrate 110. The plurality of data transistors may be formed by a semiconductor process. For example, the plurality of data transistors may be formed as CMOS transistors. The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 410. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, a sub-pixel SP is selected by a write scan signal of the scan driver 610, and a data voltage may be supplied to the selected sub-pixel SP. The gate driver 600 and the data driver 700 may be any one of the signal drivers included in the driving unit 100.

[0086] The first pad area PDA1 may include a plurality of first pads PD1 arranged in the first direction DR1. The plurality of first pads PD1 may be electrically connected to a plurality of second pads PD2 of the display portion 200, and may be electrically connected to the circuit board 300 through the second pads PD2. The first pads PD1 may transmit an electrical signal applied from the circuit board 300 to the driving circuit portion 400, the gate driver 600, the data driver 700, and the pixel circuit portion 800.

[0087] The pixel circuit unit 800 includes a plurality of pixel transistors formed on the first single crystal semiconductor substrate 110. The plurality of pixel transistors may be formed by a semiconductor process. For example, the plurality of pixel transistors may be formed as CMOS transistors. The pixel circuit unit 800 may be any one of the driving circuits included in the driving unit 100.

[0088] A plurality of pixel circuits PXC, a plurality of second scanning lines GBL (see Figure 4 ) and a plurality of emission control lines EL (see Figure 4 ) may be positioned in the pixel circuit portion 800. A plurality of pixel circuits PXC may be arranged to be spaced apart from each other in the first direction DR1 and the second direction DR2. A plurality of second scan lines GBL and emission control lines EL may extend in the first direction DR1 and may be arranged to be spaced apart from each other in the second direction DR2. The second scan lines GBL and the emission control lines EL may be any one of the signal lines included in the driving portion 100 of the display device 10.

[0089] A plurality of data lines DL and a plurality of first scan lines GWL may be positioned in the display portion 200. The plurality of data lines DL may extend in the second direction DR2 and may be arranged to be spaced apart from each other in the first direction DR1. The plurality of first scan lines GWL may extend in the first direction DR1 and may be arranged to be spaced apart from each other in the second direction DR2. The first scan lines GWL and the data lines DL may be any one of the signal lines included in the display portion 200 of the display device 10.

[0090] In the display device 10 according to one or more embodiments, the transistors T1, T2, T3, and T4 (see Figure 5 ) and a plurality of wirings respectively connected thereto may be positioned on different single crystal semiconductor substrates. The display device 10 may include a driving portion 100 and a display portion 200 each including a different single crystal semiconductor substrate, and transistors and a plurality of wirings of the pixel circuit PXC may be positioned in the driving portion 100 and the display portion 200, respectively.

[0091] For example, among the plurality of wirings, the plurality of second scanning lines GBL (see Figure 4 ) and a plurality of emission control lines EL (see Figure 4) may be positioned in the driving part 100. A plurality of data lines DL and a plurality of first scan lines GWL may be positioned in the display part 200. Among the circuit elements included in the pixel circuit PXC, the circuit elements connected to the data lines DL and the first scan lines GWL may be positioned in the display part 200, and the other circuit elements may be positioned in the pixel circuit part 800 of the driving part 100. Since some wirings and some circuit elements of the pixel circuit PXC are respectively positioned on different single crystal semiconductor substrates, the display device 10 can solve the difficulty of layout design due to high integration density in a small area, and can reduce or prevent parasitic capacitance between adjacent elements. A more detailed description thereof will be given later with reference to other drawings.

[0092] The plurality of scan lines SL may include a plurality of first scan lines GWL and a plurality of second scan lines GBL. The plurality of scan lines SL, the plurality of emission control lines EL, and the plurality of data lines DL may be electrically connected to the plurality of pixel transistors, and the pixel circuit unit 800 may be electrically connected to the sub-pixels SP of the display unit 200 to transmit electrical signals suitable for light emission of the light emitting element.

[0093] The display portion 200 may include a display area DAA in which a light emitting element emitting light is positioned to display an image and a non-display area NA positioned around the display area DAA. The display portion 200 may include a second single crystal semiconductor substrate 210, a sub-pixel circuit portion 220 positioned on the second single crystal semiconductor substrate 210 (see Fig. 9 ) and display element layer 230 (see Fig. 9 ).

[0094] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The transistor element may not be formed on the second single crystal semiconductor substrate 210. However, the present disclosure is not limited thereto. In one or more other embodiments, the second single crystal semiconductor substrate 210 may further include a circuit element suitable for driving the display device 10.

[0095] A plurality of first scan lines GWL extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of data lines DL extending in the second direction DR2 and arranged in the first direction DR1 may be positioned in the display area DAA. The first scan lines GWL and the data lines DL may be connected to the plurality of sub-pixels SP of the display area DAA. In addition, the first scan lines GWL and the data lines DL may be connected to the gate driver 600 and the data driver 700 of the driving part 100.

[0096] A plurality of sub-pixels SP including light-emitting elements may be arranged in the display area DAA. A plurality of sub-pixels SP (e.g., three sub-pixels SP) may constitute one pixel PX to display colors. However, the present disclosure is not limited thereto, and one pixel PX may include four or more sub-pixels SP. The plurality of sub-pixels SP may be arranged in a matrix form in a first direction DR1 and a second direction DR2. Each of the plurality of sub-pixels SP may be electrically connected to a pixel circuit portion 800 of the driving portion 100 and electrically connected to a sub-pixel circuit portion 220 of the display portion 200 (see Fig. 9 ). Each of the sub-pixels SP includes a light emitting element, and each of the light emitting elements may emit light according to an electrical signal applied from the pixel circuit portion 800. Some of the sub-pixels SP positioned in the display area DAA of the display portion 200 may overlap with the pixel circuit portion 800 of the driving portion 100 in the thickness direction. However, the sub-pixels SP and the pixel circuit portion 800 are positioned on separate single crystal semiconductor substrates 110 and 210, and may be connected to each other via a connection wiring layer 500 (see Fig. 9 ) are electrically connected to each other.

[0097] Each of the plurality of sub-pixels SP may be connected to the first scan line GWL and the data line DL, and to the second scan line GBL and the emission control line EL of the pixel circuit part 800. Each of the plurality of sub-pixels SP may receive a data voltage of the data line DL according to a write scan signal of the first scan line GWL, and may emit light from its light emitting element according to the data voltage.

[0098] The non-display area NA may surround the display area DAA (eg, in a plan view). The non-display area NA may be an area where no pixel PX is located and thus no light is emitted therefrom. A plurality of through hole areas TSA1 and TSA2 and a second pad area PDA2 may be located in the non-display area NA.

[0099] The second pad area PDA2 may include a plurality of second pads PD2 arranged in the first direction DR1. The plurality of second pads PD2 may be electrically connected to the plurality of first pads PD1 of the driving part 100, and the circuit board 300 may be attached to the plurality of second pads PD2. The second pads PD2 may be electrically connected to the circuit board 300 and may be used to transmit an electrical signal applied from the circuit board 300 to the driving part 100.

[0100] Each of the plurality of through hole areas TSA1 and TSA2 may be positioned toward one side of the display area DAA. For example, the first through hole area TSA1 may be positioned toward the right side of the display area DAA, which is one side in the first direction DR1. The second through hole area TSA2 may be positioned toward the lower side of the display area DAA, which is the other side in the second direction DR2. The second through hole area TSA2 may be positioned between the display area DAA and the second pad area PDA2. However, the positions of the through hole areas TSA1 and TSA2 are not limited thereto and may be changed according to the design of the display unit 200 and the driving unit 100.

[0101] A plurality of first scan lines GWL may extend from the first through hole area TSA1 in the first direction DR1 to be positioned in the display area DAA. The first scan lines GWL may be connected to the first terminals TD1 positioned in the first through hole area TSA1. A plurality of data lines DL may extend from the second through hole area TSA2 in the second direction DR2 to be positioned in the display area DAA. The data lines DL may be connected to the second terminals TD2 positioned in the second through hole area TSA2.

[0102] In the display device 10, different elements, wirings, circuits, etc. located in the driving part 100 and the display part 200 can be connected to each other via a through hole passing through the second single crystal semiconductor substrate 210 of the display part 200. For example, the first terminal TD1 can be connected through a through hole TSV3 (see Figure 7 ) is connected to the gate driver 600 of the driving part 100. The second terminal TD2 can be connected to the gate driver 600 of the driving part 100 by a through hole TSV4 (see Figure 7 ) is connected to the data driver 700 of the driving unit 100. In addition, in one or more embodiments, the sub-pixel circuit unit 220 (see Fig. 9 ) and the light emitting elements of the sub-pixels SP may also be electrically connected to the pixel circuit portion 800 of the driving portion 100 through a plurality of through holes formed in the display area DAA. In the display device 10, elements for light emission of the light emitting elements may be positioned in the driving portion 100 and the display portion 200, respectively. The driving portion 100 may have a large number of circuit elements arranged at a high integration density, and power consumption may be reduced due to the miniaturization of the elements. In addition, since the elements of the pixel circuit PXC for light emission of the sub-pixels SP are also positioned in the driving portion 100 and the display portion 200, respectively, the concentration of circuit elements in the driving portion 100 may be reduced or prevented, thereby solving the design difficulties associated with the high integration density. In addition, since the circuit elements are not concentrated in the driving portion 100 having a relatively small area, the parasitic capacitance between adjacent elements may be reduced.

[0103] Figure 5is an equivalent circuit diagram of one pixel according to one or more embodiments.

[0104] Reference Figure 5 , the pixel circuit PXC of the sub-pixel SP may include a plurality of transistors T1, T2, T3 and T4 and a plurality of capacitors C1 and C2. The pixel circuit PXC may be connected to the light emitting element LE, the first scan line GWL, the second scan line GBL, the emission control line EL and the data line DL. In addition, the pixel circuit PXC may be connected to a first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied and a second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied. The first driving voltage line VSL may be a low potential voltage line, and the second driving voltage line VDL may be a high potential voltage line.

[0105] The pixel circuit PXC of the sub-pixel SP includes a plurality of transistors T1 , T2 , T3 , and T4 , which are electrically connected to the light emitting element LE, a first capacitor C1 , and a second capacitor C2 .

[0106] The light emitting element LE may emit light in response to a driving current flowing in the channel of the first transistor T1. The light emission amount of the light emitting element LE may be proportional to the driving current. The light emitting element LE may be positioned between the first transistor T1 and the first driving voltage line VSL. The first electrode of the light emitting element LE may be connected to the drain electrode of the first transistor T1, and the second electrode thereof may be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE may be an anode, and the second electrode of the light emitting element LE may be a cathode. The light emitting element LE may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer positioned between the first electrode and the second electrode, but is not limited thereto. For example, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first electrode and the second electrode.

[0107] The first transistor T1 may be a driving transistor that controls a source-drain current (hereinafter referred to as a "driving current") flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the third transistor T3, and a drain electrode connected to the second node N2.

[0108] The second transistor T2 may be positioned between the gate electrode of the first transistor T1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the first scan line GWL to connect the gate electrode of the first transistor T1 to the data line DL. As a result, the data voltage of the data line DL may be applied to the gate electrode of the first transistor T1. The second transistor T2 includes a gate electrode connected to the first scan line GWL, a drain electrode connected to the data line DL, and a source electrode connected to the gate electrode of the first transistor T1.

[0109] The third transistor T3 may be positioned between the second driving voltage line VDL and the third node N3 as the source electrode of the first transistor T1. The third transistor T3 is turned on by the emission control signal of the emission control line EL to connect the second driving voltage line VDL to the source electrode of the first transistor T1. Therefore, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1. The third transistor T3 includes a gate electrode connected to the emission control line EL, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the third node N3 as the source electrode of the first transistor T1.

[0110] The fourth transistor T4 may be positioned between the second drive voltage line VDL and the second node N2 as the drain electrode of the first transistor T1. The fourth transistor T4 is turned on by the bias scan signal of the second scan line GBL to connect the second node N2 to the second drive voltage line VDL. As a result, the second drive voltage VDD of the second drive voltage line VDL may be applied to the first electrode of the light emitting element LE. However, the second drive voltage VDD applied by the fourth transistor T4 may be an initialization voltage for initializing the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the second scan line GBL, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the second node N2.

[0111] The first capacitor C1 is formed between the first node N1 and the third node N3. In other words, the first capacitor C1 may be formed between the source electrode and the gate electrode of the first transistor T1. The first capacitor C1 includes one electrode connected to the first node N1 and another electrode connected to the third node N3. The second capacitor C2 is formed between the first node N1 and the second node N2. In other words, the second capacitor C2 may be formed between the gate electrode and the drain electrode of the first transistor T1. The second capacitor C2 includes one electrode connected to the first node N1 and another electrode connected to the second node N2.

[0112] The first node N1 is a contact point of the gate electrode of the first transistor T1, the source electrode of the second transistor T2, one electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a contact point of the drain electrode of the first transistor T1, the drain electrode of the fourth transistor T4, the other electrode of the second capacitor C2, and the first electrode of the light emitting element LE. The third node N3 is a contact point of the source electrode of the first transistor T1, the other electrode of the first capacitor C1, and the drain electrode of the third transistor T3.

[0113] Each of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be a P-type MOSFET, but is not limited thereto. Each of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be an N-type MOSFET. Alternatively, some of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be a P-type MOSFET, and each of the remaining transistors may be an N-type MOSFET.

[0114] although Figure 5 The pixel circuit PXC of the sub-pixel SP is shown to include four transistors T1, T2, T3 and T4 and two capacitors C1 and C2, but it should be noted that the pixel circuit PXC is not limited to Figure 5 For example, the number of transistors and the number of capacitors of the pixel circuit PXC of the sub-pixel SP are not limited to Figure 5 The example shown in .

[0115] According to one or more embodiments, in the display device 10, the first transistor T1, the third transistor T3, the fourth transistor T4, the first capacitor C1, and the second capacitor C2 of the pixel circuit PXC may be positioned in the driving portion 100, and the second transistor T2 may be positioned in the display portion 200. In addition, the light emitting element LE of the sub-pixel SP may be positioned in the display portion 200. The first transistor T1, the third transistor T3, the fourth transistor T4, the first capacitor C1, and the second capacitor C2 may be positioned in the pixel circuit portion 800 of the driving portion 100 and formed on the first single crystal semiconductor substrate 110. The second transistor T2 may be positioned in the display area DAA of the display portion 200 or the sub-pixel circuit portion 220 (see Fig. 9 ) and is formed on the second single crystal semiconductor substrate 210. The light emitting element LE may be positioned in the display region DAA of the display portion 200 or the display element layer 230 (see Fig. 9 )middle.

[0116] The circuit elements and the light emitting element LE formed on different single crystal semiconductor substrates may be connected through the through holes TSV1, TSV2, TSV3 and TSV4. For example, the light emitting element LE may be positioned in the display portion 200 and may be electrically connected to the first transistor T1 of the driving portion 100 through the first through hole TSV1. The second transistor T2 may be positioned in the display portion 200 and may be electrically connected to the first transistor T1 of the driving portion 100 through the second through hole TSV2.

[0117] The second scan line GBL, the emission control line EL, and the second driving voltage line VDL may be located in the driving part 100, and the first scan line GWL and the data line DL may be located in the display part 200. The first scan line GWL may be connected to the gate driver 600 of the driving part 100 through the third through hole TSV3 to receive the write scan signal. The data line DL may be connected to the data driver 700 of the driving part 100 through the fourth through hole TSV4 to receive the data signal.

[0118] Figure 6 is an enlarged plan view of a portion of a driving portion in a display device according to one or more embodiments. Figure 7 is an enlarged plan view showing a part of a display portion in a display device according to one or more embodiments. Figure 8 Schematically illustrates the connection between the driving section and the display section in a display device according to one or more embodiments. Figure 8 A general arrangement of the driving part 100 , the display part 200 , and through-vias TSV1 , TSV2 , TSV3 , and TSV4 serving as connection paths between the driving part 100 and the display part 200 is shown.

[0119] Reference Figures 6 to 8 According to one or more embodiments, the display device 10 may include a plurality of through holes TSV1, TSV2, TSV3, and TSV4 penetrating the second single crystal semiconductor substrate 210 of the display portion 200. The plurality of through holes TSV1, TSV2, TSV3, and TSV4 may be positioned in the display area DAA or the non-display area NA of the display portion 200. The through holes positioned in the display area DAA of the display portion 200 may form a path through which the light emitting element LE and the transistor (e.g., the second transistor T2 of the pixel circuit PXC) of the display portion 200 are connected to the pixel circuit portion 800. The through holes positioned in the non-display area NA of the display portion 200 may form a path through which the first scan line GWL and the data line DL are connected to the gate driver 600 and the data driver 700, respectively. The routing line RM (see FIG. 2 ) to be described later may be formed. Fig. 9 ) may be positioned in each of the plurality of through holes TSV1, TSV2, TSV3, and TSV4, and the display part 200 may be electrically connected to the driving part 100 through the routing line RM.

[0120] For example, the display device 10 may include a plurality of first through holes TSV1 and a plurality of second through holes TSV2 overlapping the display area DAA of the display part 200. The routing line positioned in the first through hole TSV1 may be electrically connected to the pixel circuit part 800 of the driving part 100 and electrically connected to the light emitting element LE of the display part 200. The routing line positioned in the second through hole TSV2 may be electrically connected to the pixel circuit part 800 of the driving part 100 and electrically connected to the second transistor T2 of the display part 200. The first through hole TSV1 may be a path for electrical connection between the pixel circuit PXC and the light emitting element LE, and the second through hole TSV2 may be a path for electrical connection between some transistors of the pixel circuit PXC and other circuit elements.

[0121] According to one or more embodiments, the number of the plurality of first through holes TSV1 and the second through holes TSV2 may be equal to the number of the plurality of pixel circuits PXC positioned in the pixel circuit portion 800, or may be equal to the number of the plurality of sub-pixels SP positioned in the display portion 200. Since one pixel circuit PXC corresponds to one sub-pixel SP and one light emitting element LE, one pixel circuit PXC may be electrically connected to the light emitting element LE and the second transistor T2 positioned in the display portion 200 through one first through hole TSV1 and one second through hole TSV2, respectively. However, in the display device 10, the display portion 200 and the driving portion 100 may have different areas in a plan view. The display area DAA of the display portion 200 and the pixel circuit portion 800 of the driving portion 100 may also have different areas in a plan view. Therefore, the first through hole TSV1 and the second through hole TSV2 may not necessarily overlap with the pixel circuit portion 800 and the pixel circuit PXC.

[0122] The display device 10 may include a plurality of third through holes TSV3 and a plurality of fourth through holes TSV4 overlapping the non-display area NA of the display part 200. The third through holes TSV3 may be positioned in the first through hole area TSA1 of the non-display area NA. The fourth through hole TSV4 may be positioned in the second through hole area TSA2. A plurality of terminals TD1 and TD2 may be positioned in the first through hole area TSA1 and the second through hole area TSA2, respectively, and the first through hole area TSA1 and the second through hole area TSA2 may be areas where the plurality of third through holes TSV3 and the plurality of fourth through holes TSV4 are formed to overlap the terminals TD1 and TD2, respectively.

[0123] The first scan line GWL may be connected to the first terminal TD1 in the first through hole area TSA1. The first terminal TD1 may be electrically connected to the gate driver 600 of the driving part 100 through a routing line positioned in the third through hole TSV3. The data line DL may be connected to the second terminal TD2 in the second through hole area TSA2. The second terminal TD2 may be electrically connected to the data driver 700 of the driving part 100 through a routing line positioned in the fourth through hole TSV4. However, as described above, in the display device 10, the display part 200 and the driving part 100 may have different areas in a plan view. The through hole areas TSA1 and TSA2 of the display part 200 may have different areas from the gate driver 600 and the data driver 700 of the driving part 100 in a plan view. Therefore, the third through hole TSV3 and the fourth through hole TSV4 may not necessarily overlap with the gate driver 600 and the data driver 700, respectively.

[0124] According to one or more embodiments, the number of the third through holes TSV3 may be equal to the number of the first scan lines GWL. The number of the fourth through holes TSV4 may be equal to the number of the data lines DL. In one or more embodiments, the number of the third through holes TSV3 may be equal to the number of rows of the pixel circuits in the array of the pixel circuits PXC. The number of the fourth through holes TSV4 may be equal to the number of columns of the pixel circuits in the array of the pixel circuits PXC.

[0125] For example, one first scan line GWL may extend in the first direction DR1 to be connected to a plurality of sub-pixels SP belonging to the same row. The number of first scan lines GWL may be equal to the number of pixel rows in the array of the plurality of sub-pixels SP. Since the plurality of sub-pixels SP respectively correspond to the plurality of pixel circuits PXC, the number of first scan lines GWL may be equal to the number of rows of pixel circuits in the array of the pixel circuits PXC, which may also be equal to the number of third through holes TSV3.

[0126] One data line DL may extend in the second direction DR2 to be connected to a plurality of sub-pixels SP belonging to the same column. The number of data lines DL may be equal to the number of pixel columns in the array of the plurality of sub-pixels SP. Since the plurality of sub-pixels SP respectively correspond to the plurality of pixel circuits PXC, the number of data lines DL may be equal to the number of columns of pixel circuits in the array of the pixel circuits PXC, which may also be equal to the number of fourth through holes TSV4. Therefore, in the display device 10, the number of each of the first through holes TSV1 and the second through holes TSV2 may be greater than the number of the third through holes TSV3 and the number of the fourth through holes TSV4.

[0127] In the display device 10 according to one or more embodiments, the light emitting element LE and the pixel circuit unit 800 positioned in the sub-pixel SP may be positioned on different single crystal semiconductor substrates. Some circuit elements (e.g., transistors) of the pixel circuit PXC in the pixel circuit unit 800 may also be positioned on different single crystal semiconductor substrates. In the display device 10, the pixel circuit unit 800, the light emitting element LE, and some of the above-mentioned circuit elements may be positioned on different single crystal semiconductor substrates, respectively, thereby alleviating high integration density and obtaining design freedom. In addition, some transistors of the pixel circuit PXC may be formed on different substrates, thereby reducing the formation of parasitic capacitance between adjacent circuit elements.

[0128] Fig. 9 is a schematic cross-sectional view of a display device according to one or more embodiments.

[0129] Reference Fig. 9 The display device 10 according to one or more embodiments may include a driving portion 100 including a first single crystal semiconductor substrate 110 and a driving circuit layer 120 positioned on the first single crystal semiconductor substrate 110. The display device 10 may also include a display portion 200 including a second single crystal semiconductor substrate 210 and a sub-pixel circuit portion 220 and a display element layer 230 positioned on the second single crystal semiconductor substrate 210. The display device 10 may include two different single crystal semiconductor substrates 110 and 210 overlapping each other in a third direction DR3 which is a thickness direction of the display device 10.

[0130] The driving part 100 may include circuit elements suitable for light emission of the light emitting element included in the display element layer 230 of the display part 200. As described above, the driving circuit layer 120 of the driving part 100 may include a driving circuit part 400, a gate driver 600, a data driver 700, a pixel circuit part 800, etc., and the circuit elements (such as transistors and capacitors) constituting them may be formed by CMOS on the first single crystal semiconductor substrate 110.

[0131] The display section 200 may include a plurality of light emitting elements that emit light to display an image of the display device 10. The light emitting elements may be electrically connected to circuit elements formed in the driving section 100 to emit light. In addition, the display section 200 may include a sub-pixel circuit section 220 in which a plurality of wirings and some circuit elements constituting the pixel circuit PXC of the pixel circuit section 800 are located. The sub-pixel circuit section 220 may include some circuit elements of the pixel circuit PXC (e.g., Figure 5 In addition, the sub-pixel circuit portion 220 may include a first scan line GWL and a data line DL positioned in a display area DAA of the display portion 200, and may include a plurality of terminals TD1 and TD2 positioned in through hole areas TSA1 and TSA2.

[0132] According to one or more embodiments, in the display device 10, in a plan view, the area of ​​the driving portion 100 or the first single crystal semiconductor substrate 110 may be smaller than the area of ​​the display portion 200 or the second single crystal semiconductor substrate 210. A plurality of transistors formed in the driving portion 100 may be formed by a semiconductor microprocess and thus may have a relatively very small size or line width. The driving portion 100 has an aspect in which a large number of circuit elements may be positioned at a high degree of integration, and power consumption may be reduced due to miniaturization of elements.

[0133] In addition, since the driving unit 100 includes only circuit elements formed by CMOS on the first single crystal semiconductor substrate 110, and does not include light-emitting elements, the driving unit 100 can appropriately ensure a space for accommodating elements formed by microprocessing therein. Even if the first single crystal semiconductor substrate 110 has an area smaller than that of the second single crystal semiconductor substrate 210, and a large number of driving units 100 can be manufactured on a single wafer substrate on which a process for forming the driving circuit layer 120 is performed, the manufacturing yield can be improved. For example, since a high-cost semiconductor process is performed to manufacture the driving unit 100, such an increase in the manufacturing yield of the driving unit 100 can lead to a cost reduction. In addition, in the display unit 200, since a large number of light-emitting elements can be formed on the second single crystal semiconductor substrate 210 having a relatively large area, a high-resolution display device can be realized.

[0134] According to one or more embodiments, the display device 10 may include a connection wiring layer 500 positioned between the second single crystal semiconductor substrate 210 of the display portion 200 and the driving circuit layer 120 of the driving portion 100. The connection wiring layer 500 may be positioned on the bottom surface of the second single crystal semiconductor substrate 210. The connection wiring layer 500 may include a plurality of routing lines RM (RM1, RM2, RM3, RM4, and RMF), and the routing lines RM may connect the sub-pixel circuit portion 220 positioned in the display portion 200, the light emitting element of the display element layer 230, and the circuit board 300 to the driving portion 100. The driving circuit layer 120 of the driving portion 100 may be electrically connected to the display portion 200 and to the circuit board 300 through the routing lines RM of the connection wiring layer 500 to transmit an electrical signal for light emission.

[0135] The first routing line RM1 may be connected to the display element layer 230 positioned in the display part 200. The first routing line RM1 may be electrically connected to the light emitting element of the display element layer 230 and the pixel circuit part 800 of the driving part 100. The first routing line RM1 may be a wiring that transmits a circuit signal suitable for light emission of the light emitting element included in the display element layer 230.

[0136] The second routing line RM2, the third routing line RM3, and the fourth routing line RM4 may each be connected to the sub-pixel circuit section 220 of the display section 200. The second routing line RM2 may be electrically connected to some circuit elements (e.g., the second transistor T2) located in the sub-pixel circuit section 220 and constituting the pixel circuit PXC, and electrically connected to the pixel circuit section 800 of the driving section 100. The second routing line RM2 may be a wiring that connects the second transistor T2 located in the sub-pixel circuit section 220 to the pixel circuit PXC of the pixel circuit section 800.

[0137] The third routing line RM3 may be electrically connected to the first terminal TD1 positioned in the sub-pixel circuit portion 220 and the gate driver 600 of the driving portion 100. The fourth routing line RM4 may be electrically connected to the second terminal TD2 positioned in the sub-pixel circuit portion 220 and electrically connected to the data driver 700 of the driving portion 100. The third routing line RM3 and the fourth routing line RM4 may be wirings for transmitting a write scan signal and a data signal from the driving portion 100, respectively.

[0138] The fifth routing line RMF may be connected to the circuit board 300. The fifth routing line RMF may be electrically connected to the first pad PD1 of the driving part 100 and the second pad PD2 of the display part 200. The fifth routing line RMF may be a wiring for transmitting a signal applied from the circuit board 300 to the driving part 100.

[0139] According to one or more embodiments, the display portion 200 of the display device 10 may include a plurality of through holes formed in the second single crystal semiconductor substrate 210, and the routing line RM of the connection wiring layer 500 may be electrically connected to the sub-pixel circuit portion 220 or the display element layer 230 through the through hole of the second single crystal semiconductor substrate 210. The second single crystal semiconductor substrate 210 may be positioned between the display element layer 230 and the driving circuit layer 120, and may include one or more through holes to provide an electrical connection path for the routing line RM.

[0140] The routing line RM may include connection lines RML1, RML2, and RML3 positioned in the connection wiring layer 500 (see Fig.12 ) and conductive vias RVA1, RVA2 and RVA3 positioned in the through hole of the second single crystal semiconductor substrate 210 (see Fig.12 The routing line RM may be a wiring that electrically connects layers positioned above and below the second single crystal semiconductor substrate 210, and the arrangement and design of vias formed in the second single crystal semiconductor substrate 210 may vary depending on the arrangement of the layers electrically connected to the routing line RM.

[0141] For example, in Fig. 9In one or more corresponding embodiments, since the area of ​​the second single crystal semiconductor substrate 210 is larger than the area of ​​the first single crystal semiconductor substrate 110 in a plan view, some sub-pixels SP included in the display element layer 230 of the display unit 200 may overlap with the pixel circuit unit 800 in the thickness direction, while some other sub-pixels SP may not overlap with the pixel circuit unit 800 in the thickness direction.

[0142] The first routing line RM1 may be electrically connected to the light emitting elements LE positioned in the plurality of sub-pixels SP of the display element layer 230 and electrically connected to the pixel circuit section 800 of the driving section 100. The conductive via RVA1 (see FIG. 1 ) of the first routing line RM1 Fig.12 ) may be arranged to overlap the display element layer 230 of the display portion 200 in the thickness direction, and among the plurality of through holes formed in the second single crystal semiconductor substrate 210, the first through hole TSV1 (see Fig.12 ) may also overlap the display element layer 230 in the thickness direction. The connection line RML1 of the first routing line RM1 (see Fig.12 ) may be electrically connected to the conductive via RVA1 and electrically connected to the pixel circuit part 800 of the driving part 100. At least an end portion of the connection line RML1 connected to the pixel circuit part 800 may overlap with the driving part 100.

[0143] In one or more embodiments, the conductive via RVA1 (see Fig.12 ) and a first through-hole TSV1 in which a first routing line RM1 is located (see Fig.12 ) may be arranged to overlap with the driving part 100, and some of the others may not overlap with the driving part 100. For example, in one or more embodiments in which the display area DAA of the display part 200 has a size larger than that of the driving part 100 in a plan view, the conductive via RVA1 (see Fig.12 ) and a first through-hole TSV1 in which a first routing line RM1 is located (see Fig.12 ) may not overlap with the driving portion 100.

[0144] The second routing line RM2 may be electrically connected to some circuit elements (eg, the second transistor T2) of the pixel circuit PXC of the sub-pixel circuit section 220 and to the pixel circuit section 800 of the driving section 100. The conductive via RVA2 (see Fig.12 ) may be arranged to overlap the sub-pixel circuit portion 220 of the display portion 200 in the thickness direction, and among the plurality of through holes formed in the second single crystal semiconductor substrate 210, the second through hole TSV2 (see Fig.12) may also overlap the sub-pixel circuit portion 220 in the thickness direction. The connection line RML2 of the second routing line RM2 (see Fig.12 ) can be electrically connected to the conductive via RVA2 (see Fig.12 ) and the pixel circuit portion 800 of the driving portion 100. At least an end portion of the connection line RML2 connected to the pixel circuit portion 800 may overlap with the driving portion 100.

[0145] In one or more embodiments, the conductive via RVA2 (see Fig.12 ) and a second through hole TSV2 in which a second routing line RM2 is located (see Fig.12 ) may be arranged to overlap with the driving portion 100, and some of the others may not overlap with the driving portion 100. For example, in one or more embodiments in which the sub-pixel circuit portion 220 of the display portion 200 has an area larger than that of the driving portion 100 in a plan view, the conductive via RVA2 (see Fig.12 ) and a second through hole TSV2 in which a second routing line RM2 is located (see Fig.12 ) may not overlap with the driving portion 100.

[0146] The third routing line RM3 and the fourth routing line RM4 may be electrically connected to the sub-pixel circuit part 220 and electrically connected to the gate driver 600 or the data driver 700 of the driving part 100. The conductive via RVA3 (see Fig.12 ) may be arranged in the first through hole area TSA1 positioned in the non-display area NA of the display portion 200, and the conductive via of the fourth routing line RM4 may be arranged in the second through hole area TSA2 positioned in the non-display area NA of the display portion 200. Therefore, the conductive via RVA3 of the third routing line RM3 (see Fig.12 ) and a third through hole TSV3 in which a third routing line RM3 is located (see Fig.12 ) may not overlap with the driving part 100 in the thickness direction. However, due to the connection line RML3 (see Fig.12 ) is connected to the conductive via RVA3 and the driving part 100, so at least the end of the connection line RML3 connected to the gate driver 600 may overlap the driving part 100. The description of the arrangement of the third through via TSV3 and the third routing line RM3 may also apply to the fourth routing line RM4.

[0147] The conductive via of the fifth routing line RMF may be arranged to overlap with the first pad PD1 of the driving part 100. Among the plurality of through holes formed in the second single crystal semiconductor substrate 210, the through hole in which the fifth routing line RMF is positioned may also overlap with the first pad PD1 in the thickness direction. The connection line of the fifth routing line RMF may be electrically connected to the second pad PD2 of the display part 200 to form a path for electrically connecting to the conductive via connected to the first pad PD1.

[0148] However, the present disclosure is not limited thereto. The arrangement and connection design of the plurality of routing lines RM may be modified in various ways.

[0149] The passivation layer 900 may be positioned around the driving part 100. The passivation layer 900 may be positioned on the bottom surface of the display part 200 while surrounding the driving part 100. In the manufacturing process of the display device 10, the passivation layer 900 may be formed to cover the driving part 100 to fill the step between the driving part 100 and the display part 200. In the manufacturing process of the display device 10, if the first single crystal semiconductor substrate 110 is attached to the bottom surface of the second single crystal semiconductor substrate 210 whose area is different from that of the first single crystal semiconductor substrate 110, the passivation layer 900 may fill the step between the first single crystal semiconductor substrate 110 and the second single crystal semiconductor substrate 210, and an additional process may be performed on the second single crystal semiconductor substrate 210.

[0150] In one or more embodiments, the thickness of the passivation layer 900 may be greater than the thickness of the first single crystal semiconductor substrate 110. The passivation layer 900 may be thicker than or equal to the sum of the thicknesses of the first single crystal semiconductor substrate 110 of the driving part 100 and the driving circuit layer 120 positioned thereon. The passivation layer 900 may be formed to be thicker than the driving part 100, so that a portion of the passivation layer 900 may directly contact the bottom surface of the display part 200, and another portion thereof may directly contact the bottom surface of the driving part 100. Therefore, the driving part 100 and the display part 200 may be completely covered by the passivation layer 900 on the bottom surface of the display device 10.

[0151] In addition, in a plan view, the passivation layer 900 may have the same area as that of the second single crystal semiconductor substrate 210, and a side surface of the passivation layer 900 may be parallel to a side surface of the second single crystal semiconductor substrate 210. In the manufacturing process of the display device 10, when the second single crystal semiconductor substrate 210 is separated from the wafer substrate, the passivation layer 900 may be separated together with the second single crystal semiconductor substrate 210. The area of ​​the passivation layer 900 in a plan view may be equal to the area of ​​the second single crystal semiconductor substrate 210 in a plan view. Even if the display device 10 includes the first single crystal semiconductor substrate 110 and the second single crystal semiconductor substrate 210 having different areas in a plan view, all local steps may be compensated by the passivation layer 900 to ensure structural stability.

[0152] Hereinafter, the structures of the driving circuit layer 120 of the driving part 100 and the display element layer 230 of the display part 200 will be described in detail with reference to other drawings.

[0153] Fig.10 is a schematic cross-sectional view of a driving portion according to one or more embodiments.

[0154] Reference Fig.10 , the driving part 100 may include a first single crystal semiconductor substrate 110 and a driving circuit layer 120 positioned thereon. Fig.10 The cross-sectional structure of the data driver 700 and the pixel circuit portion 800 positioned in the circuit portion in the driving portion 100 is schematically shown.

[0155] The first single crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first single crystal semiconductor substrate 110 may be a substrate doped with a first type of impurity. A plurality of well regions may be positioned on the top surface of the first single crystal semiconductor substrate 110. The plurality of well regions may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, if the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, if the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0156] The first single crystal semiconductor substrate 110 may include a plurality of first transistors PTR1 constituting a plurality of circuit elements of the driving portion 100. Each of the well regions formed in the first single crystal semiconductor substrate 110 may include a source region SA corresponding to a source electrode of the first transistor PTR1, a drain region DA corresponding to a drain electrode of the first transistor PTR1, and a channel region CH positioned between the source region SA and the drain region DA.

[0157] In one or more embodiments in which the first single crystal semiconductor substrate 110 is doped with first type impurities, each of the source region SA and the drain region DA may be doped with the first type impurities. The gate electrode GE may overlap with the well region between the source region SA and the drain region DA, and the channel region CH may be formed between the source region SA and the drain region DA (e.g., in a plan view). A portion of the first semiconductor insulating layer SINS1 may overlap with the gate electrode GE and may be positioned between the gate electrode GE and the well region. In some embodiments, both ends of the gate electrode GE and the portion of the first semiconductor insulating layer SINS1 overlapping with the gate electrode GE may partially overlap with the source region SA and the drain region DA, respectively. The first transistor PTR1 constituting the pixel circuit portion 800 shown in the drawings may be a transistor constituting Figure 5The transistor of the pixel circuit PXC of the data driver 700 may be one of the transistors of the pixel circuit PXC and may be any one of the first transistor T1, the third transistor T3 and the fourth transistor T4 positioned in the driving part 100. The transistor of the data driver 700 may be a transistor constituting a circuit such as the timing control circuit 410 and the power supply circuit 420.

[0158] When the driving circuit layer 120 is formed on a silicon wafer substrate, a process of reducing the thickness of the first single crystalline semiconductor substrate 110 may be performed. The first single crystalline semiconductor substrate 110 may have a thickness smaller than that of a wafer substrate on which a semiconductor process for forming the driving circuit layer 120 is performed. In some embodiments, the thickness of the first single crystalline semiconductor substrate 110 may be about 100 μm or less, for example, in a range of about 80 μm to about 100 μm.

[0159] The driving circuit layer 120 may include a first semiconductor insulating layer SINS1, a second semiconductor insulating layer SINS2, a plurality of contact electrodes CTE, a first interlayer insulating layer INS1, a second interlayer insulating layer INS2, a plurality of conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7, and ML8, and a plurality of vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, and VA8. The driving circuit layer 120 may include wirings electrically connected to the plurality of first transistors PTR1 included in the first single crystal semiconductor substrate 110.

[0160] The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be positioned on the first single crystal semiconductor substrate 110 (as used herein, "on" may mean "above" or "over"). The first semiconductor insulating layer SINS1 may be an insulating layer positioned on the first single crystal semiconductor substrate 110, and the second semiconductor insulating layer SINS2 may be an insulating layer positioned on the gate electrode GE of the first transistor PTR1. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic layer, but not limited thereto. In the drawings, the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 are each shown as a single layer having a corresponding thickness (e.g., a predetermined thickness), but not limited thereto. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may have a structure in which one or more layers are stacked on top of each other.

[0161] A plurality of contact electrodes CTE may be positioned on the first single crystal semiconductor substrate 110. The plurality of contact electrodes CTE may be connected to one of the gate electrode GE, the source region SA, and the drain region DA of each first transistor PTR1 formed on the first single crystal semiconductor substrate 110 through holes penetrating the semiconductor insulating layers SINS1 and SINS2. The plurality of contact electrodes CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. Top surfaces of the plurality of contact electrodes CTE may be exposed without being covered by the semiconductor insulating layers SINS1 and SINS2.

[0162] The first interlayer insulating layer INS1 may be positioned on the plurality of contact electrodes CTE and the semiconductor insulating layers SINS1 and SINS2. The second interlayer insulating layer INS2 may be positioned on the first interlayer insulating layer INS1. Each of the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto. Although it is shown in the drawings that each of the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 is formed as a single layer, the present disclosure is not limited thereto. Each of the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may have a structure in which one or more layers are stacked on top of each other, and may be positioned between a plurality of first conductive layers ML1, a plurality of second conductive layers ML2, a plurality of third conductive layers ML3, a plurality of fourth conductive layers ML4, a plurality of fifth conductive layers ML5, a plurality of sixth conductive layers ML6, a plurality of seventh conductive layers ML7, and a plurality of eighth conductive layers ML8 to be described later.

[0163] The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 can be electrically connected to the multiple contact electrodes CTE and can form the pixel circuit part 800 or the driving circuit part 400 of the driving part 100 and the drivers 600 and 700. A plurality of first transistors PTR1 formed on the first single crystal semiconductor substrate 110 may be electrically connected to each other through the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7, and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, and the eighth via VA8, and may form the driving circuit portion 400, the gate driver 600, the data driver 700, and the pixel circuit portion 800 of the driving portion 100. For example, Figure 5 The first transistor T1, the third transistor T3 and the fourth transistor T4 included in the pixel circuit PXC of the sub-pixel SP shown in the figure may be a plurality of first transistors PTR1 included in the first single crystal semiconductor substrate 110, and the connection between the first capacitor C1 and the second capacitor C2 and the transistors T1, T3 and T4 may be formed through the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8.

[0164] The first conductive layer ML1 may be connected to the contact electrode CTE through the first via VA1. The first conductive layer ML1 may be positioned on the contact electrode CTE, and the first via VA1 may be positioned between the first conductive layer ML1 and the contact electrode CTE to contact both of them.

[0165] The second conductive layer ML2 may be connected to the first conductive layer ML1 through the second via VA2. The second conductive layer ML2 may be positioned on the first conductive layer ML1, and the second via VA2 may be positioned between the first conductive layer ML1 and the second conductive layer ML2 to contact both of them.

[0166] The third conductive layer ML3 may be connected to the second conductive layer ML2 through a third via VA3. The fourth conductive layer ML4 may be connected to the third conductive layer ML3 through a fourth via VA4. The fifth conductive layer ML5 may be connected to the fourth conductive layer ML4 through a fifth via VA5. The sixth conductive layer ML6 may be connected to the fifth conductive layer ML5 through a sixth via VA6.

[0167] The third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be sequentially positioned on the second conductive layer ML2. The third via VA3, the fourth via VA4, the fifth via VA5 and the sixth via VA6 may be positioned between the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6, respectively. The third via VA3, the fourth via VA4, the fifth via VA5 and the sixth via VA6 may contact different metal layers positioned above and below them, respectively. The seventh via VA7 may be positioned on the sixth conductive layer ML6. The seventh via VA7 may contact the seventh conductive layer ML7 and the sixth conductive layer ML6 positioned thereon.

[0168] The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6 and the seventh via VA7 may be positioned in the first interlayer insulating layer INS1. The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6 and the seventh via VA7 may constitute a first driving circuit layer positioned in the first interlayer insulating layer INS1 of the driving circuit layer 120.

[0169] The seventh conductive layer ML7 may be connected to the sixth conductive layer ML6 through the seventh via VA7. The seventh conductive layer ML7 may be positioned on the first interlayer insulating layer INS1 and the sixth conductive layer ML6. The seventh via VA7 may be positioned between the sixth conductive layer ML6 and the seventh conductive layer ML7 to contact them. The eighth conductive layer ML8 may be connected to the seventh conductive layer ML7 through the eighth via VA8. The eighth conductive layer ML8 is positioned on the seventh conductive layer ML7. The eighth via VA8 may be positioned between the seventh conductive layer ML7 and the eighth conductive layer ML8 to contact them. The top surface of the eighth conductive layer ML8 may be exposed without being covered by the second interlayer insulating layer INS2, and may be electrically connected to the routing line RM positioned in the display portion 200.

[0170] The seventh conductive layer ML7 , the eighth via VA8 , and the eighth conductive layer ML8 may be positioned in the second interlayer insulating layer INS2 . The seventh conductive layer ML7 , the eighth via VA8 , and the eighth conductive layer ML8 may constitute a second driving circuit layer positioned in the second interlayer insulating layer INS2 of the driving circuit layer 120 .

[0171] In the drawings, although the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7, and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, and the eighth via VA8 are shown as being sequentially stacked on top of each other, their layout and connection may be modified in various ways according to the circuits of the driving circuit part 400, the gate driver 600, the data driver 700, and the pixel circuit part 800 of the driving part 100. The connection structure shown in the drawings is only an example, and the connection of the driving circuit layer 120 positioned in the driving part 100 of the display device 10 is not limited thereto. In addition, the driving circuit layer 120 may not necessarily include the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8, and some of these layers may be omitted, or more layers may be provided.

[0172] The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 may be formed of substantially the same material. For example, the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any of them.

[0173] The thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be respectively greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be about The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be about 1000 Å. The thickness of each of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6 may be about 100 mm.

[0174] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, or the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, or the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately The thickness of each of the seventh via hole VA7 and the eighth via hole VA8 may be about

[0175] Fig.11 is a plan view showing a layout of pixels positioned in a display area of ​​a display section according to one or more embodiments. Fig.12 is a cross-sectional view showing a part of a display region and a part of a non-display region in a display portion according to one or more embodiments.

[0176] Reference Fig.11 and Fig.12, each of the plurality of pixels PX may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 as different emission areas. Each of the plurality of emission areas EA1, EA2, and EA3 may correspond to one sub-pixel SP.

[0177] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral shape such as a rectangle, a square, or a rhombus in a plan view. For example, the first emission area EA1 may have a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2 in a plan view. In addition, each of the second emission area EA2 and the third emission area EA3 may have a rectangular shape having long sides in the first direction DR1 and short sides in the second direction DR2 in a plan view.

[0178] The length of the first emission area EA1 in the first direction DR1 may be smaller than the length of the second emission area EA2 in the first direction DR1, and may be smaller than the length of the third emission area EA3 in the first direction DR1. The length of the second emission area EA2 in the first direction DR1 and the length of the third emission area EA3 in the first direction DR1 may be substantially the same.

[0179] The length of the first emission region EA1 in the second direction DR2 may be greater than the sum of the lengths of the second emission region EA2 and the third emission region EA3 in the second direction DR2. The length of the second emission region EA2 in the second direction DR2 may be greater than the length of the third emission region EA3 in the second direction DR2.

[0180] Although the drawings illustrate that each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 has a rectangular shape in a plan view, the present disclosure is not limited thereto. For example, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape in a plan view.

[0181] In each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. In addition, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first emission region EA1, the area of ​​the second emission region EA2, and the area of ​​the third emission region EA3 may be different.

[0182] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the light of the first color may be light of a blue wavelength band, the light of the second color may be light of a green wavelength band, and the light of the third color may be light of a red wavelength band. For example, the blue wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 370nm to about 460nm, the green wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 480nm to about 560nm, and the red wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 600nm to about 750nm.

[0183] Although it is shown in the drawings that each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four emission areas.

[0184] In addition, the layout of the emission regions of the plurality of pixels PX is not limited to the layout shown in the drawings. For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the emission regions are arranged in the first direction DR1, in which the emission regions are arranged in a diamond shape, or in a plurality of pixels PX. structure, or a hexagonal structure in which emission regions having a hexagonal shape in a plan view are arranged side by side ( and PENTILE TM is a registered trademark of Samsung Display Co., Ltd. of South Korea).

[0185] Fig.13 and Fig.14 is a plan view showing a layout of a display area of ​​a display portion according to one or more other embodiments.

[0186] Reference Fig.13 and Fig.14 In the display device 10 according to one or more embodiments, the layout of the emission areas EA1, EA2, and EA3 of the display part 200 may be different from Fig.11 For example, in Fig.13 In the display device 10, in each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the second direction DR2. In addition, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second direction DR2. In addition, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first direction DR1. The area of ​​the first emission area EA1, the area of ​​the second emission area EA2, and the area of ​​the third emission area EA3 may be different. Although Fig.11 The first emission area EA1 in the display device 10 has a shape extending in the second direction DR2, but Fig.11The first emission area EA1 in the display device 10 may have a shape extending in the first direction DR1.

[0187] exist Fig.14 In the display device 10 of FIG. 1 , each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a hexagonal shape in a plan view, and they may be arranged while being spaced apart from each other in an oblique direction. In the drawings, it is shown that the first emission area EA1 and the second emission area EA2 are spaced apart from each other in a horizontal direction, and the third emission area EA3 is spaced apart from each of the first emission area EA1 and the second emission area EA2 in an oblique direction. However, the arrangement of the plurality of emission areas EA1, EA2, and EA3 is not limited thereto.

[0188] The display portion 200 may include a second single crystal semiconductor substrate 210, a reflective layer MIL, a light emitting element layer EML, an encapsulation layer TFE, an optical layer OPL, and a cover layer CVL. The connection wiring layer 500 may be positioned between the second single crystal semiconductor substrate 210 and the first single crystal semiconductor substrate 110. Alternatively, the connection wiring layer 500 may be positioned between the light emitting element layer EML and the first single crystal semiconductor substrate 110.

[0189] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The second single crystal semiconductor substrate 210 may be a substrate doped with impurities. A plurality of well regions may be positioned on the top surface of the second single crystal semiconductor substrate 210. The plurality of well regions may be regions doped with second type impurities. The second type impurities may be different from the first type impurities described above. For example, if the first type impurity is a p-type impurity, the second type impurity may be an n-type impurity. Alternatively, if the first type impurity is an n-type impurity, the second type impurity may be a p-type impurity. However, the present disclosure is not limited thereto. The second single crystal semiconductor substrate 210 may be a silicon substrate not doped with impurities.

[0190] Reference Fig.12 , the second single crystal semiconductor substrate 210 may include a second transistor PTR2 as a circuit element of the pixel circuit PXC. Each of the well regions formed in the second single crystal semiconductor substrate 210 may include a source region SA corresponding to a source electrode of the second transistor PTR2, a drain region DA corresponding to a drain electrode of the second transistor PTR2, and a channel region CH positioned between the source region SA and the drain region DA. The second transistor PTR2 shown in the drawings may be a Figure 5 The second transistor PTR2 may be one of the transistors of the pixel circuit PXC and may be the second transistor T2 positioned in the display unit 200. However, the present disclosure is not limited thereto, and the second transistor PTR2 may be Figure 5 Another transistor included in the pixel circuit PXC.

[0191] On the other hand, in the display device 10, a wafer substrate on which the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 of the driving part 100 is formed may be different from a wafer substrate on which the second transistor PTR2 formed on the second single crystal semiconductor substrate 210 of the display part 200 is formed. According to one or more embodiments, in the display device 10, the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 and the second transistor PTR2 formed on the second single crystal semiconductor substrate 210 may have different sizes, line widths, etc.

[0192] For example, in the display device 10, the minimum line width of the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 may be smaller than the minimum line width of the second transistor PTR2 formed on the second single crystal semiconductor substrate 210. The semiconductor process performed on the first wafer substrate for forming the first transistor PTR1 is a process having a higher resolution than the resolution of the semiconductor process performed on the second wafer substrate for forming the second transistor PTR2. Therefore, the size of the element such as the manufactured transistor can be smaller. In other words, the semiconductor process performed on the first wafer substrate can be a finer process than the semiconductor process performed on the second wafer substrate.

[0193] As described above, the first single crystal semiconductor substrate 110 of the driving part 100 may have an area smaller than that of the second single crystal semiconductor substrate 210 of the display part 200 in a plan view, and small-sized elements may be arranged at a high integration density to reduce power consumption and improve manufacturing yield. On the other hand, the second single crystal semiconductor substrate 210 of the display part 200 may have an area larger than that of the first single crystal semiconductor substrate 110 in a plan view, and a process having a relatively large line width may be performed. The second transistor PTR2 positioned in the second single crystal semiconductor substrate 210 may be formed in a larger area than when formed in the first single crystal semiconductor substrate 110, and the second transistor PTR2 constituting the pixel circuit PXC may not require a high integration density. Therefore, the semiconductor process performed on the first wafer substrate may be performed as a high-cost process having a small line width, and the semiconductor process performed on the second wafer substrate may be performed as a low-cost process having a relatively large line width.

[0194] In one or more embodiments, the lengths of the channel regions CH of the plurality of transistors PTR1 and PTR2 may be different from each other, and the minimum line width or the length of the channel region CH of the first transistor PTR1 may be smaller than the minimum line width or the length of the channel region CH of the second transistor PTR2. The minimum line width or the length of the channel region CH of the first transistor PTR1 may be equal to or less than about 100 nm, or may be in the range from about 2 nm to about 80 nm. The minimum line width or the length of the channel region CH of the second transistor PTR2 may be greater than or equal to about 100 nm, or may be in the range from about 100 nm to about 5 μm.

[0195] The second single crystal semiconductor substrate 210 may include a plurality of through holes TSV1, TSV2, and TSV3 spaced apart from each other. The through holes TSV1, TSV2, and TSV3 may penetrate from the top surface of the second single crystal semiconductor substrate 210 to the bottom surface thereof, and the conductive vias RVA1, RVA2, and RVA3 of the routing lines RM1, RM2, and RM3 may be positioned therein. The through holes TSV1, TSV2, and TSV3 may form a connection path for the routing lines RM1, RM2, and RM3 to electrically connect the driving part 100 to the sub-pixel circuit part 220 or the light emitting element of the display part 200. In some embodiments, the through holes TSV1, TSV2, and TSV3 of the second single crystal semiconductor substrate 210 may be formed by a through silicon via (TSV) process in which a hole penetrating a wafer substrate is formed. Through the through holes TSV1 , TSV2 , and TSV3 formed in the second single crystal semiconductor substrate 210 , the display element layer 230 and the driving part 100 may be electrically connected to each other through the routing lines RM1 , RM2 , and RM3 without additional wiring.

[0196] After the driving part 100 is bonded to the silicon wafer substrate, a process of reducing the thickness of the second single crystal semiconductor substrate 210 may be performed. The second single crystal semiconductor substrate 210 may have a thickness greater than that of the wafer substrate on which the process for forming the conductive layer is performed. In some embodiments, the thickness of the second single crystal semiconductor substrate 210 may be about 100 μm or less, for example, in the range of about 80 μm to about 100 μm.

[0197] The sub-pixel circuit portion 220 may be positioned on the second single crystal semiconductor substrate 210. The sub-pixel circuit portion 220 may include a third semiconductor insulating layer SINS3, a fourth semiconductor insulating layer SINS4, a third interlayer insulating layer INS3, a fourth interlayer insulating layer INS4, a fifth interlayer insulating layer INS5, a contact electrode of the second transistor PTR2, and a plurality of routing conductive layers RMT. The sub-pixel circuit portion 220 may include wiring electrically connected to a plurality of second transistors PTR2 formed in the second single crystal semiconductor substrate 210, and a first scan line GWL, a data line DL, and terminals TD1 and TD2 positioned in the display portion 200.

[0198] The sub-pixel circuit portion 220 of the display portion 200 may have a structure similar to that of the driving circuit layer 120 of the driving portion 100. For example, the third semiconductor insulating layer SINS3 and the fourth semiconductor insulating layer SINS4 may be positioned on the second single crystal semiconductor substrate 210. The third semiconductor insulating layer SINS3 may be an insulating layer positioned on the second single crystal semiconductor substrate 210, and the fourth semiconductor insulating layer SINS4 may be an insulating layer positioned on the gate electrode GE of the second transistor PTR2. The third semiconductor insulating layer SINS3 and the fourth semiconductor insulating layer SINS4 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto.

[0199] A plurality of contact electrodes connected to the second transistor PTR2 may be positioned on the second single crystal semiconductor substrate 210. The plurality of contact electrodes may be connected to one of the gate electrode GE, the source area SA, and the drain area DA of each of the second transistors PTR2 formed in the second single crystal semiconductor substrate 210 through holes penetrating the semiconductor insulating layers SINS3 and SINS4.

[0200] The third interlayer insulating layer INS3 may be positioned on the plurality of contact electrodes and the semiconductor insulating layers SINS3 and SINS4. The fourth interlayer insulating layer INS4 may be positioned on the third interlayer insulating layer INS3. Each of the third interlayer insulating layer INS3 and the fourth interlayer insulating layer INS4 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto.

[0201] The routing conductive layer RMT may have a structure similar to that of the plurality of conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7, and ML8 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, and VA8 of the driving circuit layer 120. The routing conductive layer RMT may include one or more conductive layers and vias positioned therebetween to form the terminals TD1 and TD2 or wiring positioned in the display portion 200. For example, the routing conductive layer RMT of the sub-pixel circuit portion 220 positioned in the display area DAA may be electrically connected to the second transistor PTR2. Fig.12 The second transistor PTR2 shown in FIG. 1 may be Figure 5 The second transistor T2 included in the pixel circuit PXC of FIG. 20 . The routing conductive layer RMT may be used as a connection line connecting the second transistor PTR2 to other circuit elements. In addition, in one or more embodiments, some of the routing conductive layers RMT of the sub-pixel circuit portion 220 positioned in the display area DAA may be the first scan line GWL or the data line DL.

[0202] The sub-pixel circuit part 220 may include a plurality of first terminals TD1 located in the non-display area NA. The first terminals TD1 may be electrically connected to the first scan line GWL or the data line DL located in the display area DAA.

[0203] The connection wiring layer 500 may be positioned on the bottom surface of the second single crystalline semiconductor substrate 210. The connection wiring layer 500 may include an interlayer insulating layer RINS and a plurality of connection lines RML1, RML2, and RML3.

[0204] The interlayer insulating layer RINS may be positioned on the bottom surface of the second single crystal semiconductor substrate 210. The interlayer insulating layer RINS may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x In the drawings, the interlayer insulating layer RINS is shown as a single layer, but is not limited thereto, and may have a structure in which one or more layers are stacked on top of each other and they may be positioned between the connection lines RML1, RML2, and RML3.

[0205] The connecting wires RML1, RML2 and RML3 may form routing wires RM1, RM2 and RM3 together with a plurality of conductive vias RVA1, RVA2 and RVA3. The connecting wires RML1, RML2 and RML3 may include one or more conductive layers and one or more vias connecting them to each other. The connection and structure of the connecting wires RML1, RML2 and RML3 may be the same as the connection and structure described above for the conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7 and ML8 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7 and VA8. The connecting wires RML1, RML2 and RML3 may be electrically connected to the light emitting element or sub-pixel circuit portion 220 of the light emitting element layer EML through the conductive vias RVA1, RVA2 and RVA3 positioned in the through holes TSV1, TSV2 and TSV3 of the second single crystal semiconductor substrate 210, and may be electrically connected to the driving circuit layer 120 of the driving portion 100.

[0206] According to one or more embodiments, the display portion 200 of the display device 10 may include a first through hole TSV1, a second through hole TSV2, and a third through hole TSV3 penetrating the second single crystal semiconductor substrate 210. The first through hole TSV1 and the second through hole TSV2 may be positioned in the display area DAA, and the third through hole TSV3 may be positioned in the non-display area NA (e.g., the first through hole area TSA1). In addition, in one or more embodiments, the display device 10 may further include a fourth through hole TSV4 positioned in the second through hole area TSA2 of the non-display area NA.

[0207] A first routing line RM1 that connects a light emitting element of the light emitting element layer EML to be described later to the driving circuit layer 120 of the driving part 100 may be positioned in the first through hole TSV1. The first routing line RM1 may include a first conductive via RVA1 positioned in the first through hole TSV1 and a first connection line RML1 positioned in the connection wiring layer 500. The first through hole TSV1 may penetrate the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3, INS4, and INS5 to extend from the bottom surface of the reflective layer MIL to be described later to the bottom surface of the second single crystal semiconductor substrate 210. The first conductive via RVA1 may also be positioned from the bottom surface of the reflective layer MIL to the bottom surface of the second single crystal semiconductor substrate 210 to be connected to each of the reflective layer MIL and the first connection line RML1. The first routing line RM1 may connect the light emitting element of the light emitting element layer EML to the pixel circuit part 800 of the driving part 100.

[0208] The second routing line RM2 that connects the second transistor PTR2 to the driving circuit layer 120 of the driving part 100 through the routing conductive layer RMT of the sub-pixel circuit part 220 may be positioned in the second through hole TSV2. The second routing line RM2 may include a second conductive via RVA2 positioned in the second through hole TSV2 and a second connection line RML2 positioned in the connection wiring layer 500. The second through hole TSV2 may penetrate a portion of the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3 and INS4 to extend from the bottom surface of any conductive layer of the routing conductive layer RMT to the bottom surface of the second single crystal semiconductor substrate 210. The second conductive via RVA2 may also be positioned from the bottom surface of any conductive layer of the routing conductive layer RMT to the bottom surface of the second single crystal semiconductor substrate 210 to connect to each of the routing conductive layer RMT and the second connection line RML2. The second routing line RM2 may connect the second transistor PTR2 positioned in the display part 200 to the pixel circuit PXC positioned in the pixel circuit part 800 of the driving part 100.

[0209] The third routing line RM3 connecting the first terminal TD1 of the sub-pixel circuit part 220 to the driving circuit layer 120 of the driving part 100 may be positioned in the third through hole TSV3. The third routing line RM3 may include a third conductive via RVA3 positioned in the third through hole TSV3 and a third connection line RML3 positioned in the connection wiring layer 500. The third through hole TSV3 may penetrate a portion of the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3 and INS4 to extend from the bottom surface of the first terminal TD1 to the bottom surface of the second single crystal semiconductor substrate 210. The third conductive via RVA3 may also be positioned from the bottom surface of the first terminal TD1 to the bottom surface of the second single crystal semiconductor substrate 210 to connect to each of the first terminal TD1 and the third connection line RML3. The third routing line RM3 may connect the first scan line GWL or the data line DL to the driving circuit layer 120 or to the gate driver 600 or the data driver 700 of the driving part 100 through the first terminal TD1 positioned in the display part 200.

[0210] According to one or more embodiments, at least some of the through holes TSV1, TSV2 and TSV3, the connecting lines RML1, RML2 and RML3, and the conductive vias RVA1, RVA2 and RVA3 may be positioned in the display area DAA. For example, the first through hole TSV1, the second through hole TSV2, the first conductive via RVA1 and the second conductive via RVA2 may be positioned in the display area DAA. Among them, the first through hole TSV1 and the first conductive via RVA1 may overlap with the emission areas EA1, EA2 and EA3 of the light emitting element layer EML in the thickness direction. In some cases, the second through hole TSV2 and the second conductive via RVA2 may overlap with the emission areas EA1, EA2 and EA3 of the light emitting element layer EML, but are not limited thereto. The accompanying drawings show a case where the second through hole TSV2 and the second conductive via RVA2 do not overlap with the emission areas EA1, EA2 and EA3 of the light emitting element layer EML.

[0211] In addition, the third through hole TSV3 and the third conductive via RVA3 may overlap the non-display area NA. As described above, the third through hole TSV3 may be positioned in the first through hole area TSA1 of the non-display area NA, and the third through hole TSV3 and the third conductive via RVA3 may not overlap the display area DAA. In one or more embodiments, the same may apply to the fourth through hole TSV4 and the conductive via of the fourth routing line RM4.

[0212] Some of the connection lines RML1, RML2, and RML3 may be positioned in the display area DAA, and some of the others may be positioned in the non-display area NA. For example, the first connection line RML1 and the second connection line RML2 may be positioned in the display area DAA, and the third connection line RML3 may be positioned in the non-display area NA. Some of the connection lines RML1, RML2, and RML3 positioned in the display area DAA may overlap with the light emitting element layer EML. In one or more embodiments, the connection line of the fourth routing line RM4 may also be positioned in the non-display area NA.

[0213] Since the routing lines RM1, RM2 and RM3 electrically connect the elements positioned on the second single crystal semiconductor substrate 210 to the driving circuit layer 120 positioned on the first single crystal semiconductor substrate 110, the arrangement of the connecting lines RML1, RML2 and RML3, the through holes TSV1, TSV2 and TSV3, and the conductive vias RVA1, RVA2 and RVA3 can be modified in various ways depending on their relative arrangements relative to the light emitting element layer EML and the first single crystal semiconductor substrate 110.

[0214] For example, the connection wiring layer 500 may be positioned on the bottom surface of the second single crystalline semiconductor substrate 210, the through holes TSV1, TSV2, and TSV3 and the conductive vias RVA1, RVA2, and RVA3 may be arranged across the entire second single crystalline semiconductor substrate 210, and the connection wires RML1, RML2, and RML3 may be arranged across the entire second single crystalline semiconductor substrate 210 but may be concentrated in a region where the first single crystalline semiconductor substrate 110 is positioned. According to one or more embodiments, in the display device 10, the first through hole TSV1, the second through hole TSV2, the first conductive via RVA1, and the second conductive via RVA2 may be arranged in the display area DAA and may overlap with the light emitting element layer EML in the thickness direction, and each of them may have at least a portion overlapping with the first single crystalline semiconductor substrate 110 in the thickness direction. As described above, the area of ​​the first single crystal semiconductor substrate 110 in a plan view may be smaller than the area of ​​the second single crystal semiconductor substrate 210 in a plan view, and only some of the first through-holes TSV1, the second through-holes TSV2, the first conductive vias RVA1, and the second conductive vias RVA2 arranged across the entire second single crystal semiconductor substrate 210 may overlap with the first single crystal semiconductor substrate 110 in the thickness direction. On the other hand, the third through-holes TSV3 and the third conductive vias RVA3 may be arranged in the non-display area NA without overlapping with the light emitting element layer EML in the thickness direction and without overlapping with the first single crystal semiconductor substrate 110 in the thickness direction.

[0215] At least some of the connection lines RML1, RML2, and RML3 may also not overlap with the first single crystal semiconductor substrate 110 in the thickness direction. The first connection line RML1 may electrically connect the first conductive via RVA1 positioned in the display area DAA to the pixel circuit portion 800 formed on the first single crystal semiconductor substrate 110. Some of the plurality of first connection lines RML1 may overlap with the first single crystal semiconductor substrate 110 in the thickness direction, and ends of the first connection lines RML1 formed by a plurality of layers may also overlap with the first single crystal semiconductor substrate 110 in the thickness direction. In addition, among the plurality of first connection lines RML1, the connection lines connected to the first conductive vias RVA1 not overlapping with the first single crystal semiconductor substrate 110 may not overlap with the first single crystal semiconductor substrate 110 in the thickness direction, but ends of the first connection lines RML1 formed by a plurality of layers may overlap with the first single crystal semiconductor substrate 110 in the thickness direction. Similar to the first connection wires RML1, some of the second connection wires RML2 may overlap with the first single crystal semiconductor substrate 110, and others thereof may not overlap with the first single crystal semiconductor substrate 110. However, ends of the second connection wires RML2 formed of a plurality of layers may overlap with the first single crystal semiconductor substrate 110 in a thickness direction.

[0216] The third connection lines RML3 may electrically connect the third conductive vias RVA3 positioned in the non-display area NA to the gate driver 600 or the data driver 700 formed on the first single crystal semiconductor substrate 110. The plurality of third connection lines RML3 may not overlap the first single crystal semiconductor substrate 110 in the thickness direction, but ends of the third connection lines RML3 formed of a plurality of layers may overlap the first single crystal semiconductor substrate 110 in the thickness direction. The connection lines RML1, RML2, and RML3 may form paths for electrically connecting the conductive vias RVA1, RVA2, and RVA3 positioned across the entire second single crystal semiconductor substrate 210 having a larger area to the driving circuit layer 120 positioned on the first single crystal semiconductor substrate 110 having a relatively small area.

[0217] In the display device 10, the circuit part provided in the driving part 100 can be formed by a relatively high-cost micro-semiconductor process, and thus can be formed with high integration density on a first single crystal semiconductor substrate 110 having a relatively small area. The manufacturing process of the driving part 100 can have a high yield per unit wafer substrate, and the circuit element (for example, the first transistor) can have a small size, resulting in reduced power consumption. In addition, some wiring for light emission of the light emitting element and some circuit elements of the pixel circuit PXC can be positioned in the display part 200, thereby solving the problem that the integration density of the first single crystal semiconductor substrate 110 becomes too high. In addition, the circuit elements arranged with high integration density can be positioned on different single crystal semiconductor substrates 110 and 210, respectively, thereby reducing or minimizing the formation of parasitic capacitance between adjacent circuit elements.

[0218] The display element layer 230 may include a reflective layer MIL, a light emitting element layer EML, an encapsulation layer TFE, an optical layer OPL, and a cover layer CVL. The display element layer 230 may include a light emitting element electrically connected to the sub-pixel circuit part 220 and the pixel circuit part 800 of the driving part 100 to emit light.

[0219] The reflective layer MIL may be positioned on the second single crystal semiconductor substrate 210. Alternatively, the reflective layer MIL may be positioned on the sub-pixel circuit portion 220. The reflective layer MIL may include one or more layers of reflective electrodes RL1, RL2, RL3, and RL4. Each of the plurality of reflective electrodes RL1, RL2, RL3, and RL4 of the reflective layer MIL may overlap with the emission areas EA1, EA2, and EA3. When light emitted from the light emitting element layer EML positioned on the reflective layer MIL is emitted toward the second single crystal semiconductor substrate 210, the reflective layer MIL may reflect them toward the upper portion of the display portion 200. In addition, the reflective layer MIL may be formed of a conductive metal layer and may be electrically connected to each of the first electrode AND of the light emitting element and the first connection line RML1.

[0220] Each of the first reflective electrodes RL1 may be positioned on the fifth interlayer insulating layer INS5 and may be connected to the first routing line RM1. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0221] Each of the second reflective electrodes RL2 may be positioned on the corresponding first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of them. For example, the second reflective electrode RL2 may be made of titanium nitride (TiN).

[0222] A step layer STPL may be positioned on the second reflective electrode RL2 overlapping the first emission region EA1. The step layer STPL may not be positioned on the second reflective electrode RL2 overlapping the second emission region EA2 or the third emission region EA3. In order to promote reflection of light emitted from the intermediate layers IL1, IL2, and IL3, the thickness of the step layer STPL may be set in consideration of the wavelength of the light and the distance from the second electrode CAT of the light emitting element to the fourth reflective electrode RL4. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto. The thickness of the step layer STPL may be about

[0223] In the first emission area EA1, the third reflective electrode RL3 may be positioned on the second reflective electrode RL2 and the step layer STPL. In the second emission area EA2 and the third emission area EA3, the third reflective electrode RL3 may be positioned on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0224] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0225] The fourth reflective electrode RL4 may be positioned on the third reflective electrode RL3, respectively. The fourth reflective electrode RL4 may reflect light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. Among the plurality of reflective electrodes RL1, RL2, RL3, and RL4, at least the uppermost fourth reflective electrode RL4 may include a metal having a high reflectivity to promote light reflection. The fourth reflective electrode RL4 may be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy which is an alloy of silver (Ag), palladium (Pd), and copper (Cu), or a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but is not limited thereto. Each of the fourth reflective electrodes RL4 may have a thickness of about 100 Å. Thickness.

[0226] On the other hand, the method of making the light emitted from the intermediate layers IL1, IL2, and IL3 appropriately reflected by the reflective layer MIL is not limited to providing the step layer STPL. Depending on the thickness of the sixth interlayer insulating layer INS6 positioned between the first electrode AND of the light emitting element and the fourth reflective electrode RL4, the reflection of the light emitted from the intermediate layers IL1, IL2, and IL3 may be appropriate. In the display device 10, the thickness of the sixth interlayer insulating layer INS6 positioned between the first electrode AND of the light emitting element and the fourth reflective electrode RL4 in some emission areas EA1, EA2, and EA3 may be adjusted in consideration of the wavelength of light emitted from different emission areas EA1, EA2, and EA3.

[0227] In with Fig.12 In the display device 10 of one or more corresponding embodiments, the step layer STPL overlaps with the light-emitting element in the first emission area EA1, and the step layer STPL is not positioned in the second emission area EA2 and the third emission area EA3. However, the present disclosure is not limited to this, and the step layer STPL may also be positioned in at least one of the second emission area EA2 and the third emission area EA3. Alternatively, the step layer STPL may be omitted, and the thickness of the sixth interlayer insulating layer INS6 may vary between the first electrode AND of the light-emitting element and the fourth reflective electrode RL4.

[0228] The sixth interlayer insulating layer INS6 may be positioned on the fifth interlayer insulating layer INS5 and the fourth reflective electrode RL4. The sixth interlayer insulating layer INS6 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic layer is formed, but not limited thereto. In the drawings, it is shown that the sixth interlayer insulating layer INS6 is formed of a single layer, but not limited thereto. The sixth interlayer insulating layer INS6 may have a structure in which one or more layers are stacked on each other.

[0229] A via VAM may be positioned between the fourth reflective electrode RL4 and the light emitting element layer EML. The via VAM may be positioned between the fourth reflective electrode RL4 and the first electrode AND of the light emitting element layer EML, and may be connected to each of them. The via VAM may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of them. Due to the step layer STPL, the thickness of the via VAM overlapping the first emission area EA1 may be less than the thickness of the via VAM in each of the second emission area EA2 and the third emission area EA3. For example, the thickness of the via VAM in the first emission area EA1 may be about And the thickness of the via hole VAM in each of the second emission area EA2 and the third emission area EA3 may be about

[0230]

[0231] The light emitting element layer EML may be positioned on the sixth interlayer insulating layer INS6. The light emitting element layer EML may include light emitting elements LE each having a first electrode AND, intermediate layers IL1, IL2, and IL3, and a second electrode CAT, a pixel defining layer PDL, and a plurality of trenches TRC.

[0232] The first electrode AND of each of the light emitting elements LE may be positioned on the sixth interlayer insulating layer INS6 and may be connected to the via hole VAM. The first electrode AND of each of the light emitting elements LE may be electrically connected to the pixel circuit portion 800 of the driving portion 100 through the via hole VAM, the first to fourth reflective electrodes RL1 to RL4, and the first routing line RM1. The first electrode AND of each of the light emitting elements LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the light emitting elements LE may be titanium nitride (TiN).

[0233] The pixel defining layer PDL may be positioned on a portion of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL may cover an edge of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL may separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0234] The first emission area EA1 may be defined as a region where the first electrode AND, the intermediate layers IL1, IL2, and IL3, and the second electrode CAT are sequentially stacked in the first sub-pixel to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the intermediate layers IL1, IL2, and IL3, and the second electrode CAT are sequentially stacked in the second sub-pixel to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the intermediate layers IL1, IL2, and IL3, and the second electrode CAT are sequentially stacked in the third sub-pixel to emit light.

[0235] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be positioned on the edge of the first electrode AND of each of the light emitting elements LE, the second pixel defining layer PDL2 may be positioned on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be positioned on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO x )-based inorganic layer, but is not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have a thickness of about Thickness.

[0236] Each of the plurality of trenches TRC may penetrate the first pixel defining layer PDL1 , the second pixel defining layer PDL2 , and the third pixel defining layer PDL3 . The sixth interlayer insulating layer INS6 may be partially recessed at each of the plurality of trenches TRC.

[0237] At least one trench TRC may be positioned between adjacent emission areas EA1, EA2, and EA3. Fig.12 Two grooves TRC are shown positioned between adjacent emission regions EA1, EA2, and EA3, but the present disclosure is not limited thereto. In the process of forming intermediate layers IL1, IL2, and IL3 to be described later, the grooves TRC can reduce or prevent the possibility of the materials of the intermediate layers IL1, IL2, and IL3 being connected between different emission regions EA1, EA2, and EA3 or the openings of the pixel defining layer PDL.

[0238] The intermediate layers IL1 , IL2 , and IL3 may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0239] The intermediate layers IL1, IL2, and IL3 may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 emitting different lights. For example, the intermediate layers IL1, IL2, and IL3 may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked sequentially. The stacking order of the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 emitting light of different colors may be changed.

[0240] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0241] A first charge generation layer for supplying charges to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 may be positioned between the first intermediate layer IL1 and the second intermediate layer IL2. A second charge generation layer for supplying charges to the third intermediate layer IL3 and electrons to the second intermediate layer IL2 may be positioned between the second intermediate layer IL2 and the third intermediate layer IL3.

[0242] The first intermediate layer IL1 may be positioned on the first electrode AND, and may be positioned on the bottom surface of each groove TRC. Due to the groove TRC, the first intermediate layer IL1 may be cut off between adjacent emission areas EA1, EA2, and EA3. The second intermediate layer IL2 may be positioned on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 may be cut off between adjacent emission areas EA1, EA2, and EA3. The third intermediate layer IL3 may be positioned on the second intermediate layer IL2. Due to the groove TRC, the third intermediate layer IL3 may be cut off between adjacent emission areas EA1, EA2, and EA3. That is, each of the plurality of grooves TRC may be a structure for cutting off the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light emitting element layer EML between adjacent emission areas EA1, EA2, and EA3.

[0243] In order to stably cut off the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light emitting element layer EML between the adjacent emission areas EA1, EA2, and EA3, the depth of each of the plurality of grooves TRC may be greater than the height of the pixel defining layer PDL. The depth of each of the plurality of grooves TRC may be the length of the groove TRC measured in the third direction DR3. The height of the pixel defining layer PDL may be the length of the pixel defining layer PDL measured in the third direction DR3.

[0244] In some embodiments, another structure may be positioned instead of the trench TRC to cut off the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light emitting element layer EML between the adjacent emission regions EA1, EA2, and EA3. For example, an inverted tapered partition wall may be positioned on the pixel defining layer PDL between the adjacent emission regions EA1, EA2, and EA3.

[0245] The number of the intermediate layers IL1, IL2, and IL3 emitting different lights is not limited to Fig. 9 For example, the intermediate layers IL1, IL2, and IL3 may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and for supplying charges to the other intermediate layer may be positioned between the two intermediate layers.

[0246] In addition, the drawings show that the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all positioned in each of the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the present disclosure is not limited thereto. For example, the first intermediate layer IL1 may be positioned in the first emission area EA1 and may be omitted from the second emission area EA2 and the third emission area EA3. In addition, the second intermediate layer IL2 may be positioned in the third emission area EA3 and may be omitted from the first emission area EA1 and the second emission area EA2. In addition, the third intermediate layer IL3 may be positioned in the second emission area EA2 and may be omitted from the first emission area EA1 and the third emission area EA3. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0247] The second electrode CAT may be positioned on the third intermediate layer IL3. The second electrode CAT may be positioned on the third intermediate layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency of each of the emission areas EA1, EA2, and EA3 may be improved due to the microcavity effect.

[0248] The encapsulation layer TFE may be positioned on the light emitting element layer EML. The encapsulation layer TFE may include at least one inorganic layer TFE1 and TFE3 to reduce or prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic layer to protect the light emitting element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0249] The first encapsulation inorganic layer TFE1 may be positioned on the second electrode CAT, the encapsulation organic layer TFE2 may be positioned on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be positioned on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be formed by alternately stacking silicon nitride (SiN x ) layer, silicon oxynitride (SiO x N y ) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layer. The encapsulating organic layer TFE2 may be a monomer. Alternatively, the encapsulating organic layer TFE2 may be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or the like.

[0250] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0251] The optical layer OPL may include a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be positioned on the adhesive layer ADL.

[0252] The first color filter CF1 may overlap the first emission area EA1. The first color filter CF1 may transmit light of a first color (e.g., light of a blue wavelength band). The blue wavelength band may be about 370 nm to about 460 nm. The first color filter CF1 may transmit light of a first color among the light emitted from the first emission area EA1.

[0253] The second color filter CF2 may overlap with the second emission area EA2. The second color filter CF2 may transmit light of a second color (e.g., light of a green wavelength band). The green wavelength band may be about 480 nm to about 560 nm. The second color filter CF2 may transmit light of a second color among the light emitted from the second emission area EA2.

[0254] The third color filter CF3 may overlap the third emission area EA3. The third color filter CF3 may transmit light of a third color (e.g., light of a red wavelength band). The red wavelength band may be about 600 nm to about 750 nm. The third color filter CF3 may transmit light of a third color among the light emitted from the third emission area EA3.

[0255] The plurality of lenses LNS may be positioned on the first, second, and third color filters CF1, CF2, and CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing a ratio of light guided to the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

[0256] The filling layer FIL may be positioned on the plurality of lenses LNS. The filling layer FIL may have a refractive index (e.g., a predetermined refractive index) such that light travels in the third direction DR3 at an interface between the filling layer FIL and the plurality of lenses LNS. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0257] The cover layer CVL may be positioned on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it may be used as a packaging substrate. When the cover layer CVL is a polymer resin, it may be directly applied to the filling layer FIL.

[0258] In one or more embodiments, the display unit 200 may further include a polarizer positioned on the cover layer CVL. The polarizer may be positioned on one surface of the cover layer CVL. The polarizer may be a structure for reducing or preventing visibility degradation caused by reflection of external light. The polarizer may include a linear polarizer and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter wave plate), but is not limited thereto. However, if the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizer may be omitted.

[0259] Hereinafter, various embodiments of the display device 10 will be described with reference to other drawings.

[0260] Fig.15 is an equivalent circuit diagram of a sub-pixel of a display device according to one or more other embodiments.

[0261] Reference Fig.15In the display device 10 according to one or more embodiments, the transistor of the pixel circuit PXC formed on the different second single crystal semiconductor substrate 210 is not necessarily limited to the second transistor T2. In some embodiments, in the display device 10, the fourth transistor T4 of the pixel circuit PXC may be positioned in the display portion 200, and the first transistor T1, the second transistor T2, and the third transistor T3 and the capacitors C1 and C2 may be positioned in the driving portion 100. In addition, the second scan line GBL and the light emitting element LE may be positioned in the display portion 200, and the data line DL, the first scan line GWL, the emission control line EL, etc. may be positioned in the driving portion 100.

[0262] Since the circuit elements of the pixel circuit PXC can be located on the first single crystal semiconductor substrate 110 of the driving unit 100 and the second single crystal semiconductor substrate 210 of the display unit 200, respectively, parasitic capacitance that may be formed between adjacent circuit elements can be reduced. The circuit elements located on the second single crystal semiconductor substrate 210 can be selected as circuit elements that can more effectively reduce parasitic capacitance. For example, in the case of Figure 5 In one or more corresponding embodiments, the second transistor T2 used as a switching element is formed on the second single crystal semiconductor substrate 210, but is Fig.15 In one or more corresponding embodiments, the fourth transistor T4 used as a switching element may be formed on the second single crystal semiconductor substrate 210. Accordingly, the type of the signal line positioned on the second single crystal semiconductor substrate 210 may also vary. At least one transistor constituting the pixel circuit PXC may be formed on the second single crystal semiconductor substrate 210, and at least one signal line electrically connected to the above transistor may be positioned on the second single crystal semiconductor substrate 210. If the display device 10 can reduce the high integration density required for the driving part 100 by including a plurality of through holes TSV1, TSV2, TSV3, and TSV4 positioned in the display area DAA and the non-display area NA of the display part 200, the arrangement design of the pixel circuit PXC may be modified in various ways.

[0263] Fig.16 is a schematic cross-sectional view of a display device according to one or more other embodiments.

[0264] Reference Fig.16 In the display device 10 according to one or more embodiments, a connection wiring layer 500 including a plurality of connection lines may be positioned between the second single crystal semiconductor substrate 210 and the display element layer 230. Since the connection wiring layer 500 is positioned on the top surface of the second single crystal semiconductor substrate 210 instead of the bottom surface thereof, the arrangement of the connection lines and the conductive vias and through holes of the routing lines RM1, RM2, RM3, and RM4 may be different from that in the above-described embodiments.

[0265] The connection wiring layer 500 may be positioned on the top surface of the second single crystal semiconductor substrate 210. The interlayer insulating layer RINS (see Fig.12 ) may be positioned on the top surface of the second single crystal semiconductor substrate 210. Since the description thereof is the same as above, the detailed description thereof will be omitted.

[0266] One end of the routing lines RM1, RM2, RM3, RM4, and RMF positioned in the display part 200 may be formed across the entire second single crystal semiconductor substrate 210, and the other end thereof connected to the driving part 100 may be formed to correspond to the first single crystal semiconductor substrate 110. Since the connection wiring layer 500 is positioned on the top surface of the second single crystal semiconductor substrate 210, one end of the routing lines RM1, RM2, RM3, RM4, and RMF may be a connection line, and the other end may be a conductive via.

[0267] In one or more embodiments, the plurality of routing lines RM1, RM2, RM3, RM4, and RMF may be arranged such that the conductive vias positioned in the through-holes overlap the driving part 100. On the other hand, some of the connection lines of the routing lines RM1, RM2, RM3, RM4, and RMF may overlap the driving part 100, and others thereof may not overlap the driving part 100. The connection lines of the routing lines RM1, RM2, RM3, RM4, and RMF may be positioned across the entire second single crystal semiconductor substrate 210, but ends thereof connected to the conductive vias may be concentrated in a region where the first single crystal semiconductor substrate 110 is positioned.

[0268] As described above, the area of ​​the first single crystal semiconductor substrate 110 in a plan view may be smaller than the area of ​​the second single crystal semiconductor substrate 210 in a plan view, and only some of the connection wires positioned across the entire second single crystal semiconductor substrate 210 may overlap with the first single crystal semiconductor substrate 110 in the thickness direction. Therefore, the connection wires may be arranged across the entire second single crystal semiconductor substrate 210, but ends of the connection wires formed of a plurality of layers may overlap with the first single crystal semiconductor substrate 110 in the thickness direction and may be connected to a plurality of through holes and conductive vias.

[0269] Fig.17 is a perspective view showing a head mounted display device according to one or more embodiments. Fig.18 It is shown Fig.17 An exploded perspective view of an example of a head-mounted display device.

[0270] Reference Fig.17 and Fig.18According to one or more embodiments, a head-mounted display device 1000 includes a first display device 11, a second display device 12, a display device container 1100, a container cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0271] The first display device 11 provides an image to the left eye of the user, and the second display device 12 provides an image to the right eye of the user. Figure 1 The display devices 10 described are substantially the same, and thus descriptions of the first display device 11 and the second display device 12 will be omitted.

[0272] The first optical member 1510 may be positioned between the first display device 11 and the first eyepiece 1210. The second optical member 1520 may be positioned between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0273] The middle frame 1400 may be positioned between the first display device 11 and the control circuit board 1600 and between the second display device 12 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 11, the second display device 12, and the control circuit board 1600.

[0274] The control circuit board 1600 may be positioned between the middle frame 1400 and the display device receiver 1100. The control circuit board 1600 may be connected to the first display device 11 and the second display device 12 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA (see Figure 4 ), and the digital video data DATA can be sent to the first display device 11 and the second display device 12 through the connector.

[0275] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 11, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 12. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 11 and the second display device 12.

[0276] The display device container 1100 is used to accommodate the first display device 11, the second display device 12, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600 and the connector. The container cover 1200 covers an open surface of the display device container 1100. The container cover 1200 may include a first eyepiece 1210 at which the user's left eye is positioned and a second eyepiece 1220 at which the user's right eye is positioned. The first eyepiece 1210 and the second eyepiece 1220 are shown to be positioned separately in the drawings, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0277] The first eyepiece 1210 may be aligned with the first display device 11 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 12 and the second optical member 1520. Therefore, the user may observe the image of the first display device 11 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may observe the image of the second display device 12 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0278] The headband 1300 is used to fix the display device container 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the container cover 1200 remain positioned on the user's left eye and right eye, respectively. When the display device container 1100 is implemented to be lightweight and compact, as Fig.19 As shown in , the head mounted display device 1000 may be provided with a glasses frame instead of a head mounted band 1300 .

[0279] In addition, the head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0280] Fig.19 is a perspective view showing a head mounted display device according to one or more embodiments.

[0281] Reference Fig.19The head mounted display device 1000_1 according to one or more embodiments may be a glasses type display device in which the display device container 1200_1 is implemented in a lightweight and compact manner. The head mounted display device 1000_1 according to one or more embodiments may include a display device 13, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device container 1200_1.

[0282] The display device container 1200_1 may include the display device 13, the optical member 1060, and the optical path conversion member 1070. The image displayed on the display device 13 may be magnified by the optical member 1060, and the optical path may be changed by the optical path conversion member 1070 to provide the image to the right eye of the user through the right eye lens 1020. As a result, the user may observe an augmented reality image in which a virtual image displayed on the display device 13 and a real image viewed through the right eye lens 1020 are combined through the right eye.

[0283] The display device container 1200_1 is shown in the drawings as being positioned at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device container 1200_1 may be positioned on the left end of the support frame 1030, and in this case, the image of the display device 13 may be provided to the left eye of the user. Alternatively, the display device container 1200_1 may be positioned on both the left and right ends of the support frame 1030, and in this case, the user may observe the image displayed on the display device 13 through both the left and right eyes.

[0284] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without departing from the aspects of the present disclosure. Therefore, the embodiments of the present disclosure disclosed are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: a first single crystal semiconductor substrate; a plurality of first transistors, the plurality of first transistors being located above the first single crystal semiconductor substrate; as well as a second single crystal semiconductor substrate, which is located above the first single crystal semiconductor substrate, has an area larger than that of the first single crystal semiconductor substrate in a plan view, and includes a display region in which a plurality of light emitting elements are positioned and a non-display region located around the display region in a plan view, The second single crystal semiconductor substrate defines a first through hole, a second through hole and a third through hole, the first through hole is defined in the display area and has a first conductive via electrically connected to the light emitting element, the second through hole is defined in the display area and has a second conductive via electrically connected to the first transistor, and the third through hole is defined in the non-display area and has a third conductive via in the third through hole.

2. The display device according to claim 1, further comprising: a pixel circuit portion located over the first single crystal semiconductor substrate and including some of the plurality of first transistors; a signal driver, the signal driver being located above the first single crystal semiconductor substrate and including other first transistors of the plurality of first transistors; as well as A plurality of second transistors are provided, wherein the plurality of second transistors are located above the second single crystal semiconductor substrate.

3. The display device according to claim 2, wherein: One of the plurality of light emitting elements is electrically connected to one of the plurality of first transistors of the pixel circuit portion through the first conductive via, and Among them, one of the plurality of second transistors is electrically connected to the one first transistor among the plurality of first transistors of the pixel circuit portion through the second conductive via. 4 . The display device according to claim 2 , further comprising a signal line located across the display area and the non-display area on the second single crystal semiconductor substrate and connected to the third conductive via in the non-display area.

5. The display device according to claim 4, wherein: The signal line is electrically connected to the second transistor in the display area and is electrically connected to the signal driver through the third conductive via.

6. The display device according to claim 2, wherein: A minimum line width of the first transistor is smaller than a minimum line width of the second transistor.

7. The display device according to claim 1, wherein: The number of the first through holes is equal to the number of the second through holes.

8. The display device according to claim 1, wherein: The number of each of the first through holes and the second through holes is greater than the number of the third through holes.

9. The display device according to claim 1, wherein: The first through hole overlaps with the light emitting element in a thickness direction.

10. The display device according to claim 1, wherein: Some of the first through-holes or the second through-holes do not overlap with the first single crystal semiconductor substrate.

11. The display device according to claim 1, wherein: The third through hole does not overlap with the first single crystal semiconductor substrate.

12. The display device according to claim 1 further includes a connection wiring layer, which includes a connection line electrically connected to one of the first conductive via, the second conductive via and the third conductive via and is located between the first single crystal semiconductor substrate and the light emitting element layer including the plurality of light emitting elements.

13. The display device according to claim 12, wherein: The connection wiring layer is located between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate.

14. The display device according to claim 12, wherein: The connection wiring layer is located between the second single crystal semiconductor substrate and the light emitting element layer. 15 . The display device according to claim 1 , further comprising a passivation layer surrounding the first single crystal semiconductor substrate and partially contacting the second single crystal semiconductor substrate.

16. A display device, comprising: a first single crystal semiconductor substrate; a plurality of first transistors, the plurality of first transistors being located above the first single crystal semiconductor substrate; a second single crystal semiconductor substrate, the second single crystal semiconductor substrate being located above the first single crystal semiconductor substrate; a plurality of second transistors, the plurality of second transistors being located above the second single crystal semiconductor substrate; at least one signal line electrically connected to the second transistor; a light emitting element layer, the light emitting element layer being located above the second single crystal semiconductor substrate and including a plurality of light emitting elements; as well as a connection wiring layer, the connection wiring layer being located between the light emitting element layer and the first single crystal semiconductor substrate and comprising: a first connection line connected to a first conductive via located in a first through hole penetrating the second single crystal semiconductor substrate and electrically connected to one of the plurality of second transistors and one of the plurality of first transistors; as well as a second connection line connected to a second conductive via located in a second through hole penetrating the second single crystal semiconductor substrate and electrically connected to one of the at least one signal line.

17. The display device according to claim 16, wherein: The connection wiring layer further includes a third connection line connected to a third conductive via located in a third through hole penetrating the second single crystal semiconductor substrate, and The third connection line is electrically connected to one of the plurality of light emitting elements and one of the plurality of first transistors.

18. The display device according to claim 16, wherein: The signal line is electrically connected to one of the plurality of first transistors located above the first single crystal semiconductor substrate through the second conductive via and the second connection line.

19. The display device according to claim 16, wherein: An area of ​​the first single crystal semiconductor substrate in a plan view is smaller than an area of ​​the second single crystal semiconductor substrate in a plan view.

20. A head mounted display device, comprising: a frame mounted on the user's body and corresponding to the left eye and the right eye; a display device, wherein the display device is located in the frame; as well as a lens, wherein the lens is located above the display device, Wherein, the display device comprises: a first single crystal semiconductor substrate; a first transistor, the first transistor being located above the first single crystal semiconductor substrate; a second single crystal semiconductor substrate, the second single crystal semiconductor substrate being located above the first single crystal semiconductor substrate; a second transistor, the second transistor being located above the second single crystal semiconductor substrate; at least one signal line electrically connected to the second transistor; a light emitting element layer located above the second single crystal semiconductor substrate and including a light emitting element; and a connection wiring layer, the connection wiring layer being located between the light emitting element layer and the first single crystal semiconductor substrate and comprising: a first connection line connected to a first conductive via located in a first through hole penetrating the second single crystal semiconductor substrate and electrically connected to the second transistor and the first transistor; and a second connection line connected to a second conductive via located in a second through hole penetrating the second single crystal semiconductor substrate and electrically connected to one of the at least one signal line.

Images