Manufacturing method

Abstract

The embodiment of the invention relates to a manufacturing method. The description relates to a method of manufacturing an electronic device, the electronic device comprising a phase change memory cell, the method comprising: forming a first layer made of a resistive material; forming a stack of layers on the first layer, the stack comprising at least one second layer made of a phase change material; etching the stack, the etching being stopped when the first layer reaches around the location of the memory cell; forming spacers on sidewalls of the stack; the first layer is then etched such that the stack is on a central portion of the first layer and the spacer is on a peripheral portion of the first layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present disclosure is based upon and claims the priority of French patent application FR2311846 filed on October 31, 2023, entitled “Procédé defabrication”, the contents of which are incorporated herein by reference to the extent authorized by law. Technical Field

[0003] The present description relates generally to electronic devices and methods of making the same, and more particularly to phase change memory devices. Background Art

[0004] In conventional phase-change memory, each memory cell includes a layer of phase-change material, for example, in contact with a resistive element. Phase-change material is a material that can switch between a crystalline phase and an amorphous phase. The switch is triggered by an increase in the temperature of the resistive element of the circulating current. The resistance difference between the amorphous phase of the material and its crystalline phase is used to define at least two memory states, i.e., 0 and 1.

[0005] The memory is usually arranged in an array consisting of word lines and bit lines, i.e. rows and columns. A memory cell containing binary information is located at each intersection of a row and a column.

[0006] The information contained in a phase change memory cell is accessed or read, for example, by measuring the resistance between a bit line and a word line of the memory cell.

[0007] The phase change memory cells are for example located in an interconnect network. The interconnect network refers to a stack of insulating layers formed during a manufacturing step known as "back end of line" with metal tracks coupled together by conductive vias located therein. Preferably, the layers of the interconnect network, each comprising a conductive track in an insulating layer and a conductive via in an insulating layer, have a constant height.

[0008] Some phase change memory cell manufacturing methods include an etching step of a metal layer. The metal layer is made of a material that can be etched by the same etching method as the phase change material of the memory cell. Therefore, such methods may result in unintended etching of the phase change material, which may result in performance degradation. Summary of the invention

[0009] One embodiment provides a method for manufacturing an electronic device, the electronic device including a phase change memory cell, the method comprising: forming a first layer made of a resistive material; forming a stack of layers on the first layer, the stack including at least one second layer made of a phase change material; etching the stack, the etching being stopped when the first layer reaches around the location of the memory cell; forming spacers on the sidewalls of the stack; and then, etching the first layer so that the stack is located on a central portion of the first layer and the spacers are located on a peripheral portion of the first layer.

[0010] Another embodiment provides an electronic device, the electronic device including a memory cell, the phase change memory cell including: a first layer made of a resistive material; a stack of layers located on a central portion of the first layer, the stack including at least one second layer made of a phase change material; and spacers located on side walls of the stack and on a peripheral portion of the first layer.

[0011] According to one embodiment, the second layer is in contact with the first layer.

[0012] According to one embodiment, the first layer is completely covered by the stack and the spacers.

[0013] According to one embodiment, the first layer is made of a material having a resistivity greater than 10 mΩ / cm.

[0014] According to one embodiment, the maximum distance between an inner wall of the spacer and a nearest outer wall of the spacer is less than 5 nm.

[0015] According to one embodiment, the thickness of the first layer is in the range of 2 nm to 3 nm.

[0016] According to one embodiment, the stack comprises at least one third layer made of an electrically conductive material, the at least one third layer covering the second layer.

[0017] According to one embodiment, the stack comprises at least one fourth layer made of insulating material, the at least one fourth layer covering the third layer.

[0018] According to one embodiment, the second layer is made of an alloy comprising at least one chalcogen.

[0019] According to one embodiment, the first layer is in contact with the L-shaped resistive element.

[0020] According to one embodiment, the first layer is made of a refractory metal and / or a refractory metal nitride, for example of tantalum, tungsten, TiSiN, TiN or TaN.

[0021] According to one embodiment, the spacers are made of SiCl4, SiN or SiC.

[0022] According to one embodiment, the formation of the spacers is performed in the same enclosure as the etching steps of the stack, without the device being removed from the enclosure between the steps.

[0023] According to one embodiment, etching of the stack forms a pattern of the stack on the first layer.

[0024] According to one embodiment, prior to the etching step of the stack, an etching mask is formed, the etching mask covering the locations of the memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above-mentioned features and advantages and other features and advantages will be described in detail in the remainder of the specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0026] Figure 1 An embodiment of a device including a memory cell is shown;

[0027] Figure 2 The steps of a method of manufacturing an electronic device are illustrated;

[0028] Figure 3 Another step of the method of manufacturing an electronic device is illustrated;

[0029] Figure 4 Another step of the method of manufacturing an electronic device is illustrated;

[0030] Figure 5 illustrates another step in the method of manufacturing an electronic device; and

[0031] Figure 6 A further step of the method of manufacturing an electronic device is illustrated. DETAILED DESCRIPTION

[0032] The same features have been designated by the same reference numerals in the various figures. In particular, common structural and / or functional features between the various embodiments may have the same reference numerals, and may be provided with the same structure, dimensions, and material properties.

[0033] For clarity, only those steps and elements that are helpful for understanding the described embodiments are shown and described in detail.

[0034] Unless otherwise stated, when reference is made to two elements being connected together, this means a direct connection without any intervening elements other than conductors, and when reference is made to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0035] In the following description, when reference is made to absolute position qualifiers, such as "front", "back", "top", "top", "left", "right", etc., or relative position qualifiers, such as "top", "bottom", "upper", "lower", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation of the drawing unless otherwise specified.

[0036] Unless otherwise indicated, the phrases "about," "approximately," "substantially," and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0037] Figure 1 An embodiment of a device comprising a memory cell 1 is shown.

[0038] The device comprises an insulating layer 10, for example located on a substrate not shown. Conductive elements 12, for example vias or walls, are located in the layer 10. The elements 12 pass through the layer 10 from the upper surface to the lower surface, for example to reach the substrate in contact with the lower surface.

[0039] The device further includes a resistive element 14, which has, for example, an L-shape. More specifically, the device includes an insulating layer 16, which is penetrated by the resistive element 14 to reach the conductive element 12. The element 14 includes, for example, a horizontal portion located on the element 12 and a vertical portion extending between the lower and upper surfaces of the layer 16 to contact the element 12 and to make one end flush with the upper surface of the layer 16.

[0040] The device further comprises layer 18. Layer 18 partially covers layer 16. More specifically, layer 18 covers and contacts the upper ends of elements 14, the upper ends of elements 14 are flush with the upper surface of layer 16, and the upper surface of layer 16 surrounds the upper ends of elements 14. Layer 18 is preferably a planar layer.

[0041] The layer 18 preferably has a constant thickness. The layer 18 has, for example, a thickness in the range of 2 nm to 3 nm.

[0042] Layer 18 is made of a material with a relatively high resistivity, preferably a metal. In other words, layer 18 has a resistivity at least equal to 10 mΩ / cm. Layer 18 is preferably made of the same material as the resistive element 14. Layer 18 is made, for example, of a refractory metal and / or a refractory metal nitride. Layer 18 is made, for example, of tantalum, tungsten, TiSiN, TiN or TaN.

[0043] The device further comprises a stack of layers, the stack of layers comprising at least one layer 20 made of a phase change material. Figure 1 In the example of FIG. 1 , the stack further includes a layer 22 and a layer 24 .

[0044] Layers 20, 22, 24 preferably have substantially the same lateral dimensions. The sidewalls of layers 20, 22, 24 are preferably coplanar.

[0045] Layer 18 covers the central portion of layer 14. Thus, the central portion of the upper surface of layer 18 is covered by and in contact with layer 20. The peripheral portion of the upper surface of layer 18 is not covered by layer 20. The peripheral portion is not covered by layer 22 or layer 24. The peripheral portion completely surrounds the central portion.

[0046] Layer 20 is made of a phase-change material, i.e. a material that changes phase when layer 20 is subjected to a programming current having a value higher than a threshold value. Layer 20 is, for example, made of a homogeneous material, i.e. each part of layer 20 is made of the same material, preferably in the same proportions. Layer 20 preferably comprises a chemical element from the chalcogen group. The chalcogen group more specifically comprises oxygen, sulfur, selenium, tellurium and polonium. Layer 20 is, for example, a single chalcogen element or preferably an alloy comprising a chalcogen element. Layer 20 is, for example, made of an alloy of germanium, antimony and tellurium. Layer 20 is, for example, made of an alloy of germanium and tellurium. More generally, layer 20 is, for example, made of an alloy of germanium with at least one chemical element from at least one of columns 13, 14, 15 and 16 of the periodic table. The elements of column 13 are considered to be boron, aluminum, gallium, indium, thallium and The elements of column 14 are considered to be carbon, silicon, germanium, tin, lead and flerovium. The elements of column 15 are considered to be nitrogen, phosphorus, arsenic, antimony, bismuth and molybdenum. The elements of column 16 are considered to be oxygen, sulfur, selenium, tellurium, polonium and livermorium.

[0047] Preferably, the layer 20 has a constant thickness. The layer 20 has, for example, a thickness in the range of 40 nm to 60 nm.

[0048] The layer 22 preferably completely covers the layer 20. The layer 22 preferably completely contacts the layer 20. The layer 22 is a conductive layer, for example made of metal, for example made of titanium nitride.

[0049] Layer 24 preferably completely covers layer 22. Layer 24 preferably completely contacts layer 22. Layer 24 is an insulating layer, for example made of silicon nitride.

[0050] The device includes spacers 28, which extend over the sidewalls of layer 20, the sidewalls of layer 22, and the sidewalls of layer 24. Spacers 28 are made of an insulating material (e.g., SiCl4, SiN, or SiC). Spacers 28 extend at least over the sidewalls of layer 20. Spacers 28 extend from the upper surface of layer 18. Spacers 28 extend at least to the upper surface of layer 20. Figure 4 In the example shown, spacers 28 extend to the upper surface of layer 24 .

[0051] The maximum thickness of the spacer 28, i.e., the maximum distance between the inner wall of the spacer and the nearest outer wall, is preferably less than 5 nm, preferably in the range of 2 nm to 3 nm. The inner wall refers to the wall in contact with the layer 20, layer 22, layer 24. The outer wall refers to the wall opposite to the inner wall, i.e., the wall that is not in contact with either the layer 18 or the layer 20, layer 22, layer 24.

[0052] The spacers 28 completely cover the peripheral portion of the upper surface of the layer 18. The upper surface of the layer 18 is thus completely covered by the layer 20 and the spacers 28.

[0053] The device also includes a passivation layer 30 on the memory cell. Layer 30 is made of an insulating material, such as silicon nitride or silicon carbide. Layer 30 preferably conformally covers the upper surface of layer 16, the sidewalls of layer 18, spacers 28, and the upper surface of layer 24.

[0054] Figures 2 to 6 The preferred sequential steps of a method for manufacturing an electronic device including a memory are illustrated. More specifically, Figures 1 to 6 A method of manufacturing a memory cell of a device is illustrated. The described method can of course be used to manufacture a plurality of memory cells.

[0055] Figure 2 The steps of a method for manufacturing an electronic device are illustrated.

[0056] During this step, an insulating layer 10 is formed, for example on a substrate not shown. Conductive elements 12, for example vias or walls, are formed in layer 10. Elements 12 pass through layer 10 from the upper surface to the lower surface, for example to the substrate in contact with the lower surface.

[0057] Figure 2 The step further includes forming a resistor element 14, the resistor element 14 having an L shape, for example. More specifically, Figure 2 The step includes forming an insulating layer 16 and forming a resistive element 14, which passes through the layer 16 and reaches the conductive element 12. The element 14 includes, for example, a horizontal portion located on the element 12 and a vertical portion extending between the lower surface and the upper surface of the layer 16 to contact the element 12 and make one end flush with the upper surface of the layer 16.

[0058] Figure 2 The step further comprises forming a stack 17 on the layer 16 and on the upper end of the element 14. The stack 17 is for example formed over the entire structure resulting from the formation of the layer 16 and the element 14. The stack 17 covers at least the location of the memory cell.

[0059] The stack 17 comprises a layer 18 below. The layer 18 is therefore the layer of the stack 17 that is closest to the layer 16. More specifically, the layer 18 covers the layer 16, as well as the upper end of the element 14. Preferably, the layer 18 completely covers the upper surface of the layer 16, i.e. the surface of the layer 16 that is farthest from the layer 10. The layer 18 covers and contacts the end of the vertical portion of the element 14, which end of the vertical portion of the element 14 is flush with the upper surface of the layer 16. The layer 18 is preferably a planar layer.

[0060] The layer 18 preferably has a constant thickness. For example, the layer 18 has a thickness in the range of 2 nm to 3 nm.

[0061] Layer 18 is made of a material (preferably a metal) having a relatively high resistivity. In other words, layer 18 has a resistivity of at least 10 mΩ / cm. Layer 18 is preferably made of the same material as the material of resistive element 14. Layer 18 is made of, for example, a refractory metal and / or a refractory metal nitride. For example, layer 18 is made of tantalum, tungsten, TiSiN, TiN or TaN.

[0062] The stack 17 comprises a layer 20. The layer 20 is made of a phase change material, ie a material that changes phase when the layer 20 is subjected to a programming current having a value higher than a threshold value. The layer 20 preferably completely covers the layer 18. The layer 20 preferably is in complete contact with the layer 18.

[0063] The layer 20 is for example made of a homogeneous material, that is, each part of the layer 20 is made of the same material, preferably in the same proportions. The layer 20 preferably comprises a chemical element from the chalcogen group. The chalcogen group more specifically comprises oxygen, sulfur, selenium, tellurium and polonium. The layer 20 is for example a single chalcogen element, or preferably an alloy comprising a chalcogen element. The layer 20 is for example made of an alloy of germanium, antimony and tellurium. The layer 20 is for example made of an alloy of germanium and tellurium. More generally, the layer 20 is made of an alloy comprising at least germanium and a chalcogen element. The layer 20 is made of an alloy comprising, for example, germanium, a chalcogen element and at least one element from columns 13, 14, 15, 16 of the periodic table.

[0064] The layer 20 preferably has a constant thickness. The layer 20 has, for example, a thickness in the range of 40 nm to 60 nm.

[0065] The stack 17 may comprise a layer 22. The layer 22 preferably completely covers the layer 20. The layer 22 preferably completely contacts the layer 20. The layer 20 is an electrically conductive layer, for example made of metal, for example made of titanium nitride.

[0066] The stack 17 may comprise a layer 24. The layer 24 preferably completely covers the layer 22. The layer 24 preferably completely contacts the layer 22. The layer 24 is an insulating layer, for example made of silicon nitride.

[0067] Figure 3A further step of the method of manufacturing an electronic device is illustrated.

[0068] During this step, stack 17 is etched outside the location of the memory cell, except for layer 18. In other words, Figure 3 In the example of , layers 20, 22, and 24 are etched around the location of the memory cell. Figure 3 The steps include, for example, a step of etching stack 17 downward to an upper surface of layer 18, wherein a portion of stack 17 located between memory cell columns is etched, and a step of etching stack 17 downward to an upper surface of layer 18, wherein a portion of stack 17 located between memory cell rows is etched.

[0069] exist Figure 3 The etching performed at step is configured to reach the upper surface of layer 18. Figure 3 During the step of etch, layer 18 is not etched.

[0070] Figure 4 Another step of the method for manufacturing an electronic device is illustrated.

[0071] During this step, layer 26 is Figure 3 Preferably, layer 26 covers the structure obtained by the step of Figure 3 The entire structure produced by the steps of Figure 3 The sidewalls of the layers of stack 17 that have been etched during the step of etch, and the upper surface of the upper layer of stack 17, that is, Figure 4 Layer 24 in the example.

[0072] Layer 26 is made of an insulating material. Layer 26 is made of silicon nitride, for example. Layer 26 corresponds, for example, to a stack of one or more silicon nitride layers and one or more silicon carbide layers. Layer 26 preferably has a thickness of less than 5 nm, for example a thickness in the range of 2 nm to 3 nm.

[0073] According to a first embodiment, the layer 26 is formed ex situ, ie in Figure 3 The outer part of the shell is formed by performing an etching step. The layer is then formed by depositing a layer of silicon nitride or a layer made of silicon nitride and silicon carbide.

[0074] According to a second embodiment, the layer 26 is formed in situ, ie in Figure 3 The etching step is performed in the shell to be formed. Preferably, Figure 3 The structure obtained by the steps is not Figure 3 The housing is removed from the housing between the step of forming the layer 26. Forming the layer 26 (eg, comprising silicon, nitrogen and chlorine) for example comprises forming a plasma and applying SiCl4 and N2 gases.

[0075] Figure 5 Another step of the method for manufacturing an electronic device is illustrated.

[0076] Figure 5 The step includes a step of anisotropically etching layer 26. More specifically, Figure 5 The step of forming spacers 28 includes forming spacers 28, spacers 28 extending over, for example, sidewalls of layer 20, sidewalls of layer 22, and sidewalls of layer 24. Spacers 28 extend at least over the sidewalls of layer 20. Spacers 28 extend from the upper surface of layer 18. Spacers 28 extend at least to the upper surface of layer 20. Figure 5 In the example shown, spacers 28 extend to the upper surface of layer 24 .

[0077] The maximum thickness of the spacer 28, i.e. the maximum distance between the inner wall of the spacer and the nearest outer wall, is preferably less than 5 nm, preferably in the range of 2 nm to 3 nm. The inner wall refers to the wall in contact with the layer 20, layer 22, layer 24. The outer wall refers to the wall opposite to the inner wall, i.e. the wall that is not in contact with the layer 18 nor with the layer 20, layer 22, layer 24.

[0078] Figure 6 Another step of the method for manufacturing an electronic device is illustrated.

[0079] Figure 6 The step of etch comprises a partial etching of layer 18. More specifically, the portion of layer 18 surrounding the cell is etched. In other words, the portion of layer 18 not protected by spacer 28 and layers 20, 22, 24 is etched.

[0080] The method for etching layer 18 is, for example, a chlorine-based chemical etch. The etching of layer 18 is preferably performed by the same etching method as used to etch layers 20, 22, and 24. The etching is preferably performed with a selectivity to the material of layer 18 over the material of layer 24 and the material of spacer 28. Selectivity means that the etching rate of the material of layer 18 is at least twice that of the material of layer 24 and spacer 28.

[0081] Layer 18 comprises side walls coplanar with the outer walls of the lower part of the spacer. Layer 18 is thus completely covered by the spacer and layer 20.

[0082] The method also includes Figure 6 During this step, a passivation layer, not shown, is formed on the memory cell. More specifically, a layer made of an insulating material (eg, silicon nitride or silicon carbide) is preferably formed conformally on the memory cell. Figure 5 Layer 16 thus covers the upper surface of layer 16 , the sidewalls of layer 18 , spacers 28 , and the upper surface of layer 24 .

[0083] It may be chosen not to form spacers 28, and to etch layer 18 simultaneously with the rest of stack 17. However, the material of layers 20, 22, 24 is etched faster than the material of layer 18. Therefore, during the etching of layer 18, layer 20 at the location of the memory cell will be etched from the sidewalls. The profile of the cell, as well as its critical dimensions, will not correspond to the target values. Furthermore, there may be critical dimension and profile variations between cells of the same device.

[0084] An advantage of the described embodiments is that a stack comprising a high resistance layer and a phase change material may be etched without causing damage to the layer of phase change material.

[0085] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will be apparent to those skilled in the art.

[0086] Finally, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art based on the above functional indications.

[0087] A method of manufacturing an electronic device (1) including a phase change memory cell is summarized as comprising: forming a first layer (18) made of a resistive material; forming a stack of layers (20, 22, 24) on the first layer (18), the stack including at least one second layer (20) made of a phase change material; etching the stack (20, 22, 24), the etching being stopped when the first layer (18) reaches around the location of the memory cell; forming spacers (28) on the sidewalls of the stack (20, 22, 24); and then etching the first layer (18) so that the stack (20, 22, 24) is located on a central portion of the first layer (18) and the spacers (28) are located on a peripheral portion of the first layer (18).

[0088] An electronic device (1) is outlined as comprising a memory cell, the phase change memory cell comprising: a first layer (18) made of a resistive material, a stack of layers (20, 22, 24) located on a central portion of the first layer (18), the stack comprising at least one second layer (20) made of a phase change material; and spacers (28) located on side walls of the stack and on a peripheral portion of the first layer (18).

[0089] The second layer (20) is in contact with the first layer (18).

[0090] The first layer (18) is completely covered by the stack (20, 22, 24) and the spacer (28).

[0091] The first layer (18) is made of a material having a resistivity greater than 10 mΩ / cm.

[0092] The maximum distance between the inner wall of the spacer (28) and the nearest outer wall of the spacer (28) is shorter than 5 nm.

[0093] The thickness of the first layer (18) is in the range of 2 nm to 3 nm.

[0094] The stack (20, 22, 24) comprises at least one third layer (22) made of an electrically conductive material, the at least one third layer (22) covering the second layer (20).

[0095] The stack (20, 22, 24) comprises at least one fourth layer (24) made of insulating material, the at least one fourth layer (24) covering the third layer (22).

[0096] The second layer (20) is made of an alloy including at least one chalcogenide element.

[0097] The first layer (18) contacts the L-shaped resistor element (14).

[0098] The first layer (18) is made of a refractory metal and / or a refractory metal nitride, for example tantalum, tungsten, TiSiN, TiN or TaN.

[0099] The spacer (28) is made of SiCl4, SiN or SiC.

[0100] The formation of the spacers (28) is performed in the same housing as the step of etching the stack (20, 22, 24), the device not being removed from the housing between these steps.

[0101] Etching of the stack (20, 22, 24) forms a pattern of the stack on the first layer (18).

[0102] Prior to the step of etching the stack, an etching mask is formed covering the locations of the memory cells.

[0103] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified as necessary to employ the concepts of the various patents, applications and publications to provide further embodiments.

[0104] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A method for manufacturing an electronic device, comprising: forming a first layer of resistive material on a first insulating layer, the first insulating layer comprising a resistive element extending along a first direction from a first side of the first insulating layer to a second side, the second side being opposite to the first side, the resistive element being coupled to the first layer and to a conductive element on the second side; forming a stack of layers on the first layer, the stack including at least one second layer of phase change material; etching the stack along the first direction, the etching stopping when the first layer is reached; forming a spacer on each of a plurality of sidewalls of the stack, the sidewalls extending along the first direction; as well as The first layer is etched along the first direction to the first insulating layer so that the stack is on a central portion of the first layer and the spacers are on a peripheral portion of the first layer. 2 . The method of claim 1 , wherein the conductive element is in a second insulating layer, the second insulating layer covering the second side of the first insulating layer. The method of claim 1 , wherein the second layer is in contact with the first layer.

4. The method according to claim 1, wherein: During the formation of the spacer, the first layer is completely covered by the stack and the spacer. The method of claim 1 , wherein the first layer comprises a material having a resistivity greater than 10 mΩ / cm. 6 . The method of claim 1 , wherein a maximum distance between an inner wall of the spacer and an outer wall of the spacer on one of the plurality of sidewalls along a second direction is less than 5 nm, the second direction being transverse to the first direction. The method according to claim 1 , wherein a thickness of the first layer along the first direction is in the range of 2 nm to 3 nm. 8 . The method according to claim 1 , wherein the stack comprises at least one third layer, the at least one third layer being made of a conductive material, the at least one third layer covering the second layer. 9 . The method according to claim 8 , wherein the stack comprises at least one fourth layer, the at least one fourth layer being made of an insulating material, the at least one fourth layer covering the third layer.

10. The method of claim 1, wherein the second layer is made of an alloy including at least one chalcogen element.

11. The method of claim 1, wherein the resistive element is L-shaped.

12. The method of claim 1, wherein the first layer is made of a refractory metal.

13. The method of claim 1, wherein forming the spacers is performed in the same housing as etching the stack, the device not being removed from the housing between the steps.

14. The method of claim 1, wherein etching the stack forms a pattern of the stack on the first layer.

15. The method of claim 1, wherein before etching the stack, an etching mask is formed, the etching mask covering the location of the memory cell.

16. An electronic device comprising: a first insulating layer, the first insulating layer having a first side, the first side being opposite to the second side along a first direction; a second insulating layer on the first side; a conductive element, wherein the conductive element is in the second insulating layer; a first resistive layer, the first resistive layer being on the second side of the first insulating layer; an L-shaped resistive element extending from the first resistive layer completely through the first insulating layer to the conductive element; a stack of layers, said stack of layers being located on a central portion of said first layer, said stack comprising at least one phase change layer; as well as A spacer covers a plurality of sidewalls of the stack and is on a peripheral portion of the first layer. 17 . The device of claim 16 , wherein the spacer comprises one of silicon tetrachloride (SiCl 4 ), silicon nitride (SiN), or silicon carbide (SiC).

18. The device according to claim 16, wherein the L-shaped resistive element comprises a first portion and a second portion, the first portion extending along the first direction and coupled between the first resistive layer and the conductive element, the second portion extending along a second direction, the second direction being transverse to the first direction, and the second portion being coplanar with the first side of the first insulating layer.

19. A method for manufacturing an electronic device, comprising: forming a first resistive layer on a first side of a first insulating layer, the first insulating layer comprising an L-shaped resistive element, the L-shaped resistive element extending completely from the first side to a second side, the second side being opposite to the first side; forming a stack of layers on the first layer, the stack including at least one second phase change layer; etching the stack from a first surface of the stack completely through the second phase change layer to the first layer; forming a second insulating layer on the first surface of the stack, each of a plurality of sidewalls of the stack being transverse to the first surface of the stack and the first resistive layer; forming a spacer on each of the plurality of sidewalls by etching the second insulating layer to the first resistive layer; as well as The first layer is etched to the first insulating layer.

20. The method according to claim 19, further comprising: A second insulating layer on the second side of the first insulating layer and a conductive element in the second insulating layer, the L-shaped resistive element being directly coupled to the first resistive layer and the conductive element.

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