Driving circuit structure, array substrate, display device and preparation method of array substrate

Abstract

The invention provides a driving circuit structure, an array substrate, a display device and a preparation method of the array substrate. The driving circuit structure comprises a substrate; the initial signal line is positioned on the substrate; the clock signal line is positioned on the substrate; and the first insulating layer is positioned on one side, far away from the substrate, of the initial signal line and comprises a first via hole. The initial signal line is connected with the clock signal line through the first via hole.

Description

Driving circuit structure, array substrate, display device, and method for manufacturing array substrate

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit structure, an array substrate, a display device, and a method for preparing the array substrate.

[0002] In the field of display technology, such as a display panel, its pixel array usually includes multiple rows of gate lines and multiple columns of data lines interlaced therewith. The driving of the gate lines can be achieved by a bound integrated driving circuit. In recent years, with the continuous improvement of the preparation process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line driving circuit can also be directly integrated on the array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA composed of multiple cascaded shift register units can be used to provide scanning signals for multiple rows of gate lines, thereby controlling the opening and closing of multiple rows of gate lines. At present, more and more display panels use GOA technology to drive the gate lines. GOA technology helps to achieve a narrow frame design of the display panel and can reduce the production cost of the display panel.

[0003]

[0004] According to one aspect of the present disclosure, a driving circuit structure is provided, comprising: a substrate; an initial signal line located on the substrate; a clock signal line located on the substrate; and a first insulating layer located on a side of the initial signal line away from the substrate and comprising a first via hole. The initial signal line is connected to the clock signal line via the first via hole.

[0005] In some embodiments, the driving circuit structure further includes: a second insulating layer located on a side of the first insulating layer away from the substrate and including a second via hole; and a protection pad filling at least the second via hole. The orthographic projection of the protection pad on the substrate at least partially overlaps with the orthographic projection of the first via hole on the substrate.

[0006] In some embodiments, the clock signal line is located on a side of the initial signal line away from the substrate, a conductive portion is provided in the first via, one end of the conductive portion is directly connected to the initial signal line, and the other end of the conductive portion is directly connected to the clock signal line.

[0007] In some embodiments, the orthographic projection of the initial signal line on the substrate partially overlaps with the orthographic projection of the clock signal line on the substrate to form an overlapping region, and the orthographic projection of the first via on the substrate falls within the overlapping region.

[0008] In some embodiments, the initial signal line and the clock signal line are located in the same layer, and an orthographic projection of the initial signal line on the substrate does not overlap with an orthographic projection of the clock signal line on the substrate.

[0009] In some embodiments, the driving circuit structure further includes: a first routing group, including at least one of the initial signal lines extending along a first direction; a second routing group, including at least one of the clock signal lines extending along the first direction, the orthographic projection of the second routing group on the substrate does not overlap with the orthographic projection of the first routing group on the substrate; and at least one first connecting line, extending along a second direction intersecting the first direction and located on a side of the first insulating layer away from the substrate. At least one clock signal line in the second routing group is connected to any one of the initial signal lines in the first routing group via the first connecting line.

[0010] In some embodiments, the clock signal line includes a hollow portion and a solid portion, the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the solid portion on the substrate, and the orthographic projection of the first connecting line and the first via on the substrate does not overlap with the orthographic projection of the hollow portion on the substrate.

[0011] In some embodiments, the driving circuit structure further includes at least one second connecting line extending along the second direction. Each clock signal line in the second wiring group is connected to a corresponding second connecting line, and the orthographic projection of the first connecting line on the substrate does not overlap with the orthographic projection of the second connecting line on the substrate.

[0012] In some embodiments, the first insulating layer further includes a plurality of groups of third vias, and each clock signal line in the second wiring group is connected to the corresponding second connecting line via a group of third vias in the plurality of groups of third vias.

[0013] In some embodiments, a clock signal line in the second routing group has two cutting openings. A first connecting line among the at least one first connecting line is connected to the clock signal line with two cutting openings, and the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the clock signal line with two cutting openings on the substrate, and the overlapping part is the first orthographic projection, and the orthographic projection of one group of third vias among the plurality of groups of third vias on the substrate is the second orthographic projection, and the second orthographic projection falls within the orthographic projection of the clock signal line with two cutting openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings on the substrate.

[0014] In some embodiments, the first connecting line includes a first end and a second end opposite to each other, the first end of the first connecting line is connected to any initial signal line in the first routing group via the first via, and the second end of the first connecting line is connected to any clock signal line in the second routing group via the first via.

[0015] In some embodiments, the second routing group includes a plurality of clock signal lines arranged in parallel along the first direction, the first connecting line crosses the plurality of clock signal lines in the second routing group along the second direction, the first connecting line includes a first end and a second end relative to each other, the first end of the first connecting line is connected to any one of the initial signal lines in the first routing group via the first via, and the orthographic projection of the second end of the first connecting line on the substrate falls within the orthographic projection of the clock signal line farthest from the initial signal line among the plurality of clock signal lines of the second routing group on the substrate.

[0016] In some embodiments, one of the at least one first connecting line is fused to the clock signal line having two cutting openings.

[0017] In some embodiments, the driving circuit structure further includes a first power signal line and a second power signal line extending along the first direction. The first power signal line and the second power signal line are located on a side of the second wiring group away from the first wiring group, and the orthographic projection of the cutting opening and the fusion area of ​​the clock signal line on the substrate does not overlap with the orthographic projection of the first power signal line and the second power signal line on the substrate.

[0018] In some embodiments, one of the at least one first connection line is connected to the clock signal line having two cutting openings through the first via hole.

[0019] In some embodiments, the first via hole includes a first opening and a second opening opposite to each other, the first opening and the second opening are circular or elliptical in shape, the longitudinal section of the first via hole is rectangular or inverted trapezoidal, and the longitudinal section is parallel to the thickness direction of the substrate.

[0020] According to another aspect of the present disclosure, an array substrate is provided, which includes the driving circuit structure described in any of the above embodiments.

[0021] In some embodiments, the array substrate also includes: a first conductive layer, which is located on the same layer as the initial signal line; a second conductive layer, which is located on a side of the first insulating layer away from the substrate, and the first conductive layer is connected to the second conductive layer through a conductive portion in the first via; a second insulating layer, which is located on a side of the second conductive layer away from the substrate and includes a fourth via; and a third conductive layer, which is located on a side of the second insulating layer away from the substrate and connected to the second conductive layer via the fourth via.

[0022] In some embodiments, the second insulating layer further includes a fifth via hole, the third conductive layer fills the fourth via hole and the fifth via hole, and a depth of the fifth via hole is greater than a depth of the fourth via hole.

[0023] According to yet another aspect of the present disclosure, a display device is provided, comprising the array substrate described in any one of the above embodiments.

[0024] In some embodiments, the display device includes a display area and a peripheral area arranged around the display area, and the driving circuit structure is arranged in the peripheral area.

[0025] According to another aspect of the present disclosure, a method for preparing an array substrate is provided, comprising: providing a substrate; forming a plurality of initial signal lines on the substrate; forming a plurality of clock signal lines on the substrate; and forming a first insulating layer comprising a plurality of first vias on a side of the initial signal lines away from the substrate, the initial signal lines being connected to the clock signal lines via the first vias.

[0026] In some embodiments, the initial signal line, the clock signal line, and the first insulating layer are respectively formed using different masks having a first size, so that the array substrate has a second size that is different from the first size.

[0027] In some embodiments, the first size is greater than the second size, and the array substrate having the second size has a bar shape.

[0028] In some embodiments, the first dimension is 65 inches and the second dimension is 58.5 inches.

[0029] In some embodiments, a plurality of initial signal lines, a plurality of clock signal lines, and a first insulating layer are formed on the substrate, including: depositing a first metal layer on the substrate, and composing the first metal layer by blocking a portion of a first mask having the first size to form the plurality of initial signal lines; depositing a first intermediate insulating layer on a side of the initial signal line away from the substrate, and composing the first intermediate insulating layer by blocking a portion of a second mask having the first size to form the first insulating layer including a plurality of first vias, wherein the first vias expose a portion of the surface of the initial signal line; and depositing a second metal layer on a side of the first insulating layer away from the substrate, and composing the second metal layer by blocking a portion of a third mask having the first size to form the plurality of clock signal lines on a side of the first insulating layer away from the substrate, and forming a conductive portion in the first via, wherein the initial signal line is connected to the clock signal line via the conductive portion.

[0030] In some embodiments, the method also includes: depositing a second intermediate insulating layer on a side of the clock signal line away from the substrate, and composing the second intermediate insulating layer by blocking a portion of the second mask plate to form a second insulating layer including a plurality of second vias, wherein the second vias expose a portion of the surface of the clock signal line; and depositing a third metal layer on a side of the second insulating layer away from the substrate, and composing the third metal layer by blocking a portion of a fourth mask plate having the first size to form a protective pad, wherein the protective pad at least fills the second vias.

[0031] In some embodiments, a plurality of initial signal lines and a plurality of clock signal lines are formed on the substrate, including: depositing a first metal layer on the substrate, and patterning the first metal layer by blocking a portion of a first mask having the first size to form a first routing group and a second routing group, the first routing group including a plurality of initial signal lines arranged along a first direction, the second routing group including a plurality of clock signal lines arranged along the first direction, and an orthographic projection of the first routing group on the substrate and an orthographic projection of the second routing group on the substrate do not overlap.

[0032] In some embodiments, the method further includes: depositing a first intermediate insulating layer on a side of the initial signal line and the clock signal line away from the substrate, and patterning the first intermediate insulating layer by blocking a portion of a second mask having the first size to form a first insulating layer including the plurality of first vias and a plurality of groups of third vias, wherein the first vias expose a portion of the surface of the initial signal line and the clock signal line, and the third vias expose a portion of the surface of the clock signal line; depositing a second metal layer on a side of the first insulating layer away from the substrate, and patterning the second metal layer by blocking a portion of a third mask having the first size to form at least one first connecting line and at least one second connecting line arranged along a second direction, wherein the first connecting line includes a first end and a second end opposite to each other, and the first end of the first connecting line is connected to the first connecting line via the first via. A hole is connected to any initial signal line in the first routing group, the second end of the first connecting line is connected to any clock signal line in the second routing group via the first via hole, each clock signal line in the second routing group is connected to a corresponding second connecting line via a group of third via holes in the multiple groups of third via holes, and the second direction intersects with the first direction; a second intermediate insulating layer is deposited on the side of the first connecting line and the second connecting line away from the substrate, and the second intermediate insulating layer is composed by blocking a part of the second mask plate to form a second insulating layer including a plurality of second via holes; and a third metal layer is deposited on the side of the second insulating layer away from the substrate, and the third metal layer is composed by blocking a part of the fourth mask plate having the first size to form a protection pad, and the protection pad at least fills the second via hole.

[0033] In some embodiments, the method further includes: cutting a clock signal line in the second routing group so that the clock signal line has two cutting openings. The orthographic projection of the first connecting line connected to the clock signal line with two cutting openings on the substrate partially overlaps with the orthographic projection of the clock signal line with two cutting openings on the substrate, the overlapping part is the first orthographic projection, the orthographic projection of one group of third vias in the plurality of groups of third vias on the substrate is the second orthographic projection, the second orthographic projection falls within the orthographic projection of the clock signal line with two cutting openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings on the substrate.

[0034] In some embodiments, the method further includes: depositing a first intermediate insulating layer and a second metal layer in sequence on a side of the initial signal line and the clock signal line away from the substrate, and patterning the first intermediate insulating layer and the second metal layer by blocking a portion of a second mask having the first size to form a first insulating layer including the plurality of first vias and the plurality of groups of third vias, and at least one first connecting line and at least one second connecting line arranged along a second direction, wherein the first via exposes a portion of the surface of the initial signal line, the third via exposes a portion of the surface of the clock signal line, the first connecting line crosses over the plurality of clock signal lines in the second routing group along the second direction, the first connecting line includes a first end and a second end opposite to each other, and the first end of the first connecting line is connected to any first routing line in the first routing group via the first via. an initial signal line, the orthographic projection of the second end of the first connecting line on the substrate falls within the orthographic projection of the clock signal line farthest from the initial signal line among the multiple clock signal lines of the second wiring group on the substrate, each clock signal line in the second wiring group is connected to a corresponding second connecting line via a group of third vias in the multiple groups of third vias, and the second direction intersects with the first direction; a second intermediate insulating layer is deposited on a side of the first connecting line and the second connecting line away from the substrate, and the second intermediate insulating layer is composed by blocking a part of the third mask having the first size to form a second insulating layer; and a third metal layer is deposited on a side of the second insulating layer away from the substrate, and the third metal layer is composed by blocking a part of the fourth mask having the first size to form a pixel electrode.

[0035] In some embodiments, the method further includes: cutting a clock signal line in the second routing group so that the clock signal line has two cutting openings; and fusing the clock signal line having the two cutting openings with the first connecting line located between the two cutting openings in a fusing area. The orthographic projection of the fusing area on the substrate is a first orthographic projection, the orthographic projection of a group of third vias in the plurality of groups of third vias on the substrate is a second orthographic projection, the second orthographic projection falls within the orthographic projection of the clock signal line having the two cutting openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings on the substrate.

[0036] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, in which:

[0037] FIG1 shows a schematic diagram of the arrangement of a driving circuit;

[0038] FIG2 shows a partial enlarged view of area ① in FIG1 ;

[0039] FIG3 shows a top view and a cross-sectional view of a local area of ​​a driving circuit structure according to an embodiment of the present disclosure;

[0040] FIG4 is a schematic plan view showing a circuit arrangement of a driving circuit structure according to an embodiment of the present disclosure;

[0041] FIG5 shows an electron microscope image of a first via hole according to an embodiment of the present disclosure;

[0042] FIG6 shows an electron microscope image of a local area of ​​a driving circuit structure in a preparation stage according to an embodiment of the present disclosure;

[0043] FIG7 shows a top view of a local area of ​​a driving circuit structure according to an embodiment of the present disclosure under an electron microscope during the preparation stage;

[0044] FIG8 shows a cross-sectional view of the driving circuit structure taken along the cutting line of FIG7 ;

[0045] FIG9 is a schematic diagram showing a circuit arrangement of a driving circuit structure according to an embodiment of the present disclosure;

[0046] FIG10 is a schematic cross-sectional view of a local area of ​​the driving circuit structure taken along line BB' of FIG9;

[0047] FIG11 is a schematic cross-sectional view of a local area of ​​a driving circuit structure;

[0048] FIG12 is a schematic diagram showing a circuit arrangement of a driving circuit structure according to an embodiment of the present disclosure;

[0049] FIG13 is a schematic diagram showing a circuit arrangement of a driving circuit structure according to an embodiment of the present disclosure;

[0050] FIG14 shows a schematic structural diagram of a local area of ​​an array substrate;

[0051] FIG15 shows a top view of a local area of ​​an array substrate according to an embodiment of the present disclosure;

[0052] FIG16 is a schematic cross-sectional view of a local area of ​​the array substrate taken along line CC' of FIG15;

[0053] FIG. 17 shows comparative data of contact resistance and current resistance parameters of a conventional array substrate and an array substrate according to an embodiment of the present disclosure;

[0054] FIG18 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0055] FIG. 19 is a flow chart showing a method for preparing an array substrate according to an embodiment of the present disclosure;

[0056] FIG20 is a schematic diagram showing how to respectively prepare a first-size product and a second-size product using a first-size mask according to an embodiment of the present disclosure;

[0057] FIG21 is a schematic diagram showing a method for preparing a first metal layer by using an embodiment of the present disclosure;

[0058] FIG22 is a schematic diagram showing a method for preparing a first insulating layer by using an embodiment of the present disclosure;

[0059] FIG23 is a schematic diagram showing a method for preparing a second metal layer by using an embodiment of the present disclosure;

[0060] FIG24 is a schematic diagram showing a second insulating layer prepared by the method provided by an embodiment of the present disclosure; and

[0061] FIG. 25 shows a schematic diagram of preparing a third metal layer using the method provided in an embodiment of the present disclosure.

[0062] It should be understood that the accompanying drawings are only schematic illustrations of exemplary embodiments of the present disclosure, and are not intended to limit the present disclosure, nor are they necessarily drawn to scale. In addition, in the accompanying drawings, identical or similar components are indicated by identical or similar reference numerals.

[0063] The technical solutions in the embodiments of the present disclosure will be described clearly below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0064] Before formally describing the technical solutions of the embodiments of the present disclosure, certain terms used in the embodiments of the present disclosure are explained and defined as follows to help those skilled in the art to more clearly understand the technical solutions of the embodiments of the present disclosure.

[0065] As used herein, terms such as "A and B are located in the same layer" means that A and B are formed by the same patterning process, but this does not limit layer A and layer B to have the same height or thickness. In the case of "A and B are located in the same layer", layer A and layer B are generally composed of the same material. Similarly, terms such as "A and B are located in different layers" mean that A and B are generally formed by different patterning processes, layer A and layer B can be composed of the same material or different materials, and layer A and layer B can have the same height and / or thickness, or have different heights and / or thicknesses.

[0066] As used herein, the term "patterning process" or "patterning" includes but is not limited to processes such as depositing a film layer, coating a photoresist, exposing, developing, etching, and stripping the photoresist. After the "patterning process" or "patterning", the "layer" contains at least one pattern.

[0067] GOA technology is a technology that integrates the gate drive circuit on the array substrate to form a scanning drive for the gate line, which can improve the integration of the array substrate and reduce the number of gate drive circuits used. GOA technology helps to achieve a narrow frame design for the display panel and can reduce the production cost of the display panel.

[0068] In order to further reduce product development costs and to quickly respond to customer needs for products of different sizes, the inventors of the present application have discovered that the mask used to prepare products of existing sizes can be used to make other (some) other sized products by shielding exposure and partial exposure. Since GOA products usually place the initial signal line of GOA (or STV line) on the opposite side of the data line pad, when sharing the existing product mask to make other products of different sizes, some GOA units and initial signal lines need to be cut off, which makes it impossible for the STV signal on the initial signal line to be transmitted to the GOA unit, resulting in the product not being able to work properly.

[0069] At present, one method to solve the above problem is to use the maintenance method of cutting and welding, and introduce the STV signal by borrowing the clock signal line (or called CLK routing) to realize GOA driving. As shown in Figure 1, it shows five rows of GOA units, namely GOA1~GOA4 and Dummy GOA, GOA3 is the 1084th row of GOA units, GOA2 is the 1085th row of GOA units, GOA1 is the 1086th row of GOA units, and Dummy GOA is the 1087th row of GOA units. The scanning direction is from GOA1 to GOA4. As mentioned above, in order to share the existing product mask to make another size product, it is necessary to cut off part of the structure of GOA1~GOA3. The cutting position is the position shown by the black solid line in Figure 1, and a total of about 12 places need to be cut. In order to introduce the STV signal through the CLK routing, the CLK routing and the STV routing need to be welded. Figure 1 shows 5 welding positions, of which ① shows two welding positions and ② shows three welding positions. By welding the CLK routing and the STV routing, the STV signal at point ① can be introduced into the three wires at point ② through the CLK routing. The three wires at point ② are connected to the GOA1~GOA3 units respectively, so that the STV signal can be introduced into the GOA1~GOA3 units.

[0070] FIG2 is a partial enlarged view of point ① in FIG1. ​​As shown in FIG2, VDDO and VDDE are arranged on both sides of the CLK line, and both VDDO and VDDE partially overlap with the STV line. The STV line, CLK line, VDDO line, and VDDE line are arranged relatively closely to each other. In the process of welding the STV line and the CLK line at the maintenance point ①, it is very easy to cause the STV line to short-circuit with the adjacent VDDO line and / or VDDE line, resulting in display abnormality or even failure of display on the display panel, reducing the production yield of the product.

[0071] In view of this, embodiments of the present disclosure provide some drive circuit structures. These drive circuit structures include: a substrate, an initial signal line (also referred to as an STV line) arranged on the substrate, a clock signal line (also referred to as a CLK line) arranged on the substrate, and a first insulating layer located on a side of the initial signal line away from the substrate, the first insulating layer including a first via, and the initial signal line is connected to the clock signal line via the first via. The drive circuit structure can be, for example, a gate drive circuit structure, which can use a GOA composed of a plurality of cascaded shift register units to provide a scan signal for a plurality of rows of gate lines, thereby controlling the opening and closing of the plurality of rows of gate lines.

[0072] It should be noted that the phrase "the initial signal line is connected to the clock signal line via the first via" means that the connection between the initial signal line and the clock signal line requires the participation of the first via, but this does not exclude the presence of other electrical components. For example, the initial signal line can be connected to the clock signal line only via the first via (and the conductive material contained in the first via), that is, one end of the first via is directly connected to the initial signal line, and the other end of the first via is directly connected to the clock signal line. Alternatively, the initial signal line can be connected to the clock signal line via the first via and other electrical components (including but not limited to wires).

[0073] In the driving circuit structure provided by the embodiment of the present disclosure, the initial signal line is connected to the clock signal line via the first via hole, so that the STV signal on the initial signal line is introduced into the GOA unit. In this way, the initial signal line can be prevented from short-circuiting with other lines, so that the display panel can display normally, which helps to improve the production yield of the display panel.

[0074] The following describes in more detail the arrangement of various driving circuit structures provided by the embodiments of the present disclosure with the help of several exemplary embodiments.

[0075] FIG3 shows a schematic diagram of a local area of ​​the driving circuit structure 100, wherein the left figure is a top view of the local area of ​​the driving circuit structure 100, and the right figure is a cross-sectional view taken along the AA' line of the left figure. As shown in FIG3, the driving circuit structure 100 includes: a substrate 101, an initial signal line 102 arranged on the substrate 101, a first insulating layer 104 located on a side of the initial signal line 102 away from the substrate 101, and a clock signal line 103 located on a side of the first insulating layer 104 away from the substrate 101. The first insulating layer 104 includes a first via 105, and the initial signal line 102 is connected to the clock signal line 103 via the first via 105. More specifically, as shown in Figure 3, a conductive portion 106 is provided in the first via 105, one end 1061 of the conductive portion 106 is directly connected to the initial signal line 102, and the other end 1062 of the conductive portion 106 is directly connected to the clock signal line 103, so that the initial signal line 102 is connected to the clock signal line 103 through the conductive portion 106 in the first via 105.

[0076] The initial signal line 102 is connected to the clock signal line 103 through the conductive portion 106 in the first via hole 105, without being connected to the clock signal line 103 by welding. In this way, it is possible to avoid short circuits between the initial signal line 102 and other surrounding wirings during the welding process, so that the display panel including the driving circuit structure 100 can display normally. In addition, since the depth of the first via hole 105 is usually shallow (for example, the depth is about several hundred nanometers), the initial signal line 102 is connected to the clock signal line 103 by using the first via hole 105, which can improve the reliability and success rate of the connection between the initial signal line 102 and the clock signal line 103, and help to significantly improve the production yield of the display panel including the driving circuit structure 100. If the first via hole 105 has a deeper depth, in the process of etching the first insulating layer 104 to form the first via hole 105, due to the metal induced plasma effect, the etching rate of the portion of the first insulating layer 104 close to the clock signal line 103 is usually greater than the etching rate of other portions, which easily causes the first insulating layer 104 at the bottom of the clock signal line 103 to be hollowed out, thereby forming a chamfer (Undercut). The existence of the chamfer easily causes other film layers to break at the chamfer, which in turn causes problems such as abnormal connection and electrostatic breakdown. In contrast, in the driving circuit structure 100 of FIG. 3, the first via hole 105 has a shallower depth. In the process of forming the first via hole 105, the first insulating layer 104 will not be chamfered, which can avoid the negative impact of the chamfer and help improve the reliability of the product. In addition, the existence of the first via hole 105 can improve the recognition of the maintenance point, which helps to improve the efficiency of maintenance personnel and the success rate of maintenance.

[0077] The initial signal line 102 can be used to provide a start signal (STV signal) for the driving circuit structure 100, the clock signal line 103 can be used to provide a clock signal for the driving circuit structure 100, and at least one clock signal line 103 can be used to transmit the STV signal on the initial signal line 102 to the driving circuit structure 100.

[0078] The first via hole 105 penetrates the first insulating layer 104 and includes a first opening 1051 and a second opening 1052 opposite to each other. The shapes of the first opening 1051 and the second opening 1052 may be circular or elliptical. Exemplarily, the longitudinal section of the first via hole 105 may be rectangular or inverted trapezoidal. The longitudinal section of the first via hole 105 is the section shown in the right figure of FIG. 3 , which is parallel to the thickness direction of the substrate 101. The inverted trapezoidal first via hole 105 is more conducive to the connection between the clock signal line 103 and the initial signal line 102, so that the via hole resistance is smaller.

[0079] It should be noted that the first insulating layer 104 includes a plurality of first vias 105, but not all of the first vias 105 are used to connect the initial signal line 102 and the clock signal line 103. For example, a portion of the first vias 105 can be used to connect the initial signal line 102 and the clock signal line 103, and a portion of the first vias 105 can be used to connect the initial signal line 102 to other wirings, or to connect the metal layer located at the same layer as the initial signal line 102 to other metal layers.

[0080] As shown in FIG3 , the initial signal line 102 and the clock signal line 103 are located in different layers. The initial signal line 102 can be located in the same layer as the gate line, the gate electrode, etc., for example, and the same mask plate can be used to form the initial signal line 102, the gate line, the gate electrode, and other structures. The clock signal line 103 can be located in the same layer as the first power signal line 110, the second power signal line 111, the source / drain (not shown), etc., for example, and the same mask plate can be used to form the clock signal line 103, the first power signal line 110, the second power signal line 111, the source / drain, and other structures. The orthographic projection of the initial signal line 102 on the substrate 101 partially overlaps with the orthographic projection of the clock signal line 103 on the substrate 101 to form an overlapping region R, and the orthographic projection of the first via 105 on the substrate 101 falls within the overlapping region R.

[0081] The first power signal line 110 (for example, it can be a VDDO line) and the second power signal line 111 (for example, it can be a VDDE line) can be used to transmit voltage signals. As shown in FIG3 , the first power signal line 110 and the second power signal line 111 are arranged on both sides of the clock signal line 103, and the orthographic projections of the first power signal line 110 and the second power signal line 111 on the substrate 101 partially overlap with the orthographic projections of the initial signal line 102 on the substrate 101. Since the initial signal line 102 and the clock signal line 103 are connected through the first via 105 instead of being connected by welding, even if the first power signal line 110 and the second power signal line 111 are arranged relatively closely with the initial signal line 102, the initial signal line 102 will not be short-circuited with the nearby first power signal line 110 and / or second power signal line 111, thereby ensuring the normal display of the display panel and helping to improve the production yield of the product.

[0082] In some embodiments, the driving circuit structure 100 may further include a second insulating layer 107 and a protective pad 109, the second insulating layer 107 is located on the side of the clock signal line 103 away from the substrate 101 and includes a second via 108, the protective pad 109 at least fills the second via 108, and the orthographic projection of the protective pad 109 on the substrate 101 overlaps at least partially with the orthographic projection of the first via 105 on the substrate 101. The protective pad 109 may cover the surface of the clock signal line 103 exposed by the second via 108. The protective pad 109 may be used to prevent corrosion of the clock signal line 103 and the conductive portion 106 in the first via 105 by external water vapor, so as to protect the clock signal line 103 and the conductive portion 106 in the first via 105.

[0083] FIG4 shows a schematic diagram of the arrangement of the driving circuit structure 100 on the array substrate, which shows regions I and II, wherein the enlarged view of region I of FIG4 is the left view of FIG3. Region I of FIG4 shows two first vias 105, and region II shows three first vias 105. At region I, the initial signal line 102 is connected to the clock signal line 103 via two first vias 105, and the clock signal line 103 is connected to three horizontal connection lines at region II via three first vias 105, respectively, and the three horizontal connection lines are connected to corresponding GOA units, respectively. In this way, the STV signal on the initial signal line 102 can be introduced into the corresponding GOA unit with the help of the clock signal line 103 to realize GOA driving.

[0084] Fig. 5 is a top view of the first via hole 105, which is an electron microscope picture of the first via hole 105. As shown in the figure, the shape of the first via hole 105 can be circular or elliptical, and its size can be determined according to product requirements.

[0085] FIG6 is a cross-sectional view after the SD metal layer is deposited, which is an electron microscope image. In FIG6, the Gate layer can be the aforementioned initial signal line 102, gate line, gate and other structures, the GI layer represents the aforementioned first insulating layer 104, which can be a gate insulating layer, and the SD layer can be a clock signal line 103, a first power signal line 110, a second power signal line 111, a source / drain and other structures. As shown in the figure, the first via 105 in the GI layer is filled with the SD layer deposition, so that the Gate layer and the SD layer are connected via the first via 105, thereby avoiding the short circuit problem caused by welding. Exemplarily, the thickness of the Gate layer can be about 456.4nm, the thickness of the GI layer can be about 390.3nm, the thickness of the SD layer can be about 562.2nm, the thickness of the intermediate layer between the GI layer and the SD layer can be about 36.38nm, and the thickness of the intermediate layer between the Gate layer and the substrate can be about 39.69nm. In some examples, the slope angle of the portion of the SD layer near the first via 105 of the GI layer is about 54.69°. In some examples, the first via hole 105 may be in an inverted trapezoidal shape, and the slope angle of the side surface of the first via hole 105 is about 84.09°.

[0086] Fig. 7 shows an electron microscope image after a second insulating layer 107 (also referred to as a PVX layer) is formed on the SD layer, and Fig. 8 is a cross-sectional view taken along the black solid line of Fig. 7. As shown in Figs. 7 and 8, the SD layer is not only located on the side of the GI layer away from the Gate layer, but also filled in the first via hole 105 of the GI layer, the PVX layer is located on the side of the SD layer away from the GI layer, and the SD layer in the first via hole 105 is wrapped by the PVX layer.

[0087] The display panel including the above-mentioned driving circuit structure 100 can be a display panel of various suitable types and various suitable sizes. Exemplarily, the display panel including the above-mentioned driving circuit structure 100 can be a display panel in the shape of a strip, for example, it can be used to be installed on a subway for display. In some embodiments, the display panel including the above-mentioned driving circuit structure 100 is a strip screen, and its size is 58.5 inches. The existing 65-inch mask for non-strip screens (for example, a mask for preparing a 65-inch TV) can be optimized and designed, for example, the pattern of the first via 105 and / or the pattern of the protective pad 109 are added to the 65-inch mask, and then the optimized 65-inch mask is used to prepare a 58.5-inch strip screen to achieve the sharing of the mask. The specific preparation method will be described later and will not be described in detail here.

[0088] 9 shows a schematic diagram of the arrangement of another driving circuit structure 200. Different from the driving circuit structure 100, in the driving circuit structure 200, the initial signal line 102 and the clock signal line 103 are located in the same layer.

[0089] FIG10 shows a cross-sectional view taken along the BB' line of FIG9. As shown in FIG9 and FIG10, the driving circuit structure 200 includes: a substrate 101; a first routing group arranged on the substrate 101, which includes at least one initial signal line 102 extending along the first direction D1; a second routing group arranged on the substrate 101, which includes at least one clock signal line 103 extending along the first direction D1, the initial signal line 102 and the clock signal line 103 are located in the same layer, and the orthographic projection of each initial signal line 102 on the substrate 101 does not overlap with the orthographic projection of each clock signal line 103 on the substrate 101. As an example, FIG9 shows that the first routing group includes two initial signal lines 102, which are respectively represented as STV1 and STV2. Of course, this is only an example, and the first routing group may include more initial signal lines. 9 shows that the second routing group includes 12 clock signal lines 103, respectively represented as CLK1-CLK12, of course, this is only an example, and the second routing group may include more or fewer clock signal lines. The disclosed embodiment does not specifically limit the number of initial signal lines 102 and clock signal lines 103.

[0090] The inventor of the present application has found that in a product where the initial signal line 102 and the clock signal line 103 are located in different layers, when preparing the clock signal line 103, the metal layer where the clock signal line 103 is located needs to climb over the metal layer where the initial signal line 102 is located, and the two will overlap. Since the initial signal line 102 has a certain thickness, when the clock signal line 103 climbs over the initial signal line 102, it is possible that the line will be broken. Therefore, during the preparation stage and the detection stage, it is necessary to pay attention to whether the relevant lines are broken. In the driving circuit structure 200, the initial signal line 102 and the clock signal line 103 are located in the same layer, which can reduce or even avoid the problem of the clock signal line 103 being broken. In addition, the initial signal line 102 and the clock signal line 103 do not overlap each other, which helps to reduce the load on the signal line.

[0091] As shown in FIGS. 9 and 10 , the driving circuit structure 200 further includes: a first insulating layer 104 located on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101, the first insulating layer 104 including a plurality of first vias 105 and a plurality of third vias 114; at least one first connecting line 112 extending along the second direction D2 and located on the side of the first insulating layer 104 away from the substrate 101; and at least one second connecting line 113 extending along the second direction D2 and located on the same layer as the first connecting line 112, the first direction D1 intersects with the second direction D2. For the sake of simplicity, FIG. 9 only schematically shows three first connecting lines 112 and two second connecting lines 113, but in fact, the number of first connecting lines 112 can be arbitrary, for example, the number of first connecting lines 112 can be equal to the number of clock signal lines 103 in the second wiring group. The number of second connecting lines 113 can also be arbitrary, for example, the number of second connecting lines 113 can be equal to the number of clock signal lines 103 in the second wiring group.

[0092] The first connection line 112 includes an opposite first end 1121 and a second end 1122. The first end 1121 of the first connection line 112 is connected to any one of the initial signal lines 102 in the first routing group via the first via 105, and the second end 1122 of the first connection line 112 is connected to any one of the clock signal lines 113 in the second routing group via another first via 115. For example, with respect to the embodiment of FIG. 9 , twelve first connection lines 112 may be provided. The first end 1121 of one of the twelve first connection lines 112 may be connected to any one of the initial signal lines STV1 and STV2 via the first via 105, and the second end 1122 of the first connection line 112 may be connected to any one of the clock signal lines CLK1 to CLK12 via another first via 105. The first end 1121 of another first connection line 112 among the twelve can be connected to any one of the initial signal lines STV1 and STV2 via the first via 105, and the second end 1122 of the first connection line 112 can be connected to any one of the remaining 11 clock signal lines via another first via 105, and so on. In this way, the first end 1121 of each first connection line 112 is connected to the initial signal line 102 via the first via 105, and the second end 1122 of each first connection line 112 is connected to the clock signal line 103 via the first via 105. In addition, each clock signal line 103 in the second routing group is connected to a corresponding second connection line 113 via a group of third vias 114, and the other end of the second connection line 113 that is not connected to the clock signal line 103 can be connected to the GOA unit, thereby realizing a complete signal transmission path.

[0093] Any clock signal line in the second routing group has two cutting openings 115 and 116. Which clock signal line in the second routing group is cut means selecting which clock signal line is used to transmit the STV signal on the initial signal line 102, and the uncut clock signal line will not transmit the STV signal. Any clock signal line among the clock signal lines CLK1 to CLK12 can be selected to transmit the STV signal. FIG9 takes the example of transmitting the STV signal through the clock signal line CLK3. As shown in Figure 9, the clock signal line CLK3 has two cutting openings 115 and 116. The first end 1121 of the first connecting line 112 is connected to the initial signal line STV2 via the first via 105, and the second end 1122 of the first connecting line 112 is connected to the clock signal line CLK3 via the first via 105. The orthographic projection of the first connecting line 112 on the substrate 101 partially overlaps with the orthographic projection of the clock signal line CLK3 on the substrate 101, and the overlapping part is the first orthographic projection. The clock signal line CLK3 is connected to the second connecting line 113 via a group of third vias 114, and the second orthographic projection of the group of third vias 114 on the substrate 101 falls within the orthographic projection of the clock signal line CLK3 on the substrate 101. The first orthographic projection and the second orthographic projection need to be located between the orthographic projections of the two cutting openings 115 and 116 on the substrate 101 to form an effective transmission path for the STV signal. The clock signal line CLK3 is selected to transmit the STV signal. The effective transmission path of the STV signal is: the STV signal on the initial signal line STV2 is transmitted to the clock signal line CLK3 via the first connection line 112 , and the clock signal line CLK3 transmits the STV signal to the GOA unit via the second connection line 113 .

[0094] Each clock signal line in the second routing group can be connected to a corresponding first connection line 112. In this way, even if a clock signal line is found to be broken during the production process, one of the other clock signal lines that have not been broken can be selected to be cut to transmit the STV signal. This design method greatly increases the selectivity of the cutting position. In addition, in the driving circuit structure 200, the initial signal line 102 is connected to the first connection line 112 via the first via 105, and the first connection line 112 is connected to the clock signal line 103 via the first via 105, that is, the initial signal line 102 is connected to the clock signal line 103 via the first via 105 and the first connection line 112, avoiding welding with the clock signal line 103. Therefore, in the driving circuit structure 200, only the clock signal line 103 needs to be cut, and there is no need to weld the clock signal line 103, so that the STV signal can be introduced into the GOA unit through the clock signal line 103 to realize GOA driving.

[0095] As shown in FIG9 , in order to reduce resistance, the initial signal line 102 and the clock signal line 103 are designed to include a hollow portion and a solid portion. The orthographic projection of the first connecting line 112 on the substrate 101 can partially overlap with the orthographic projection of the solid portion of the clock signal line 103 on the substrate 101, but the orthographic projection of the first connecting line 112 and the first via 105 on the substrate 101 does not overlap with the orthographic projection of the hollow portion of the clock signal line 103 on the substrate 101, that is, avoids the hollow portion of the clock signal line 103. Since the first connecting line 112 and the clock signal line 103 are located in different layers, by making the first connecting line 112 and the first via 105 avoid the hollow portion of the clock signal line 103, the problem of disconnection that may occur when the first connecting line 112 climbs over the clock signal line 103 with a certain thickness can be reduced or even avoided, thereby improving the connection success rate between the clock signal line 103 and the first connecting line 112.

[0096] In some embodiments, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the second connection line 113 on the substrate 101, thereby avoiding a short circuit between the two. Exemplarily, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the third via 114 on the substrate 101.

[0097] As shown in FIG9 , the driving circuit structure 200 may further include a first power signal line 110 (or referred to as a VDDO line), a second power signal line 111 (or referred to as a VDDE line), a common electrode lead COM, a third power signal line LVGL, etc. extending along the first direction D1. The second line group is located between the first line group and the first power signal line 110, and the display area of ​​the display panel may be located on a side of the third power signal line LVGL away from the second line group.

[0098] As shown in FIG. 10 , in some embodiments, the driving circuit structure 200 may further include a second insulating layer 107 and a protective pad 109. The second insulating layer 107 is located on a side of the first connecting line 112 away from the substrate 101 and includes a second via 108. The protective pad 109 at least fills the second via 108, and the orthographic projection of the protective pad 109 on the substrate 101 overlaps at least partially with the orthographic projection of the first via 105 on the substrate 101. The protective pad 109 may cover the surface of the first connecting line 112 exposed by the second via 108. The protective pad 109 may be used to prevent corrosion of the first connecting line 112 and the conductive portion 106 in the first via 105 by external water vapor, so as to protect the first connecting line 112 and the conductive portion 106 in the first via 105. The first connecting line 112 and the conductive portion 106 may be formed by the same patterning process.

[0099] The display panel including the above-mentioned driving circuit structure 200 can be a display panel of various appropriate types and sizes. Exemplarily, the display panel including the above-mentioned driving circuit structure 200 can be a strip display panel, which can be used to be installed on a subway for display, for example. In some embodiments, the display panel including the above-mentioned driving circuit structure 200 is a strip screen, and its size is 58.5 inches. The existing 65-inch mask plate can be optimized and designed, for example, the pattern of the first via 105, the pattern of the first connecting line 112, the pattern of the protective pad 109, etc. are pre-added to the existing 65-inch mask plate, and then the optimized 65-inch mask plate is used to prepare a 58.5-inch strip screen to achieve the sharing of the mask plate. The specific preparation method will be described later and will not be described in detail here.

[0100] Of course, the optimized 65-inch mask can continue to be used to prepare 65-inch non-strip screen products (such as TVs) without any adverse effects on the structure of non-strip screen products. For example, FIG11 shows a cross-sectional view of a local area of ​​a driving circuit structure of a non-strip screen product. As shown in FIG11, the driving circuit structure includes a substrate 11, an initial signal line 12, a first insulating layer 14, a second insulating layer 17, a clock signal line 18, a protective pad 19 and other structures.

[0101] Fig. 12 shows a schematic diagram of the layout of another driving circuit structure 300. Different from the driving circuit structure 100, in the driving circuit structure 300, the initial signal line 102 and the clock signal line 103 are located in the same layer.

[0102] As shown in FIG12, the driving circuit structure 300 includes: a substrate 101 (not shown); a first routing group arranged on the substrate 101, which includes at least one initial signal line 102 extending along the first direction D1; a second routing group arranged on the substrate 101, which includes at least one clock signal line 103 extending along the first direction D1, the initial signal line 102 and the clock signal line 103 are located in the same layer, and the orthographic projection of each initial signal line 102 on the substrate 101 does not overlap with the orthographic projection of each clock signal line 103 on the substrate 101. As an example, FIG12 shows that the first routing group includes two initial signal lines 102, respectively represented as STV1 and STV2. Of course, this is only an example, and the first routing group may include more initial signal lines 102. As an example, FIG12 shows that the second routing group includes 12 clock signal lines 103, respectively represented as CLK1 to CLK12. Of course, this is only an example, and the second routing group may include more or fewer clock signal lines 103. The disclosed embodiment does not specifically limit the number of initial signal lines 102 and clock signal lines 103. In the driving circuit structure 300, the initial signal line 102 and the clock signal line 103 are located in the same layer, which can prevent the clock signal line 103 from climbing over the initial signal line 102 with a certain thickness, thereby reducing or even preventing the problem of disconnection of the clock signal line 103. In addition, the initial signal line 102 and the clock signal line 103 do not overlap each other, which helps to reduce the load of the signal line.

[0103] The driving circuit structure 300 also includes: a first insulating layer 104 located on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101, the first insulating layer 104 including a plurality of first vias 105 and a plurality of groups of third vias 114; at least one first connecting line 112 extending along the second direction D2 and located on the side of the first insulating layer 104 away from the substrate 101; and at least one second connecting line 113 extending along the second direction D2 and located on the same layer as the first connecting line 112. For the sake of simplicity, FIG. 12 only schematically shows three first connecting lines 112 and three second connecting lines 113, but in fact, any number of first connecting lines 112 can be arranged, as long as the first connecting lines 112 avoid the hollow areas of the third vias 114 and the clock signal line 103. The number of second connecting lines 113 can be equal to the number of clock signal lines 103 in the second routing group.

[0104] The first connection line 112 includes a first end 1121 and a second end 1122 opposite to each other. The first end 1121 of the first connection line 112 is connected to any one of the initial signal lines 102 in the first wiring group via the first via 105. The orthographic projection of the second end 1122 of the first connection line 112 on the substrate 101 falls within the orthographic projection of the clock signal line 103 farthest from the initial signal line 102 among the multiple clock signal lines of the second wiring group on the substrate 101, that is, the first connection line 112 crosses the multiple clock signal lines in the second wiring group along the second direction D2. Different from the driving circuit structure 200, the first connection line 112 is not connected to the clock signal line 103 through the first via 105, but is connected to the clock signal line 103 by welding at the welding area 117. Since the first connection line 112 crosses over the multiple clock signal lines in the second routing group along the second direction D2, the first connection line 112 can be welded with any clock signal line 103 in the second routing group, thereby greatly increasing the selectivity of the position of the welding area 117, making the selection of the welding area 117 more flexible. Moreover, by adopting the arrangement mode that the first connection line 112 crosses over the multiple clock signal lines in the second routing group along the second direction D2, even if a clock signal line 103 in the second routing group has a fault such as a broken line, other clock signal lines 103 in the second routing group that have not failed can be selected to be welded with the first connection line 102, thereby greatly improving the connection reliability between the first connection line 112 and the clock signal line 103, and improving the production yield of the product.

[0105] Each clock signal line 103 in the second wiring group is connected to one end of a corresponding second connection line 113 via a group of third vias 114 , and the other end of the second connection line 113 may be connected to the GOA unit.

[0106] Any clock signal line in the second routing group has two cutting openings 115 and 116, and the first connecting line 112 is fused with the clock signal line 103 having two cutting openings at the fusion zone 117. Which clock signal line in the second routing group is cut and fused means selecting which clock signal line is used to transmit the STV signal on the initial signal line 102, and the clock signal line that is not cut and fused will not transmit the STV signal. Any clock signal line among the clock signal lines CLK1 to CLK12 can be selected to transmit the STV signal. FIG12 takes the clock signal line CLK3 as an example to transmit the STV signal. As shown in Figure 12, the clock signal line CLK3 has two cutting openings 115 and 116. The first end 1121 of the first connecting line 112 is connected to the initial signal line STV2 via the first via 105, and the first connecting line 112 is fused to the clock signal line CLK3 at the fusion zone 117. The initial signal line STV2 is connected to the clock signal line CLK3 by means of the first via 105, the first connecting line 112, and the fusion zone 117. The orthographic projection of the first connection line 112 on the substrate 101 partially overlaps with the orthographic projection of the clock signal line CLK3 on the substrate 101, and the overlapping part is the first orthographic projection. The clock signal line CLK3 is connected to the second connection line 113 via a group of third vias 114, and the second orthographic projection of the group of third vias 114 on the substrate 101 falls within the orthographic projection of the clock signal line CLK3 on the substrate 101. The first orthographic projection and the second orthographic projection need to be located between the orthographic projections of the two cutting openings 115 and 116 on the substrate 101 to form an effective transmission path for the STV signal. For example, the clock signal line CLK3 is selected to transmit the STV signal, and the effective transmission path of the STV signal is: the STV signal on the initial signal line STV2 is transmitted to the clock signal line CLK3 via the first connection line 112, and the clock signal line CLK3 transmits the STV signal to the GOA unit via the second connection line 113.

[0107] As shown in FIG. 12 , the driving circuit structure 300 may further include a first power signal line 110 (or referred to as a VDDO line), a second power signal line 111 (or referred to as a VDDE line), a common electrode lead COM, a third power signal line LVGL, etc. extending along the first direction D1. The display area of ​​the display panel may be located on the side of the third power signal line LVGL away from the second line group. The first power signal line 110 and the second power signal line 111 are located on the side of the second line group away from the first line group, and the orthographic projections of the cutting openings 115, 116 and the fusion zone 117 of the clock signal line on the substrate 101 do not overlap with the orthographic projections of the first power signal line 110 and the second power signal line 111 on the substrate 101. As mentioned above, in the related art, the initial signal line is very close to the first and second power signal lines. When the initial signal line is fused with the clock signal line, it is easy to cause the initial signal line to be short-circuited with the nearby first and second power signal lines, thereby causing display abnormality of the display panel. In contrast, in the driving circuit structure 300 of the embodiment of the present disclosure, the first power signal line 110 and the second power signal line 111 are designed to be far away from the initial signal line 102, and the cutting openings 115, 116 and the welding area 117 of the clock signal line 103 do not overlap with the first power signal line 110 and the second power signal line 111. In this way, even if the STV signal is introduced into the GOA unit by cutting and welding the clock signal line 103, it will not cause the initial signal line 102 to be short-circuited with the first power signal line 110 and the second power signal line 111.

[0108] As shown in FIG12 , in order to reduce resistance, the initial signal line 102 and the clock signal line 103 are designed to include a hollow portion and a solid portion. The orthographic projection of the first connecting line 112 on the substrate 101 can partially overlap with the orthographic projection of the solid portion of the clock signal line 103 on the substrate 101, but the orthographic projection of the first connecting line 112 and the first via 105 on the substrate 101 does not overlap with the orthographic projection of the hollow portion of the clock signal line 103 on the substrate 101, that is, avoids the hollow portion of the clock signal line 103. Since the first connecting line 112 and the clock signal line 103 are located in different layers, by making the first connecting line 112 and the first via 105 avoid the hollow portion of the clock signal line 103, the problem of disconnection when the first connecting line 112 crosses the clock signal line 103 with a certain thickness can be reduced or even avoided, thereby improving the connection success rate between the clock signal line 103 and the first connecting line 112.

[0109] In some embodiments, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the second connection line 113 on the substrate 101, thereby avoiding a short circuit between the two. Exemplarily, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the third via 114 on the substrate 101.

[0110] Since the first connection line 112 is connected to the clock signal line 103 by welding, it is possible to avoid providing the first via hole 105 at the position of the first insulating layer 104 corresponding to the clock signal line 103. Furthermore, since the first via hole 105 is not provided at the position corresponding to the clock signal line 103, external water vapor will not corrode the clock signal line 103 and / or the first connection line 112, and thus there is no need to provide a protective pad at the position corresponding to the first via hole 105.

[0111] The display panel including the above-mentioned drive circuit structure 300 can be a display panel of various appropriate types and sizes. Exemplarily, the display panel including the above-mentioned drive circuit structure 300 can be a strip display panel, for example, it can be used to be installed on a subway for display. In some embodiments, the display panel including the above-mentioned drive circuit structure 300 is a strip screen, and its size is 58.5 inches. The existing 65-inch mask plate can be optimized and designed, for example, the pattern of the first connecting line 112 is added to the existing 65-inch mask plate, and then the optimized 65-inch mask plate is used to prepare a 58.5-inch strip screen to achieve the sharing of the mask plate. The specific preparation method will be described later and will not be described in detail here.

[0112] FIG13 provides a schematic diagram of the arrangement of another driving circuit structure 400, which is a variation of the driving circuit structure 300. The driving circuit structure 400 shown in FIG13 has substantially the same construction as the driving circuit structure 300 shown in FIG12, and therefore the same reference numerals are used to refer to the same components. For the sake of brevity, the similarities between the driving circuit structure 400 and the driving circuit structure 300 are not repeatedly described, and only the differences are described below.

[0113] Different from the driving circuit structure 300, in the driving circuit structure 400, the first connecting line 112 is connected to the clock signal line 103 through the first via 105. Specifically, the first connecting line 112 crosses the multiple clock signal lines 103 in the second routing group along the second direction D2, and the first connecting line 112 includes a first end 1121 and a second end 1122 opposite to each other. The first end 1121 of the first connecting line 112 is connected to any initial signal line 102 in the first routing group via the first via 105, and the orthographic projection of the second end 1122 of the first connecting line 112 on the substrate 101 falls within the orthographic projection of the clock signal line 103 farthest from the initial signal line 102 among the multiple clock signal lines of the second routing group on the substrate 101. Any clock signal line 103 in the second routing group has two cutting openings 115 and 116, and the first connecting line 112 is connected to the clock signal line 103 having the two cutting openings via the first via 105.

[0114] In the driving circuit structure 400, the initial signal line 102 is connected to the first connection line 112 via the first via 105, and the first connection line 112 is connected to the clock signal line 103 via the first via 105, that is, the initial signal line 102 is connected to the clock signal line 103 via the first via 105 and the first connection line 112, thereby avoiding welding with the clock signal line 103. Therefore, in the driving circuit structure 400, only the clock signal line 103 needs to be cut, and there is no need to weld the clock signal line 103, so as to introduce the STV signal into the GOA unit by using the clock signal line 103 and realize GOA driving.

[0115] For other technical effects of the driving circuit structure 400 , reference may be made to the technical effects of the driving circuit structure 300 , and for the sake of brevity, they will not be described in detail here.

[0116] FIG14 is a schematic diagram of the structure of a local area of ​​a conventional array substrate 20. As shown in FIG14, the array substrate 20 includes: a substrate 11; a first conductive layer 21; a first insulating layer 22; a second conductive layer 23; a second insulating layer 24, which includes a via 26 and a via 27; and a third conductive layer 25. The second conductive layer 23 is connected to the third conductive layer 25 via the via 26, and the first conductive layer 21 is connected to the third conductive layer 25 via the via 27, that is, the second conductive layer 23 is connected to the first conductive layer 21 via the third conductive layer 25 (and the vias 26 and 27). The first conductive layer 21 can be an initial signal line, and the second conductive layer 23 can be a clock signal line.

[0117] The array substrate 20 mainly has the following two problems: on the one hand, since the second conductive layer 23 must be connected to the first conductive layer 21 by means of the third conductive layer 25, and the material of the third conductive layer 25 is usually different from that of the first conductive layer 21 and the second conductive layer 23, and the third conductive layer 25 usually has a certain area, the third conductive layer 25 has a large contact resistance, which is not conducive to meeting the electrical requirements of the array substrate 20; on the other hand, since the second conductive layer 23 must be connected to the first conductive layer 21 by means of vias 26 and 27, and the depth of the via 27 is relatively deep, in the process of etching the first insulating layer 22 and the second insulating layer 24 to form the via 27, due to the metal induced plasma effect, the etching rate of the first insulating layer 22 and the second insulating layer 24 close to the second conductive layer 23 is usually greater than the etching rate of other parts, which easily leads to the first insulating layer 22 under the second conductive layer 23 being hollowed out, thereby forming a chamfer. The existence of the chamfer easily causes other film layers to break at the chamfer, thereby causing problems such as abnormal connection and electrostatic breakdown.

[0118] The embodiment of the present disclosure provides an array substrate, which includes the driving circuit structure described in any of the above embodiments. The array substrate provided by the embodiment of the present disclosure can at least overcome the technical problems existing in the conventional array substrate 20 .

[0119] FIG15 shows a top view of a partial structure of an array substrate 500, and FIG16 shows a cross-sectional view taken along line CC' of FIG15. As shown in FIG15 and FIG16, the array substrate 500 includes: a substrate 101; a first conductive layer 501 located on the substrate 101, the first conductive layer 501 and the aforementioned initial signal line 101 being located on the same layer; a first insulating layer 104, which includes a first via 105; a second conductive layer 502, which is located on a side of the first insulating layer 104 away from the substrate 101 and connected to the first conductive layer 501 via a conductive portion 106 in the first via 105; a second insulating layer 107, which is located on a side of the second conductive layer 502 away from the substrate 101 and includes a fourth via 504; and a third conductive layer 503, which is located on a side of the second insulating layer 107 away from the substrate 101 and connected to the second conductive layer 502 via the fourth via 504.

[0120] 15 and 16 show a local area of ​​the array substrate 500, which may be a GOA area of ​​the array substrate 500, or a fan-out area of ​​the array substrate 500, or a display area of ​​the array substrate 500. When the local area is the GOA area of ​​the array substrate 500, the first conductive layer 501 may refer to the initial signal line 102, and the second conductive layer 502 may refer to the clock signal line 103, that is, the structure corresponds to the driving circuit structure 100; or, the first conductive layer 501 may refer to the initial signal line 102 and / or the clock signal line 103, and the second conductive layer 502 may refer to the first connecting line 112, that is, the structure corresponds to the driving circuit structure 200, 300, 400. When the local area is the display area of ​​the array substrate 500, the first conductive layer 501 may refer to the gate line and / or the gate, the second conductive layer 502 may refer to the source and drain, and the third conductive layer 503 may be the pixel electrode.

[0121] Different from the array substrate 20, in the array substrate 500, the first conductive layer 501 is not connected to the second conductive layer 502 by means of the third conductive layer 503, but is connected to the second conductive layer 502 by means of the conductive portion 106 in the first via hole 105, and the second conductive layer 502 and the conductive portion 106 in the first via hole 105 are formed by the same patterning process, so the conductive portion 106 in the first via hole 105 is made of the same material as the second conductive layer 502, so the contact resistance of the conductive portion 106 in the first via hole 105 can be ignored, that is, zero, which helps to improve the current resistance value of the array substrate 500. On the other hand, compared with the via hole 27 of the array substrate 20, the first via hole 105 of the array substrate 500 has a shallower depth, and in the process of forming the first via hole 105, the first insulating layer 104 will not be chamfered, thereby avoiding problems such as film breakage, abnormal connection, and electrostatic breakdown, which helps to improve the reliability of the array substrate 500.

[0122] As shown in FIG. 16 , in some embodiments, the second insulating layer 107 may further include a fifth via 505, the third conductive layer 503 fills the fourth via 504 and the fifth via 505, and the depth T2 of the fifth via 505 is greater than the depth T1 of the fourth via 504. In the product design stage, the size of the fourth via 504 may be smaller than the size of the fifth via 505, because, in the actual preparation process, it is necessary to first form a shallower fourth via 504, and then form a deeper fifth via 505. In the process of etching the fifth via 505, the fourth via 504 will inevitably continue to be etched, resulting in a further increase in the size of the fourth via 504. Therefore, in the design stage, the size of the fourth via 504 will be designed to be smaller than the size of the fifth via 505, so as not to cause a large size difference between the fourth via 504 and the fifth via 505. On the premise of meeting the design rules, the larger the size of the fourth via 504 and the fifth via 505 is, the better, because the fourth via 504 and the fifth via 505 are connected through the third conductive layer 503, and the larger the size of the fourth via 504 and the fifth via 505 is, the larger the contact area of ​​the third conductive layer 503 is, so that the resistance of the fourth via 504 and the fifth via 505 is lower, and the current resistance of the product is better, thereby avoiding static electricity problems caused by excessive via current.

[0123] FIG17 shows comparative data of contact resistance and current carrying capacity parameters of a conventional array substrate 20 and an array substrate 500 according to an embodiment of the present disclosure. In the via pattern of FIG17 , the light-colored area refers to the first conductive layer, the dark-colored area refers to the second conductive layer, the squares at the light-colored area represent deep holes, and the squares at the dark-colored area represent shallow holes. In the conventional array substrate 20, the first conductive layer 21 is connected to the second conductive layer 23 via vias 26 (shallow holes) and vias 27 (deep holes). In the array substrate 500, the first conductive layer 501 is connected to the second conductive layer 502 via the conductive portion 106 in the first via 105. It can be seen from the data in FIG17 that the conventional array substrate 20 has a larger resistance value and a smaller current carrying capacity at the vias; while the array substrate 500 has a negligible resistance value (0Ω) and a larger current carrying capacity (>10Ω) at the vias. 3 mA).

[0124] In some alternative embodiments, the second insulating layer 107 may include only the fourth via hole 504, but not the fifth via hole 505, that is, the fifth via hole 505 is filled. In this way, during the preparation process, it is not necessary to etch the fifth via hole 505 with a deeper depth, thereby reducing the etching time, and the size of the fourth via hole 504 can be reduced. The size of other via holes in the display area formed by the same process as the fourth via hole 504 can also be reduced accordingly, thereby helping to increase the aperture ratio of the display area, which is beneficial to improving the transmittance of the array substrate 500 and reducing the power consumption of the array substrate 500.

[0125] 18 shows a schematic diagram of the structure of a display device 600, which includes an array substrate 500. The array substrate 500 may include the driving circuit structure 100, 200, 300, 400 described in any of the above embodiments. Examples of the display device 600 include, but are not limited to, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, and navigators.

[0126] The display device 600 includes a display area 601 and a peripheral area 602 arranged around the display area 601, and the driving circuit structure 100, 200, 300, 400 can be arranged at a suitable position in the peripheral area 602. The driving circuit structure 100, 200, 300, 400 can be a gate drive circuit structure, which can include a plurality of cascaded shift register circuits. The gate drive circuit structure can generate a plurality of gate drive signals for outputting to the gate line, and a plurality of gate drive signals can be sequentially applied to each gate line. For example, the gate drive circuit structure can be integrated in the display device 600 as an array substrate row drive (gate driver on array, GOA) circuit.

[0127] The technical effects of the display device 600 may refer to the technical effects of the driving circuit structures described in the previous embodiments. For the sake of simplicity, the technical effects of the display device 600 will not be repeatedly described here.

[0128] FIG19 shows a flow chart of a method 700 for preparing an array substrate, where the array substrate may include the driving circuit structure described in any of the above embodiments. The method 700 may include the following steps:

[0129] S701: providing a substrate 101.

[0130] S702 : forming a plurality of initial signal lines 102 on the substrate 101 .

[0131] S703 : forming a plurality of clock signal lines 103 on the substrate 101 .

[0132] S704 : forming a first insulating layer 104 including a plurality of first via holes 105 on a side of the initial signal line 102 away from the substrate 101 , and the initial signal line 102 is connected to the clock signal line 103 via the first via holes 105 .

[0133] In method 700, the initial signal line 102 is connected to the clock signal line 103 via the first via 105, so that the STV signal on the initial signal line 102 is introduced into the GOA unit via the clock signal line 103. In this way, the initial signal line 102 can be prevented from short-circuiting with other lines, which helps to improve the production yield of the array substrate.

[0134] First, the general process of the method for preparing the conventional array substrate 20 can be described with reference to FIG. 14 .

[0135] A substrate 11 is provided.

[0136] Then, a first metal layer is deposited on the substrate 11, and photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed on the metal layer using mask template 1 to form a first conductive layer 21. The first conductive layer 21 can be an initial signal line, a gate line, a gate, etc.

[0137] Then, a gate insulating layer, an amorphous silicon layer, an ohmic contact layer, and a second metal layer are sequentially deposited on the side of the first conductive layer 21 away from the substrate 11, and photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed on the second metal layer using mask template 2 to form a first insulating layer 22 and a second conductive layer 23. The second conductive layer 23 includes, for example, a clock signal line, a first power signal line, a second power signal line, a source and a drain, etc.

[0138] Afterwards, an insulating layer is deposited on the side of the second conductive layer 23 away from the substrate 11, and photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed on the insulating layer using mask template three to form a second insulating layer 24. The second insulating layer 24 has via patterns formed in the display area and the GOA area, for example, including vias 26 and 27.

[0139] Finally, an electrode layer is deposited on the side of the second insulating layer 24 away from the substrate 11, and a photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed on the second insulating layer 24 using a mask plate 4 to form a third conductive layer 25. The third conductive layer 25 may include a pixel electrode in the display area and a connection layer in the GOA area. As shown in FIG. 14 , there is no via between the first conductive layer 21 and the second conductive layer 23, and the first conductive layer 21 and the second conductive layer 23 are connected via the third conductive layer 25.

[0140] In some embodiments, the size of the mask plates 1, 2, 3, and 4 is 65 inches. For example, the array substrate 20 can be applied to a 65-inch TV.

[0141] The above-mentioned mask plates one, two, three, and four can be optimized and improved accordingly, and the array substrate provided by the embodiment of the present disclosure can be prepared by shielding exposure and partial exposure to achieve the sharing of the mask plates. The size of the array substrate provided by the embodiment of the present disclosure is different from the size of the above-mentioned mask plates one, two, three, and four. The size of the above-mentioned mask plates one, two, three, and four is a first size, and the size of the array substrate formed by method 700 is a second size, and the first size is different from the second size. Exemplarily, the size of the above-mentioned mask plates one, two, three, and four is 65 inches, and the size of the array substrate formed by method 700 is 58.5 inches, which can be formed into a strip display screen. The strip display screen can be installed on a subway, for example, for display.

[0142] It should be noted that terms such as "the size of mask plates one, two, three, and four is the first size" means that the length of the diagonal of mask plates one, two, three, and four is the first size. Similarly, terms such as "the size of the array substrate is the second size" means that the length of the diagonal of the array substrate is the second size.

[0143] By optimizing and improving the existing mask, the existing mask can be used not only to prepare products of the first size, but also to prepare products of the second size, thereby improving the utilization rate of the mask and reducing the development cost. In addition, since the existing mask can be optimized to prepare other (some) other sizes of film layers, there is no need to redesign and prepare new mask, so it is possible to respond to customer needs for products of different sizes more quickly.

[0144] Next, with the help of FIG. 20 , it is described in more detail how to prepare an array substrate of a second size with the help of an existing mask of a first size.

[0145] In the example of FIG. 20 , the length of the existing mask along the first direction D1 is y inches, the width along the second direction D2 is 2x inches, and the length of its diagonal is 65 inches, i.e., the first size. The existing mask can be used to prepare a certain film layer(s) on the array substrate, or can be used to prepare a certain film layer(s) on the color filter substrate. Half of the existing mask is blocked along the second direction D2, so that its length along the first direction D1 is still y inches, the width along the second direction D2 becomes x inches, and the length of its diagonal becomes 58.5 inches, thereby forming a mask of the second size. On a substrate with a length of 2940 mm in the first direction D1 and a length of 3370 mm in the second direction D2, by covering half of the existing mask plate for exposure, ten substrates with a diagonal length of 58.5 inches can be formed, wherein the substrate A1 can be a 58.5-inch array substrate, and the substrate C1 can be a 58.5-inch color filter substrate; by using the existing mask plate for normal exposure, two substrates A2 with a diagonal length of 65 inches can be formed on the right side of the substrate. Therefore, on a substrate with a length of 2940 mm in the first direction D1 and a length of 3370 mm in the second direction D2, 10 58.5-inch strip-shaped substrates and 2 65-inch non-strip-shaped substrates can be formed.

[0146] It should be noted that the use of a 65-inch mask plate to prepare a 58.5-inch strip screen is only an example of using a common mask plate to make a strip screen. The specific size of the strip screen can be determined according to customer needs and scene applications. When a strip screen of other sizes is required, a strip screen of the corresponding size can be obtained by blocking 1 / 3, 1 / 4, etc. of the 65-inch mask plate. Alternatively, a strip screen of other required sizes can be obtained by partially blocking a mask plate of other sizes.

[0147] Next, a method for preparing an array substrate including a driving circuit structure 100 is described with reference to FIGS. 21-25 .

[0148] The left side of FIG. 21 is a top view, and the right side of FIG. 21 is a cross-sectional view taken along the DD' line of the top view. As shown in FIG. 21, a substrate 101 is first provided, and the material of the substrate 101 can be, for example, glass. Then, a first metal layer is deposited on the substrate 101, a portion of a first mask having a first size is shielded, and then processes such as photoresist coating, exposure, development, etching, and photoresist stripping are performed to pattern the first metal layer to form a plurality of initial signal lines 102, gate lines, gates, and other structures. The first mask can be the aforementioned mask 1. The material of the first metal layer includes, but is not limited to, molybdenum aluminum molybdenum (Mo / AL / Mo), molybdenum copper (Mo / Cu), molybdenum niobium copper (Mo / Nb / Cu), and molybdenum niobium copper molybdenum titanium (Mo / Nb / Cu / Mo / Ti).

[0149] The left side of FIG. 22 is a top view, and the right side of FIG. 22 is a cross-sectional view taken along the EE' line of the top view. As shown in FIG. 22, a gate insulating layer, an amorphous silicon layer, and an ohmic contact layer are sequentially deposited on the side of the initial signal line 102 away from the substrate 101, a portion of the second mask having a first size is shielded, and then processes such as photoresist coating, exposure, development, etching, and photoresist stripping are performed to form a first insulating layer 104 and a plurality of first vias 105 penetrating the first insulating layer 104, wherein the first vias 105 expose a portion of the surface of the initial signal line 102. The position of the first via 105 is the position where the initial signal line 102 overlaps with the clock signal line 103. By adding a design pattern of the first via 105 at the position where the initial signal line 102 overlaps with the clock signal line 103 on the aforementioned mask three, a second mask can be obtained.

[0150] Compared with FIG. 14 , the method provided in the embodiment of the present disclosure adds a mask process for separately preparing the first insulating layer 104. In FIG. 14 , the first insulating layer 22 has no vias at the position corresponding to the second conductive layer 23, and the first insulating layer 22 and the second conductive layer 23 are formed by sharing a mask. In FIG. 22 , the first insulating layer 104 includes a first via 105 at the position corresponding to the clock signal line 103, and the first intermediate insulating layer needs to be patterned. Therefore, a separate mask process is required to prepare the first insulating layer 104.

[0151] The left side of FIG. 23 is a top view, and the right side of FIG. 23 is a cross-sectional view taken along the FF' line of the top view. As shown in FIG. 23, a second metal layer is deposited on the side of the first insulating layer 104 away from the substrate 101, a portion of the third mask having a first size is shielded, and then photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed to pattern the second metal layer, so as to form a plurality of clock signal lines 103, a first power signal line 110, a second power signal line 111, a source and drain (not shown) and other structures on the side of the first insulating layer 104 away from the substrate 101, and at the same time, a conductive portion 106 is formed in the first via hole 105, and the initial signal line 102 is connected to the clock signal line 103 via the conductive portion 106 in the first via hole 105. The third mask can be the aforementioned mask two. In some embodiments, the material of the second metal layer includes but is not limited to molybdenum aluminum molybdenum (Mo / AL / Mo), molybdenum copper (Mo / Cu), molybdenum niobium copper (Mo / Nb / Cu), and molybdenum niobium copper molybdenum titanium (Mo / Nb / Cu / Mo / Ti).

[0152] The initial signal line 102 is connected to the clock signal line 103 through the conductive part 106 in the first via hole 105, and does not need to be connected to the clock signal line 103 by welding. In this way, the initial signal line 102 can be prevented from short-circuiting with other surrounding lines during the welding process, so that the display panel including the driving circuit structure 100 can display normally. In addition, in FIG. 23, the initial signal line 102 is connected to the clock signal line 103 by the conductive part 106 in the first via hole 105. The depth of the first via hole 105 is much smaller than the depth of the via hole 27 of the conventional array substrate 20. Therefore, in the process of etching the first intermediate insulating layer to form the first via hole 105, no chamfer is formed, thereby avoiding problems such as film breakage, abnormal connection, and electrostatic breakdown. In addition, the existence of the first via hole 105 can improve the recognition of the maintenance point, which helps to improve the efficiency and success rate of maintenance personnel. The design of the first via hole 105 enriches the product design rules and expands the utilization rate of the mask.

[0153] The left side of FIG24 is a top view, and the right side of FIG24 is a cross-sectional view taken along the GG' line of the top view. As shown in FIG24, a second intermediate insulating layer is deposited on the side of the clock signal line 103 away from the substrate 101 to block a portion of the second mask having a first size, and then photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed to form a second insulating layer 107, the second insulating layer 107 includes a plurality of vias in the display area, and includes a plurality of second vias 108 in the GOA area, and the second vias 108 expose a portion of the surface of the clock signal line 103. The first insulating layer 104 and the second insulating layer 107 are formed by sharing a second mask.

[0154] The left side of Figure 25 is a top view, and the right side of Figure 25 is a cross-sectional view taken along the AA' line of the top view. As shown in Figure 25, a third metal layer is deposited on the side of the second insulating layer 107 away from the substrate 101 to block a portion of the fourth mask having a first size, and then photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed to form pixel electrodes in the display area and protective pads 109 in the GOA area, and the protective pads 109 at least fill the second vias 108. The protective pads 109 are mainly used to prevent the corrosion of the clock signal line 103 and the conductive part 106 by water vapor in the external environment. By adding the pattern of the protective pad 109 to the aforementioned mask four, a fourth mask can be obtained.

[0155] In the preparation of an array substrate including a driving circuit structure 100, by optimizing and improving the structure of some of the mask plates in the aforementioned mask plates one, two, three, and four, for example, by adding a design pattern of a first via 105 at a position corresponding to the clock signal line 103 on the mask plate three, and adding a design pattern of a protective pad 109 on the mask plate four, the first, second, third, and fourth mask plates can be obtained. By performing shielding exposure and partial exposure on the first, second, third, and fourth mask plates having a first size, an array substrate of a second size can be prepared, thereby realizing the sharing of the mask plate. In this way, the mask plate of the first size can be used not only to prepare an array substrate of the first size, but also to prepare an array substrate of the second size, thereby improving the utilization rate of the mask plate and saving product investment costs. In some embodiments, the first size can be 65 inches, and the second size can be 58.5 inches. By shielding half of the mask plate of the first size for partial exposure, an array substrate of the second size can be obtained. The array substrate of the second size can be in a strip shape to form a strip display screen, and the strip display screen can be installed on a subway for display, for example.

[0156] Next, a method for preparing an array substrate including a driving circuit structure 200 is briefly described with reference to FIG. 9 .

[0157] Provide a substrate 101. Then, deposit a first metal layer on the substrate 101, and pattern the first metal layer by blocking a portion of a first mask having a first size to form a first routing group, a second routing group, a gate line, a gate and other structures. The first routing group includes a plurality of initial signal lines 102, and the second routing group includes a plurality of clock signal lines 103. The initial signal lines 102 and the clock signal lines 103 are arranged along a first direction and are located in the same layer, and the orthographic projection of the initial signal lines 102 on the substrate 101 and the orthographic projection of the clock signal lines 103 on the substrate 101 do not overlap. The first mask may be the aforementioned mask 1.

[0158] A first intermediate insulating layer is deposited on a side of the initial signal line 102 and the clock signal line 103 away from the substrate 101, and the first intermediate insulating layer is patterned by blocking a portion of the second mask having a first size to form a first insulating layer 104 including a plurality of first vias 105 and a plurality of groups of third vias 114, wherein the first vias 105 expose a portion of the surface of the initial signal line 102 and the clock signal line 103, and the third vias 114 expose a portion of the surface of the clock signal line 103. By adding a design pattern of the first vias 105 at a position corresponding to the clock signal line 103 on the aforementioned mask three, a second mask can be obtained.

[0159] A second metal layer is deposited on a side of the first insulating layer 104 away from the substrate 101, and the second metal layer is patterned by blocking a portion of a third mask having a first size to form at least one first connection line 112 and at least one second connection line 113 arranged along the second direction D2, a first power signal line 110, a second power signal line 111, a source and drain (not shown), and other structures. The first connection line 112 includes a first end 1121 and a second end 1122 opposite to each other, the first end 1121 of the first connection line 112 is connected to any initial signal line 102 in the first wiring group via a first via 105, the second end 1122 of the first connection line 112 is connected to any clock signal line 103 in the second wiring group via a first via 105, and each clock signal line 103 in the second wiring group is connected to a corresponding second connection line 113 via a group of third vias 114. By adding the design pattern of the first connection line 112 to the aforementioned mask plate 2, a third mask plate can be obtained.

[0160] A second intermediate insulating layer is deposited on a side of the first connection line 112 and the second connection line 113 away from the substrate 101, and the second intermediate insulating layer is patterned by covering a portion of the second mask to form a second insulating layer 107 including a plurality of second vias 108. The first insulating layer 104 and the second insulating layer 107 can be formed by sharing a second mask.

[0161] A third metal layer is deposited on a side of the second insulating layer 107 away from the substrate 101, and the third metal layer is patterned by covering a portion of the fourth mask having the first size to form a pixel electrode in the display area and a protection pad 109 in the GOA area, and the protection pad 109 at least fills the second via 108. The protection pad 109 is mainly used to prevent the corrosion of the first connection line 112, the second connection line 113 and the conductive material in the first via 105 by water vapor in the external environment. By adding the design pattern of the protection pad 109 to the aforementioned mask four, a fourth mask can be obtained.

[0162] Any clock signal line 103 in the second routing group is cut so that the clock signal line 103 has two cutting openings 115 and 116. The orthographic projection of the clock signal line 103 with two cutting openings 115 and 116 on the substrate 101 partially overlaps with the orthographic projection of the first connecting line 112 connected to the clock signal line 103 on the substrate 101, and the overlapping part is the first orthographic projection. The orthographic projection of one group of third vias 114 in the plurality of groups of third vias 114 on the substrate 101 is the second orthographic projection, and the second orthographic projection falls within the orthographic projection of the clock signal line 103 with two cutting openings 115 and 116 on the substrate 101. The first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings 115 and 116 on the substrate 101. Which clock signal line 103 is cut, that is, which clock signal line 103 is selected to transmit the STV signal on the initial signal line 102, and those clock signal lines 103 that are not cut do not transmit the STV signal. An effective transmission path for the STV signal can be formed by locating the two cutting openings 115 and 116 on the clock signal line 103 at the upper and lower sides of the first connecting line 112 and the third via 114. In this embodiment, the initial signal line 102 is connected to the clock signal line 103 by means of the first via 105 and the first connecting line 112. The clock signal line 103 only needs to be cut, and there is no need to weld the clock signal line 103 and the first connecting line 112, so that the STV signal can be transmitted by means of the clock signal line 103, which helps to improve production efficiency.

[0163] In the preparation of an array substrate including a driving circuit structure 200, by optimizing and improving the structure of some of the mask plates in the aforementioned mask plates one, two, three, and four, for example, by adding a design pattern of the first connecting line 112 on the mask plate two, adding a design pattern of the first via 105 at the position corresponding to the clock signal line 103 on the mask plate three, and adding a design pattern of the protection pad 109 on the mask plate four, the first, second, third, and fourth mask plates can be obtained. By performing shielding exposure and partial exposure on the first, second, third, and fourth mask plates having a first size, an array substrate of a second size can be prepared, thereby realizing the sharing of the mask plate. In this way, the mask plate of the first size can be used not only to prepare an array substrate of the first size, but also to prepare an array substrate of the second size, thereby improving the utilization rate of the mask plate and saving product investment costs. In some embodiments, the first size can be 65 inches, and the second size can be 58.5 inches. By shielding half of the mask plate of the first size for partial exposure, an array substrate of the second size can be obtained. The array substrate of the second size may be in a strip shape to form a strip display screen. The strip display screen may be installed on a subway for display, for example.

[0164] Next, a method for preparing an array substrate including a driving circuit structure 300 is briefly described with reference to FIG. 12 .

[0165] Provide a substrate 101. Then, deposit a first metal layer on the substrate 101, and pattern the first metal layer by blocking a portion of a first mask having a first size to form a first routing group, a second routing group, a gate line, a gate and other structures. The first routing group includes a plurality of initial signal lines 102, and the second routing group includes a plurality of clock signal lines 103. The initial signal lines 102 and the clock signal lines 103 are arranged along a first direction D1 and are located in the same layer, and the orthographic projection of the initial signal lines 102 on the substrate 101 and the orthographic projection of the clock signal lines 103 on the substrate 101 do not overlap. The first mask may be the aforementioned mask 1.

[0166] A first intermediate insulating layer and a second metal layer are sequentially deposited on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101, and the first intermediate insulating layer and the second conductive layer are patterned by blocking a portion of the second mask having a first size to form a first insulating layer 104 including a plurality of first vias 105 and a plurality of groups of third vias 114, at least one first connecting line 112 and at least one second connecting line 113 arranged along the second direction D2, a first power signal line 110, a second power signal line 111, a source and a drain (not shown), etc. It should be noted that, unlike the driving circuit structure 200, in this embodiment, the first insulating layer 104 only includes the first via 105 at the position corresponding to the initial signal line 102, but does not include the first via 105 at the position corresponding to the clock signal line 103. The first connection line 112 crosses over the multiple clock signal lines 103 in the second routing group along the second direction D2. The first connection line 112 includes a first end 1121 and a second end 1122 opposite to each other. The first end 1121 of the first connection line 112 is connected to any one of the initial signal lines 102 in the first routing group via a first via 105. The orthographic projection of the second end 1122 of the first connection line 112 on the substrate 101 falls within the orthographic projection of the clock signal line 103 farthest from the initial signal line 102 among the multiple clock signal lines of the second routing group on the substrate 101. The first connection line 112 crosses over the multiple clock signal lines, so that multiple welding points can be provided, thereby greatly increasing the selectivity of the welding position. Each clock signal line 103 in the second routing group is connected to one end of a corresponding second connection line 113 via a group of third vias 114, and the other end of the second connection line 113 is connected to the GOA unit.

[0167] In this embodiment, the first insulating layer 104 does not have an additional first via 105 at the position corresponding to the clock signal line 103, and the structure of the first insulating layer 104 is the same as the structure of the first insulating layer 22 in the related art. Therefore, in the process of preparing the driving circuit structure 300, the first insulating layer 104 can share a second mask plate with the first connecting line 112 and the second connecting line 113, and there is no need to add a separate mask process for the first insulating layer 104. By adding the design pattern of the second connecting line 112 to the aforementioned mask plate 2, a second mask plate can be obtained.

[0168] A second intermediate insulating layer is deposited on the side of the first connection line 112 and the second connection line 113 away from the substrate 101, and the second intermediate insulating layer is patterned by blocking a portion of the third mask having the first size to form a second insulating layer 107. Since the first insulating layer 104 does not have an additional first via 105 at the position corresponding to the clock signal line 103, it is not necessary to provide a protective pad to protect the metal, and further, it is not necessary to form a second via 108 for accommodating the protective pad at the position of the second insulating layer 107 corresponding to the first via 105. The third mask can be the aforementioned mask three.

[0169] A third metal layer is deposited on a side of the second insulating layer 107 away from the substrate 101, and the third metal layer is patterned by blocking a portion of the fourth mask having the first size to form a pixel electrode in the display area. As described above, since there is no need to provide a protective pad, there is no need to form a protective pad in the GOA area, and only the pixel electrode needs to be formed in the display area. The fourth mask can be the aforementioned mask four.

[0170] Any clock signal line 103 in the second routing group is cut so that the clock signal line 103 has two cutting openings 115 and 116; and the clock signal line 103 having the two cutting openings 115 and 116 is fused with the first connecting line 112 located between the two cutting openings 115 and 116 at the fusion point 117. The orthographic projection of the clock signal line 103 having the two cutting openings 115 and 116 on the substrate 101 partially overlaps with the orthographic projection of the first connecting line 112 fused with the clock signal line 103 on the substrate 101, and the overlapping part is the first orthographic projection, and the orthographic projection of one group of third vias 114 in the plurality of groups of third vias 114 on the substrate 101 is the second orthographic projection, and the second orthographic projection falls within the orthographic projection of the clock signal line 103 having the two cutting openings 115 and 116 on the substrate 101, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings 115 and 116 on the substrate 101.

[0171] Which clock signal line 103 is cut and welded, that is, which clock signal line 103 is selected to transmit the STV signal on the initial signal line 102, and those clock signal lines 103 that are not cut and welded do not transmit the STV signal. By making the two cutting openings 115 and 116 on the clock signal line 103 located on the upper and lower sides of the first connecting line 112 and the third via 114, an effective transmission path for the STV signal can be formed. In this embodiment, although the clock signal line 103 needs to be cut and welded to transmit the STV signal, the first power signal line 110 and the second power signal line 111 are designed to be away from the initial signal line 102, and the cutting openings 115, 116 and the welding area 117 of the clock signal line 103 do not overlap with the first power signal line 110 and the second power signal line 111. In this way, even if the STV signal is introduced into the GOA unit by cutting and welding the clock signal line 103 , the initial signal line 102 will not be short-circuited with the first power signal line 110 and the second power signal line 111 .

[0172] In the process flow of preparing the array substrate including the driving circuit structure 300, it is only necessary to add the design pattern of the first connecting line 112 on the mask plate 2, and it is not necessary to add the design pattern of the first via 105 on the mask plate 3 and the design pattern of the protection pad 109 on the mask plate 4, and it is not necessary to set a separate round of mask process for the first insulating layer 104. Therefore, compared with the array substrate 20 of the related art, except that the design pattern of the first connecting line 112 needs to be added on the mask plate 2, the process flow of the array substrate including the driving circuit structure 300 is basically the same as the process flow of the array substrate 20. By sharing the mask plates 1, 3, 4 and the improved mask plate 2 of the first size mentioned above, an array substrate of the second size can be prepared, thereby realizing the sharing of the mask plates. In this way, the mask plate of the first size can be used not only to prepare the array substrate of the first size, but also to prepare the array substrate of the second size, thereby improving the utilization rate of the mask plate and saving the product investment cost. In some embodiments, the first size can be 65 inches, and the second size can be 58.5 inches. By blocking half of the mask plate of the first size for partial exposure, an array substrate of the second size can be obtained. The array substrate of the second size may be in a strip shape to form a strip display screen. The strip display screen may be installed on a subway for display, for example.

[0173] It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed above may be referred to as a second element, component, region, layer or part without departing from the teaching of the present disclosure.

[0174] Spatially relative terms such as "row", "column", "below", "above", "left", "right", etc. may be used herein for ease of description to describe the relationship between one element or feature and another element or feature as illustrated in the figure. It will be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, the element described as "below other elements or features" will be oriented as "above other elements or features". Therefore, the exemplary term "below" can cover both the orientations above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used in this article are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between two layers", it can be the only layer between the two layers, or there can also be one or more intermediate layers.

[0175] The terms used herein are only for the purpose of describing a specific embodiment and are not intended to limit the present disclosure. As used herein, the singular forms "one", "one" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the presence of the features, wholes, steps, operations, elements and / or parts when used in this specification, but do not exclude the presence of one or more other features, wholes, steps, operations, elements, parts and / or their groups or add one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In the description of this specification, the description of the reference terms "one embodiment", "another embodiment" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily have to be directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Furthermore, those skilled in the art may combine different embodiments or examples and features of different embodiments or examples described in this specification without mutual contradiction.

[0176] It will be understood that when an element or layer is referred to as being "on another element or layer," "connected to another element or layer," "coupled to another element or layer," or "adjacent to another element or layer," it may be directly on another element or layer, directly connected to another element or layer, directly coupled to another element or layer, or directly adjacent to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on another element or layer," "directly connected to another element or layer," "directly coupled to another element or layer," or "directly adjacent to another element or layer," there are no intermediate elements or layers. However, in no case should "on..." or "directly on..." be interpreted as requiring that one layer completely cover the layer below.

[0177] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the zones illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the zones of the device and are not intended to limit the scope of the present disclosure.

[0178] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0179] As will be appreciated by those skilled in the art, although the various steps of the method in the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order unless the context clearly states otherwise. Additionally or alternatively, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution. In addition, other method steps may be inserted between steps. The inserted steps may represent improvements to the method as described herein, or may be unrelated to the method. In addition, a given step may not be fully completed before the next step begins.

[0180] Although the foregoing discussion contains several specific implementation details, these should not be construed as limitations on any invention or the scope of what may be claimed, but rather as descriptions of features that may be limited to specific embodiments of specific inventions. Specific features described in different embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, different features described in a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination.

[0181] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

A driving circuit structure, comprising: substrate; an initial signal line, located on the substrate; a clock signal line, located on the substrate; and a first insulating layer, which is located at a side of the initial signal line away from the substrate and includes a first via hole, wherein the initial signal line is connected to the clock signal line via the first via hole. The driving circuit structure according to claim 1, further comprising: A second insulating layer, located on a side of the first insulating layer away from the substrate and comprising a second via hole; and a protection pad filling at least the second via hole, wherein an orthographic projection of the protection pad on the substrate at least partially overlaps with an orthographic projection of the first via hole on the substrate. The driving circuit structure according to claim 1, wherein: The clock signal line is located on a side of the initial signal line away from the substrate. A conductive portion is provided in the first via hole. One end of the conductive portion is directly connected to the initial signal line, and the other end of the conductive portion is directly connected to the clock signal line. The driving circuit structure according to claim 3, wherein: The orthographic projection of the initial signal line on the substrate partially overlaps with the orthographic projection of the clock signal line on the substrate to form an overlapping area, and the orthographic projection of the first via on the substrate falls within the overlapping area. The driving circuit structure according to claim 1, wherein: The initial signal line and the clock signal line are located in the same layer, and an orthographic projection of the initial signal line on the substrate does not overlap with an orthographic projection of the clock signal line on the substrate. The driving circuit structure according to claim 5, further comprising: A first wiring group, comprising at least one initial signal line extending along a first direction; A second routing group, comprising at least one of the clock signal lines extending along the first direction, wherein an orthographic projection of the second routing group on the substrate does not overlap with an orthographic projection of the first routing group on the substrate; And at least one first connecting line extends along a second direction intersecting the first direction and is located on a side of the first insulating layer away from the substrate, wherein at least one clock signal line in the second wiring group is connected to any initial signal line in the first wiring group via the first connecting line. The driving circuit structure according to claim 6, wherein: The clock signal line includes a hollow portion and a solid portion, the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the solid portion on the substrate, and the orthographic projection of the first connecting line and the first via on the substrate does not overlap with the orthographic projection of the hollow portion on the substrate. The driving circuit structure according to claim 6, further comprising at least one second connecting line extending along the second direction, wherein Each clock signal line in the second wiring group is connected to a corresponding second connecting line, and an orthographic projection of the first connecting line on the substrate does not overlap with an orthographic projection of the second connecting line on the substrate. The driving circuit structure according to claim 8, wherein: The first insulating layer further includes a plurality of groups of third via holes, and each clock signal line in the second wiring group is connected to the corresponding second connecting line via a group of third via holes in the plurality of groups of third via holes. The driving circuit structure according to claim 9, wherein: A clock signal line in the second routing group has two cutting openings, wherein a first connecting line among the at least one first connecting line is connected to the clock signal line with two cutting openings, and the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the clock signal line with two cutting openings on the substrate, and the overlapping part is the first orthographic projection, and the orthographic projection of one group of third vias among the multiple groups of third vias on the substrate is the second orthographic projection, and the second orthographic projection falls within the orthographic projection of the clock signal line with two cutting openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings on the substrate. The driving circuit structure according to claim 10, wherein: The first connection line includes a first end and a second end opposite to each other. The first end of the first connection line is connected to any initial signal line in the first wiring group via the first via hole. The second end of the first connection line is connected to any clock signal line in the second wiring group via the first via hole. The driving circuit structure according to claim 10, wherein: The second routing group includes a plurality of clock signal lines arranged in parallel along the first direction, the first connecting line crosses the plurality of clock signal lines in the second routing group along the second direction, the first connecting line includes a first end and a second end opposite to each other, the first end of the first connecting line is connected to any one of the initial signal lines in the first routing group via the first via, and the orthographic projection of the second end of the first connecting line on the substrate falls within the orthographic projection of the clock signal line farthest from the initial signal line among the plurality of clock signal lines of the second routing group on the substrate. The driving circuit structure according to claim 12, wherein: One of the at least one first connecting line is fused to the clock signal line having two cutting openings. The driving circuit structure according to claim 13, further comprising a first power signal line and a second power signal line extending along the first direction, wherein: The first power signal line and the second power signal line are located on a side of the second routing group away from the first routing group, and the orthographic projections of the cutting opening and the fusion area of ​​the clock signal line on the substrate do not overlap with the orthographic projections of the first power signal line and the second power signal line on the substrate. The driving circuit structure according to claim 12, wherein: One of the at least one first connecting line is connected to the clock signal line having two cutting openings through the first via hole. The driving circuit structure according to any one of claims 1 to 15, wherein: The first via hole includes a first opening and a second opening opposite to each other. The first opening and the second opening are circular or elliptical in shape. The longitudinal section of the first via hole is rectangular or inverted trapezoidal, and the longitudinal section is parallel to the thickness direction of the substrate. An array substrate comprises a driving circuit structure according to any one of claims 1 to 16. The array substrate according to claim 17, further comprising: A first conductive layer, located at the same layer as the initial signal line; A second conductive layer is located on a side of the first insulating layer away from the substrate, and the first conductive layer is connected to the second conductive layer through a conductive portion in the first via hole; a second insulating layer located on a side of the second conductive layer away from the substrate and comprising a fourth via hole; and a third conductive layer located on a side of the second conductive layer away from the substrate and connected to the second conductive layer via the fourth via hole. The array substrate according to claim 18, wherein: The second insulating layer further includes a fifth via hole, the third conductive layer fills the fourth via hole and the fifth via hole, and a depth of the fifth via hole is greater than a depth of the fourth via hole. A display device comprises an array substrate according to any one of claims 17 to 19. The display device according to claim 20, wherein The display device comprises a display area and a peripheral area arranged around the display area, and the driving circuit structure is arranged in the peripheral area. A method for preparing an array substrate, comprising: Providing a substrate; forming a plurality of initial signal lines on the substrate; forming a plurality of clock signal lines on the substrate; A first insulating layer including a plurality of first via holes is formed on a side of the initial signal line away from the substrate, and the initial signal line is connected to the clock signal line via the first via holes. The method according to claim 22, wherein The initial signal line, the clock signal line, and the first insulating layer are formed respectively using different masks having a first size, so that the array substrate has a second size, the first size is larger than the second size, and the array substrate having the second size has a strip shape. The method according to claim 23, wherein A plurality of initial signal lines, a plurality of clock signal lines, and a first insulating layer are formed on the substrate, comprising: depositing a first metal layer on the substrate, and patterning the first metal layer by blocking a portion of a first mask having the first size to form the plurality of initial signal lines; depositing a first intermediate insulating layer on a side of the initial signal line away from the substrate, and patterning the first intermediate insulating layer by blocking a portion of a second mask having the first size to form the first insulating layer including a plurality of first via holes, wherein the first via holes expose a portion of the surface of the initial signal line; depositing a second metal layer on a side of the first insulating layer away from the substrate, and patterning the second metal layer by blocking a portion of a third mask having the first size. The first insulating layer is patterned to form the multiple clock signal lines on the side of the first insulating layer away from the substrate, and a conductive portion is formed in the first via, and the initial signal line is connected to the clock signal line via the conductive portion; a second intermediate insulating layer is deposited on the side of the clock signal line away from the substrate, and the second intermediate insulating layer is patterned by blocking a portion of the second mask to form a second insulating layer including a plurality of second vias, and the second vias expose a portion of the surface of the clock signal line; and a third metal layer is deposited on the side of the second insulating layer away from the substrate, and the third metal layer is patterned by blocking a portion of the fourth mask having the first size to form a protection pad, and the protection pad at least fills the second via. The method according to claim 23, wherein A plurality of initial signal lines and a plurality of clock signal lines are formed on the substrate, comprising: depositing a first metal layer on the substrate, and patterning the first metal layer by blocking a portion of a first mask having the first size to form a first routing group and a second routing group, wherein the first routing group comprises a plurality of initial signal lines arranged along a first direction, the second routing group comprises a plurality of clock signal lines arranged along the first direction, and an orthographic projection of the first routing group on the substrate and an orthographic projection of the second routing group on the substrate do not overlap. The method according to claim 25, further comprising: Depositing a first intermediate insulating layer on a side of the initial signal line and the clock signal line away from the substrate, and patterning the first intermediate insulating layer by blocking a portion of a second mask having the first size to form a first insulating layer including the plurality of first vias and a plurality of groups of third vias, wherein the first vias expose a portion of the surface of the initial signal line and the clock signal line, and the third vias expose a portion of the surface of the clock signal line; A second metal layer is deposited on a side of the first insulating layer away from the substrate, and the second metal layer is patterned by blocking a portion of a third mask having the first size to form at least one first connecting line and at least one second connecting line arranged along a second direction, wherein the first connecting line includes a first end and a second end opposite to each other, the first end of the first connecting line is connected to any one of the initial signal lines in the first routing group via the first via hole, the second end of the first connecting line is connected to any one of the clock signal lines in the second routing group via the first via hole, each clock signal line in the second routing group is connected to a corresponding one of the second connecting lines via a group of third via holes in the plurality of groups of third via holes, and the second direction intersects with the first direction; a second intermediate insulating layer is deposited on a side of the first connecting line and the second connecting line away from the substrate, and the second intermediate insulating layer is patterned by blocking a portion of the second mask to form a second insulating layer including a plurality of second via holes; A third metal layer is deposited on a side of the second insulating layer away from the substrate, and the third metal layer is patterned by blocking a portion of a fourth mask having the first size to form a protection pad, wherein the protection pad at least fills the second via; and a clock signal line in the second routing group is cut so that the clock signal line has two cutting openings, wherein the orthographic projection of a first connecting line connected to the clock signal line with two cutting openings on the substrate partially overlaps with the orthographic projection of the clock signal line with two cutting openings on the substrate, and the overlapping portion is the first orthographic projection, and the orthographic projection of a group of third vias in the multiple groups of third vias on the substrate is the second orthographic projection, and the second orthographic projection falls within the orthographic projection of the clock signal line with two cutting openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings on the substrate. The method according to claim 25, further comprising: A first intermediate insulating layer and a second metal layer are sequentially deposited on a side of the initial signal line and the clock signal line away from the substrate, and the first intermediate insulating layer and the second metal layer are patterned by blocking a portion of a second mask having the first size to form a first insulating layer including the plurality of first vias and the plurality of groups of third vias, and at least one first connecting line and at least one second connecting line arranged along a second direction, wherein the first via exposes a portion of the surface of the initial signal line, the third via exposes a portion of the surface of the clock signal line, the first connecting line crosses the plurality of clock signal lines in the second routing group along the second direction, the first connecting line includes a first end and a second end opposite to each other, the first end of the first connecting line is connected to any one of the initial signal lines in the first routing group via the first via, the orthographic projection of the second end of the first connecting line on the substrate falls within the orthographic projection of the clock signal line farthest from the initial signal line among the plurality of clock signal lines in the second routing group on the substrate, and each clock signal line in the second routing group is connected to a corresponding clock signal line via a group of third vias in the plurality of groups of third vias. The second connecting line is connected, and the second direction intersects with the first direction; a second intermediate insulating layer is deposited on the side of the first connecting line and the second connecting line away from the substrate, and the second intermediate insulating layer is composed by blocking a part of the third mask plate with the first size to form a second insulating layer; a third metal layer is deposited on the side of the second insulating layer away from the substrate, and the third metal layer is composed by blocking a part of the fourth mask plate with the first size to form a pixel electrode; a clock signal line in the second wiring group is cut so that the clock signal line has two cutting openings; and the clock signal line with the two cutting openings is welded with the first connecting line located between the two cutting openings in a welding area, wherein the orthographic projection of the welding area on the substrate is a first orthographic projection, and the orthographic projection of a group of the third vias in the multiple groups of third vias on the substrate is a second orthographic projection, and the second orthographic projection falls within the orthographic projection of the clock signal line with the two cutting openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings on the substrate.

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