Display driving method, display driving device and display equipment

Abstract

A display driving device (200, 920), a display driving method and a display device (900) relate to the technical field of display. The display driving device (200, 920) comprises: a display driving chip (210) comprising: a first register (212); a plurality of pins (211); the processing circuit (213) is configured to write duration of a first level of a gate trigger signal corresponding to the display mode information into the first register (212), and at the end moment of the first level, the gate trigger signal jumps from the first level to a second level; generating a gate trigger signal based on the duration stored by the first register (212); acquiring a reference voltage corresponding to the duration; and outputting a gate trigger signal and a reference voltage through the plurality of pins (211).

Description

Display driving method, display driving device and display equipment Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display driving method, a display driving apparatus, and a display device. Background Art

[0002] A display device (such as an OLED display) may include a display panel, a gate driver, and a display driver chip. The display panel includes a pixel circuit composed of multiple pixels. The display driver chip inputs a trigger signal to the gate driver circuit, which in turn generates a drive signal that is supplied to the pixel circuit.

[0003] During the process of driving the pixel circuit, the threshold voltage drift of the driving transistor in the pixel circuit may cause a display afterimage, thereby affecting the display effect of the display panel.

[0004] Summary of the Invention

[0005] The present disclosure provides a display driving method, a display driving apparatus, and a display device.

[0006] According to a first aspect, the present disclosure provides a display driver device, comprising: a display driver chip, comprising: a first register; a plurality of pins; and a processing circuit, configured to write the duration of a first level of a gate trigger signal corresponding to display mode information into the first register, wherein at the end moment of the first level, the gate trigger signal jumps from the first level to the second level; based on the duration stored in the first register, a gate trigger signal is generated; a reference voltage corresponding to the duration is obtained; and the gate trigger signal and the reference voltage are output through the plurality of pins.

[0007] For example, the processing circuit is also configured to: receive a display mode switching request through multiple pins, the switching request including a target display mode; read the current duration of the first level of the gate trigger signal from the first register; when it is determined that the target duration corresponding to the target display mode is inconsistent with the current duration, write the target duration into the first register; and generate a gate trigger signal based on the target duration stored in the first register.

[0008] For example, the processing circuit is also configured to: receive a display mode switching request through multiple pins, the switching request including a target display mode; read the current duration of the first level of the gate trigger signal from the first register; and generate a gate trigger signal based on the current duration stored in the first register when it is determined that the target duration corresponding to the target display mode is consistent with the current duration.

[0009] For example, the display driver chip also includes: a second register configured to store a second duration; wherein the first register is also configured to store a first duration, and the first duration is less than the second duration; and the processing circuit is further configured to: receive a display mode switching request through multiple pins, the switching request including a target display mode; when it is determined that the target display mode is a highlight mode, generate a gate trigger signal based on the first duration stored in the first register; and when it is determined that the target display mode is a constant display mode, generate a gate trigger signal based on the second duration stored in the second register.

[0010] For example, the display driver chip further includes: a first storage unit configured to store a reference voltage; wherein the processing circuit is further configured to read the reference voltage corresponding to the duration from the first storage unit.

[0011] For example, the display driving device further includes: a second storage unit configured to store a reference voltage; wherein the processing circuit is further configured to read the reference voltage corresponding to the duration from the second storage unit.

[0012] For example, the second storage unit is further configured to store the duration of the first level of the gate trigger signal corresponding to the display mode information; and the processing circuit is further configured to read the duration from the second storage unit and write the duration into the first register.

[0013] For example, the duration is greater than or equal to the reference time difference; wherein, in I scanning cycles, the time difference between the starting time of the first level of the clock signal in the first scanning cycle and the ending time of the first level of the clock signal in the I scanning cycle is the reference time difference, and I is an integer greater than 1.

[0014] For example, the processing circuit is further configured to: write a first duration into the first register when determining that the display mode information is a highlight mode; and write a second duration into the first register when determining that the display mode information is a constant display mode; wherein the second duration is greater than the first duration.

[0015] For example, the processing circuit is further configured to: when it is determined that the display mode information is the standard mode, write the first duration into the first register.

[0016] For example, the first duration is greater than or equal to the first reference time difference, and the second duration is greater than or equal to the second reference time difference; wherein, within M scanning cycles, the time difference between the starting moment of the first level of the clock signal in the first scanning cycle and the ending moment of the first level of the clock signal in the Mth scanning cycle is the first reference time difference; within N scanning cycles, the time difference between the starting moment of the first level of the clock signal in the first scanning cycle and the ending moment of the first level of the clock signal in the Nth scanning cycle is the second reference time difference, wherein M<N, and M and N are both integers greater than 1.

[0017] According to a second aspect, the present disclosure provides a display driving method for driving a pixel circuit, including: setting the duration of a first level of a gate trigger signal according to display mode information, wherein at the end moment of the first level, the gate trigger signal jumps from the first level to the second level; obtaining a reference voltage corresponding to the duration; and driving the pixel circuit through the gate trigger signal and the reference voltage.

[0018] For example, the duration is greater than or equal to the reference time difference; wherein, in I scanning cycles, the time difference between the starting time of the first level of the clock signal in the first scanning cycle and the ending time of the first level of the clock signal in the I scanning cycle is the reference time difference, and I is an integer greater than 1.

[0019] For example, the display mode information includes a highlight mode and a constant display mode, and the duration includes a first duration and a second duration; according to the display mode information, setting the duration of the first level of the gate trigger signal includes: when it is determined that the display mode information is a highlight mode, setting the duration to the first duration; and when it is determined that the display mode information is a constant display mode, setting the duration to the second duration; wherein the second duration is greater than the first duration.

[0020] For example, the display mode information also includes a standard mode; according to the display mode information, setting the duration of the first level of the gate trigger signal further includes: when it is determined that the display mode information is the standard mode, setting the duration to the first duration.

[0021] For example, the first duration is greater than or equal to the first reference time difference, and the second duration is greater than or equal to the second reference time difference; wherein, within M scanning cycles, the time difference between the starting moment of the first level of the clock signal in the first scanning cycle and the ending moment of the first level of the clock signal in the Mth scanning cycle is the first reference time difference; within N scanning cycles, the time difference between the starting moment of the first level of the clock signal in the first scanning cycle and the ending moment of the first level of the clock signal in the Nth scanning cycle is the second reference time difference, wherein M<N, and M and N are both integers greater than 1.

[0022] For example, according to the display mode information, setting the duration of the first level of the gate trigger signal includes: in response to a received display mode switching request, obtaining the current duration of the first level of the gate trigger signal and the target display mode included in the switching request; and when it is determined that the target duration corresponding to the target display mode is inconsistent with the current duration, modifying the current duration to the target duration.

[0023] For example, according to the display mode information, setting the duration of the first level of the gate trigger signal includes: in response to a received display mode switching request, obtaining the current duration of the first level of the gate trigger signal and the target display mode included in the switching request; and maintaining the current duration when it is determined that the target duration corresponding to the target display mode is consistent with the current duration.

[0024] For example, driving the pixel circuit by the gate trigger signal and the reference voltage includes: generating a gate drive signal according to the gate trigger signal; generating a drive voltage according to the reference voltage; and driving the pixel circuit by the gate drive signal and the drive voltage.

[0025] For example, the duration is greater than or equal to the gate time difference; wherein, in I scanning cycles, the time difference between the starting time of the first level of the gate drive signal in the first scanning cycle and the ending time of the first level of the gate drive signal in the I scanning cycle is the gate time difference.

[0026] According to a third aspect, the present disclosure provides a display device, including: a display panel; and a display driving apparatus provided by an embodiment of the present disclosure, configured to drive the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1A is a schematic structural diagram of an exemplary pixel circuit;

[0028] FIG1B is a signal timing diagram of the pixel circuit in FIG1A ;

[0029] FIG2 is a schematic structural diagram of a display driving device according to an embodiment of the present disclosure;

[0030] FIG3 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0031] FIG4A is a signal timing diagram according to one embodiment of the present disclosure;

[0032] FIG4B is a signal timing diagram according to another embodiment of the present disclosure;

[0033] FIG4C is a signal timing diagram according to another embodiment of the present disclosure;

[0034] FIG5 is a signal timing diagram according to another embodiment of the present disclosure;

[0035] FIG6 is a schematic structural diagram of a display driving device according to another embodiment of the present disclosure;

[0036] 7 is a schematic structural diagram of a display driving device according to another embodiment of the present disclosure;

[0037] FIG8 is a schematic structural diagram of a display driving device according to another embodiment of the present disclosure;

[0038] FIG9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure; and

[0039] FIG10 is a flowchart of a display driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0041] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure shall have the same general meaning as those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components.

[0042] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may refer to a direct connection between two components or a connection between two components via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0043] It should be noted that in the description of the embodiments of the present disclosure, the symbol Vdata can represent both a data signal and the level of the data signal. Similarly, the symbol Gate can represent both a gate drive signal and the level of the gate drive signal. The symbol VINT can represent both a predetermined initial voltage terminal and the voltage of the initial signal. The symbol ELVDD can represent both a power supply and the power supply voltage provided by the power supply. The following embodiments are the same and will not be repeated here.

[0044] Active Matrix Organic Light Emitting Diode (AMOLED) display panels can provide more vivid and high-contrast images, so wearable electronic products use flexible AMOLED display panels. The pixel unit of the pixel circuit of an AMOLED display panel can be a 7T1C structure, that is, each pixel unit consists of seven thin-film transistors (TFTs) and one capacitor (C), as shown in Figure 1.

[0045] Figure 1A is a schematic structural diagram of an exemplary pixel circuit. Figure 1B is a signal timing diagram of the pixel circuit in Figure 1A.

[0046] In the example of FIG. 1A , transistors T1 to T7 may be P-type transistors.

[0047] In the example of FIG1B , in the initialization phase P1 , the reset signal Reset is at a low level. In the data writing phase P2 , the gate drive signal Gate is at a low level. In the light emitting phase, the light emitting control signal EM is at a low level.

[0048] During the initialization phase P1, transistor T1 is turned on by the low level of the reset signal Reset. The initialization signal VINT initializes the gate voltage of the driving transistor T3 to VINT, and simultaneously charges the storage capacitor CST. At this point, the voltage at point N1 is VINT.

[0049] Under the control of the low level of the reset signal Reset, the transistor T7 is turned on, and the initialization signal VINT is written to the anode of the light-emitting element OLED along the initialization path from the predetermined initial voltage terminal to the light-emitting element OLED, thereby initializing the anode voltage of the light-emitting element OLED to VINT. This can release the residual charge on the anode of the light-emitting element OLED, thereby eliminating the residual voltage on the anode of the light-emitting element OLED.

[0050] In the data writing phase P2, under the low level control of the gate drive signal Gate, transistors T2 and T4 are turned on. The driving transistor T3 is turned on by the voltage signal stored in the storage capacitor CST. The data signal Vdata is written to the node N1 along the data signal terminal through the transistors T4, T3 and T2. At this time, the data signal Vdata can charge the storage capacitor CST, and the driving transistor T3 is gradually turned off. When Vgs = Vg-Vs = Vg-Vdata ≥ Vth is satisfied, the driving transistor T3 is turned off, and the charging of the storage capacitor CST is completed. At this time, the potential at point N1 is Vg = Vth + Vdata.

[0051] It can be understood that Vth is the threshold voltage of the driving transistor T3, Vgs is the gate-source voltage of the driving transistor T3, Vg is the gate voltage of the driving transistor T3, and Vs is the source voltage of the driving transistor T3. The voltage difference (VINT-ELVSS) between the initial signal terminal VINT and the second power supply terminal ELVSS should be less than the threshold voltage Vth of the light-emitting element OLED, thereby ensuring that the light-emitting element OLED does not emit light during the data writing phase.

[0052] In the light-emitting phase P3, under the low-level control of the light-emitting control signal EM, transistors T5 and T6 are turned on. At this time, the source potential Vs of the driving transistor T3 is Vdd, the gate potential Vg is Vth+Vdata, Vgs is Vth+Vdata-Vdd<Vth, and the driving transistor T3 is turned on by the voltage signal stored in the storage capacitor CST. Transistors T5 and T6 are turned on, the voltage of the first power supply terminal ELVDD is written into the circuit, and the driving current is applied to the light-emitting element OLED along the light-emitting path from the power supply to the light-emitting element OLED through the transistor T5, the driving transistor T3 and the transistor T6, so that the light-emitting element OLED emits light. At this time, the current flowing through the pixel Id is A(Vdd-Vdata) 2 , where A is a constant. The 7T1C circuit can eliminate the Vth difference between different pixel units, making the brightness uniformity of the display panel better.

[0053] During initialization of the anode of the light-emitting element OLED, the voltage at the second power supply terminal ELVSS may cause incomplete initialization of the anode of the light-emitting element OLED, resulting in abnormal display brightness of the light-emitting element OLED and affecting the image display. In addition, the long-term application of voltage to the gate of the driving transistor T3 may cause the threshold voltage of the driving transistor T3 to drift, which may cause display afterimages.

[0054] To address the issue of image retention on a display screen, the present disclosure provides a display driver device comprising a display driver chip. The display driver chip includes a first register; multiple pins; and a processing circuit configured to write the duration of a first level of a gate trigger signal corresponding to display mode information into the first register; generate a gate trigger signal based on the duration stored in the first register; obtain a reference voltage corresponding to the duration; and output the gate trigger signal and the reference voltage via the multiple pins.

[0055] FIG2 is a schematic structural diagram of a display driving device according to an embodiment of the present disclosure.

[0056] As shown in FIG. 2 , the display driving device 200 may include a display driving chip 210 .

[0057] In the embodiment of the present disclosure, the display driver chip 210 includes a plurality of pins 211, a first register 212, and a processing circuit 213. For example, the display driver chip 210 may be a drive integrated circuit (DIC).

[0058] In the embodiment of the present disclosure, the processing circuit 213 writes the duration of the first level of the gate trigger signal corresponding to the display mode information into the first register 212, and generates a gate trigger signal based on the duration stored in the first register 212. The processing circuit 213 obtains a reference voltage corresponding to the duration and outputs the gate trigger signal and the reference voltage through the plurality of pins 211.

[0059] For example, the gate trigger signal and the reference voltage output by the processing circuit 213 may drive a pixel circuit in a display panel.

[0060] For example, at the end of the first level, the gate trigger signal jumps from the first level to the second level. For example, the first level can be greater than the second level, the first level is a high level, and the second level is a low level. For example, the first level can also be less than the second level, for example, the first level is a low level, and the second level is a high level.

[0061] For example, when the low level of the reset signal Reset is used as the effective level for turning on the transistor of the pixel unit, the first level may be a low level and the second level may be a high level. When the high level of the reset signal Reset is used as the effective level for turning on the transistor of the pixel unit, the first level may be a high level and the second level may be a low level.

[0062] For example, the display mode information is the display mode of the display panel. For example, the display mode information may include a normal mode, a High Brightness Monitor (HBM) mode, and an Always On Display (AOD) mode.

[0063] During the use of the display panel, standard mode and HBM mode can be used to display complex pictures. For example, when the user browses information through the display panel, the display panel can be set to standard mode or HBM mode. When the display panel is in standby mode, AOD mode can be used to display simple pictures. For example, when the user is not using the display panel, the display panel can only display a simple wallpaper picture or a static picture. For example, the display panel can only display a clock picture, and the background of the clock picture can be a solid color background. For example, a digital dial or an analog dial is displayed on a solid color background.

[0064] For example, the processing circuit 213 can control the array substrate row driver (GOA) circuit to generate a gate drive signal Gate and a reset signal Reset through the gate trigger signal. Based on the gate drive signal Gate and the reset signal Reset, the conductive state of the transistors in each row of pixel units is controlled, thereby driving the light-emitting elements in the pixel circuit to emit light. For example, the processing circuit 213 outputs the gate trigger signal to the GOA circuit, and the GOA circuit receives the gate trigger signal and outputs the gate drive signal Gate and the reset signal Reset.

[0065] By setting the duration of the first level of the gate trigger signal, the duration of the first level of the gate drive circuit Gate and the reset signal Reset output by the GOA circuit can be controlled, thereby controlling the initialization time of the anode of the light-emitting element OLED and the time of applying voltage to the gate of the driving transistor, thereby improving the initialization state of the light-emitting element and the voltage application time to the gate of the driving transistor.

[0066] For example, since the standard mode and HBM mode are used to display complex images, and the AOD mode is used to display simple images, different types of display images need to be adapted to different display brightnesses. Therefore, the processing circuit 213 needs to adapt the corresponding display brightness for multiple display modes to display corresponding types of images.

[0067] For example, the reference voltage may be a gamma voltage. Gamma tuning can be used to obtain gamma voltages corresponding to a plurality of durations in advance, thereby determining the corresponding relationship among the display mode, duration, and gamma voltage.

[0068] The reference voltage may include a gamma upper limit voltage and a gamma lower limit voltage. The source driver circuit may convert received image data into a data signal Vdata based on the gamma upper limit voltage and the gamma lower limit voltage. By setting the gamma voltage corresponding to the duration, a data voltage Vdata corresponding to the gate drive signal Gate and the reset signal Reset may be obtained. Thus, driven by the gate drive signal Gate, the reset signal Reset, and the data signal Vdata, the display screen in different display modes has good display brightness and accurately displays the image to the user.

[0069] For example, the display panel includes a pixel circuit. By setting the gate trigger signal and the reference voltage according to the display mode information by the processing circuit 213 according to the disclosed embodiment, the gate drive signal Gate, the reset signal Reset and the data signal Vdata matching the display mode can be input to the pixel circuit, thereby improving the display afterimage that appears on the display panel under different display modes.

[0070] In the disclosed embodiment, the processing circuit 213 can control the GOA circuit to generate a gate drive signal based on the gate trigger signal. The processing circuit 213 can also control the source drive circuit to generate a drive voltage based on the reference voltage. In this case, the light-emitting element of the pixel circuit can emit light under the gate drive signal and the drive voltage.

[0071] For example, the driving voltage may be a voltage value of a first level of the data signal. The source driving circuit may output the data signal Vdata based on the reference voltage.

[0072] For example, the GOA circuit can output a gate drive signal, Gate, and a reset signal, Reset, based on a gate trigger signal and a clock signal. The timing of the gate drive circuit, Gate, and the reset signal, Reset, is related to the timing of the clock signal, and the level variation pattern of the gate drive signal, Gate, and the reset signal, Reset, is consistent with the level variation pattern of the clock signal.

[0073] The process of driving the display panel is described with reference to FIG. 3 and FIG. 4A to FIG. 4C .

[0074] FIG3 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0075] As shown in FIG3 , the display device 300 includes a pixel unit 310, a gate driving circuit 320, and a display driving chip 330. The pixel unit 310 includes a plurality of pixel units 311 arranged in an array. The circuit structure of each pixel unit 311 may be as shown in FIG1 .

[0076] The display driver chip 330 outputs a gate trigger signal and a clock signal to the gate driver circuit 320. The gate driver circuit 320 is a GOA circuit, which generates a gate driver signal Gate and a reset signal Reset according to the gate trigger signal and the clock signal.

[0077] The gate driving circuit 320 can use the gate driving signal Gate and the reset signal Reset to scan the pixel circuit 310 row by row. For example, the gate driving circuit 320 can use the gate driving signal Gate1 and the reset signal Reset1 to scan the plurality of pixel units in the first row horizontally along the direction from X to X'.

[0078] The gate drive circuit 320 also cooperates with the clock signal to trigger the scanning of the next row of pixel units. For example, the gate drive circuit 320 can use the gate drive signal Gate2 and the reset signal Reset2 to perform horizontal scanning on multiple pixel units in the second row of pixel units along the Y to Y' direction, and use the gate drive signal Gate3 and the reset signal Reset3 to perform horizontal scanning on multiple pixel units in the third row of pixel units, thereby completing the scanning of each row of pixel units in the pixel circuit 310.

[0079] 4A to 4C illustrate timing diagrams of input signals and output signals of the gate driving circuit 320 in FIG. 3 .

[0080] For example, the input signals of the GOA circuit include a gate trigger signal GSTV, a first clock signal GCK, and a second clock signal GCB. The output signals of the GOA circuit include multiple output signals Gout. For example, in the case where the pixel unit 310 shown in FIG3 includes n rows of pixel units, the GOA circuit includes n rows of GOA units, and the n rows of GOA units can output n output signals Gout.

[0081] As shown in Figures 4A to 4C, the output signals Gout1, Gout2, and Gout3 may be signals input to the first three rows of pixel units of the pixel unit 310. For example, the output signal Gout1 is the gate drive signal Gate1 and the reset signal Reset1 input to the first row of pixel units of the pixel circuit 310 shown in Figure 3. The output signal Gout2 is the gate drive signal Gate2 and the reset signal Reset2 input to the second row of pixel units of the pixel circuit 310 shown in Figure 3. The output signal Gout3 is the gate drive signal Gate3 and the reset signal Reset3 input to the third row of pixel units of the pixel circuit 310 shown in Figure 3.

[0082] The first level of the first clock signal GCK has the same width as the first level of the second clock signal GCB. For example, the low level of the first clock signal GCK or the second clock signal GCB can be used as the effective level for turning on the transistor. The low levels of the first clock signal GCK and the second clock signal GCB appear alternately.

[0083] For example, the sum of the durations of a high level and a low level of the first clock signal GCK is a scan cycle. The width of the low level of the output signals Gout1, Gout2 and Gout3 is consistent with the width of the low level of the first clock signal GCK in each scan cycle. That is, the duration L of the low level of the first clock signal GCK is C The duration L of the low level of the output signals Gout1, Gout2 and Gout3 is G1 , L G2 and L G3 All are equal.

[0084] FIG4A is a signal timing diagram according to one embodiment of the present disclosure.

[0085] As shown in FIG4A , the start time of the low level of the gate trigger signal GSTV is close to the start time of the low level of the first clock signal GCK. For example, the start time of the low level of the gate trigger signal GSTV may be slightly earlier than the start time of the low level of the first clock signal GCK. From the start time of the low level of the gate trigger signal GSTV to the end time of the low level of the gate trigger signal GSTV, a low level appears once in the timing of the first clock signal GCK. When the timing of the first clock signal GCK satisfies the above conditions, for each frame of data displayed on the display screen, a low level only appears once in the timing of the output signals Gout1, Gout2, and Gout3 of the corresponding row of pixel units. For example, when the transistors in the pixel units are P-type transistors, the low levels of the output signals Gout1, Gout2, and Gout3 can be used as the effective levels for turning on the transistors in the pixel units. The times at which the first levels of the output signals Gout1, Gout2, and Gout3 appear are shifted sequentially.

[0086] Based on the timing variation of the first clock signal GCK and the second clock signal GCB and the number of pixel rows, the starting times of the first levels of the output signals Gout1, Gout2, and Gout3 are shifted row by row in timing. For example, the ending time of the first level of the output signal Gout1 is the starting time of the first level of the output signal Gout2, and the ending time of the first level of the output signal Gout2 is the starting time of the first level of the output signal Gout3.

[0087] For example, the time period during which both the first clock signal GCK and the gate trigger signal GSTV are at a low level is defined as the first low-level period of the first clock signal GCK. After the first low-level period of the first clock signal GCK lasts for time Lc (the level changes to a high level), the level of the output signal Gout1 for scanning the first row of pixel cells changes to a low level. After the low level of the output signal Gout1 lasts for LG1, the level changes to a high level, completing the scanning of the first row of pixel cells using the first frame data. After the low level of the output signal Gout1 changes to a high level, the level of the output signal Gout2 for scanning the second row of pixel cells changes to a low level. After the low level of the output signal Gout2 lasts for LG2, the level changes to a high level, completing the scanning of the second row of pixel cells using the first frame data. After the low level of the output signal Gout2 changes to a high level, the level of the output signal Gout3 for scanning the third row of pixel cells changes to a low level. After the low level of the output signal Gout3 lasts for LG3, the level changes to a high level, completing the scanning of the third row of pixel cells using the first frame data.

[0088] For example, the duration L of the low level of the gate trigger signal GSTV is from the start time of the low level of the gate trigger signal GSTV to the end time of the low level of the gate trigger signal GSTV. GS The duration of the low level of the gate trigger signal GSTV is L GS Slightly longer than the duration L of the low level of the first clock signal GCK C .

[0089] The timing changes of the output signal Gout shown in FIG4A correspond to the gate drive signal Gate and the reset signal Reset shown in FIG1B . Based on the gate trigger signal GSTV shown in FIG4A , the gate drive signal Gate and the reset signal Reset output by the GOA circuit can respectively initialize the gate of the driving transistor and the anode of the light-emitting element once before the light-emitting element emits light.

[0090] In the embodiment of the present disclosure, from the starting moment of the low level of the gate trigger signal GSTV to the ending moment of the low level of the gate trigger signal GSTV, a low level appears once in the timing of the first clock signal GCK. Correspondingly, for the display of one frame of data on the display screen, only one low level appears in the timing of the output signals Gout1, Gout2 and Gout3 of each row of pixel units, and the low level can be used as the effective level for the transistor to be turned on in the pixel unit. Therefore, when the timing of the first clock signal GCK satisfies this condition, one scanning cycle of the first clock signal GCK can be considered as (the sum of the duration of an adjacent high level and a low level) a reference scanning cycle TREF (as shown in FIG4A ). It can be understood that, for the display of one frame of data on the display screen, in one reference scanning cycle, the gate drive signal Gate and the reset signal Reset each have a first level applied to a row of pixel units. At this time, the duration L of the low level of the gate trigger signal GSTV is GS Can be recorded as 1GSTV.

[0091] Optionally, when the high level of the output signals Gout1, Gout2, and Gout3 is used as the first level for turning on the transistor in the pixel unit, the high level appears once in the timing sequence of the first clock signal GCK from the start time of the high level of the gate trigger signal GSTV to the end time of the high level of the gate trigger signal GSTV. Accordingly, for displaying one frame of data on the display screen, the high level also appears only once in the timing sequence of the output signals Gout1, Gout2, and Gout3 when scanning a row of pixel units. The duration L of the high level of the gate trigger signal GSTV is GS Can be recorded as 1GSTV.

[0092] FIG4B is a signal timing diagram according to another embodiment of the present disclosure.

[0093] As shown in Figure 4B, the start time of the first level of the gate trigger signal GSTV is close to the start time of the first level of the first clock signal GCK. From the start time of the low level of the gate trigger signal GSTV to the end time of the low level of the gate trigger signal GSTV, the first clock signal GCK has two low levels in its timing sequence. When the timing of the first clock signal GCK satisfies the above conditions, for the display of a frame of data on the display screen, the output signals Gout1, Gout2, and Gout3 corresponding to a row of pixel units also have two low levels in their timing sequence. The low level of the output signal can be used as the effective level for turning on the transistors in the pixel units. The start time of the first level of the output signals Gout1, Gout2, and Gout3 is also shifted row by row in timing sequence. For example, the end time of the first first level of the output signal Gout1 is the start time of the first first level of the output signal Gout2, and the end time of the first first level of the output signal Gout2 is the start time of the first first level of the output signal Gout3.

[0094] For example, the duration L of the low level of the gate trigger signal GSTV is GS Slightly longer than the time from the start time of the first low level of the first clock signal GCK to the end time of the second low level.

[0095] Understandably, based on the gate trigger signal GSTV shown in FIG4B , the gate drive signal Gate and the reset signal Reset output by the GOA circuit, the gate of the driving transistor and the anode of the light emitting element can be initialized twice respectively before the light emitting element emits light.

[0096] In this case, for the display of one frame of data on the display screen, in two reference scanning cycles, the gate drive signal Gate and the reset signal Reset are respectively applied to a row of pixel units for two low levels. At this time, the duration L of the low level of the gate trigger signal GSTV is GS Can be recorded as 2GSTV.

[0097] FIG4C is a signal timing diagram according to another embodiment of the present disclosure.

[0098] As shown in Figure 4C, the starting time of the low level of the gate trigger signal GSTV is close to the starting time of the low level of the first clock signal GCK. From the starting time of the low level of the gate trigger signal GSTV to the ending time of the low level of the gate trigger signal GSTV, the low level appears three times in the timing of the first clock signal GCK. When the timing of the first clock signal GCK satisfies the above conditions, for the display of a frame of data on the display screen, the timing of the output signals Gout1, Gout2, and Gout3 corresponding to a row of pixel units also appears three times in the timing. The starting time of the first level of the output signals Gout1, Gout2, and Gout3 is also shifted row by row in timing. For example, the ending time of the first first level of the output signal Gout1 is the starting time of the first first level of the output signal Gout2, and the ending time of the first first level of the output signal Gout2 is the starting time of the first first level of the output signal Gout3.

[0099] For example, the duration LGS of the low level of the gate trigger signal GSTV is slightly longer than the time from the start time of the first low level to the end time of the third low level of the first clock signal GCK.

[0100] Understandably, based on the gate trigger signal GSTV shown in FIG4C , the gate drive signal Gate and the reset signal Reset output by the GOA circuit, the gate of the driving transistor and the anode of the light emitting element can be initialized three times respectively before the light emitting element emits light.

[0101] In this case, for the display of one frame of data on the display screen, in three reference scanning cycles, the gate drive signal Gate and the reset signal Reset are respectively applied to a row of pixel units with three low levels. At this time, the duration L of the low level of the gate trigger signal GSTV is GS It can be recorded as 3GSTV.

[0102] 5, the duration L of the low level of the gate trigger signal GSTV GS The timing of the output signal Gout in the case of 3GSTV will be described.

[0103] FIG5 is a signal timing diagram according to another embodiment of the present disclosure, and FIG5 shows the timing changes of signals applied to a row of pixel units in a pixel circuit.

[0104] 5 , in phases T1_1, T1_2, and T1_3, the low level of the reset signal Reset serves as the effective level for turning on the transistor of the pixel unit. In phases T2_1, T2_2, and T2_3, the low level of the gate drive signal Gate serves as the effective level for turning on the transistor of the pixel unit.

[0105] For example, the operation process of the pixel unit in phases T1_1, T1_2, and T1_3 is similar to the initialization phase P1 shown in Figures 1A and 1B. The operation process of the pixel unit in phases T2_1, T2_2, and T2_3 is similar to the data writing phase P1 shown in Figures 1A and 1B. The operation process of the pixel unit in phase T3 is similar to the light-emitting phase P3 shown in Figures 1A and 1B.

[0106] In the timing variation shown in FIG5 , the initialization phase and the data writing phase appear three times alternately before the light emitting phase. GS In the case of 3GSTV, based on the gate drive signal Gate and the reset signal Reset, the gate of the driving transistor in the pixel unit can be reset twice (T2_1 and T2_2 are used for resetting, and T2_3 is used for data writing), and the anode of the light-emitting element can be initialized three times. This can fully release the residual charge in the anode of the light-emitting element and reduce the possibility of drift in the driving transistor, thereby improving the afterimage display phenomenon of the display panel.

[0107] Through the embodiments of the present disclosure, when the low level of the output signal Gout is used as the effective level for turning on the transistor of the pixel unit, by setting the duration of the low level of the gate trigger signal GSTV to 2GSTV or 3GSTV, the gate of the driving transistor in the pixel unit can be reset multiple times and the anode of the light-emitting element can be initialized multiple times by using the gate drive signal Gate and the reset signal Reset in multiple reference scan cycles before the light-emitting stage, thereby improving the afterimage display phenomenon of the display panel.

[0108] In some embodiments, the duration of the first level of the gate trigger signal GSTV is greater than or equal to a reference time difference. In one scanning cycle, the time difference between the start time of the first level of the clock signal in the first scanning cycle and the end time of the first level of the clock signal in the first scanning cycle is the reference time difference, where I is an integer greater than 1.

[0109] For example, when the first level of the clock signal ends, the level of the clock signal jumps from the first level to the second level.

[0110] When the low level of the output signal Gout is used as the effective level for turning on the transistor of the pixel unit, the first level may be a low level and the second level may be a high level. When the high level of the output signal Gout is used as the effective level for turning on the transistor of the pixel unit, the first level may be a high level and the second level may be a low level.

[0111] For example, the scan cycle is a reference scan cycle. Within multiple reference scan cycles, the time difference between the start time of the first level of the clock signal in the first reference scan cycle and the end time of the first level of the clock signal in the last reference scan cycle is the reference time difference. Therefore, from the start time to the end time of the first level of the gate trigger signal GSTV, the clock signal reaches the first level at least twice. For example, Figures 4B and 4C illustrate the timing of the gate trigger signal GSTV, the first clock signal GCK, and the output signal Gout.

[0112] For example, 1 can be 2, 3, 4, and 5. For example, the duration of the first level of the gate trigger signal GSTV can be 2GSTV, 3GSTV, 4GSTV, and 5GSTV. From the start time to the end time of the first level of the gate trigger signal GSTV, the clock signal can appear at the first level twice, three times, four times, or five times.

[0113] Accordingly, the duration of the first level of the gate trigger signal GSTV is greater than or equal to the gate time difference. In one scanning cycle, the time difference between the start time of the first level of the gate drive signal in the first scanning cycle and the end time of the first level of the gate drive signal in the first scanning cycle is the gate time difference.

[0114] For example, in multiple reference scanning cycles, the time difference between the start time of the first level of the clock signal in the first reference scanning cycle and the end time of the first level of the clock signal in the last reference scanning cycle is the reference time difference. Therefore, to display one frame of data on the display screen, the gate drive signal scanning a row of pixel units appears at least twice at the first level. For example, Figures 4B and 4C show the timing of the gate trigger signal GSTV, the first clock signal GCK, and the output signal Gout.

[0115] Because the duration of the first level of the gate trigger signal GSTV is set to be greater than or equal to the reference time difference, the gate drive signal Gate output by the GOA circuit based on the gate trigger signal GSTV can reset the gate of the drive transistor at least once (using the last first level of the gate drive signal Gate to write data), thereby alleviating the drift phenomenon of the drive transistor. The reset signal Reset output by the GOA circuit based on the gate trigger signal GSTV can initialize each row of pixel units at least twice, fully initializing the anodes of the light-emitting elements, allowing the residual charge in the anodes of the light-emitting elements to be fully discharged, thereby alleviating the afterimage phenomenon of the display panel.

[0116] In some embodiments, the display mode information includes an HBM mode and an AOD mode, and the duration includes a first duration and a second duration. If the display mode information is determined to be the HBM mode, the processing circuit 213 shown in FIG2 writes the first duration into the first register 212 shown in FIG2. If the display mode information is determined to be the AOD mode, the processing circuit 213 writes the second duration into the first register 212. The second duration is greater than the first duration.

[0117] For example, by setting the duration of the first level of the gate trigger signal GSTV to a longer duration, the gate of the drive transistor can be reset and the anode of the light-emitting element can be initialized multiple times before the light-emitting element emits light, thereby improving image persistence. However, if the gate of the drive transistor is reset too many times, the gate voltages of the drive transistors of some pixel units in the pixel circuit may vary, resulting in uneven display brightness on the display panel and the visual appearance of virtual edges.

[0118] In the AOD mode, since the displayed images are mostly single, pure-color images, even when the display panel's brightness is uneven, no obvious virtual edge phenomenon will appear visually, thus minimizing the impact on the user experience. In the HBM mode, the displayed images are mostly complex images, requiring higher brightness of the display panel. Therefore, the processing circuit 213 writes the first duration into the first register 212 to set the duration of the first level of the gate trigger signal GSTV, controlling the number of times the gate of the drive transistor is reset and the number of times the anode of the light-emitting element is initialized in the HBM mode, thereby balancing the afterimage phenomenon and the virtual edge phenomenon of the displayed image.

[0119] Under the premise that the virtual edge phenomenon in the AOD mode does not affect the user's visual experience, the duration of the first level of the gate trigger signal GSTV in the AOD mode can be set to a second duration that is longer than the first duration, thereby improving the image retention phenomenon. Under the premise that the virtual edge phenomenon in the HBM mode affects the user's visual experience, the duration of the first level of the gate trigger signal GSTV in the HBM mode can be set to the first duration that is shorter than the second duration, thereby improving the image retention phenomenon and not causing the virtual edge phenomenon.

[0120] For example, when the display mode of the display panel is set to HBM mode, the processing circuit 213 may write a first duration into the first register 212 and set the duration of the first level of the gate trigger signal GSTV to the first duration, so that before the light-emitting phase, the first levels of the gate drive signal and the reset signal may alternate A times, thereby resetting the gate of the drive transistor A-1 times and initializing the anode of the light-emitting element A times. When the display mode of the display panel is set to AOD mode, the processing circuit 213 may write a second duration into the first register 212 and set the duration of the first level of the gate trigger signal GSTV to the second duration, so that before the light-emitting phase, the first levels of the gate drive signal and the reset signal may alternate B times, thereby resetting the gate of the drive transistor B-1 times and initializing the anode of the light-emitting element B times.

[0121] For example, since the second duration is greater than the first duration, the relationship between A and B may be 1<A<B.

[0122] In the embodiment of the present disclosure, the display mode information further includes a standard mode. When it is determined that the display mode information is the standard mode, the processing circuit 213 writes the first duration into the first register 212 .

[0123] Because the type of display content of the display panel in standard mode is similar to the type of display content of the display panel in HBM mode, the processing circuit 213 can write the first duration into the first register 212 in both standard mode and HBM mode, and set the duration of the first level of the gate trigger signal GSTV to be the same. For example, when the display mode of the display panel is set to standard mode, the duration can also be set to the first duration, so that before the light-emitting stage, the first levels of the gate drive signal and the reset signal can alternately appear A times, thereby resetting the gate of the drive transistor A-1 times and initializing the anode of the light-emitting element A times.

[0124] In the embodiment of the present disclosure, the first duration is greater than or equal to the first reference time difference, and the second duration is greater than or equal to the second reference time difference.

[0125] For example, within M scanning cycles, the time difference between the start time of the first level of the clock signal within the first scanning cycle and the end time of the first level of the clock signal within the Mth scanning cycle is the first reference time difference. Within N scanning cycles, the time difference between the start time of the first level of the clock signal within the first scanning cycle and the end time of the first level of the clock signal within the Nth scanning cycle is the second reference time difference. M<N, where M and N are both integers greater than 1.

[0126] For example, the scanning period may be a reference scanning period. Since M<N, the second reference time difference is greater than the first reference time difference.

[0127] For example, the first duration is greater than or equal to the first reference time difference, and the duration is set to the first duration. The first levels of the gate drive signal and the reset signal may alternate M times before the light-emitting phase. The second duration is greater than or equal to the second reference time difference, and the duration is set to the second duration. The first levels of the gate drive signal and the reset signal may alternate N times before the light-emitting phase.

[0128] In this case, the number of times the first levels of the gate driving signal and the reset signal alternately appear corresponding to the second duration is greater than the number of times the first levels of the gate driving signal and the reset signal alternately appear corresponding to the first duration.

[0129] By setting the duration of the first level of the corresponding gate trigger signal GSTV for different display modes, the gate drive signal and reset signal of the corresponding timing are obtained, so that the gate of the driving transistor is reset a corresponding number of times and the anode of the light-emitting element is initialized a corresponding number of times. This makes it possible to set adaptive afterimage improvement operations for different display modes.

[0130] For example, in the AOD mode for displaying simple images, the duration of the first level of the gate trigger signal GSTV can be set to the second duration, thereby resetting the gate of the drive transistor more times and initializing the anode of the light-emitting element more times, effectively improving the display afterimage phenomenon. In the standard mode and HBM mode for displaying complex images, the duration of the first level of the gate trigger signal GSTV can be set to the first duration, thereby resetting the gate of the drive transistor less times and initializing the anode of the light-emitting element less times, improving the display afterimage phenomenon and preventing the virtual edge phenomenon.

[0131] In the embodiment of the present disclosure, the relationship between M, N, and I may be M<N≤I. Therefore, the value range of N may be 3, 4, and 5, and the value range of M may be 2, 3, and 4. For example, in AOD mode, N may be 3. Correspondingly, in standard mode and HBM mode, M may be 2. For example, when N is 3, the timing of the gate trigger signal GSTV, the gate drive signal, and the reset signal may be as shown in FIG4C . When M is 2, the timing of the gate trigger signal GSTV, the gate drive signal, and the reset signal may be as shown in FIG4B .

[0132] In some embodiments, the processing circuit 213 shown in FIG2 further receives a display mode switching request via multiple pins, the switching request including a target display mode. The processing circuit 213 reads the current duration of the first level of the gate trigger signal GSTV from the first register 212 shown in FIG2 . If it is determined that the target duration corresponding to the target display mode is inconsistent with the current duration, the processing circuit 213 writes the target duration into the first register 212 and generates the gate trigger signal GSTV based on the target duration stored in the first register 212.

[0133] For example, the default display mode of the display panel may be a standard mode, and the duration of the first level of the gate trigger signal GSTV corresponding to the standard mode may be a first duration. After the display is turned on, the duration of the first level of the gate trigger signal GSTV may be set to the first duration by default. After receiving a request to switch the display mode, the current duration is determined to be the first duration. The target display mode included in the switching request may be an AOD mode, and the duration of the first level of the gate trigger signal GSTV corresponding to the AOD mode may be a second duration. Therefore, when it is determined that the target display mode is the second duration and the current duration mode is the first duration mode, the processing circuit 213 writes the second duration into the first register 212, and generates the gate trigger signal GSTV based on the second duration stored in the first register 212.

[0134] For example, the display driver chip 210 shown in Figure 2 can have a built-in default operating program that generates a gate drive signal based on a first duration for a duration. When the processing circuit 213 modifies the duration stored in the first register 212 to a second duration, an operating program that generates a gate drive signal based on the second duration can be input to the display driver chip 210 from the outside. For example, the external host can send a mode switching instruction and a corresponding operating program to the display driver chip 210 through the Mobile Industry Processor Interface (MIPI) protocol. For example, the processing circuit 213 can also receive a mode switching instruction and a corresponding operating program from an external host based on the MIPI protocol through pin 211.

[0135] When the AOD mode is switched back to the standard mode, the processing circuit 213 may modify the duration stored in the first register 212 from the second duration to the first duration, and generate the gate trigger signal GSTV based on the built-in default operating program.

[0136] Due to the different durations of the first level of the gate trigger signal, there will be certain differences in the voltage between the gates of some driving transistors in the pixel circuit, which will cause the brightness of the display screen corresponding to different durations to be different. For example, for the same screen, the display brightness corresponding to the duration of 3GSTV is greater than the display brightness corresponding to the duration of 2GSTV, and the display brightness corresponding to the duration of 2GSTV is greater than the display brightness corresponding to the duration of 1GSTV. To address this situation, gamma voltages corresponding to different durations can be stored in the display driver chip 210 in advance through gamma debugging.

[0137] After the processing circuit 213 writes the duration into the first register 212, the pixel circuit can also be driven according to the gamma voltage corresponding to the duration pre-stored in the display driver chip 210. This can make the duration corresponding to the display brightness consistent with the duration corresponding to the gamma voltage, thereby ensuring that the gamma voltage matches the display brightness of the display panel in different display modes.

[0138] In the embodiment of the present disclosure, when it is determined that the target duration corresponding to the target display mode is consistent with the current duration, the processing circuit 213 generates the gate trigger signal GSTV based on the current duration stored in the first register 212 .

[0139] For example, the default display mode of the display panel may be a standard mode, and the duration of the first level of the gate trigger signal corresponding to the standard mode may be a first duration. After the display is turned on, the first register 212 stores the first duration by default. After receiving a request to switch the display mode, the processing circuit 213 determines that the current duration is the first duration. The target display mode included in the switching request may be an HBM mode, and the duration of the first level of the gate trigger signal corresponding to the HBM mode is the first duration. Therefore, when it is determined that the target display mode is the first duration and the current continuous mode is also the first continuous mode, the processing circuit 213 can generate a gate trigger signal GSTV based on the first duration stored by default in the first register 212. At this time, the processing circuit 213 can generate a gate drive signal GSTV based on the default running program built into the display driver chip 210.

[0140] For example, after receiving a display mode switching request, the processing circuit 213 determines that the current duration is the first duration. The target display mode included in the switching request may be the AOD mode, and the duration of the first level of the gate trigger signal corresponding to the AOD mode may be the second duration. Therefore, if it is determined that the target display mode is the second duration and the current duration mode is the first duration mode, the processing circuit 213 modifies the first duration stored by default in the first register 212 to the second duration, and generates a gate trigger signal based on the execution of the program corresponding to the received second duration.

[0141] When the AOD mode is switched to the standard mode or the HBM mode, the processing circuit 213 may modify the second duration stored in the first register 212 to the first duration, and generate the gate trigger signal GSTV based on a built-in default operating program.

[0142] For example, the first duration may be 2GSTV, and the timing of the gate trigger signal GSTV, the gate drive signal, and the reset signal may be shown in FIG4B . The second duration may be 3GSTV, and the timing of the gate trigger signal GSTV, the gate drive signal, and the reset signal may be shown in FIG4C .

[0143] FIG6 is a schematic structural diagram of a display driving device according to another embodiment of the present disclosure.

[0144] As shown in FIG. 6 , the display driving device 600 may include a display driving chip 610 .

[0145] In the embodiment of the present disclosure, the display driver chip 610 includes a plurality of pins 611 , a first register 612 , a processing circuit 613 and a first storage unit 614 .

[0146] The processing circuit 613 performs similar operations to the processing circuit 213 shown in Figure 2, the first register 612 has a similar function to the first register 212 shown in Figure 2, and the pin 611 has a similar function to the pin 211 shown in Figure 2, which will not be repeated here.

[0147] In the embodiment of the present disclosure, the first storage unit 614 stores reference voltages. For example, the first storage unit 614 stores a reference voltage corresponding to a first duration and a reference voltage corresponding to a second duration. The first storage unit 614 may also store an operating program corresponding to the first duration and an operating program corresponding to the second duration.

[0148] The processing circuit 613 can generate the gate drive signal GSTV based on the first duration stored in the first register 612 and the program corresponding to the first duration stored in the first storage unit 614. The processing circuit 613 can also generate the gate drive signal GSTV based on the second duration stored in the first register 612 and the program corresponding to the second duration stored in the first storage unit 614. Figure 7 is a schematic diagram of the structure of a display driver device according to another embodiment of the present disclosure.

[0149] As shown in FIG. 7 , the display driving device 700 may include a display driving chip 710 .

[0150] In the embodiment of the present disclosure, the display driver chip 710 includes a plurality of pins 711 , a first register 712 , a processing circuit 713 and a second register 715 .

[0151] The processing circuit 713 performs operations similar to those of the processing circuit 213 shown in FIG2 , the first register 712 functions similarly to the first register 212 shown in FIG2 , and the pin 711 functions similarly to the pin 211 shown in FIG2 , which will not be described in detail here.

[0152] In an embodiment of the present disclosure, the first register 712 is configured to store a first duration, and the second register 715 is configured to store a second duration, where the first duration is less than the second duration.

[0153] The processing circuit 713 receives a display mode switching request through multiple pins 711, and the switching request includes a target display mode; when it is determined that the target display mode is the HBM mode, a gate trigger signal is generated based on the first duration stored in the first register 712; and when it is determined that the target display mode is the AOD mode, a gate trigger signal is generated based on the second duration stored in the second register 715.

[0154] For example, a first register 712 and a second register 715 for controlling the duration of the first level of the gate trigger signal are provided within the display driver chip 710. For example, the physical storage space of the first register 712 stores the first duration, and the address of the first register 712 is bound to the standard mode and the HBM mode. The physical storage space of the second register 715 stores the second duration, and the address of the second register 715 is bound to the AOD mode.

[0155] After the display is powered on, the default display mode of the display panel may be the standard mode, and the duration of the first level of the gate trigger signal may be set by default to the first duration. Upon receiving a display mode switching request, the display driver 700 in the display determines that the target display mode included in the switching request may be the AOD mode. The display driver 700 in the display may read the second duration stored in the second register 715 based on the address of the second register 715 associated with the AOD mode, and generate a gate trigger signal based on the corresponding running program.

[0156] When the AOD mode is switched to the standard mode or the HBM mode, the display driving device 700 can read the first duration stored in the first register 712 based on the address of the first register 712 bound to the standard mode and the HBM mode, and generate a gate trigger signal based on the corresponding running program.

[0157] In the embodiment of the present disclosure, the processing circuit 713 can also read a reference voltage corresponding to the duration from the first storage unit and use the reference voltage together with the gate trigger signal to drive the pixel circuit. For example, the first storage unit can be a storage unit within the display driver device 700, which is not shown in FIG7 .

[0158] FIG8 is a schematic structural diagram of a display driving device according to another embodiment of the present disclosure.

[0159] As shown in FIG. 8 , the display driving device 800 may include a display driving chip 810 and a second storage unit 820 .

[0160] In the embodiment of the present disclosure, the display driver chip 810 includes a plurality of pins 811 , a first register 812 , and a processing circuit 813 .

[0161] The processing circuit 813 performs similar operations to the processing circuit 213 shown in Figure 2, the first register 812 has a similar function to the first register 212 shown in Figure 2, and the pin 811 has a similar function to the pin 211 shown in Figure 2, which will not be repeated here.

[0162] In the embodiment of the present disclosure, the second storage unit 820 is configured to store a reference voltage. The processing circuit 813 may read the reference voltage corresponding to the duration from the second storage unit 820 .

[0163] For example, the second storage unit 820 may also store touch firmware / demura (eliminating uneven brightness) or other circuit-related data.

[0164] For example, the second storage unit 820 may be a flash memory and is located outside the display driver chip 810 .

[0165] For example, the display driver chip 810 can communicate with the second storage unit 820 through a communication protocol such as a serial peripheral interface (SPI) and a serial transmission bus (I2C), thereby calling the data stored in the second storage unit 820.

[0166] For example, the Flash memory can be erased / written multiple times, so multiple gamma tunings can be performed for different display modes, and the obtained gamma voltages can be stored in the Flash memory.

[0167] For example, the processing circuit 813 may receive a mode switching instruction and a corresponding running program from an external host via the pin 811 based on the MIPI protocol.

[0168] The first storage unit inside the display driver chip 810 also stores a default operating program, which corresponds to the first duration and is used to enter the standard mode and HBM mode. The first storage unit is not shown in Figure 8. After the display is turned on, the duration of the first level of the gate trigger signal can be set to the first duration by default. After receiving a request to switch the display mode, the processing circuit 813 in the display determines that the current duration is the first duration. The target display mode included in the switching request can be an AOD mode, and the duration of the first level of the gate trigger signal corresponding to the AOD mode can be a second duration. Therefore, when it is determined that the target display mode is the second duration and the current duration mode is the first duration mode, the processing circuit 813 modifies the duration of the first level of the gate trigger signal set by default to the second duration, and generates a gate trigger signal based on the received operating program corresponding to the second duration.

[0169] When the AOD mode is switched to the standard mode or the HBM mode, the processing circuit 813 may modify the duration of the first level of the gate trigger signal from the second duration to the first duration, and generate a gate trigger signal based on a built-in default operating program.

[0170] In the embodiment of the present disclosure, the processing circuit 813 may also read a reference voltage corresponding to the duration from the second storage unit 820 , and use the reference voltage together with the gate trigger signal to drive the pixel circuit.

[0171] In the embodiment of the present disclosure, the second storage unit 820 is further configured to store the duration of the first level of the gate trigger signal corresponding to the display mode information. The processing circuit 813 can read the duration from the second storage unit 820 and write the duration into the first register 812.

[0172] For example, the second storage unit 820 may also store an operating program corresponding to a duration.

[0173] For example, the processing circuit 813 may receive a mode switching instruction from an external host based on the MIPI protocol via pin 811. The processing circuit 813 may read the first duration or the second duration corresponding to the display mode from the second storage unit 820 and write the read first duration or the read second duration into the first register 812. The processing circuit 813 may read the running program corresponding to the duration from the second storage unit 820, generate a gate trigger signal, and read a reference voltage corresponding to the duration from the second storage unit 820, and use the reference voltage together with the gate trigger signal to drive the pixel circuit.

[0174] FIG. 9 is a block diagram of a display device according to an embodiment of the present disclosure.

[0175] As shown in FIG. 9 , a display device 900 may include a display panel 910 and a display driving apparatus 920 .

[0176] The display driving device 920 is configured to drive the display panel 910 .

[0177] The display driving device 920 may be the display driving device 200 , the display driving device 600 , the display driving device 700 , or the display driving device 800 described above, and details thereof will not be repeated here.

[0178] FIG10 is a flowchart of a display driving method according to an embodiment of the present disclosure.

[0179] As shown in FIG. 10 , the driving method may include operations S1010 to S1030 .

[0180] In operation S1010, a duration of a first level of a gate trigger signal is set according to display mode information.

[0181] In operation S1020 , a reference voltage corresponding to the duration is acquired.

[0182] In operation S1030 , the pixel circuit is driven by the gate trigger signal and the reference voltage.

[0183] In the embodiment of the present disclosure, operations S1010 to S1030 are similar to the operations performed by the processing circuit 213 described above, and are not described again herein.

[0184] For example, the duration is greater than or equal to a reference time difference. In one scanning cycle, the time difference between the start time of the first level of the clock signal in the first scanning cycle and the end time of the first level of the clock signal in the I-th scanning cycle is the reference time difference, and I is an integer greater than 1.

[0185] For example, the display mode information includes an HBM mode and an AOD mode, and the duration includes a first duration and a second duration. Operation S1010, based on the display mode information, sets the duration of the first level of the gate trigger signal. The operation may include: if the display mode information is determined to be the HBM mode, setting the duration to the first duration; and if the display mode information is determined to be the AOD mode, setting the duration to the second duration. The second duration is greater than the first duration.

[0186] For example, the display mode information also includes a standard mode. Operation S1010 setting the duration of the first level of the gate trigger signal according to the display mode information may further include: if it is determined that the display mode information is the standard mode, setting the duration to a first duration.

[0187] For example, the first duration is greater than or equal to the first reference time difference, and the second duration is greater than or equal to the second reference time difference. Within M scanning cycles, the time difference between the start time of the first level of the clock signal in the first scanning cycle and the end time of the first level of the clock signal in the Mth scanning cycle is the first reference time difference. Within N scanning cycles, the time difference between the start time of the first level of the clock signal in the first scanning cycle and the end time of the first level of the clock signal in the Nth scanning cycle is the second reference time difference. M<N, where M and N are both integers greater than 1.

[0188] For example, operation S1010 may include setting the duration of the first level of the gate trigger signal according to the display mode information: in response to a received display mode switching request, obtaining the current duration of the first level of the gate trigger signal and the target display mode included in the switching request; and modifying the current duration to the target duration when it is determined that the target duration corresponding to the target display mode is inconsistent with the current duration.

[0189] For example, operation S1010 may include setting the duration of the first level of the gate trigger signal according to the display mode information: in response to a received display mode switching request, obtaining the current duration of the first level of the gate trigger signal and the target display mode included in the switching request; and maintaining the current duration when it is determined that the target duration corresponding to the target display mode is consistent with the current duration.

[0190] For example, operation S1030 of driving the pixel circuit by the gate trigger signal and the reference voltage includes: generating a gate driving signal according to the gate trigger signal; generating a driving voltage according to the reference voltage; and driving the pixel circuit by the gate driving signal and the driving voltage.

[0191] For example, the duration is greater than or equal to the gate time difference. In one scanning cycle, the time difference between the start time of the first level of the gate drive signal in the first scanning cycle and the end time of the first level of the gate drive signal in the first scanning cycle is the gate time difference.

[0192] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0193] Those skilled in the art will appreciate that various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, even if such combinations or combinations are not explicitly described in this disclosure. In particular, various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0194] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A display driving device, comprising: Display driver chip, including: First register; Multiple pins; and a processing circuit configured to write the duration of the first level of the gate trigger signal corresponding to the display mode information into the first register, wherein at the end moment of the first level, the gate trigger signal jumps from the first level to a second level; generating the gate trigger signal based on the duration stored in the first register; acquiring a reference voltage corresponding to the duration; and The gate trigger signal and the reference voltage are output through the plurality of pins.

2. The display driving device according to claim 1, wherein: The processing circuit is further configured to: receiving a display mode switching request through the plurality of pins, the switching request including a target display mode; Reading a current duration of the first level of the gate trigger signal from the first register; When it is determined that the target duration corresponding to the target display mode is inconsistent with the current duration, writing the target duration into the first register; as well as The gate trigger signal is generated based on the target duration stored in the first register.

3. The display driving device according to claim 1, wherein: The processing circuit is further configured to: receiving a display mode switching request through the plurality of pins, the switching request including a target display mode; Reading a current duration of the first level of the gate trigger signal from the first register; as well as When it is determined that the target duration corresponding to the target display mode is consistent with the current duration, the gate trigger signal is generated based on the current duration stored in the first register.

4. The display driving device according to claim 1, wherein: The display driver chip also includes: a second register configured to store a second duration; wherein the first register is further configured to store a first duration, the first duration being less than the second duration; and The processing circuit is further configured to: receiving a display mode switching request through the plurality of pins, the switching request including a target display mode; In the case where it is determined that the target display mode is the highlight mode, generating the gate trigger signal based on the first duration stored in the first register; and When it is determined that the target display mode is the constant display mode, the gate trigger signal is generated based on the second duration stored in the second register.

5. The display driving device according to claim 1, wherein: The display driver chip also includes: A first storage unit configured to store the reference voltage; The processing circuit is further configured to read a reference voltage corresponding to the duration from the first storage unit.

6. The display driving device according to claim 1, further comprising: a second storage unit configured to store a reference voltage; The processing circuit is further configured to read a reference voltage corresponding to the duration from the second storage unit.

7. The display driving device according to claim 6, wherein: The second storage unit is further configured to store a duration of a first level of the gate trigger signal corresponding to the display mode information; as well as The processing circuit is further configured to read the duration from the second storage unit and write the duration into the first register.

8. The display driving device according to claim 1, wherein: The duration is greater than or equal to the reference time difference; Among them, in I scanning cycles, the time difference between the starting time of the first level of the clock signal in the first scanning cycle and the ending time of the first level of the clock signal in the I scanning cycle is the reference time difference, and I is an integer greater than 1.

9. The display driving device according to claim 1, wherein: The processing circuit is further configured to: When it is determined that the display mode information is the highlight mode, the first duration is written into the first register. Memory; and When it is determined that the display mode information is the constant display mode, writing a second duration into the first register; The second duration is greater than the first duration.

10. The display driving device according to claim 9, wherein: The processing circuit is further configured to: When it is determined that the display mode information is the standard mode, the first duration is written into the first register.

11. The display driving device according to claim 9 or 10, wherein: The first duration is greater than or equal to a first reference time difference, and the second duration is greater than or equal to a second reference time difference; Among them, within M scanning cycles, the time difference between the starting time of the first level of the clock signal in the first scanning cycle and the ending time of the first level of the clock signal in the Mth scanning cycle is the first reference time difference; within N scanning cycles, the time difference between the starting time of the first level of the clock signal in the first scanning cycle and the ending time of the first level of the clock signal in the Nth scanning cycle is the second reference time difference, wherein M<N, M and N are both integers greater than 1.

12. A display device, comprising: Display panel; as well as The display driving device according to any one of claims 1 to 11 is configured to drive the display panel.

13. A display driving method for driving a pixel circuit, comprising: According to the display mode information, setting the duration of the first level of the gate trigger signal, wherein at the end moment of the first level, the gate trigger signal jumps from the first level to the second level; Acquire a reference voltage corresponding to the duration; as well as The pixel circuit is driven by the gate trigger signal and the reference voltage.

14. The method according to claim 13, wherein: The duration is greater than or equal to the reference time difference; Among them, in I scanning cycles, the time difference between the starting time of the first level of the clock signal in the first scanning cycle and the ending time of the first level of the clock signal in the I scanning cycle is the reference time difference, and I is An integer greater than 1.

15. The method according to claim 13, wherein: The display mode information includes a highlight mode and a constant display mode, and the duration includes a first duration and a second duration; The step of setting the duration of the first level of the gate trigger signal according to the display mode information includes: When it is determined that the display mode information is the highlight mode, setting the duration to the first duration; and When it is determined that the display mode information is the constant display mode, setting the duration to the second duration; The second duration is greater than the first duration.

16. The method according to claim 15, wherein: The display mode information further includes a standard mode; and setting the duration of the first level of the gate trigger signal according to the display mode information further includes: When it is determined that the display mode information is the standard mode, the duration is set to a first duration.

17. The method according to claim 15 or 16, wherein: The first duration is greater than or equal to a first reference time difference, and the second duration is greater than or equal to a second reference time difference; Among them, within M scanning cycles, the time difference between the starting time of the first level of the clock signal in the first scanning cycle and the ending time of the first level of the clock signal in the Mth scanning cycle is the first reference time difference; within N scanning cycles, the time difference between the starting time of the first level of the clock signal in the first scanning cycle and the ending time of the first level of the clock signal in the Nth scanning cycle is the second reference time difference, wherein M<N, M and N are both integers greater than 1.

18. The method according to claim 13, wherein: The step of setting the duration of the first level of the gate trigger signal according to the display mode information includes: In response to a received display mode switching request, acquiring a current duration of the first level of the gate trigger signal and a target display mode included in the switching request; and When it is determined that the target duration corresponding to the target display mode is inconsistent with the current duration, the current duration is modified to the target duration.

19. The method according to claim 13, wherein: The step of setting the duration of the first level of the gate trigger signal according to the display mode information includes: In response to a received display mode switching request, acquiring a current duration of the first level of the gate trigger signal and a target display mode included in the switching request; and When it is determined that the target duration corresponding to the target display mode is consistent with the current duration, the current duration is maintained.

20. The method according to claim 13, wherein: The driving of the pixel circuit by the gate trigger signal and the reference voltage comprises: Generate a gate drive signal according to the gate trigger signal; generating a driving voltage according to the reference voltage; and The pixel circuit is driven by the gate driving signal and the driving voltage.

21. The method according to claim 20, wherein: The duration is greater than or equal to the gate time difference; Among them, in I scanning cycles, the time difference between the starting time of the first level of the gate driving signal in the first scanning cycle and the ending time of the first level of the gate driving signal in the I scanning cycle is the gate time difference.

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