Semiconductor device, method of manufacturing the same, and storage system

Abstract

Embodiments of the present application disclose a semiconductor device, a manufacturing method thereof and a storage system. The device comprises a stack structure; the stack structure comprises a first region and a second region; a channel structure located in the first region and penetrating the stack structure along a first direction; and a gate line isolation structure located in the second region and extending along a second direction, the gate line isolation structure penetrating the stack structure along the first direction, and the gate line isolation structure being concave-convex along a third direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device, its fabrication method, and a storage system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of process technology, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D memory structures to approach its upper limit.

[0003] To overcome the limitations of 2D memory structures, the industry has developed memory with three-dimensional structures, which increases storage density by arranging memory cells three-dimensionally on a substrate.

[0004] Three-dimensional memory can include semiconductor structures as storage arrays and peripheral devices. How to improve the fabrication yield and reliability of the aforementioned semiconductor structures is a problem to be solved. Summary of the Invention

[0005] This application provides a semiconductor device, a method for manufacturing the same, and a storage system thereof, which improves the yield and reliability of the semiconductor device.

[0006] In a first aspect, this application provides a method for fabricating a semiconductor device, comprising:

[0007] A stacked layer is provided; the stacked layer includes interleaved dielectric layers and sacrificial layers, and the stacked layer includes a first region and a second region;

[0008] A plurality of channel holes are formed in the first region, penetrating the stacked layer along a first direction, and a plurality of first virtual channel holes are formed in the second region, penetrating the stacked layer along the first direction;

[0009] Multiple channel structures are formed in the multiple channel holes;

[0010] A grid line slot trench is formed that extends in a second direction and surrounds the plurality of first virtual channel holes, wherein the second direction intersects the first direction;

[0011] A grid line isolation structure is formed in the grid line slot groove, and the grid line isolation structure has a concave-convex shape along a third direction; the third direction intersects the first direction and the second direction.

[0012] In one embodiment of this application, the step of forming the grid slot trenches extending in a second direction and surrounding the plurality of first virtual channel holes includes:

[0013] A plurality of first virtual channel holes are etched to form a plurality of second virtual channel holes, and the plurality of second virtual channel holes are connected in the second direction to form the gate wire slot trench.

[0014] In one embodiment of this application, prior to the step of forming a plurality of channel structures in the plurality of channel holes, the method further includes:

[0015] Sacrificial material is filled into the channel hole and the first virtual channel hole, and then the sacrificial material in the channel hole is removed.

[0016] In one embodiment of this application, after the sacrificial material is filled into the channel hole and the first virtual channel hole, and before the step of removing the sacrificial material from the channel hole, the method further includes:

[0017] A capping layer is formed on top of the stacked layers, and the capping layer located above the channel holes is removed.

[0018] In one embodiment of this application, prior to the step of forming the gate wire slot trenches extending in the second direction and surrounding the plurality of first virtual channel holes, the method further includes:

[0019] Remove the sacrificial material from the first virtual channel hole.

[0020] In one embodiment of this application, after the step of forming a plurality of channel structures in the plurality of channel holes and before the step of removing the sacrificial material in the first virtual channel hole, the method further includes: forming a protective layer on top of the stacked layer.

[0021] In one embodiment of this application, the protective layer comprises polycrystalline silicon.

[0022] In one embodiment of this application, before forming the grid line isolation structure in the grid line slot trench, the method further includes:

[0023] The sacrificial layer in the stacked layers is replaced with a gate line layer.

[0024] In one embodiment of this application, the shape of the first virtual channel hole includes either an ellipse or a circle, and the shape of the channel hole includes a circle.

[0025] In one embodiment of this application, the stacked layer includes a core region and a stepped region;

[0026] A plurality of first virtual channel holes with equal diameters are formed in the core area and the stepped area along the third direction.

[0027] In one embodiment of this application, the stacked layer includes a core region and a stepped region;

[0028] The diameter of the plurality of first virtual channel holes formed in the core area along the third direction is smaller than the diameter of the plurality of first virtual channel holes formed in the stepped area along the third direction.

[0029] In one embodiment of this application, the step of forming a plurality of channel holes penetrating the stacked layer in the first region along the first direction and forming a plurality of first virtual channel holes penetrating the stacked layer in the second region along the first direction includes:

[0030] A composite photolithography layer is formed on the dielectric layer at the top of the stacked layers; and a plurality of first trenches and a plurality of second trenches are formed in the composite photolithography layer; the first trenches are located in the first region, and the second trenches are located in the second region;

[0031] The stacked layers in the first region are etched through the first trench to form a plurality of the channel holes; and,

[0032] The stacked layers in the second region are etched through the second trench to form a plurality of the first virtual channel holes.

[0033] In one embodiment of this application, the plurality of channel holes and the plurality of first virtual channel holes are formed in the same process.

[0034] In one embodiment of this application, the step of forming a composite photolithography layer on the dielectric layer at the top of the stacked layers includes:

[0035] A stop layer is formed on the top dielectric layer, and a first mask layer is formed on the stop layer;

[0036] The first mask layer is etched through the stop layer until the dielectric layer on top of the stacked layers is exposed to form the composite photolithography layer.

[0037] In one embodiment of this application, the first mask layer includes a hard mask layer or a photoresist layer.

[0038] To address the above problems, embodiments of the present invention also provide a semiconductor device, comprising:

[0039] A stacked structure; the stacked structure includes interleaved dielectric layers and gate line layers, and the stacked structure includes a first region and a second region;

[0040] A channel structure located in the first region and penetrating the stacked structure along a first direction;

[0041] A gate line isolation structure located in the second region and extending along the second direction, the gate line isolation structure penetrating the stacked structure along the first direction, the gate line isolation structure having a concave-convex shape along the third direction, wherein the second direction intersects the first direction, and the third direction intersects the first direction and the second direction.

[0042] In one embodiment of this application, the semiconductor device further includes a protective layer disposed on top of the stacked structure.

[0043] In one embodiment of this application, the grid isolation structure includes a sidewall extending along the second direction, the sidewall including a plurality of substructures connected end to end, and two adjacent substructures are not coplanar.

[0044] In one embodiment of this application, the stacked structure includes a core region and a stepped region;

[0045] The dimension of the grid isolation structure located in the core area along the third direction is equal to the dimension of the grid isolation structure located in the stepped area along the third direction.

[0046] In one embodiment of this application, the stacked structure includes a core region and a stepped region;

[0047] The dimension of the gate isolation structure located in the core area along the third direction is smaller than the dimension of the gate isolation structure located in the stepped area along the third direction.

[0048] To address the aforementioned problems, embodiments of the present invention also provide a storage system, comprising: a controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory, and the three-dimensional memory includes any of the semiconductor devices described above.

[0049] The beneficial effects of this application are as follows: The stacked layer includes a first region and a second region. A plurality of channel vias penetrating the stacked layer along a first direction are formed in the first region, and a plurality of first virtual channel vias penetrating the stacked layer along the first direction are formed in the second region. Then, a plurality of channel structures are formed in the plurality of channel vias, forming gate line slot trenches extending in a second direction and surrounding the plurality of first virtual channel vias. The second direction intersects the first direction. Gate line isolation structures are formed in the gate line slot trenches, and the gate line isolation structures have an uneven shape along a third direction. This application can improve the yield and reliability of the device. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a top view schematic diagram of the semiconductor device exemplified in this application;

[0052] Figures 2-3 yes Figure 1 A schematic diagram of the structure of several stages in the example semiconductor device;

[0053] Figures 4-16 This is a schematic diagram of the structure of several stages in the semiconductor device provided in the embodiments of this application;

[0054] Figures 17-26 This is a top view schematic diagram of several stages in the semiconductor device provided in the embodiments of this application;

[0055] Figure 27 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0056] Figure 28 This is a schematic diagram of the storage system provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0058] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0059] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0060] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0061] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more gate layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0062] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0063] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0064] Three-dimensional memory (3D memory) has high storage density and large storage capacity, and therefore has been increasingly widely used. The fabrication process of 3D memory in related technologies typically includes the following main steps: forming a channel hole (CH) in the core region of the stacked structure, forming a staircase structure (SS) around the core region, forming a dummy channel hole (DCH) in the staircase, subsequently replacing the sacrificial layer in the stacked layers to form a gate line structure (GL), and forming gate contacts (CT) in the staircase to lead out each gate line layer, etc.

[0065] For example, such as Figure 1 This is a top view diagram of a 3D NAND flash memory, as shown below. Figures 2-3 This is a schematic diagram of the structure of a 3D NAND memory. Figures 2-3 for Figure 1 Cross-sectional views of a 3D NAND memory along the X-Cut line and along the Y-Cut line. (Example) Figures 2 to 3 As shown, firstly, a channel hole 33 is formed penetrating the stacked layer 201, and a channel structure 330 is formed in the channel hole 33. Then, a gate wire slot trench 101 extending along a second direction (e.g., the X-axis direction) and penetrating the stacked layer 201 needs to be formed at predetermined positions between the channel structures 330. Then, a gate wire isolation structure 102 is formed in the gate wire slot trench 101 to obtain the desired result. Figure 1 The 3D NAND memory shown.

[0066] However, since the aspect ratio of the formed gate wire slot trench 101 is larger than that of the communication hole, and the sidewall of the gate wire isolation structure 102 formed in the gate wire slot trench 101 is straight, the cut of the gate wire isolation structure 102 is very fragile. Moreover, the gate wire isolation structure 102 extends a long distance along its extension direction, and the sidewall of the gate wire isolation structure 102 is equivalent to a very high wall. Under stress, it is easy to tilt or twist, causing the gate wire isolation structure 102 to lose its shape. This will result in the inability to guarantee the continuity of the conductive material in the gate wire isolation structure 102 after the conductive material is filled, which will lead to gate wire short circuit and device failure.

[0067] Furthermore, as the number of memory layers increases, the aspect ratio of the etched channel vias 33 and gate line slot trenches 101 continuously increases, leading to increased difficulty in the etching process. Figures 2 to 3 The separate etching of the via 33 and the gate slot trench 101, as shown, is not only costly but also causes mutual interference due to tilting, resulting in a certain degree of yield loss. Furthermore, the increasing aspect ratio of the etched via 33 and gate slot trench 101 leads to mutual interference due to tilting, hindering the further development and production of 3D NAND memories with more storage layers.

[0068] To solve the above problems, refer to Figures 4 to 28 As shown, this application provides a semiconductor device 100, its fabrication method, and a memory system. In this application, when etching a channel via 33 onto a stacked layer 201 in a first region 202, a first virtual channel via 34 is formed onto the stacked layer 201 in a second region 203 using the same process. Subsequently, through a series of processes, a gate line slot trench 101 is formed using the first virtual channel via 34 in the second region 203, thereby achieving a single etching process for the channel via 33 in the first region 202 and the gate line slot trench 101 in the second region 203. The semiconductor device 100 of this application has low manufacturing cost and solves the yield loss problem caused by the tilt of the channel structure 330 and the gate line isolation structure 102.

[0069] Please see Figure 27 The diagram shown is a flowchart illustrating the fabrication method of the semiconductor device 100 provided in this embodiment of the application. A detailed flowchart is provided below. Figures 4 to 26 The structural diagram may include the following steps:

[0070] Step S100: Provide a stacked layer 201; the stacked layer 201 includes an interleaved dielectric layer 30 and a sacrificial layer 40, and the stacked layer 201 includes a first region 202 and a second region 203.

[0071] In some embodiments of this application, the following are provided: Figure 4The diagram shows a stacked layer 201, comprising a dielectric layer 30 and a sacrificial layer 40 that are staggered in a first direction and extend along a second and a third direction. The second direction intersects the first direction, and the third direction intersects both the first and second directions. Here, "the second direction intersecting the first direction" can be understood as the angle between the second and first directions being less than or equal to 90 degrees, and "the third direction intersecting the first and second directions" can be understood as the angle between the third direction and the plane containing the first and second directions being less than or equal to 90 degrees. In some specific examples of this application, the angle between the second and first directions is equal to 90 degrees, and the angle between the third direction and the plane containing the first and second directions is equal to 90 degrees.

[0072] In some specific examples, the first direction can be understood as in Figures 4-26 The Z-axis direction shown in the figure, the second direction can be understood as in Figures 4-26 The X-axis direction shown in the figure, the third direction can be understood as in Figures 4-26 The Y-axis direction is shown in the figure.

[0073] Specifically, a substrate 50 is first provided, which extends in a second direction (X-axis direction) and a third direction (Y-axis direction) to form substrate stacking surfaces, and a stacked layer 201 is formed on the stacking surfaces. As an example, the substrate 50 can be selected according to the actual needs of the device, for example, it can include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, etc. Preferably, in this embodiment, the substrate 50 includes a single-crystal silicon substrate.

[0074] In some embodiments of this application, the substrate 50 is a semiconductor substrate. For example, the substrate can be a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. It should be noted that the substrate can be an ion-doped substrate, specifically, a P-type doped substrate or an N-type doped substrate. A suitable material can be selected as the substrate according to actual needs, and this application does not impose specific limitations in this regard. Of course, in other embodiments, the substrate material can also be a semiconductor or compound including other elements. For example, the substrate can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate, etc.

[0075] In some embodiments of this application, a deposition method is selected according to actual needs to form a multi-layered stacked layer 201 on the stacked surface. Figures 4 to 16 The number of stacked layers 201 is just an example. For example, the number of dielectric layers 30 and sacrificial layers 40 in stacked layers 201 can include 32, 64, 96 or 128 layers, etc. Specifically, the number of dielectric layers 30 and sacrificial layers 40 in stacked layers 201 can be set according to actual needs, that is, the number of stacked layers 201 is not limited.

[0076] In some embodiments of this application, a substrate may be provided, on which a stacked layer 201 is formed. The stacked layer 201 includes a dielectric layer 30 and a sacrificial layer 40 extending along a second direction (e.g., the X-axis direction) and a third direction (e.g., the Y-axis direction) and staggered along a first direction (Z-axis direction). In some embodiments, the substrate may be removed in subsequent processes to obtain a semiconductor device 100 excluding the substrate 50, or it may be retained to form a semiconductor device 100 including the substrate 50; no specific limitation is made herein.

[0077] In some embodiments of this application, the materials of the sacrificial layer 40 and the dielectric layer 30 are made of insulating materials, including but not limited to any one or any combination of polycrystalline silicon, silicon nitride, silicon oxide, and aluminum oxide. Here, silicon oxide refers to silicon oxide compounds, such as SixOy, and silicon nitride refers to silicon nitrogen compounds, such as SixNy. Exemplarily, the sacrificial layer 40 can be silicon nitride, and the dielectric layer 30 can be silicon oxide. The sacrificial layer 40 and the dielectric layer 30 have different etching selectivity, and the deposition methods of the sacrificial layer 40 and the dielectric layer 30 can be, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0078] refer to Figures 4 to 19 , Figure 25 and Figure 26 As shown, the stacked layer 201 is divided into a first region 202 and a second region 203. It should be noted that the distinction between the first region 202 and the second region 203 is for ease of explanation only and does not represent a physical division of the stacked layer 201 or the size of the stacked layer 201.

[0079] Step S200: Form a plurality of channel holes 33 in the first region 202 that penetrate the stacked layer 201 along a first direction (e.g., the Z-axis direction), and form a plurality of first virtual channel holes 34 in the second region 203 that penetrate the stacked layer 201 along the first direction.

[0080] In some embodiments of this application, step S200, which involves forming a plurality of channel holes 33 penetrating the stacked layer 201 along the first direction in the first region 202 and a plurality of first virtual channel holes 34 penetrating the stacked layer 201 along the first direction in the second region 203, includes:

[0081] Step S210: A composite photolithography layer 11 is formed on the dielectric layer 30 at the top of the stacked layer 201; and a plurality of first trenches 31 and a plurality of second trenches 32 are formed in the composite photolithography layer 11; the first trenches 31 are located in the first region 202, and the second trenches 32 are located in the second region 203.

[0082] In some embodiments of this application, reference is made to Figures 4 to 6 Show the structure formed in step S210. Figure 5 and Figure 6 The structure shown includes a substrate 50, a stacked layer 201 disposed in a first direction (Z-axis direction), a plurality of first regions 202 disposed in the stacked layer 201, and a second region 203 located between two first regions 202. A composite photolithography layer 11 is disposed on a dielectric layer 30 at the top of the stacked layer 201. A plurality of first trenches 31 formed in the composite photolithography layer 11 are located in the first regions 202. The stacked layer 201 aligned with the first regions 202 is etched to form a channel hole 33 in the following embodiment. A plurality of second trenches 32 in the composite photolithography layer 11 are located in the second regions 203. The stacked layer 201 aligned with the second regions 203 is etched to form a first virtual channel hole 34 in the following embodiment.

[0083] In some embodiments of this application, step S210, which involves forming a composite photolithography layer 11 on the dielectric layer 30 at the top of the stacked layer 201, includes:

[0084] Step S211: A stop layer 20 is formed on the top dielectric layer 30, and a first mask layer 10 is formed on the stop layer 20.

[0085] Step S212: Etch the first mask layer 10 through the stop layer 20 until the dielectric layer 30 on top of the stacked layer is exposed to form the composite photolithography layer 11.

[0086] In some embodiments of this application, reference is made to Figures 4 to 6 As shown, this application employs an etching process to form a plurality of channel holes 33 penetrating the stacked layer 201 located in the first region 202 along a first direction (e.g., the Z-axis direction), and employs an etching process to form a plurality of first virtual channel holes 34 penetrating the stacked layer 201 located in the second region 203 along a first direction (e.g., the Z-axis direction). The etching process used in the embodiments of this application can be dry etching or wet etching.

[0087] In some embodiments of this application, such as Figure 4 As shown, a stop layer 20 and a patterned first mask layer 10 can be sequentially formed on the dielectric layer 30 at the top of the stacked layer 201 using a deposition process. The dielectric layer 30 can be silicon oxide, and the material of the stop layer 20 includes silicon nitride or silicon oxynitride. In practical applications, the stop layer 20 and the first mask layer 10 can be formed using deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

[0088] In some embodiments of this application, the first mask layer 10 includes a hard mask layer or a photoresist layer.

[0089] In some embodiments of this application, the first mask layer 10 may be a photoresist layer (PR). In this case, a photoresist layer is formed on the stop layer 20, and the photoresist layer is exposed using a photomask. The exposed photoresist layer is then developed to remove any photoresist layers that have not been exposed to light, thereby forming a patterned photoresist layer on the stop layer 20. In some embodiments, the first mask layer 10 may also be a hard mask layer (HM).

[0090] In some embodiments of this application, such as Figure 5 and Figure 6As shown, the patterned first mask layer 10 has photolithographic openings. Using the patterned first mask layer 10 as a mask, the stop layer 20 is etched to form a first trench 31 and a second trench 32 on the stop layer 20 corresponding to the photolithographic openings. The first trench 31 exposes the dielectric layer 30 on top of the stacked layer 201 in the first region 202, and the second trench 32 exposes the dielectric layer 30 on top of the stacked layer 201 in the second region 203. Here, the etching of the stop layer 20 is performed, for example, using a dry etching process. In practical applications, the etching process can specifically be one of sputtering etching, chemical etching, or high-density plasma etching.

[0091] In some embodiments of this application, the process of etching the stop layer 20 is as follows: using the patterned first mask layer 10 as a mask, the stop layer 20 is etched to form a structure as shown in the image. Figure 6 The first groove 31 and the second groove 32b, whose bottom opening size is greater than or equal to the top opening size, are shown, or are formed as follows: Figure 5 The first groove 31 and the second groove 32a are shown with a bottom opening size smaller than the top opening size.

[0092] In some embodiments of this application, since there is a stop layer 20 under the first mask layer 10, the etching time can be extended so that the bottom opening size of the formed first trench 31 is greater than or equal to the top opening size, and the bottom opening size of the formed second trench 32b is greater than or equal to the top opening size.

[0093] In practical applications, when etching the stop layer 20, the opening size at the bottom of the first trench 31 and the opening size at the bottom of the second trench 32 are widened, thereby avoiding the footing phenomenon caused by the edge etching rate of the first mask layer 10 being less than the center etching rate of the first mask layer 10.

[0094] In this embodiment, a patterned first mask layer 10 is used as a mask to etch the stop layer 20, forming a second trench 32b with a bottom opening size greater than or equal to the top opening size. In practical applications, since there is a stop layer 20 under the first mask layer 10, the etching time can be extended, thereby widening the bottom opening size of the second trench 32b, so that the bottom opening size of the second trench 32b formed in the first mask layer 10 is greater than or equal to the top opening size. This application adds a stop layer 20 between the first mask layer 10 and the substrate, thereby avoiding the footing phenomenon caused by excessive byproducts generated from the reaction between the etching gas and the dielectric layer 30 of the stacked layer 201. Furthermore, during the etching of the first mask layer 10, this application widens the bottom opening size of the second trench 32b, thereby avoiding the footing phenomenon caused by the edge etching rate of the first mask layer 10 being less than the center etching rate.

[0095] In this embodiment, the etching of the stop layer 20 is performed, for example, by a dry etching process or a wet etching process. In practical applications, the etching solution selected for the wet etching process can be a phosphoric acid solution, which has a high etching selectivity and a high etching rate for the stop layer 20 (e.g., silicon nitride), while the etching rate for the first mask layer 10 (e.g., silicon oxide) is almost zero.

[0096] In practical applications, when the stop layer 20 is etched using a dry etching process, the opening size of the second trench can be controlled by controlling the dry etching time; when the stop layer 20 is etched using a wet etching process, the opening size of the second trench can be controlled by controlling the wet etching time and the concentration of the etching solution.

[0097] In this embodiment of the application, the patterned first mask layer 10 can also be removed before etching the stop layer 20 through the second trench 32b, thereby reducing contaminants generated by the first mask layer 10 being bombarded by etching gas during the etching process.

[0098] Step S220: Etch the stacked layer 201 in the first region 202 through the first trench 31 to form a plurality of the channel holes 33.

[0099] Step S230: Etch the stacked layer 201 in the second region 203 through the second trench 32 to form a plurality of first virtual channel holes 34.

[0100] In some embodiments of this application, reference is made to Figures 5 to 7 as well as Figure 17 Figure 22Show the structure formed in steps S220 to S230. Figure 7 The structure shown includes a substrate 50, a stacked layer 201 disposed in a first direction (Z-axis direction), a plurality of first regions 202 disposed in the stacked layer 201, and a second region 203 located between two first regions 202. The first region 202 includes a plurality of channel holes 33 penetrating the stacked layer 201, and the second region 203 includes a plurality of first virtual channel holes 34 penetrating the stacked layer 201. Figure 7 Area 53 in the middle is Figures 17 to 19 A cross-sectional view of semiconductor device 100 along line AA'. Figure 7 Area 52 in the middle is Figures 17 to 19 A cross-sectional view of semiconductor device 100 along line BB'. Figure 7 Area 51 in the middle is Figures 17 to 19 A cross-sectional view of semiconductor device 100 along line CC'.

[0101] Some embodiments of this application employ an etching process to form a plurality of channel holes 33 penetrating the stacked layer 201 located in the first region 202 along a first direction (e.g., the Z-axis direction), and to form a plurality of first virtual channel holes 34 penetrating the stacked layer 201 located in the second region 203 along the first direction (e.g., the Z-axis direction). The etching process used in some embodiments of this application can be dry etching or wet etching.

[0102] In some embodiments, the channel aperture 33 may further extend into the substrate 50 without penetrating the substrate 50, and the first virtual channel aperture 34 may further extend into the substrate 50 without penetrating the substrate 50.

[0103] In some embodiments of this application, the plurality of channel holes 33 may be arranged in an array.

[0104] In some embodiments, a plurality of channel holes 33 located in the first region 202 and a plurality of first virtual channel holes 34 located in the second region 203 can be formed in the same process, so that a plurality of channel holes 33 and the plurality of first virtual channel holes 34 are formed simultaneously in the first region 202 and the second region 203.

[0105] In some embodiments of this application, the plurality of channel holes 33 and the plurality of first virtual channel holes 34 are staggered and interleaved in the second direction.

[0106] In some embodiments of this application, the shape of the first virtual channel hole 34 includes, but is not limited to, any one of ellipse and circle, and the shape of the channel hole 33 includes circle. For example, as Figures 17-20 As shown, the shape of the first virtual channel hole 34 includes an ellipse, and the major axis of the ellipse is located in the third direction (Y-axis direction).

[0107] In some alternative embodiments, the ellipse described above can also be replaced by other shapes that can be obtained by compressing or stretching a centrally symmetric shape (such as a circle or a square) in a certain direction by a certain proportion (such as an oval, a rectangle, a rhombus, etc.).

[0108] For example, such as Figure 7 As shown, the diameter of the first virtual channel hole 34 is denoted as D, and the diameter of the channel hole 33 is denoted as L. The diameter D of the first virtual channel hole 34 and the diameter L of the channel hole 33 can be the same or different.

[0109] In some embodiments, the number of layers in the stacked layer 201 can be 8, 32, 64, or 128. When the number of layers in the stacked layer 201 is small, such as 8 layers, the stacked layer 201 can be directly deposited and formed, and then the via 33 and the first virtual via 34 can be simultaneously etched. When the number of layers in the stacked layer 201 is large, such as 128 layers, the stacked layer 201 can be divided into multiple parts, and the first sub-stacked layer 201 and the second sub-stacked layer 201 can be formed in two deposition processes, with the first sub-stacked layer 201 located above the second sub-stacked layer 201. In this case, the via 33 and the first virtual via 34 are also formed in two etching processes, that is, the via 33 and the first virtual via 34 are formed sequentially in the first sub-stacked layer 201 and the second sub-stacked layer 201.

[0110] Additionally, it should be noted that the dashed lines in the diagram are used to distinguish different structural parts and do not represent their actual existence. The dashed arrows in the diagram are used to indicate the distance or dimensions between two parts and do not indicate any actual connection.

[0111] In some exemplary embodiments of this application, before forming a through-hole 33 in a first region 202 and a first virtual through-hole 34 in a second region 203, a patterned first mask layer 10 is formed on the top surface of the stacked layer 201 to form a first trench 31 and a second trench 32. The vertical projection of the first trench 31 onto the top of the stacked layer 201 may at least substantially overlap with the location of the through-hole 33, and the vertical projection of the second trench 32 onto the top of the stacked layer 201 may at least substantially overlap with the location of the first virtual through-hole 34.

[0112] An appropriate etching process is performed on the first mask layer 10, for example, dry etching or wet etching, to remove a portion of the dielectric layer 30 and sacrificial layer 40 of the stacked layer 201 located in the first region 202 exposed by the first trench 31, thereby forming a structure as shown in the image. Figure 7The trench 33 shown is etched until the etched trench 33 exposes the substrate 50. Furthermore, a portion of the dielectric layer 30 and sacrificial layer 40 of the stacked layer 201 located within the second region 203, exposed by the second trench 32, is removed to form a trench 33 as shown. Figure 7 The first virtual channel hole 34 shown is etched until it exposes the substrate 50. In other words, the channel hole 33 and the first virtual channel hole 34 extend from the surface of the stacked layer 201 away from the substrate 50 to the stacked surface of the substrate 50, exposing the substrate 50, and a portion of the channel hole 33 and the first virtual channel hole 34 are located in the substrate 50 but do not penetrate the substrate 50. After forming the channel hole 33 and the first virtual channel hole 34, the first mask layer 10 can be removed.

[0113] It should be noted that multiple vias 33 and first virtual vias 34 can be formed simultaneously on the stacked layer 201. That is, the first mask layer 10 can form multiple first trenches 31 corresponding to the multiple vias 33, and multiple second trenches 32 corresponding to the multiple first virtual vias 34. The positions of the multiple first trenches 31 correspond to the positions of the subsequently formed multiple vias 33, and the positions of the multiple second trenches 32 correspond to the positions of the subsequently formed multiple first virtual vias 34. In some embodiments of this application, the number, size, and arrangement of the vias 33 and the first virtual vias 34 are not specifically limited. Figure 7 , Figures 17 to 26 The channel hole 33 and the first virtual channel hole 34 shown are merely examples and are not intended to limit the position and number of the channel hole 33 and the first virtual channel hole 34.

[0114] In some embodiments of this application, a first virtual channel hole 34 is formed along a first direction (e.g., the Z-axis direction) through the stacked layer 201 using, for example, a dry / wet etching process, and the first virtual channel hole 34 may further extend into the substrate 50. The formation process of the first virtual channel hole 34 can be essentially the same as that of the channel hole 33, that is, in the embodiments of this application, the first virtual channel hole 34 can be regarded as the channel hole 33, except that the first virtual channel hole 34 located in the second region 203 is not used to form the channel structure 330, but to form a gate line slot trench 101 for isolating multiple channel structures 330.

[0115] In some embodiments of this application, when etching a channel via 33 onto the stacked layer 201 in the first region 202, a first virtual channel via 34 is formed onto the stacked layer 201 in the second region 203 using the same process. This allows for the simultaneous etching of the channel via 33 in the first region 202 and the first virtual channel via 34 in the second region 203. Subsequently, through a series of processes, a channel structure 330 is formed in the channel via 33 in the first region 202, and a gate isolation structure 102 is formed in the first virtual channel via 34 in the second region 203. The semiconductor device 100 manufactured according to some embodiments of this application has low manufacturing cost and solves the yield loss problem caused by the tilt of the channel structure 330 and the gate isolation structure 102.

[0116] Step S300: Form a plurality of channel structures 330 in the plurality of channel holes 33.

[0117] In some embodiments of this application, prior to step S300 of forming a plurality of channel structures 330 in the plurality of channel holes 33, the method further includes:

[0118] Step S250: Fill the channel hole 33 and the first virtual channel hole 34 with sacrificial material 60.

[0119] In some embodiments of this application, Figure 8 Show the structure formed by step S250. Figure 8 The structure shown includes a substrate 50, a stacked layer 201 disposed in a first direction (Z-axis direction), a plurality of first regions 202 disposed in the stacked layer 201, and a second region 203 located between two first regions 202. The first region 202 includes a plurality of channel holes 33 penetrating the stacked layer 201, and the second region 203 includes a plurality of first virtual channel holes 34 penetrating the stacked layer 201. The plurality of channel holes 33 and the plurality of first virtual channel holes 34 are all filled with sacrificial material 60.

[0120] Step S270: Remove the sacrificial material 60 from the channel hole 33.

[0121] In some embodiments of this application, after step S250 of filling the channel hole 33 and the first virtual channel hole 34 with sacrificial material 60, and before step S270 of removing the sacrificial material 60 from the channel hole 33, the method further includes:

[0122] Step S260: Form a capping layer 71 on top of the stacked layer 201, and remove the capping layer 71 located above the channel hole 33.

[0123] In some embodiments of this application, Figures 9 to 11 Show the structure formed by steps S260 to S270. Figure 9 The structure shown includes a substrate 50, a stacked layer 201 disposed in a first direction (Z-axis direction), a plurality of first regions 202 disposed in the stacked layer 201, and a second region 203 located between two first regions 202. The first region 202 includes a plurality of channel holes 33 penetrating the stacked layer 201, and the second region 203 includes a plurality of first virtual channel holes 34 penetrating the stacked layer 201. The channel holes 33 and the first virtual channel holes 34 are filled with sacrificial material 60, and a capping layer 71 is also provided above the stacked layer 201. The capping layer 71 covers the channel holes 33 filled with sacrificial material 60 and the first virtual channel holes 34 filled with sacrificial material 60. Figure 10 Showing the structure formed in step S260, Figure 10 The structure shown is relatively Figure 9 In the structure shown, the cap layer 71 located above the channel hole 33 is removed. Figure 11 The structure shown is relatively Figure 10 In terms of the structure shown, the channel hole 33 is in Figure 8 The sacrificial material 60 that was filled is removed, the first virtual channel hole 34 is filled with sacrificial material 60 and a capping layer 71a is provided above the first virtual channel hole 34.

[0124] In some embodiments, a capping layer 71 may be formed on the side of the stacked layer 201 away from the substrate 50 using a thin-film deposition process to cover the top of the stacked layer 201. The capping layer 71 may be made of a dielectric material such as silicon oxide.

[0125] like Figure 8 As shown, deposition processes can be used to separately... Figure 7 The channel holes 33 and the first virtual channel holes 34 shown are filled with sacrificial material 60, and then a deposition process can be used to form a structure on top of the stacked layer 201, such as... Figure 9 The cap layer 71 is shown. (As shown) Figure 10 As shown, the capping layer 71 above the channel hole 33 is removed by an etching process, while the capping layer 71a above the first virtual channel hole 34 is retained. The capping layer 71a covers the first virtual channel hole 34, and the projection of the capping layer 71a and the channel hole 33 on the substrate 50 does not overlap, i.e., as shown... Figure 10 The capping layer 71a shown covers the first virtual channel hole 34 but does not cover the channel hole 33. The material of the capping layer 71a is different from the sacrificial material 60. The sacrificial material 60 located in the channel hole 33 can be removed using an etching process to obtain the desired result. Figure 11 The semiconductor structure shown.

[0126] In some embodiments, the sacrificial material 60 may be, but is not limited to, any one or any combination of carbon, polycrystalline silicon, silicon nitride, silicon oxide, and aluminum oxide. In this embodiment, the sacrificial material 60 may be carbon or polycrystalline silicon, etc.

[0127] In some embodiments, both the via 33 and the first virtual via 34 may extend further into the substrate 50 without penetrating the substrate 50.

[0128] Additionally, it should be noted that after removing the sacrificial material 60 located in the channel hole 33, the capping layer 71a located above the first virtual channel hole 34 can be removed.

[0129] In some embodiments of this application, Figure 12 The steps involved in forming step S300 are shown. Figure 12 The structure shown includes a substrate 50, a stacked layer 201 disposed in a first direction (Z-axis direction), a plurality of first regions 202 disposed in the stacked layer 201, and a second region 203 located between two first regions 202. The first regions 202 include a plurality of channel structures 330 penetrating the stacked layer 201, and the second region 203 includes a plurality of first virtual channel vias 34 penetrating the stacked layer 201. The first virtual channel vias 34 are filled with a sacrificial material 60, and a capping layer 71a is disposed above the first virtual channel vias 34. A conductive layer 75 covers the top of the stacked layer 201. Figure 12 The conductive layer 75a shown covers the channel structure 330, and the conductive layer 75b covers the capping layer 71a above the first virtual channel hole 34 filled with sacrificial material 60.

[0130] In practical applications, such as Figure 12 As shown, a conductive layer 75 is deposited above the capping layer 71a and the channel structure 330 by a deposition process. The deposition rate of the conductive layer 75b above the capping layer 71a is less than the deposition rate of the conductive layer 75a above the channel structure 330, so that the thickness of the conductive layer 75b deposited above the capping layer 71a along the first direction is less than the thickness of the conductive layer 75a deposited above the channel structure 330 along the first direction.

[0131] In some embodiments, the conductive layer 75 may be any or a combination of ruthenium (Ru), iridium (Ir), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), doped silicon, silicide, or the above materials.

[0132] Specifically, the channel structure 330 can be formed by depositing multiple deposition processes on the channel vias 33. In some embodiments, the channel structure 330 includes a functional layer (poly channel layer) and a channel layer. That is, the functional layer (poly channel layer) and the channel layer can be deposited sequentially on the channel vias 33 through multiple deposition processes to form a channel structure 330 with storage function. The functional layer in the channel structure 330 is the key structure for the three-dimensional memory to complete the storage function. Specifically, the functional layer includes a silicon oxide-silicon nitride-silicon oxide (ONO) structure sequentially formed on the outer wall of the channel structure 330. That is, the sidewall of the channel structure 330 has a functional layer of silicon oxide-silicon nitride-silicon oxide (ONO) structure sequentially formed radially from the outside to the inside. Each gate layer 41 can contact the corresponding ONO structure functional layer to form multiple memory cells. In each memory cell, the gate layer 41 can contact the corresponding ONO structure functional layer, and the gate layer 41 can control the corresponding ONO structure to achieve the storage function by capturing charge. The functional layers of the ONO structure include a blocking layer, a charge trapping layer, and a tunneling layer. Furthermore, the blocking layer, the charge trapping layer, the tunneling layer, and the channel layer can be sequentially deposited on the inner wall of the channel hole 33 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof.

[0133] The barrier layer can be formed on the surface of the inner wall of the channel via 33 to block the outflow of charge (electrons or holes) stored in the charge trapping layer and to provide electrical insulation between the charge trapping layer and the stacked structure 204. Optionally, the material of the barrier layer may include, but is not limited to, silicon oxide (SiO2) and a high-k dielectric. In some embodiments, the material of the barrier layer may be a high-k dielectric. High-k dielectric materials have a thinner equivalent oxide thickness (EOT), which can effectively reduce gate leakage current while maintaining transistor performance. High-k dielectrics may be, for example, aluminum oxide, hafnium oxide, or zirconium oxide. The barrier layer may be a single-layer dielectric oxide or a multilayer model, such as high-k oxide and silicon oxide.

[0134] The charge trapping layer may be formed on the inner surface of the barrier layer. Optionally, the material of the charge trapping layer may include, but is not limited to, silicon nitride (SiN). In another embodiment, the charge trapping layer may be a multilayer structure, such as a SiN / SiON / SiN multilayer structure.

[0135] The tunneling layer may be formed on the surface of the charge trapping layer. Optionally, the material of the tunneling layer may include, but is not limited to, silicon oxide (SiO2). In some embodiments, the tunneling layer may also be a multilayer structure, such as a SiO / SiON / SiO2 multilayer structure.

[0136] The aforementioned barrier layer, charge trapping layer, and tunneling layer can be referred to as functional layers. It should be understood that the functional layers can be the storage structure of the fabricated three-dimensional memory, and the portions of the functional layers corresponding to each gate layer 41 can form independent storage cells. Each storage cell can be controlled by the gate layer 41. Charge is stored or released in the functional layer corresponding to the gate layer 41 to realize the function of a single storage cell.

[0137] The channel layer may be formed on the surface of the tunneling layer. Optionally, the material of the channel layer may include, but is not limited to, doped polysilicon.

[0138] It should be understood that some embodiments of this application may form multiple channel structures 330 that penetrate the stacked layer 201 and extend to the substrate 50. The number and arrangement of the channel structures 330 can be prepared according to actual storage requirements. The number and arrangement of the channel structures 330 shown in the figure are merely examples and do not represent the number and arrangement of the channel structures 330 in the final semiconductor structure.

[0139] Step S400: Form a grid line slot trench 101 extending in a second direction (e.g., the X-axis direction) and surrounding the plurality of first virtual channel holes 34, the second direction intersecting the first direction.

[0140] In some embodiments of this application, prior to step S400, the method further includes: forming the gate wire slot trench 101 extending in a second direction (e.g., the X-axis direction) and surrounding the plurality of first virtual channel holes 34.

[0141] Step S350: Remove the sacrificial material 60 from the first virtual channel hole 34.

[0142] In some embodiments of this application, after step S300 of forming a plurality of channel structures 330 in the plurality of channel holes 33, and before step S350 of removing the sacrificial layer 40 in the first virtual channel hole 34, the method further includes:

[0143] Step S310: A protective layer 80 is formed on top of the stacked layer 201.

[0144] In some embodiments of this application, Figure 13 Show the structure formed by step S310. Figure 13The structure shown includes a substrate 50, a stacked layer 201 disposed in a first direction (Z-axis direction), a plurality of first regions 202 disposed in the stacked layer 201, and a second region 203 located between two first regions 202. The first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201, such as the channel structure 330 forming an ONO structure with reference to the embodiment corresponding to step S300 above. The second region 203 includes a plurality of first virtual channel holes 34 penetrating the stacked layer 201. The first virtual channel holes 34 are filled with sacrificial material 60, and a capping layer 71a is provided above the first virtual channel holes 34. A conductive layer 75 covers the top of the stacked layer 201. In addition, a protective layer 80 is provided above the conductive layer 75.

[0145] In practical applications, a protective layer 80 is deposited over the conductive layer 75 using a deposition process. The protective layer 80 may include any one or any combination of carbon, polycrystalline silicon, silicon nitride, silicon oxide, and aluminum oxide. In the embodiments of this application, the protective layer 80 includes polycrystalline silicon.

[0146] In some embodiments of this application, Figure 14 Show the structure formed by step S350. Figure 14 The structure shown includes a substrate 50, a stacked layer 201 disposed in a first direction (Z-axis direction), a plurality of first regions 202 disposed in the stacked layer 201, and a second region 203 located between two first regions 202. Each first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201. The second region 203 includes a plurality of first virtual channel vias 34 penetrating the stacked layer 201. A capping layer 71a is disposed above the top dielectric layer 30 located on both sides of the first virtual channel vias 34. A conductive layer 75 is disposed above the channel structures 330, and a protective layer 80 is disposed above the conductive layer 75. In practical applications, the sacrificial material 60 filling the first virtual channel vias 34 in the second region 203 is removed by an etching process.

[0147] In some embodiments of this application, step S400 specifically includes forming the grid slot trench 101 extending in a second direction (e.g., the X-axis direction) and surrounding the plurality of first virtual channel holes 34:

[0148] Step S410: Etch a plurality of first virtual channel holes 34 to form a plurality of second virtual channel holes 35, and connect the plurality of second virtual channel holes 35 in the second direction to form the gate wire slot trench 101.

[0149] In some embodiments of this application, Figure 14 The S410 step shows the formation of a structure including multiple second virtual channel holes 35. Figure 14The structure shown includes a substrate 50, a stacked layer 201 disposed in a first direction (Z-axis direction), a plurality of first regions 202 disposed in the stacked layer 201, and a second region 203 located between two first regions 202. The first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201, a conductive layer 75 disposed above the channel structures 330, and a protective layer 80 disposed above the conductive layer 75. The second region 203 includes a plurality of second virtual channel vias 35 penetrating the stacked layer 201.

[0150] In some embodiments of this application, Figure 15 , Figures 23 to 26 The S410 step shows the formation of a structure including the grid line slot trench 101. Figure 15 , Figures 23 to 26 The structure shown includes a substrate 50, a stacked layer 201 disposed in a first direction (Z-axis direction), a plurality of first regions 202 disposed in the stacked layer 201, and a second region 203 located between two first regions 202. Each first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201, with a conductive layer 75 disposed above the channel structures 330 and a protective layer 80 disposed above the conductive layer 75. The second region 203 includes a plurality of gate line slot trenches 101 penetrating the stacked layer 201, the gate line slot trenches 101 extending along a second direction and surrounding the substrate 50. Figure 23 , Figure 24 The multiple second virtual channel holes 35 shown.

[0151] This application can be processed by etching. Figure 13 The plurality of first virtual channel holes 34 shown are etched isotropically to enlarge the aperture of the plurality of first virtual channel holes 34, thereby forming a plurality of... Figure 23 , Figure 24 The second virtual channel via 35. The process of forming the second virtual channel via 35 in this application can be as follows: a protective layer 80 and a conductive layer 75 deposited on top of the stacked layer 201 of the second region 203 are sequentially penetrated by a dry etching process, and then multiple second virtual channel vias 35 are formed by a wet etching process. The second virtual channel vias 35 penetrate the stacked layer 201 located in the second region 203 along a first direction (e.g., the Z-axis direction), and the aperture of the second virtual channel vias 35 is greater than or equal to the aperture of the first virtual channel vias 34, so that multiple second virtual channel vias 35 extend along a second direction, and two adjacent second virtual channel vias 35 partially overlap or partially overlap along the second direction to form a gate line slot trench 101 that is connected along the second direction and surrounds multiple first virtual channel vias 34.

[0152] For example, such as Figure 7 and Figure 14As shown, the diameter of the second virtual channel hole 35 is denoted as M, the diameter of the first virtual channel hole 34 is denoted as D, and the diameter of the channel hole 33 is denoted as L. The diameter M of the second virtual channel hole 35 is greater than or equal to the diameter D of the first virtual channel hole 34, that is, M≥D.

[0153] In some exemplary embodiments of this application, before forming the second virtual channel hole 35 penetrating the stacked layer 201 within the second region 203, a patterned second mask layer (not shown) is formed on the top surface of the stacked layer 201. A third trench (not shown) corresponding to the second virtual channel hole 35 is formed in the patterned second mask layer, the vertical projection of the third trench onto the top of the stacked layer 201 at least substantially overlapping the position of the second virtual channel hole 35. By providing the second mask layer, the etching location of the second virtual channel hole 35 can be determined quickly and accurately.

[0154] After exposing the etching location of the second virtual trench 35, an appropriate etching process is performed, for example, dry etching or wet etching, to remove part of the dielectric layer 30 and sacrificial layer 40 of the stacked layer 201 located in the second region 203 exposed by the third trench, thus forming a structure as shown in the image. Figure 14 , Figure 23 and Figure 24 The second virtual channel vias 35 shown extend along a second direction until the first virtual channel vias 34 formed by etching expose the substrate 50. Adjacent second virtual channel vias 35 partially overlap or intersect along the second direction to form a gate line slot trench 101 that connects along the second direction and surrounds the multiple first virtual channel vias 34. The second virtual channel vias 35 extend from the surface of the stacked layer 201 away from the substrate 50 to the stacked surface of the substrate 50, exposing the substrate 50. A portion of the second virtual channel via 35 is located within the substrate 50 but does not penetrate it. After the second virtual channel vias 35 are formed, the second mask layer can be removed.

[0155] In some embodiments, the shape of the second virtual channel hole 35 includes either an ellipse or a circle. In some alternative embodiments, the ellipse can also be replaced by other shapes that can be obtained by compressing or stretching a centrally symmetrical shape (e.g., a circle or a square) in a certain direction or by stretching it by a certain proportion (e.g., an oval, a rectangle, a rhombus, etc.).

[0156] Step S500: A grid line isolation structure 102 is formed in the grid line slot groove 101. The grid line isolation structure 102 has a concave-convex shape along a third direction; the third direction intersects the first direction and the second direction.

[0157] In some embodiments of this application, Figure 16 , Figures 23 to 26 The structure formed in step S500 is shown. The formed structure includes a substrate 50, a stacked layer 201 disposed in a first direction (Z-axis direction), a plurality of first regions 202 disposed in the stacked layer 201, and a second region 203 located between two first regions 202. Each first region 202 includes a plurality of channel structures 330 penetrating the stacked layer 201, a conductive layer 75 disposed above the channel structures 330, and a protective layer 80 disposed above the conductive layer 75. The second region 203 includes a plurality of gate line slot trenches 101 penetrating the stacked layer 201.

[0158] This application can be performed using a deposition process. Figure 15 The multiple grid line slot trenches 101 shown are filled with conductive material to form multiple... Figure 16 , Figures 23 to 26 The second region 203 shown has a gate line isolation structure 102. The gate line isolation structure 102 extends through the stacked structure 204 along a first direction, extends along a second direction, and has an uneven shape along the second direction.

[0159] In some embodiments, the conductive material may include any or a combination of ruthenium (Ru), iridium (Ir), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), doped silicon, silicide, or a combination of the above materials.

[0160] It should be understood that this application may form multiple through-stacking structures 204 extending to the substrate 50, but not through the gate isolation structures 102 of the substrate 50. The multiple gate isolation structures 102 and multiple channel structures 330 are spaced and staggered in a third direction (e.g., the Y-axis direction) to separate the multiple channel structures 330 by the gate isolation structures 102. The number and arrangement of the gate isolation structures 102 in the embodiments of this application can be fabricated according to actual storage requirements.

[0161] In some embodiments of this application, before S500 forms the gate line isolation structure 102 in the gate line slot trench 101, the method further includes replacing the sacrificial layer 40 in the stacked layer 201 with the gate line layer 41.

[0162] In some embodiments of this application, the stacked structure 204 located in the first region 202 and the stacked structure 204 located in the second region 203 both include alternately stacked dielectric layers 30 and gate line layers 41. It is understood that, initially, both the stacked structure 204 located in the first region 202 and the stacked structure 204 located in the second region 203 include a stacked layer 201 of alternately stacked dielectric layers 30 and sacrificial layers 40. In subsequent processes, the sacrificial layers 40 are replaced with gate line layers 41 to obtain the stacked structure 204.

[0163] In some embodiments of this application, the material of the gate layer 41 may include any or a combination of ruthenium (Ru), iridium (Ir), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), doped silicon, silicide, or the above materials. In this application, the gate layer 41 may be metallic tungsten.

[0164] In some embodiments of this application, the stacked layer 201 includes a core region 301 and a stepped region 302;

[0165] A plurality of first virtual channel holes 34 with equal diameters are formed in the core area 301 and the stepped area 302 along the third direction.

[0166] In some embodiments of this application, the semiconductor device 100 may have a core region, a stairstep region 302, and a peripheral region (not shown in the figures). The core region 301 is the region for forming memory cells, the stairstep region 302 is the region for forming word line connection circuits, and the peripheral region is the region for forming peripheral circuits. Adjacent first regions 202 are separated by a gate line isolation structure 102, which may extend through the core region 301 and the stairstep region 302.

[0167] See Figure 17 As shown, in this embodiment, both the core region 301 and the stepped region 302 of the stacked layer 201 are provided with a plurality of first virtual channel holes 34 arranged alternately along the second direction, and the plurality of first virtual channel holes 34 penetrate the stacked layer 201 along the first direction. A plurality of first virtual channel holes 34 with equal diameters along the third direction are formed in the core region 301, and a plurality of first virtual channel holes 34 with equal diameters along the third direction are formed in the stepped region 302. Furthermore, the dimensions of each first virtual channel hole 34 in the core region 301 along the third direction are the same as the dimensions of each first virtual channel hole 34 in the stepped region 302 along the third direction. The process of forming a plurality of first virtual channel holes 34 in the stacked layer 201 is described in the embodiment corresponding to step S230 above, and will not be repeated here.

[0168] In some embodiments of this application, the stacked layer 201 includes a core region 301 and a stepped region 302;

[0169] The diameter of the plurality of first virtual channel holes 34 formed in the core area 301 along the third direction is smaller than the diameter of the plurality of first virtual channel holes 34 formed in the stepped area 302 along the third direction.

[0170] In some embodiments of this application, see Figure 18 and Figure 19As shown, in this embodiment, both the core region 301 and the stepped region 302 of the stacked layer 201 are provided with a plurality of first virtual channel holes 34 arranged alternately along the second direction, and the plurality of first virtual channel holes 34 penetrate the stacked layer 201 along the first direction. A plurality of first virtual channel holes 34 with equal diameters along the third direction are formed in the core region 301, and a plurality of first virtual channel holes 34 with equal diameters along the third direction are formed in the stepped region 302. Furthermore, the size of each first virtual channel hole 34 in the core region 301 along the third direction is smaller than the size of each first virtual channel hole 34 in the stepped region 302 along the third direction. The process of forming a plurality of first virtual channel holes 34 in the stacked layer 201 is described in the embodiment corresponding to step S230 above, and will not be repeated here.

[0171] refer to Figure 18 As shown, the dimensions of each first virtual channel hole 34 in the core area 301 along the third direction are smaller than the dimensions of each first virtual channel hole 34 in the stepped area 302 along the third direction.

[0172] refer to Figure 19 As shown, the dimensions of each first virtual channel hole 34 in the core area 301 along the third direction are smaller than the total dimensions of the multiple first virtual channel holes 34 connected side by side in the third direction in the stepped area 302 along the third direction, that is, the sum of the dimensions of the multiple first virtual channel holes 34 along the third direction.

[0173] In some embodiments, the first virtual channel via 34 located in the core region 301 and the first virtual channel via 34 located in the stepped region 302 can be formed in the same process, so as to achieve the purpose of forming the first virtual channel via 34 in both the core region 301 and the stepped region 302 without increasing the cost. In some embodiments, the first virtual channel via 34 can penetrate the stacked layer 201 and extend into the substrate 50 without penetrating the substrate 50.

[0174] The stepped area 302 can be located on both sides of the core area 301, or the core area 301 can be located on both sides of the stepped area 302, without any specific limitation.

[0175] In this application, when etching the stacked layer 201 in the first region 202 to form the channel via 33, the same process is used to etch the stacked layer 201 in the second region 203 to form the first virtual channel via 34, thereby achieving a single etching process for the channel via 33 in the first region 202 and the first virtual channel via 34 in the second region 203. Subsequently, through a series of processes, the channel via 33 in the first region 202 is used to form the channel structure 330, and the first virtual channel via 34 in the second region 203 is used to form the gate isolation structure 102. The semiconductor device 100 of this application has a low manufacturing cost and solves the yield loss problem caused by the tilt of the channel structure 330 and the gate isolation structure 102.

[0176] The layout design of the first mask in this application is as follows: Figure 17 As shown, Figure 17 A channel structure 330 for realizing storage function can be formed within the channel hole 33. Figure 17 The first virtual channel hole 34 is formed to form the gate line gap trench 101. In this application, while etching to form the channel hole 33 located in the first region 202, the first virtual channel hole 34 located in the second region 203 is also etched. From the perspective of the overall process, one etching operation can be reduced, thereby significantly reducing the device manufacturing cost.

[0177] In this embodiment, a grid line slot groove 101 is formed in a first virtual channel hole 34 that is formed simultaneously with the channel hole 33. This ensures that the inclination of the formed channel hole 33 and the first virtual channel hole 34 is essentially consistent, effectively avoiding yield loss caused by mutual inclination between the channel hole 33 and the first virtual channel hole 34. Furthermore, since the channel hole 33 and the first virtual channel hole 34 are formed simultaneously, the function of the first virtual channel hole 34 is equivalent to that of the grid line slot hole, thus omitting the subsequent process step of forming the grid line slot hole and effectively reducing process costs. Additionally, because the channel hole 33 and the first virtual channel hole 34 are formed simultaneously, a grid line isolation structure 102 is formed through the first virtual channel hole 34 in the second region 203, resolving the influence of mutual inclination between the channel structure 330 in the first region 202 and the grid line isolation structure 102 in the second region 203.

[0178] For example, such as Figures 4 to 16As shown, a stacked layer 201 is first deposited and formed, comprising a dielectric layer 30 and a sacrificial layer 40. The dielectric layer 30 can be SiN, and the sacrificial layer 40 can be SiO. Then, a first mask layer 10 (e.g., a hard mask layer or a photoresist layer) is formed on top of the stacked layer 201. Photolithographic patterning is performed through the first mask layer 10, and openings are made in the first region 202 and the second region 203 to form first trenches 31 and second trenches 32, respectively. Multiple channel holes 33 are formed in the first region 202 through multiple first trenches 31, and multiple first virtual channel holes 34 are formed in the second region 203 through multiple second trenches 32. Sacrificial material 60 is filled into the channel holes 33 and the first virtual channel holes 34, respectively, followed by cap oxide. Subsequently, the cap oxide formed on top of the channel holes 33 in the first region 202 and the sacrificial material 60 filled in the channel holes 33 are removed sequentially. Next, a channel structure 330 is formed within the via 33, and a protective layer 80 is formed on the stacked layer 201. The material of the protective layer 80 may include polysilicon. Then, the protective layer 80 formed on top of the stacked layer 201 in the second region 203 is removed, and the sacrificial material 60 previously filled in the first virtual via 34 is removed. A wet etching process is used to remove the stacked layer 201 in the second region 203 through the first virtual via 34, forming a gate line slot trench 101 with an uneven shape along the second direction. Then, the sacrificial layer 40 of the stacked layer 201 is replaced with a gate line layer 41 to obtain the stacked structure 204. Finally, a gate line isolation structure 102 is formed in the gate line slot trench 101.

[0179] The layout design of the first mask layer 10 in this application is as follows: Figures 17 to 19 As shown, in some embodiments, the shape and size of the first virtual channel hole 34 located in the second region 203 can be set arbitrarily, as long as the first virtual channel hole 34 located in the second region 203 and the channel hole 33 located in the first region 202 are formed in the same process. In this way, a grid line isolation structure 102 with a concave-convex shape along the second direction can be formed through the first virtual channel hole 34.

[0180] In this embodiment, the first virtual channel hole 34 can have various sizes and shapes, thereby forming a virtual channel hole 34 of various sizes and shapes. Figures 23 to 26 The grid line slot groove 101 is shown. For example, as shown... Figure 20 The diagram shown is a top view of the opening dimensions of the first virtual channel aperture 34 and channel aperture 33 along the X-axis and Y-axis directions on the top of the stacked layer 201, as measured after development inspection (ADI). Figure 20The upper and lower rows of channel holes 33 along the Y-axis are circular in shape, and the first virtual channel hole 34 located between the upper and lower rows of channel holes 33 is elliptical, with the major axis of the ellipse along the Y-axis and the minor axis along the X-axis. Figure 20 The layout design shown is obtained by etching the stacked layer 201 as follows. Figure 21 and Figure 22 The first virtual channel hole 34 and channel hole 33 are shown. Figure 21 This is a top view schematic diagram of the after-development inspection (AEI) opening dimensions of the first virtual channel vias 34 and 33 along the X-axis and Y-axis directions on the top of the stacked layer 201, i.e., AEITOP CD. Figure 22 This is a top view schematic diagram of the after-development inspection (AEI) opening dimensions of the first virtual channel holes 34 and 33 along the X-axis and Y-axis directions at the bottom of the stacked layer 201, i.e., AEIBottom CD. Figure 21 and Figure 22 As shown, based on Figure 20 The etching process forms a first virtual channel hole 34 and a channel hole 33. The opening size of the first virtual channel hole 34 and the channel hole 33 at the top of the stacked layer 201 (i.e., the side of the stacked layer 201 away from the substrate 50) along the first direction and the second direction is greater than the opening size of the first virtual channel hole 34 and the channel hole 33 at the bottom of the stacked layer 201 (i.e., the side of the stacked layer 201 away from the substrate 50) along the first direction and the second direction.

[0181] In this application, the wet etching process achieves a T / B (Top / Bottom remove distance ratio, i.e., the top / bottom removal size ratio) > 0.9. Consequently, the B / T (Bottom / Top, i.e., the ratio of the bottom dimension of the gate line slot trench 101 along the third direction to the top dimension of the gate line slot trench 101 along the third direction) of the resulting equivalent gate line slot trench 101 is approximately 0.83. The spacing between the gate line slot trench 101 and the adjacent channel structure 330 along the second direction is controlled by the wet etching duration, ensuring sufficient window space.

[0182]

[0183]

[0184]

[0185] Table 1. Top and bottom removal dimensions of the gate slot trench 101 formed by wet etching.

[0186] Wherein, F satisfies half the difference between J, G, and P, and G satisfies the sum of twice E and Q. In other words, the above parameters satisfy the following formula:

[0187] F = (JGP) / 2

[0188] For example, F1 = (J - G1 - P1) / 2, F2 = (J - G2 - P2) / 2.

[0189] G satisfies twice the sum of E and Q. That is, the above parameters satisfy the following formula:

[0190] G = Q + 2E

[0191] For example, G1 = Q1 + 2E1, G2 = Q2 + 2E2.

[0192] G satisfies twice the sum of R and I. That is, the above parameters satisfy the following formula:

[0193] G = I + 2R

[0194] Generally, G is greater than I. For example, G1 = I1 + 2R1, G2 = I2 + 2R2, where R1 and R2 are both greater than zero.

[0195] H satisfies the condition that half of G minus half of the square root, where the square root is the square of G minus the square of K. In other words, the above parameters satisfy the following formula:

[0196]

[0197] For example,

[0198] Based on the method for manufacturing the semiconductor device 100 described in the embodiments of this application, the embodiments of this application also provide a semiconductor device 100, which includes the following in some embodiments:

[0199] Stacked structure 204; the stacked structure 204 includes interleaved dielectric layers 30 and gate line layers 41, and the stacked structure 204 includes a first region 202 and a second region 203;

[0200] A channel structure 330 located in the first region 202 and penetrating the stacked structure 204 along the first direction;

[0201] A gate line isolation structure 102 is located in the second region 203 and extends along the second direction. The gate line isolation structure 102 penetrates the stacked structure 204 along the first direction. The shape of the gate line isolation structure 102 along the third direction is concave and convex. The second direction intersects the first direction, and the third direction intersects the first direction and the second direction.

[0202] In some embodiments of this application, the material of the gate layer 41 may include any or a combination of ruthenium (Ru), iridium (Ir), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), doped silicon, silicide, or the above materials.

[0203] It should be understood that the structure and manufacturing process of each component of the semiconductor device 100 in the embodiments of the present invention can be referred to the above-described embodiments of the manufacturing method of the semiconductor device 100, and will not be repeated here.

[0204] In some embodiments, a protective layer 80 is provided on top of the stacked structure 204.

[0205] In some embodiments, the protective layer 80 comprises polycrystalline silicon.

[0206] In some embodiments, the grid isolation structure 102 includes a sidewall extending along the second direction, the sidewall including a plurality of end-to-end substructures 70, and adjacent substructures 70 are not coplanar.

[0207] In some embodiments of this application, it should be noted that the unevenness described in these embodiments refers to the projection of the gate isolation structure 102 onto the bottom of the stacked structure 204 or the surface of the substrate 50. Its sidewalls are not straight, but rather line segments with bends or curves at a certain angle. Optionally, in this embodiment, the sidewalls include multiple substructures 70 connected end-to-end along the extension direction of the gate isolation structure 102, i.e., the second direction, and adjacent substructures 70 are not coplanar.

[0208] Please continue reading Figure 25 and Figure 26 As shown, the shape of the gate wire isolation structure 102 provided in this embodiment is as follows: Figure 25 and Figure 26 As shown, the projection of the sidewall of the gate isolation structure 102 onto the bottom surface of the stacked structure 204 or the surface of the substrate 50 is a broken line or curve composed of multiple line segments. That is, in this embodiment, by changing the shape of the gate isolation structure 102, the sidewall of the final gate isolation structure 102 is a concave-convex curved surface, that is, a structure formed by multiple substructures 70 with different directions. The specific shape of the concave-convex shape is not limited in this embodiment; the concave-convex shape includes concave portions and convex portions adjacent to each other. Optionally, the concave-convex shape may include... Figure 25 and Figure 26 The diagram shows wave-like shapes with different curvatures and polygonal lines with different angles. It is important to note that... Figure 25 and Figure 26 This is merely an example of the shape of the gate isolation structure 102 and does not indicate that adjacent structures need to appear simultaneously in the same semiconductor device 100. Figures 25-26 The various shapes of the grid isolation structure 102 shown.

[0209] In this embodiment, the bending direction of the multiple substructures 70 is not limited. Since the location where the gate groove is set in the prior art is relatively wide, the bending direction of the multiple substructures 70 can be set according to the width of this location. Since the bending direction of each substructure 70 is different, and the internal stress of the material is perpendicular to the sidewall of the gate isolation structure 102, each substructure 70 has its own corresponding internal stress. The direction of the internal stress of the material on the substructures 70 in different directions is different, which ultimately makes the direction of the internal stress of the material on the multiple substructures 70 not singular. This reduces the sum of the internal stress of the material on the sidewall of the gate isolation structure 102 as a whole, and avoids the sidewall of the gate isolation structure 102 from tilting or twisting under the action of large internal stress, which would lead to insufficient subsequent metal filling and device failure.

[0210] Different from Figure 1 The design of the grid isolation structure 102 shown is as follows: Figure 25 and Figure 26 As shown in the graphic design, the original long strip-shaped grid isolation structure 102 is designed as a grid isolation structure 102 with a concave-convex shape along the second direction. The sidewalls of the grid isolation structure 102 in this application are set as concave-convex curved surfaces, so that the direction of the internal stress of the material perpendicular to the sidewall is different for each part of the sidewall. This makes the internal stress of the material perpendicular to the sidewall not in a single direction, reducing the degree of concentrated stress release, thereby weakening the compression of the sidewall of the grid isolation structure 102 by the internal stress of the material, so that the grid isolation structure 102 will not undergo excessive deformation. In this way, when stress mismatch occurs in the grid isolation structure 102, the stress can be effectively released through the substructures 70 set in different directions, so that the grid isolation structure 102 is not prone to tilting or twisting, reducing leakage and improving the yield of finished products, thereby improving the stability of the grid isolation structure 102.

[0211] In some embodiments, the stacked structure 204 includes a core region 301 and a stepped region 302; the dimension of the gate line isolation structure 102 located in the core region 301 along the third direction is equal to the dimension of the gate line isolation structure 102 located in the stepped region 302 along the third direction.

[0212] In some embodiments of this application, the semiconductor device 100 may have a core region, a stair step region 302, and a peripheral region (not shown in the figures). The core region 301 is the region for forming memory cells, the stair step region 302 is the region for forming word line connection circuits, and the peripheral region is the region for forming peripheral circuits. Adjacent first regions 202 are separated by a gate line isolation structure 102, which may extend through the core region 301 and the stair step region 302.

[0213] See Figures 23 to 25 As shown, in this embodiment, both the core region 301 and the stepped region 302 of the stacked structure 204 are provided with gate line isolation structures 102 extending along the second direction. Furthermore, multiple gate line isolation structures 102 penetrate the stacked structure 204 along the first direction to divide the stacked structure 204 into multiple parts. The gate line isolation structures 102 in the core region 301 and the stepped region 302 have the same dimensions along the third direction. The process of forming the gate line isolation structures 102 in the core region 301 and the stepped region 302 of the stacked structure 204 is described in the embodiment corresponding to step S500 above, and will not be repeated here.

[0214] For example, such as Figure 25 As shown, the multiple substructures 70a in the core region 301 of the stacked structure 204 and the multiple substructures 70b in the stepped region 302 of the stacked structure 204 have the same shape and size along the X-axis and Y-axis directions. The multiple substructures 70a in the core region 301 and the multiple substructures 70b in the stepped region 302 are connected end to end along the X-axis to form a gate line isolation structure 102 with a concave-convex shape along the Y-axis direction.

[0215] In some embodiments, the stacked structure 204 includes a core region 301 and a stepped region 302; the dimension of the gate line isolation structure 102 located in the core region 301 along the third direction is smaller than the dimension of the gate line isolation structure 102 located in the stepped region 302 along the third direction.

[0216] In some embodiments of this application, see Figure 26 As shown, in this embodiment, both the core region 301 and the stepped region 302 of the stacked structure 204 are provided with gate line isolation structures 102 extending along the second direction. Furthermore, multiple gate line isolation structures 102 penetrate the stacked structure 204 along the first direction to divide the stacked structure 204 into multiple parts. The dimension of the gate line isolation structure 102 in the core region 301 along the third direction is smaller than the dimension of the gate line isolation structure 102 in the stepped region 302 along the third direction. The process of forming the gate line isolation structures 102 in the core region 301 and the stepped region 302 of the stacked structure 204 is described in the following embodiments and will not be repeated here.

[0217] like Figure 23 , Figure 24 and Figure 26 As shown, in this embodiment, the width (i.e., the dimension along the third direction) of the gate line isolation structure 102 in the stepped region 302 is increased relative to the width (i.e., the dimension along the third direction) of the gate line isolation structure 102 in the core region 301. This application does not require additional steps or masks; simply increasing the width of the gate line isolation structure 102 on the top surface of the stepped region 302 will result in a corresponding increase in the width of the bottom of the gate line isolation structure 102 within the stepped region 302. This application, by increasing the width of the gate line isolation structure 102 in the stepped region 302, facilitates uniform etching of the conductive material at the bottom of the gate line isolation structure 102 and prevents the accumulation of conductive material at the bottom of the gate line isolation structure 102 in the stepped region 302, thereby preventing interference between adjacent gate line isolation structures 102 that could lead to short circuits or leakage current.

[0218] For example, such as Figure 26 As shown, the multiple substructures 70a in the core region 301 of the stacked structure 204 and the multiple substructures 70b in the stepped region 302 of the stacked structure 204 have the same shape along the X and Y axes, but the dimensions of each substructure 70a in the core region 301 along the Y axis are smaller than the dimensions of each substructure 70b in the stepped region 302 along the Y axis. The multiple substructures 70a in the core region 301 and the multiple substructures 70b in the stepped region 302 are connected end to end along the X axis to form a gate line isolation structure 102 with a concave-convex shape along the Y axis.

[0219] In some embodiments, the conductive material may include any or a combination of ruthenium (Ru), iridium (Ir), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), doped silicon, silicides, or a combination of the above materials. Preferably, the conductive material may be tungsten (W).

[0220] In some embodiments, increasing the width of the gate isolation structure 102 reduces the separation distance between the gate isolation structure 102 and adjacent structures (e.g., the channel structure 330 adjacent to the first region 202). This reduction in separation distance increases the risk of etching and causes poor electrical contact between the gate isolation structure 102 and adjacent structures. Furthermore, increasing the width of the gate isolation structure 102 occupies more device space, compressing the space occupied by the channel structure 330 and thus affecting the device's storage density. In the embodiments of this application, the width design of the gate isolation structure 102 needs to consider and weigh at least the two factors described above to design a suitable gate isolation structure 102 width for a specific device.

[0221] In this embodiment, a gate line slot trench 101 can be formed in the stacked layer 201 located in the core region 301, and also in the stacked layer 201 located in the stepped region 302. The gate line slot trench 101 extends along a second direction and penetrates the stacked layer 201 along a first direction to divide the stacked layer 201 into several portions. In this embodiment, after forming the gate line slot trench 101, it can be filled by a deposition process to form a gate line isolation structure 102. In some embodiments, conductive material can be filled within the gate line slot trench 101. In some embodiments, the gate line isolation structure 102 can penetrate the stacked structure 204 and extend to the substrate 50 without passing through the substrate 50.

[0222] In some embodiments, the gate line isolation structure 102 located in the core region 301 and the gate line isolation structure 102 located in the stepped region 302 are formed under the same process, so as to achieve the purpose of forming the gate line gap trench 101 without increasing the cost.

[0223] It should be understood that the structure and manufacturing process of each component of the semiconductor device 100 in the embodiments of the present invention can be referred to the above-described embodiments of the manufacturing method of the semiconductor device 100, and will not be repeated here.

[0224] Based on the semiconductor device 100 and its fabrication method and storage system described above, embodiments of the present invention also provide a three-dimensional memory, which includes an array storage structure and peripheral circuitry, wherein the array storage structure includes the semiconductor device 100 described above.

[0225] Specifically, the 3D NAND Flash memory includes an array memory structure and peripheral circuitry, with the semiconductor device 100 described above located within the array memory structure. The array memory structure stores information, while the peripheral circuitry can be located above, below, or around the array memory structure, and is used to control the corresponding array memory structure. Furthermore, this semiconductor device 100 can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), without specific limitations. Moreover, the semiconductor device 100 in this embodiment of the invention can be a 3D memory or a part of a peripheral memory, without particular limitation.

[0226] Based on the semiconductor device 100 and its fabrication method and storage system described above, this embodiment of the invention also provides a storage system including a controller and a three-dimensional memory. The controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data. The three-dimensional memory includes the semiconductor device 100 described above.

[0227] Specifically, such as Figure 28 As shown, the storage system 300 includes a controller 310 and one or more three-dimensional memories 320, wherein each three-dimensional memory 320 includes one or more array storage structures 321 and peripheral circuitry 322. The storage system 300 can communicate with the host 400 via the controller 310, wherein the controller 310 can be connected to one or more three-dimensional memories 320 via channels in the three-dimensional memories 320. Each three-dimensional memory 320 can be managed by the controller 310 via channels in the three-dimensional memory 320.

[0228] The foregoing has provided a detailed description of a semiconductor device and its fabrication method, as well as a memory and storage system, and a memory and storage system provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for fabricating a semiconductor device, wherein, include: Provide a stacked layer; The stacked layer includes interleaved dielectric layers and sacrificial layers, and the stacked layer includes a first region and a second region; A plurality of channel holes are formed in the first region, penetrating the stacked layer along a first direction, and a plurality of first virtual channel holes are formed in the second region, penetrating the stacked layer along the first direction; Multiple channel structures are formed in the multiple channel holes; A grid line slot trench is formed that extends in a second direction and surrounds the plurality of first virtual channel holes, wherein the second direction intersects the first direction; A grid line isolation structure is formed in the grid line slot groove, and the sidewall of the grid line isolation structure extending along the second direction has an convex-concave shape; The step of forming a gate wire slot trench extending in the second direction and surrounding the plurality of first virtual channel holes includes: etching the plurality of first virtual channel holes to form a plurality of second virtual channel holes, and connecting the plurality of second virtual channel holes in the second direction to form a concave-convex gate wire slot trench.

2. The method for fabricating a semiconductor device according to claim 1, wherein, Prior to the step of forming multiple channel structures in the multiple channel holes, the method further includes: Sacrificial material is filled into the channel hole and the first virtual channel hole, and then the sacrificial material in the channel hole is removed.

3. The method for fabricating a semiconductor device according to claim 2, wherein, After filling the channel hole and the first virtual channel hole with sacrificial material, and before the step of removing the sacrificial material from the channel hole, the method further includes: A capping layer is formed on top of the stacked layers, and the capping layer located above the channel holes is removed.

4. The method for fabricating a semiconductor device according to claim 3, wherein, Prior to the step of forming the grid slot trenches extending in the second direction and surrounding the plurality of first virtual channel holes, the method further includes: Remove the sacrificial material from the first virtual channel hole.

5. The method for fabricating a semiconductor device according to claim 4, wherein, After the step of forming a plurality of channel structures in the plurality of channel holes, and before the step of removing the sacrificial material in the first virtual channel hole, the method further includes: forming a protective layer on top of the stacked layer.

6. The method for fabricating a semiconductor device according to claim 5, wherein, The protective layer comprises polycrystalline silicon.

7. The method for fabricating a semiconductor device according to claim 1, wherein, Before forming the grid line isolation structure in the grid line slot trench, the method further includes: The sacrificial layer in the stacked layers is replaced with a gate line layer.

8. The method for fabricating a semiconductor device according to claim 1, wherein, The shape of the first virtual channel hole includes either an ellipse or a circle, and the shape of the channel hole includes a circle.

9. The method for fabricating a semiconductor device according to claim 1, wherein, The stacked layer includes a core area and a stepped area; A plurality of first virtual channel holes with equal diameters are formed in the core area and the stepped area along a third direction; the third direction intersects the first direction and the second direction.

10. The method for fabricating a semiconductor device according to claim 1, wherein, The stacked layer includes a core area and a stepped area; The diameter of the plurality of first virtual channel holes formed in the core area along the third direction is smaller than the diameter of the plurality of first virtual channel holes formed in the stepped area along the third direction; the third direction intersects the first direction and the second direction.

11. The method for fabricating a semiconductor device according to claim 1, wherein, The step of forming a plurality of channel holes penetrating the stacked layer in the first region along the first direction in the stacked layer, and forming a plurality of first virtual channel holes penetrating the stacked layer in the second region along the first direction, includes: A composite photolithography layer is formed on the dielectric layer at the top of the stacked layers; and a plurality of first trenches and a plurality of second trenches are formed in the composite photolithography layer; the first trenches are located in the first region, and the second trenches are located in the second region; The stacked layers in the first region are etched through the first trench to form a plurality of the channel holes; and, The stacked layers in the second region are etched through the second trench to form a plurality of the first virtual channel holes.

12. The method for fabricating a semiconductor device according to claim 11, wherein, The plurality of channel holes and the plurality of first virtual channel holes are formed in the same process.

13. The method for fabricating a semiconductor device according to claim 11, wherein, The step of forming a composite photolithography layer on the dielectric layer at the top of the stacked layers includes: A stop layer is formed on the top dielectric layer, and a first mask layer is formed on the stop layer; The first mask layer is etched through the stop layer until the dielectric layer on top of the stacked layers is exposed to form the composite photolithography layer.

14. A semiconductor device, wherein, The semiconductor device includes: A stacked structure; the stacked structure includes interleaved dielectric layers and gate line layers, and the stacked structure includes a first region and a second region; A channel structure located in the first region and penetrating the stacked structure along a first direction; A gate line isolation structure located in the second region and extending along the second direction, the gate line isolation structure penetrating the stacked structure along the first direction, the sidewall of the gate line isolation structure extending along the second direction having an undulating shape, the undulating sidewall comprising a plurality of contacting curved surfaces or polygons, wherein the second direction intersects the first direction.

15. The semiconductor device according to claim 14, wherein, Also includes: A protective layer is provided on top of the stacked structure.

16. The semiconductor device according to claim 14, wherein, The grid isolation structure includes a sidewall extending along the second direction, the sidewall comprising a plurality of substructures connected end to end, and adjacent substructures not being coplanar.

17. The semiconductor device according to claim 14, wherein, The stacked structure includes a core area and a stepped area; The dimension of the grid isolation structure located in the core area along the third direction is equal to the dimension of the grid isolation structure located in the stepped area along the third direction; the third direction intersects the first direction and the second direction.

18. The semiconductor device according to claim 14, wherein, The stacked structure includes a core area and a stepped area; The size of the grid isolation structure located in the core area along the third direction is smaller than the size of the grid isolation structure located in the stepped area along the third direction; the third direction intersects the first direction and the second direction.

19. A storage system, wherein, include: A controller and a three-dimensional memory, the controller being coupled to the three-dimensional memory and used to control the storage of data in the three-dimensional memory, the three-dimensional memory comprising a semiconductor device as described in any one of claims 14 to 18.

Images