Display substrate and display device

Abstract

The invention provides a display substrate and a display device, and belongs to the technical field of display, the display substrate comprises a substrate, and grid lines and data lines located on the substrate, and the grid lines and the data lines intersect to define a plurality of pixel units; the grid lines extend along a first direction, the data lines extend along a second direction, and the first direction and the second direction intersect; each pixel unit comprises a first transistor and a second transistor; an active layer of the first transistor comprises a first contact part and a second contact part, an active layer of the second transistor comprises a third contact part and a fourth contact part, the first contact part is electrically connected with the data line, the second contact part is electrically connected with the third contact part, and the fourth contact part is electrically connected with the first electrode of the pixel unit; and along the second direction, the maximum distance between the first contact part and the grid line is not less than the maximum distance between the fourth contact part and the same grid line.

Description

Display substrate and display device

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a display device.

[0002] Transistors, as switch control elements or integrated components of peripheral drive circuits, are core devices in display technology. In the semiconductor field, mobility refers to the speed at which electrons move in semiconductor materials. For semiconductor display devices, mobility means the display quality and service life that can be achieved with the same device size.

[0003] However, with the optimization design of semiconductor materials for devices, while the mobility is improved, it also brings problems such as low threshold voltage and negative shift under light.

[0004]

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display substrate and a display device.

[0006] In a first aspect, a technical solution adopted to solve the technical problem of the present disclosure is a display substrate, which includes a base substrate, and gate lines and data lines located on the base substrate, the gate lines and the data lines intersecting to define a plurality of pixel units; the gate lines extend along a first direction, the data lines extend along a second direction, and the first direction and the second direction intersect; the pixel unit includes a first transistor and a second transistor; the active layer of the first transistor includes a first contact portion and a second contact portion, the active layer of the second transistor includes a third contact portion and a fourth contact portion, the first contact portion is electrically connected to the data line, the second contact portion is electrically connected to the third contact portion, and the fourth contact portion is electrically connected to the first electrode of the pixel unit; along the second direction, the maximum spacing between the first contact portion and the gate line is not less than the maximum spacing between the fourth contact portion and the same gate line.

[0007] In some embodiments, along the first direction, a width of the first contact portion is smaller than a width of the fourth contact portion.

[0008] In some embodiments, the orthographic projection of the first contact portion on the base substrate overlaps with the orthographic projection of the data line on the base substrate, the first contact portion includes a first portion and a second portion connected to each other, the first portion is electrically connected to the data line, and along the first direction, the width of the first portion is greater than the width of the second portion.

[0009] In some embodiments, the fourth contact portion overlaps with the orthographic projection of the gate line on the substrate, the fourth contact portion includes a third portion and a fourth portion connected to each other, the fourth portion is electrically connected to the first electrode, and along the second direction, the minimum width of the fourth portion is greater than the minimum width of the third portion.

[0010] In some embodiments, the first contact portion is electrically connected to the data line through a first via hole, and the fourth contact portion is electrically connected to the first electrode through a second via hole; along the second direction, the minimum spacing between the first via hole and the gate line is greater than the minimum spacing between the second via hole and the same gate line.

[0011] In some embodiments, the first contact portion is electrically connected to the data line through a first via, and the fourth contact portion is electrically connected to the first electrode through a second via and a third via; along the second direction, the minimum spacing between the first via and the gate line is greater than the minimum spacing between the second via and the same gate line; the minimum spacing between the third via and the gate line is less than the minimum spacing between the second via and the same gate line.

[0012] In some embodiments, the pixel unit further includes an auxiliary component; the auxiliary component includes a fifth portion and a sixth portion connected to each other, the fifth portion is electrically connected to the fourth contact portion through the second via hole; the sixth portion is electrically connected to the first electrode through the third via hole.

[0013] In some embodiments, the auxiliary component is disposed in the same layer as the data line, and in the first direction, the auxiliary component is disposed between two adjacent data lines at positions where they are connected to the first contact portion.

[0014] In some embodiments, the first contact portion, the second contact portion, the third contact portion, and the fourth contact portion are disposed in the same layer.

[0015] In some embodiments, the active layer of the first transistor and / or the active layer of the second transistor includes a metal oxide semiconductor material.

[0016] In some embodiments, the active layers of the first transistor and the second transistor include a plurality of stacked sub-layers, and the mobility of the sub-layers away from the substrate is smaller than the mobility of the sub-layers close to the substrate.

[0017] In some embodiments, the gate of the first transistor is located on a side of the active layer of the first transistor away from the substrate; the gate of the second transistor is located on a side of the active layer of the second transistor away from the substrate; the active layer of the first transistor and the active layer of the second transistor are arranged on the same layer;

[0018] The data line is multiplexed as the first electrode of the first transistor; the second contact portion is multiplexed as the second electrode of the first transistor, the third contact portion is multiplexed as the first electrode of the second transistor, and the second contact portion and the third contact portion are connected as an integrated structure.

[0019] In some embodiments, the first electrode is a pixel electrode; the orthographic projections of the second contact portion and the third contact portion connected as one on the base substrate partially overlap with the orthographic projection of at least one pixel electrode on the base substrate.

[0020] In some embodiments, for two adjacent pixel units, the orthographic projection of the second contact portion and the third contact portion connected as one in one of the pixel units on the substrate partially overlaps with the orthographic projection of the other pixel unit on the substrate.

[0021] In some embodiments, the active layer of the first transistor also includes a first channel portion arranged between the first contact portion and the second contact portion, and the active layer of the second transistor also includes a second channel portion arranged between the third contact portion and the fourth contact portion; the first channel portion, the second contact portion and the third contact portion connected as a whole, and the second channel portion The contour shape of the positive projection on the substrate is U-shaped.

[0022] In some embodiments, the gate of the first transistor and the gate of the second transistor are arranged in the same layer; the active layer of the first transistor and the active layer of the second transistor are arranged in the same layer; the first electrode and the second electrode of the first transistor are arranged in the same layer as the first electrode and the second electrode of the second transistor;

[0023] The gate of the first transistor is located on a side of the active layer away from the substrate; the first electrode and the second electrode of the first transistor are located on a side of the gate away from the active layer;

[0024] The data line is multiplexed as the first electrode of the first transistor; the second electrode of the first transistor and the first electrode of the second transistor are connected as an integrated structure, and the second electrode of the first transistor is electrically connected to the second contact portion through a fourth via, and the first electrode of the second transistor is electrically connected to the third contact portion through a fifth via.

[0025] In some embodiments, the display substrate further comprises a light shielding layer disposed near the base substrate at the pixel unit;

[0026] The active layer of the first transistor further includes a first channel portion disposed between the first contact portion and the second contact portion, and the active layer of the second transistor further includes a second channel portion disposed between the third contact portion and the fourth contact portion;

[0027] The orthographic projection of the light shielding layer on the base substrate at least covers the orthographic projections of the first channel portion and the second channel portion on the base substrate.

[0028] In some embodiments, in a first direction, a first distance exists between a contour edge of an orthographic projection of the light shielding layer on the substrate and a contour edge of an orthographic projection of the first channel portion on the substrate;

[0029] In the first direction, there is a second distance between the contour edge of the orthographic projection of the light shielding layer on the base substrate and the contour edge of the orthographic projection of the second channel portion on the base substrate;

[0030] The first spacing and / or the second spacing ranges from 4 μm to 6 μm.

[0031] In some embodiments, in the second direction, there is a third distance between a contour edge of an orthographic projection of the light shielding layer on the base substrate and a contour edge of an orthographic projection of the first channel portion on the base substrate;

[0032] In the second direction, there is a fourth distance between the contour edge of the orthographic projection of the light shielding layer on the base substrate and the contour edge of the orthographic projection of the second channel portion on the base substrate;

[0033] The third spacing and / or the fourth spacing ranges from 0 to 4 μm.

[0034] In some embodiments, the pixel units in the same row are electrically connected to the same gate line; the gate line serves as a gate of the first transistor and a gate of the second transistor.

[0035] In some embodiments, a gate insulating layer is disposed on a side of the gate of the first transistor close to the active layer; and a thickness of the gate insulating layer is between 10 nm and 30 nm.

[0036] In some embodiments, the gate of the first transistor and the gate of the second transistor are arranged in the same layer; the active layer of the first transistor and the active layer of the second transistor are arranged in the same layer; the first electrode and the second electrode of the first transistor are arranged in the same layer as the first electrode and the second electrode of the second transistor;

[0037] The gate of the first transistor is located on a side of the active layer close to the substrate; the first electrode and the second electrode of the first transistor are located on a side of the active layer away from the gate;

[0038] The data line is multiplexed as the first electrode of the first transistor; the second electrode of the first transistor and the first electrode of the second transistor are connected as an integrated structure, and the second electrode of the first transistor is electrically connected to the second contact portion of the first transistor; the first electrode of the second transistor is electrically connected to the third contact portion of the second transistor.

[0039] In some embodiments, the pixel units in the same row are electrically connected to the same gate line; the gate line is used as the gate of the first transistor and the gate of the second transistor;

[0040] The gate line is a composite film layer, comprising a buffer layer and a main conductive layer which are sequentially arranged on the base substrate.

[0041] In some embodiments, a gate insulating layer is disposed on a side of the gate of the first transistor close to the active layer; and a thickness of the gate insulating layer is between 30 nm and 50 nm.

[0042] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising a display substrate as described in any one of the first aspects.

[0043] FIG. 1a is a schematic diagram of the structure of a pixel circuit provided by an embodiment of the present disclosure;

[0044] FIG1b is a schematic diagram showing the positional relationship between the contact portion of the active layer and the gate line according to an embodiment of the present disclosure;

[0045] FIG2 is a schematic diagram showing the specific distribution of the first contact portion and the second contact portion provided in an embodiment of the present disclosure;

[0046] FIG3a is a plan view showing electrical connections between a transistor and a data line provided by an embodiment of the present disclosure;

[0047] FIG3 b is a plan view showing electrical connections between a transistor, a data line and a first electrode provided in an embodiment of the present disclosure;

[0048] FIG4 is a schematic diagram of an active layer using a composite film layer provided in an embodiment of the present disclosure;

[0049] FIG5 a is a top plan view of a transistor with a top-gate structure provided by an embodiment of the present disclosure;

[0050] FIG5b is a cross-sectional view of the structure shown in FIG5a along the AA direction;

[0051] FIG6a is a schematic diagram of the plane where the active layer shown in FIG5b is located;

[0052] FIG6b is a schematic diagram of the plane where the first conductive layer shown in FIG5b is located;

[0053] FIG6c is a schematic diagram of a plane where the first via hole and the second via hole shown in FIG5b are located;

[0054] FIG6d is a schematic diagram of the plane where the second conductive layer shown in FIG5b is located;

[0055] FIG7 is a top plan view of a plurality of pixel units in a pixel unit provided by an embodiment of the present disclosure;

[0056] FIG8a is a schematic diagram of the plane where the first sub-hole is located;

[0057] FIG8b is a schematic diagram of the plane where the second electrode is located;

[0058] FIG8c is a schematic diagram of the plane where the second sub-hole is located;

[0059] FIG8d is a schematic diagram of the plane where the first electrode is located;

[0060] FIG9a is a schematic diagram of the structure of another top-gate transistor provided in an embodiment of the present disclosure;

[0061] FIG9b is a cross-sectional view of the structure shown in FIG9a along the BB direction;

[0062] FIG10 is a top view of the plane where the light shielding layer is located;

[0063] FIG11 is a top view of an exemplary light shielding layer provided in an embodiment of the present disclosure;

[0064] FIG12a is a transistor device performance test result of the dual NMOS in normal working state (-1.5V) shown in FIG9b;

[0065] FIG12 b is a transistor device performance test result of the dual NMOS in a negative bias state (-8V) shown in FIG9 b ;

[0066] FIG13a is a schematic diagram of a bottom-gate transistor provided in an embodiment of the present disclosure;

[0067] FIG13b is a cross-sectional view of the structure shown in FIG13a along the CC direction;

[0068] FIG14a is a schematic diagram of the structure of another bottom-gate transistor provided in an embodiment of the present disclosure;

[0069] FIG14b is a cross-sectional view of the structure shown in FIG14a along the DD direction;

[0070] 15a to 15j are schematic diagrams of a process for preparing the display substrate shown in FIG. 5b according to an embodiment of the present disclosure;

[0071] 16a to 16j are schematic diagrams of a preparation process of the display substrate shown in FIG. 9b provided in an embodiment of the present disclosure;

[0072] 17a to 17i are schematic diagrams of a preparation process of the display substrate shown in FIG. 13b provided in an embodiment of the present disclosure;

[0073] 18a to 18i are schematic diagrams of the preparation process of the display substrate shown in FIG. 10 provided in an embodiment of the present disclosure.

[0074] The reference numerals are as follows: 1, substrate; 2, pixel unit; 21, pixel circuit; 22, first electrode; 23, second electrode; T1, first transistor; T2, second transistor; T11, first electrode of first transistor; T12, second electrode of first transistor; T13, active layer of first transistor; 13a, first contact portion; 13b, second contact portion; 13c, first channel portion; T14, gate of first transistor; T21, first electrode of second transistor; T22, second electrode of second transistor; T23, active layer of second transistor; 23a, third contact portion; 23b, fourth contact portion; 23c, second channel portion Channel portion; T24, the gate of the second transistor; Gate, gate line; Data, data line; ACT, semiconductor layer; ACT_1, sublayer; 31, first insulating layer; 32, second insulating layer; 33, third insulating layer; 34, fourth insulating layer; 35, fifth insulating layer; 41, first conductive layer; 42, second conductive layer; 43, third conductive layer; 50, light shielding layer; X, first direction; Y, second direction; 6, auxiliary component; 61, fifth portion; 62, sixth portion; Via1, first via hole; Via2, second via hole; Via3, third via hole; Via31, first sub-hole; Via32, second sub-hole.

[0075] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0076] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0077] In the related technologies, the effective mobility of amorphous silicon (a-Si), metal oxide (IGZO), and low-temperature polycrystalline silicon (LTPS) currently used in the industry is actually about 1cm 2 / (V﹒s),10cm 2 / (V﹒s),80cm 2 / (V﹒s), it can be seen that low-temperature polysilicon (LTPS) is far ahead in terms of material performance. Conventional technology maintains a high mobility level by developing different series of metal oxide materials, such as adjusting the element ratio by increasing the indium (In) content, removing the zinc (Zn) component or adding the tin (Sn) component, etc., so as to achieve about 20cm 2 / (V﹒s)~50cm 2 / (V﹒s). However, while improving the mobility, it also brings a series of problems as follows: On the one hand, the optical band gap (Eg) of high mobility materials is small, which makes it easier to generate carriers, so that the electrons in the high mobility materials can absorb part of the visible light band to produce electronic transitions, which in turn leads to the device capability being manifested as the early opening of the thin film transistor (TFT), and the increase of new defects under light, and the serious degradation of the negative bias temperature illumination stability (NBTIS), resulting in a serious decline in service life. On the other hand, the development of high mobility materials is limited by the difficulty that mobility and Eg cannot achieve a win-win situation. At present, it has been slow to break through the mass production of high mobility materials of Mob 30 and above. The relevant technology starts from the design direction of TFT devices and the design direction of dual-gate structures. Through dual-gate TFTs and ultra-thin gate insulating layers (GI), the thickness of the layer can reach approximately 20cm. 2 / (V﹒s) and above ultra-high mobility index device performance. However, although this device design achieves high mobility, it also reduces the current value at low voltage, that is, the off-state current (Ioff), which will lead to a significant reduction in the device threshold voltage (Vth). At the same time, the reduction in GI thickness will also cause the device's breakdown voltage to decrease, thereby increasing the risk of device failure. Therefore, based on the above information, for the preparation of ultra-high mobility devices, there are problems such as low threshold voltage and negative offset under light. Based on these problems, traditional technical solutions often cannot break through 50cm 2 / (V﹒s) and above ultra-high mobility, no mass production results on the market.

[0078] In view of this, an embodiment of the present disclosure provides a display substrate, which improves the leakage problem caused by the negative bias of the threshold voltage (Vth) of the existing device by connecting two transistors electrically connected to the first electrode of the pixel unit in series, thereby improving the switching capability of the display substrate and the service life of the product.

[0079] FIG1a is a schematic diagram of the structure of a pixel circuit provided in an embodiment of the present disclosure, and FIG1b is a schematic diagram of the positional relationship between a contact portion of an active layer and a gate line provided in an embodiment of the present disclosure. As shown in FIG1a and FIG1b , a display substrate includes a base substrate 1 (not shown in FIG1a and FIG1b , see FIG4 for details), and a gate line Gate and a data line Data located on the base substrate 1, wherein the gate line Gate and the data line Data intersect to define a plurality of pixel units 2; the gate line Gate extends along a first direction X, and the data line Data extends along a second direction Y, and the first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are arranged perpendicularly. The pixel unit 2 includes a pixel circuit 21 and a first electrode 22; the pixel circuit 21 includes at least a first transistor T1 and a second transistor T2; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, the first contact portion 13a is electrically connected to the data line Data, the second contact portion 13b is electrically connected to the third contact portion 23a, and the fourth contact portion 23b is electrically connected to the first electrode 22 of the pixel unit 2; along the second direction Y, the maximum spacing d1 between the first contact portion 13a and the gate line Gate is not less than the maximum spacing d2 between the fourth contact portion 23b and the same gate line.

[0080] 1a, the second electrode T12 of the first transistor T1 is electrically connected to the first electrode T21 of the second transistor T2, and the second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22. The active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both made of metal oxide semiconductor materials.

[0081] Exemplarily, the metal oxide semiconductor material can be made of one or more materials selected from indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), and rare earth doped oxide (Ln-OS). The material can be amorphous, partially crystalline, single crystal or polycrystalline, and the prepared active layer can be a single layer or multilayer structure. According to the actual characteristics of the metal oxide semiconductor material, this material can improve the mobility of the transistor.

[0082] It should be noted that the transistor used in the embodiment of the present disclosure may be a field effect transistor (MOS transistor). Since the source and drain of the MOS transistor used are symmetrical, there is no difference between the source and drain. In the embodiment of the present disclosure and the subsequent description, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode and the other electrode is called the second electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. The materials of the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 in the embodiment of the present disclosure are both metal oxide semiconductor materials. It should be noted that transistors made of metal oxide semiconductor materials can only prepare N-type transistors. Therefore, the transistor of the embodiment of the present disclosure is an N-type transistor. Among them, the first electrode of the transistor is the drain of the N-type transistor, and the second electrode of the transistor is the source of the N-type transistor. When a high-level signal is input to the gate, the source and drain are turned on.

[0083] In practical applications of the pixel unit 2, not all transistors in the pixel unit 2 adopt the above structure to achieve similar effects. Therefore, it should be noted that for any pixel unit 2, the second transistor T2 electrically connected to the first electrode 22, the first transistor T1 is added and connected in series with the second transistor T2, the current value of one transistor will be suppressed by the other transistor, and in the extreme case, when one of the transistors has a negative bias in the conductive property, the other transistor is still in a normal working state, thereby significantly reducing the off-state current and reducing the risk of negative offset of the threshold voltage.

[0084] In the display substrate provided by the embodiment of the present disclosure, the active layers of the dual transistors electrically connected to the first electrode 22 are made of metal oxide semiconductor materials, thereby improving the mobility of the transistors; at the same time, the two transistors are connected in series, and the current value of one transistor will be suppressed by the other transistor. In extreme cases, when one of the transistors has a negative bias in its conductive properties, the other transistor is still in a normal working state, which can significantly improve the threshold voltage of the entire device, thereby effectively improving the leakage problem of the entire device and the sand bright spot (Mura) problem of the display product caused by leakage.

[0085] In some embodiments, as shown in FIG. 1 b , along the first direction X, the minimum width of the first contact portion 13 a is smaller than the minimum width of the fourth contact portion 23 b .

[0086] Here, “width” may be understood as the maximum spacing or average spacing between boundaries of a specified film layer along a specified direction, and may be a lateral dimension or a longitudinal dimension.

[0087] In some embodiments, Figure 2 is a schematic diagram of the specific distribution of the first contact portion and the second contact portion provided in the embodiment of the present disclosure. As shown in Figure 2, the orthographic projection of the first contact portion 13a on the substrate substrate 1 overlaps with the orthographic projection of the data line Data on the substrate substrate 1, and the first contact portion 13a includes a first portion 13a1 and a second portion 13a2 connected to each other. The first portion 13a1 is electrically connected to the data line Data, and along the first direction X, the width w1 of the first portion 13a1 is greater than the width w2 of the second portion 13a2.

[0088] In some embodiments, as shown in FIG. 2 , the orthographic projection of the fourth contact portion 23b on the substrate 1 overlaps with the orthographic projection of the gate line Gate on the substrate 1, and the fourth contact portion 23b includes a third portion 23b1 and a fourth portion 23b2 connected to each other, the fourth portion 23b2 is electrically connected to the first electrode 22, and along the second direction Y, the minimum width w4 of the fourth portion 23b2 is greater than the minimum width w3 of the third portion 23b1.

[0089] In some embodiments, FIG. 3a is a plan view of the electrical connection between the transistor and the data line provided in the embodiment of the present disclosure. As shown in FIG. 3a, the first contact portion 13a is electrically connected to the data line Data through the first via hole Via1, and the fourth contact portion 23b is electrically connected to the first electrode 22 through the second via hole Via2. Along the second direction Y, the minimum spacing d11 between the first via hole Via1 and the gate line Gate is greater than the minimum spacing d21 between the second via hole and the same gate line Gate.

[0090] In some embodiments, FIG. 3b is a plan view of the transistor provided for the embodiment of the present disclosure, which is electrically connected to the data line and the first electrode. As shown in FIG. 3b, the first contact portion 13a is electrically connected to the data line Data through the first via hole Via1, and the fourth contact portion 23b is electrically connected to the first electrode 22 through the second via hole Via2 and the third via hole Via3. Along the second direction Y, the minimum spacing d11 between the first via hole Via1 and the gate line Gate is greater than the minimum spacing d21 between the second via hole and the same gate line Gate. The minimum spacing d31 between the third via hole Via3 and Gate is less than the minimum spacing d21 between the second via hole Via2 and the same gate line Gate.

[0091] In some embodiments, as shown in Figure 3b, the pixel unit 2 also includes an auxiliary component 6; the auxiliary component 6 includes a fifth part 61 and a sixth part 62 connected to each other, the fifth part 61 is electrically connected to the fourth contact portion 23b through the second via hole Via2; the sixth part 62 is electrically connected to the first electrode 22 through the third via hole Via3.

[0092] In this embodiment, the position design of the third via hole Via3 and the auxiliary component 6 can reduce the via hole ratio to improve the opening ratio, and increase the overlap area and yield of the first electrode 22 (ie, the pixel electrode ITO) and other film layers.

[0093] In some embodiments, as shown in FIG. 6 d , the auxiliary component 6 is disposed in the same layer as the data line Data, and in the first direction X, an auxiliary component is disposed between the positions where two adjacent data lines Data are connected to the first contact portion 13 a .

[0094] In some embodiments, as shown in FIG. 6 a , the first contact portion 13 a , the second contact portion 13 b , the third contact portion 23 a , and the fourth contact portion 23 b are disposed in the same layer.

[0095] In some embodiments, the active layer T13 of the first transistor T1 and / or the active layer T23 of the second transistor T2 includes multiple stacked sublayers, wherein the mobility of the sublayers away from the substrate 1 is smaller than the mobility of the sublayers close to the substrate 1 .

[0096] FIG4 is a schematic diagram of an active layer using a composite film layer provided in an embodiment of the present disclosure. As shown in FIG4 , the active layer T13 of the first transistor T1 and / or the active layer T23 of the second transistor T2 include a multilayer stacked sublayer ACT_1, a sublayer ACT_2, and a sublayer ACT_3. Among them, the mobility of the sublayer ACT_3 far away from the base substrate 1 is less than the mobility of the sublayer ACT_2 close to the base substrate 1; the mobility of the sublayer ACT_2 far away from the base substrate 1 is less than the mobility of the sublayer ACT_1 close to the base substrate 1.

[0097] It should be noted that the higher the mobility, the lower the stability of the corresponding device. Therefore, in this embodiment, by sequentially depositing sub-layers ACT_1 with smaller mobility, the stability of the device is improved while ensuring that the device has a higher mobility.

[0098] In some embodiments, when the active layer T13 of the first transistor T1 includes a plurality of stacked sub-layers, the material of the sub-layers includes one of IGO, ITZO, and IGZTO; when the active layer T23 of the second transistor T2 includes a plurality of stacked sub-layers, the material of the sub-layers includes one of IGO, ITZO, and IGZTO.

[0099] The above metal oxide materials IGO, ITZO, and IGZTO all have a mobility greater than or equal to 20 cm 2 Of course, the material of the sub-layer ACT_1 provided in the embodiment of the present disclosure is not limited to the above-mentioned ones, and may also include other materials with a mobility greater than or equal to 20cm 2 / (V﹒s) semiconductor materials, for which the embodiments of the present disclosure will not list them one by one.

[0100] The preparation process of the sub-layers of the multi-layer stacked arrangement includes but is not limited to the preparation methods of oxide semiconductor devices such as ESL, BCE, and Top Gate.

[0101] In some embodiments, the first transistor T1 and / or the second transistor T2 is an N-type metal oxide semiconductor transistor, hereinafter referred to as NMOS transistor.

[0102] The embodiment of the present disclosure takes the example that the first transistor T1 and the second transistor T2 are both NMOS transistors to illustrate the specific structures of the first transistor T1 and the second transistor T2.

[0103] In some embodiments, FIG5a is a top plan view of a transistor of a top gate structure provided by an embodiment of the present disclosure, and FIG5b is a cross-sectional view of the structure shown in FIG5a in the AA direction; as shown in FIG5a and FIG5b, the first transistor T1 and the second transistor T2 can be transistors of a top gate structure. The gate T14 of the first transistor T1 is located on the side of the active layer T13 of the first transistor T1 away from the substrate 1; the gate T24 of the second transistor T2 is located on the side of the active layer T23 of the second transistor T2 away from the substrate 1; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, and a first channel portion 13c located between the first contact portion 13a and the second contact portion 13b; the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, and a second channel portion 23c located between the third contact portion 23a and the fourth contact portion 23b.

[0104] The first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b are all conductive portions formed after the active layer is conductively converted. The conductive properties of the conductive portions are higher than those of the first channel portion 13c (and also higher than those of the second channel portion 23c). The conductive properties of the conductive portions are lower than those of the metal electrodes. For example, He, Ar, H 2 NH 3 The first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b are formed by plasma treatment with gases (including mixed gases) and conductive doping.

[0105] Exemplarily, as shown in FIG. 5a and FIG. 5b, the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged in the same layer. The second contact portion 13b is multiplexed as the second electrode T12 of the first transistor T1, and the third contact portion 23a is multiplexed as the first electrode T21 of the second transistor T2, and the second contact portion 13b is connected to the third contact portion 23a as an integral structure. The first electrode T11 of the first transistor T1 is electrically connected to the first contact portion 13a and the data line Data through the first via hole Via1. The second electrode T22 of the second transistor is electrically connected to the fourth contact portion 23b and the fifth part 61 of the auxiliary component 6 through the second via hole Via2.

[0106] Compared with bottom-gate transistors, top-gate transistors have a simpler manufacturing process, require fewer photomasks, and have lower costs.

[0107] Figure 6a is a schematic diagram of the plane where the active layer shown in Figure 5b is located, Figure 6b is a schematic diagram of the plane where the first conductive layer shown in Figure 5b is located, Figure 6c is a schematic diagram of the plane where the first via and the second via shown in Figure 5b are located, and Figure 6d is a schematic diagram of the plane where the second conductive layer shown in Figure 5b is located.

[0108] Exemplarily, as shown in FIG5b, the display substrate also includes a first insulating layer 31 disposed on the base substrate 1; a semiconductor layer ACT disposed on the side of the first insulating layer 31 away from the base substrate 1 (as shown in FIG6a); a second insulating layer 32 disposed on the side of the semiconductor layer ACT away from the first insulating layer 31; a first conductive layer 41 disposed on the side of the second insulating layer 32 away from the semiconductor layer ACT (as shown in FIG6b); a third insulating layer 33 disposed on the side of the first conductive layer 41 away from the second insulating layer 32; and a second conductive layer 42 disposed on the side of the third insulating layer 33 away from the first conductive layer 41 (as shown in FIGS. 6c and 6d). The gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 (including the second contact portion 13b multiplexed as the second electrode T12 of the first transistor T1) and the active layer T23 of the second transistor T2 (including the third contact portion 23a multiplexed as the first electrode T21 of the second transistor T2) are both located in the semiconductor layer ACT; the first electrode T11 of the first transistor T1 and the second electrode T22 of the second transistor T2 are both located in the second conductive layer 42.

[0109] In some embodiments, as shown in FIG. 5 a , the contour shape of the orthographic projection of the pattern formed by the first channel portion 13 c , the second contact portion 13 b and the third contact portion 23 a connected as one, and the second channel portion 23 c on the base substrate 1 is U-shaped.

[0110] In some embodiments, Figure 7 is a top plan view of multiple pixel units provided in an embodiment of the present disclosure. As shown in Figure 7, the first electrode 22 is a pixel electrode ITO; the orthographic projection of the second contact portion 13b and the third contact portion 23a connected as a whole on the base substrate 1 partially overlaps with the orthographic projection of at least one pixel electrode ITO on the base substrate 1.

[0111] Exemplarily, the active layer is a light-transmitting layer, and the area corresponding to the orthographic projection of the pixel electrode ITO is a display light-transmitting area, so the orthographic projection between the contact portion of the active layer and the pixel electrode ITO overlaps, which does not affect the display luminescence. By overlapping the orthographic projection of the second contact portion 13b and the third contact portion 23a connected as one on the base substrate 1 with the orthographic projection of at least one pixel electrode ITO on the base substrate 1, the layout space of the single pixel unit 2 is reduced, thereby improving the resolution.

[0112] In some embodiments, as shown in FIG. 7 , two pixel units 2 are adjacently arranged along the column direction, wherein the orthographic projection of the second contact portion 13 b and the third contact portion 23 a connected as one in one pixel unit 2 on the base substrate 1 partially overlaps with the orthographic projection of another pixel electrode ITO on the base substrate 1 .

[0113] Of course, there may also be two pixel units 2 adjacently arranged in the row direction, wherein the orthographic projection of the second contact portion 13b and the third contact portion 23a connected as one in one pixel unit 2 on the base substrate 1 partially overlaps with the orthographic projection of the other pixel electrode ITO on the base substrate 1 .

[0114] In some embodiments, as shown in FIG7 , the display substrate further includes a data line Data. The data line Data is electrically connected to the first electrode T11 of the first transistor T1. The positive projection of the data line Data on the active layer T13 of the first transistor T1 runs through the active layer T13 of the first transistor T1 along the direction from the first contact portion 13a to the second contact portion 13b (i.e., the direction opposite to the Y direction), and the contour edge of the positive projection of the data line Data on the active layer T13 of the first transistor T1 is at a certain distance from the edge of the active layer T13 of the first transistor T1 in the width direction X of the data line Data. Through the structural setting of this embodiment, the layout space of the single pixel unit 2 is reduced, thereby improving the resolution.

[0115] On this basis, combined with the layout structure of the pixel electrode ITO, the orthographic projection of the pixel electrode ITO on the second contact portion 13b and the third contact portion 23a connected as one does not fall within the orthographic projection of the data line Data on the active layer, so as to further improve the pixel resolution.

[0116] FIG8a is a schematic diagram of the plane where the first sub-hole is located, FIG8b is a schematic diagram of the plane where the second electrode is located, FIG8c is a schematic diagram of the plane where the second sub-hole is located, and FIG8d is a schematic diagram of the plane where the first electrode is located.

[0117] In some embodiments, as shown in Figures 15j and 8b, the pixel unit 2 further includes a second electrode 23, and the second electrode 23 is located on a side of the pixel electrode ITO close to the base substrate 1. The second electrode 23 is a common electrode.

[0118] In some embodiments, as shown in FIG8d, the pixel electrode ITO is a slit electrode; the common electrode is a plate electrode. The pixel electrode ITO is electrically connected to the auxiliary component 6 through the third via hole via3, and the auxiliary component 6 is electrically connected to the fourth contact portion 23b through the second via hole via2. As shown in FIG8a and FIG8c, the third via hole via3 includes a first sub-hole via31 penetrating the planarization layer 342, and a second sub-hole via32 penetrating the metal protection layer 341. The pixel electrode ITO is electrically connected to the auxiliary component 6 through the first sub-hole via31 and the second sub-hole via32 in sequence.

[0119] In some embodiments, FIG. 9a is a schematic diagram of the structure of another top-gate structure transistor provided in an embodiment of the present disclosure, and FIG. 9b is a cross-sectional view of the structure shown in FIG. 9a in the BB direction. As shown in FIG. 9a and FIG. 9b, the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged in the same layer; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged in the same layer; the first electrode T11 and the second electrode of the first transistor T1 are arranged in the same layer as the first electrode T21 and the second electrode of the second transistor T2; the first transistor T1 The gate T14 is located on the side of the active layer away from the substrate 1; the first electrode T11 and the second electrode of the first transistor T1 are located on the side of the gate away from the active layer; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, and a first channel portion 13c located between the first contact portion 13a and the second contact portion 13b; the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, and a second channel portion 23c located between the third contact portion 23a and the fourth contact portion 23b.

[0120] The first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b are all conductive portions formed after the active layer is conductively converted. The conductive properties of the conductive portions are higher than those of the first channel portion 13c (and also higher than those of the second channel portion 23c). The conductive properties of the conductive portions are lower than those of the metal electrodes. For example, He, Ar, H 2 NH 3The first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b are formed by plasma treatment with gases (including mixed gases) and conductive doping.

[0121] The second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 are connected as an integral structure, and the second electrode T12 of the first transistor T1 is electrically connected to the second contact portion 13b through the fourth via hole Via4, and the first electrode T21 of the second transistor T2 is electrically connected to the third contact portion 23a through the fifth via hole Via5. The first electrode T11 of the first transistor T1 is electrically connected to the first contact portion 13a and the data line Data through the first via hole Via1. The second electrode T22 of the second transistor is electrically connected to the fourth contact portion 23b and the fifth portion 61 of the auxiliary component 6 through the second via hole Via2.

[0122] The transistor with the top gate structure shown in FIG9b is connected in series in a different manner from the transistor with the top gate structure shown in FIG5b. Compared with the transistor with the top gate structure shown in FIG5b, the transistor with the top gate structure shown in FIG9b uses a metal electrode (the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 connected as an integral structure) to achieve series connection. Since the conductivity of the metal electrode is higher than that of the second contact portion 13b and the third contact portion 23a after being conductorized, the top gate structure shown in FIG9b has higher device stability.

[0123] Exemplarily, as shown in FIG9b, the display substrate further includes a first insulating layer 31 disposed on the base substrate 1; a semiconductor layer ACT disposed on the side of the first insulating layer 31 away from the base substrate 1; a second insulating layer 32 disposed on the side of the semiconductor layer ACT away from the first insulating layer 31; a first conductive layer 41 disposed on the side of the second insulating layer 32 away from the semiconductor layer ACT; a third insulating layer 33 disposed on the side of the first conductive layer 41 away from the second insulating layer 32; and a second conductive layer 42 disposed on the side of the third insulating layer 33 away from the first conductive layer 41. The gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both located in the semiconductor layer ACT; the first electrode T11 and the second electrode T12 of the first transistor T1, and the first electrode T21 and the second electrode T22 of the second transistor T2 are both located in the second conductive layer 42.

[0124] Exemplarily, as shown in FIG9b, the first insulating layer 31 may be a buffer insulating layer, which may be provided with a single-layer structure and may be made of SiOx (x>0) material; or, the buffer insulating layer may be provided with a composite film layer structure and may be made of a composite film layer SiN / SiOx (x>0) material.

[0125] Exemplarily, as shown in FIG9b, the first insulating layer 31 can be a dielectric layer disposed between the light shielding layer 50 and the semiconductor layer ACT. In addition to its own light shielding effect, it will also produce other effects: on the one hand, electrical effects; the light shielding layer 50 is conductive, and for the device of the floating light shielding layer 50, it will induce charges to turn on the transistor in advance, and the threshold voltage Vth will be reduced. The thinner the first insulating layer 31, the greater the effect. For the light shielding layer device connected to the gate, the first insulating layer 31 needs to be thinned to provide a higher Ion capability. In general, the thickness of the first insulating layer 31 with moderate electrical requirements. On the other hand, there is the effect of process coverage; the first insulating layer 31 needs a certain thickness to ensure isolation, to prevent the active layer from breaking or short-circuiting at the edge of the light shielding layer 50, and the thickness of the first insulating layer 31 is set between 200nm and 500nm.

[0126] For example, as shown in FIG. 9 b , the second insulating layer 32 may be a gate insulating layer, and the material of the gate insulating layer may generally be SiOx (x>0) material.

[0127] Exemplarily, as shown in FIG9b, unlike the first insulating layer 31, the second insulating layer 32 exists between the first conductive layer 41 and the semiconductor layer ACT. For electrical properties, the thinner the second insulating layer 32 is, the higher the Ion is. In addition, since the second insulating layer 32 is not required for covering protection in the process of the top gate structure, and considering the process capability, the thickness of the second insulating layer 32 is set between 100nm and 300nm to prevent the film layer from being too thin and causing electrical breakdown. Exemplarily, as shown in FIG9b, the first conductive layer 41 can be set to a single-layer structure, using materials such as Al or Cu. Alternatively, the first conductive layer 41 can be set to a composite film layer structure, including a buffer layer and a main conductive layer, wherein the material of the buffer layer can be a Ti-based alloy material or a Mo-based alloy material, and the material of the main conductive layer can be a material such as Al or Cu. Alternatively, the first conductive layer 41 can be set to a single-layer structure, using Al or Cu to add Ti-based alloy materials or Mo-based alloy materials.

[0128] Exemplarily, as shown in FIG9b, the third insulating layer 33 is an intermediate dielectric layer, which can be provided with a single-layer structure and made of SiOx (x>0) material; alternatively, the intermediate dielectric layer can be provided with a composite film layer structure and made of a composite film layer SiN / SiOx (x>0) material.

[0129] Exemplarily, as shown in FIG9b, the third insulating layer 33 serves to separate the gate and the source / drain in the longitudinal section of the device. A certain thickness is required between the two to prevent short circuits and reduce the capacitance between metals to prevent pulling between electrical signals. An excessively thick intermediate dielectric layer is not conducive to the stability of engineering contact, so the thickness of the third insulating layer 33 is set between 300nm and 600nm.

[0130] Exemplarily, as shown in FIG. 9 b , the material of the second conductive layer 42 is metal.

[0131] Exemplarily, as shown in Figures 16j and 8a to 8d, the top gate structure shown in Figure 9b is connected to the pixel electrode ITO structure, as shown in Figures 16j and 8a to 8d. The pixel electrode ITO is electrically connected to the auxiliary component 6 through the third via hole via3, and the auxiliary component 6 is electrically connected to the fourth contact portion 23b through the second via hole via2. As shown in Figures 8a and 8c, the third via hole via3 includes a first sub-hole via31 that penetrates the planarization layer 342, and a second sub-hole via32 that penetrates the metal protection layer 341. The pixel electrode ITO is electrically connected to the auxiliary component 6 through the first sub-hole via31 and the second sub-hole via32 in turn.

[0132] FIG10 is a top view of the plane where the light shielding layer is located. Both the top gate structure shown in FIG5b and the top gate structure shown in FIG9b include a light shielding layer 50. In some embodiments, as shown in FIG5b, FIG9b and FIG10, the display substrate further includes a light shielding layer 50 disposed near the base substrate 1 of the pixel unit 2.

[0133] Exemplarily, the light shielding layer 50 may be provided with a composite film layer structure, using a composite film layer of Mo-based alloy / Cu material, or a composite film layer of Mo-based alloy / Al material.

[0134] As shown in FIG. 5 a or 9 a , the orthographic projection of the light shielding layer 50 on the base substrate 1 at least covers the orthographic projections of the first channel portion 13 c of the active layer T13 of the first transistor T1 and the second channel portion 23 c of the active layer T23 of the second transistor T2 on the base substrate 1 .

[0135] In this embodiment, a light-shielding layer 50 is provided to block the light emitted from the backlight source to the first channel portion 13c and the second channel portion 23c, so that the number of electron-hole pairs generated by the first contact portion 13a (or the third contact portion 23a) due to light excitation can be reduced, thereby reducing the number of electrons moving to the second contact portion 13b (or the fourth contact portion 23b) during the holding stage, thereby reducing the light leakage current and improving the flicker problem caused by the leakage current.

[0136] In some embodiments, Figure 11 is a plan view of an exemplary light-shielding layer provided in an embodiment of the present disclosure. As shown in Figure 11, there is a maximum first spacing between the contour edge of the orthographic projection of the light-shielding layer 50 on the substrate substrate 1 and the contour edge of the orthographic projection of the first channel portion 13c on the substrate substrate 1; there is a maximum second spacing between the contour edge of the orthographic projection of the light-shielding layer 50 on the substrate substrate 1 and the contour edge of the orthographic projection of the second channel portion 23c on the substrate substrate 1; the maximum first spacing and / or the maximum second spacing are in the range of 4μm to 6μm.

[0137] Exemplarily, as shown in FIG11 , in the first direction X, there is a first spacing L1 between the contour edge of the orthographic projection of the light shielding layer 50 on the substrate 1 and the contour edge of the orthographic projection of the first channel portion 13c on the substrate 1, and the range of the first spacing L1 is 4 μm to 6 μm. Since the direction in which the first contact portion 13a points to the second contact portion 13b is the current flow direction (i.e., the direction opposite to the Y direction), in order to avoid forming a current path in the side portion opposite to the first channel portion 13c along the first direction X, the width of the light shielding layer 50 in the first direction X is set slightly larger to ensure that the first channel portion 13c is not affected by light in the first direction X, thereby ensuring the stability of the first transistor T1. Similarly, in the first direction X, there is a second spacing L2 between the contour edge of the orthographic projection of the light shielding layer 50 on the substrate 1 and the contour edge of the orthographic projection of the second channel portion 23c on the substrate 1, and the range of the second spacing L2 is 4 μm to 6 μm. Since the direction in which the third contact portion 23a points to the fourth contact portion 23b is the current flow direction, that is, the second direction Y, in order to avoid forming a current path in the side portion of the second channel portion 23c opposite to the first direction X, the width of the shading layer 50 in the first direction X is set slightly larger to ensure that the second channel portion 23c is not affected by light in the first direction X, thereby ensuring the stability of the second transistor T2.

[0138] Exemplarily, as shown in FIG11 , in the second direction, there is a third spacing L3 between the contour edge of the orthographic projection of the light shielding layer 50 on the substrate substrate 1 and the contour edge of the orthographic projection of the first channel portion 13c on the substrate substrate 1, and the range of the third spacing L3 is 0 to 4 μm. In the second direction Y, there is a fourth spacing L4 between the contour edge of the orthographic projection of the light shielding layer 50 on the substrate substrate 1 and the contour edge of the orthographic projection of the second channel portion 23c on the substrate substrate 1, and the range of the fourth spacing L4 is 0 to 4 μm. Since the light shielding layer 50 is not light-transmissive, the smaller the coverage area of ​​the light shielding layer 50, the better; however, in order to ensure the stability of the device, the larger the coverage area of ​​the light shielding layer 50, the better. Based on this, taking into full consideration the influence of pixel specifications and device stability, the width of the light shielding layer 50 in the second direction Y is set slightly smaller here to improve the transmittance.

[0139] In some embodiments, as shown in FIG. 5 a or FIG. 9 a , the pixel units 2 in the same row are electrically connected to the same gate line Gate; the gate line Gate is used as the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 .

[0140] In this embodiment, the gate line Gate is reused as the transistor gate. This configuration mode of using in-plane wiring is used to achieve a narrow frame.

[0141] FIG12a is a transistor device performance test result of the dual NMOS in normal working state (-1.5V) shown in FIG9b, and FIG12b is a transistor device performance test result of the dual NMOS in negative bias state (-8V) shown in FIG9b, wherein the horizontal axis Vg represents the gate T24 (i.e., gate line Gate) voltage of the first transistor T1 and the second transistor T2, the vertical axis Ids represents the first electrode T11 (i.e., drain) current of the first transistor T1, Vth represents the threshold voltage, 01 represents the curve of the dual NMOS structure shown in FIG9b, and 02 represents the curve of the single NMOS structure. As can be seen from FIGS. 9a and 9b, the off-state current of the dual NMOS is relatively small and the threshold voltage is relatively large compared to the single NMOS, whether in normal working state or negative bias state. Therefore, compared with the prior art, the embodiments of the present disclosure can effectively improve the leakage problem of the entire device and the sand grain bright spot (Mura) problem of the display product caused by leakage.

[0142] In some embodiments, the first transistor T1 and the second transistor T2 may be bottom-gate transistors. FIG13a is a schematic diagram of a bottom-gate transistor structure provided in an embodiment of the present disclosure, and FIG13b is a cross-sectional view of the structure shown in FIG13a in the CC direction. As shown in FIG13a and FIG13b, the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged in the same layer; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged in the same layer; the first electrode T11 of the first transistor T1 and the second electrode T22 of the second transistor T2 are arranged in the same layer; the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged in the same layer; the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged in the same layer; the gate T11 of the first transistor T1 and the gate T22 of the second transistor T2 are arranged in the same layer; the gate T14 of the first transistor T1 and the gate T24 ... 4 is located on a side of the active layer close to the substrate 1; the first electrode T11 of the first transistor T1 is located on a side of the active layer T13 away from the gate T14; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, wherein the second contact portion 13b is multiplexed as a first channel portion 13c of the first transistor T1; the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, wherein the third contact portion 23a is multiplexed as a second channel portion 23c of the second transistor T2.

[0143] The first contact portion 13a and the fourth contact portion 23b are both conductive portions formed by conducting the active layer, and the conductive properties of the conductive portions are higher than the conductive properties of the first channel portion 13c (and also higher than the conductive properties of the second channel portion 23c), and the conductive properties of the conductive portions are lower than the metal electrodes. 2 NH 3 The first contact portion 13a and the fourth contact portion 23b are formed by plasma treatment of the gas (including the mixed gas) and conductive doping.

[0144] As shown in FIG. 13 a , the second contact portion 13 b and the third contact portion 23 a are connected to form an integral structure.

[0145] As shown in Fig. 13a, the data line Date is multiplexed as the first electrode T11 of the first transistor T1. The second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22 through the third via hole Via3.

[0146] In the embodiment of the present disclosure, whether it is a bottom-gate transistor or a top-gate transistor, the second contact portion 13b and the third contact portion 23a connected as one body can be used to realize the series connection of two transistors.

[0147] Compared with the top-gate transistor, the bottom-gate transistor can reuse the gate electrode on the side of the active layer close to the substrate 1 as an optical protective film for the active layer, and can prevent the carriers generated by the light emitted by the backlight source from irradiating the active layer and destroying the electrical characteristics of the active layer. Therefore, the device performance of the bottom-gate transistor is more stable than that of the top-gate transistor. In addition, in this embodiment, the second contact portion 13b and the third contact portion 23a are connected as an integral structure, that is, the first channel portion 13c and the second channel portion 23c are connected as an integral structure, which increases the channel length of the transistor and reduces the occurrence of conductorization.

[0148] Exemplarily, as shown in FIG13b, the display substrate further includes a first conductive layer 41 disposed on the base substrate 1; a first insulating layer 31 disposed on the side of the first conductive layer 41 away from the base substrate 1; a semiconductor layer ACT disposed on the side of the first insulating layer 31 away from the first conductive layer 41; a second conductive layer 42 disposed on the side of the semiconductor layer ACT away from the first insulating layer 31; and a second insulating layer 32 disposed on the side of the second conductive layer 42 away from the semiconductor layer ACT. The gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 (including the second contact portion 13b multiplexed as the second electrode T12 of the first transistor T1) and the active layer T23 of the second transistor T2 (including the third contact portion 23a multiplexed as the first electrode T21 of the second transistor T2) are both located in the semiconductor layer ACT; the first electrode T11 of the first transistor T1 and the second electrode T22 of the second transistor T2 are both located in the second conductive layer 42.

[0149] In some embodiments, FIG. 14a is a schematic diagram of the structure of another bottom-gate transistor provided in an embodiment of the present disclosure, and FIG. 14b is a cross-sectional view of the structure shown in FIG. 14a along the DD direction. As shown in FIG. 14a and FIG. 14b, the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged in the same layer; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged in the same layer; the first electrode T11 and the second electrode T12 of the first transistor T1 are arranged in the same layer as the first electrode T21 and the second electrode T22 of the second transistor T2; The gate T14 of the body transistor T1 is located on a side of the active layer close to the substrate 1; the first electrode T11 and the second electrode T12 of the first transistor T1 are located on a side of the active layer away from the gate; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, and a first channel portion 13c located between the first contact portion 13a and the second contact portion 13b; the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, and a second channel portion 23c located between the third contact portion 23a and the fourth contact portion 23b.

[0150] The first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b are all conductive portions formed after the active layer is conductively converted. The conductive properties of the conductive portions are higher than those of the first channel portion 13c (and also higher than those of the second channel portion 23c). The conductive properties of the conductive portions are lower than those of the metal electrodes. For example, He, Ar, H 2 , NH 3The first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b are formed by plasma treatment with gases (including mixed gases) and conductive doping.

[0151] As shown in Figure 14a, the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 are connected as an integrated structure, and the second electrode T12 of the first transistor T1 is electrically connected to the second contact portion 13b of the first transistor T1; the first electrode T21 of the second transistor T2 is electrically connected to the third contact portion 23a of the second transistor T2.

[0152] As shown in Fig. 14a, the data line Date is multiplexed as the first electrode T11 of the first transistor T1. The second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22 through the third via hole Via3.

[0153] The transistor with the bottom gate structure shown in FIG14b is connected in series in a different manner from the transistor with the bottom gate structure shown in FIG13b. Compared with the transistor with the bottom gate structure shown in FIG13b, the transistor with the bottom gate structure shown in FIG14b uses a metal electrode (the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 connected as an integral structure) to achieve series connection. Since the conductivity of the metal electrode is higher than the conductivity of the second contact portion 13b and the third contact portion 23a after being conductorized, the bottom gate structure shown in FIG14b is used, and the device stability is higher. In addition, in this embodiment, the two transistors are connected in series. If one of them is abnormally turned off after conductorization, the other can still ensure normal operation.

[0154] Exemplarily, as shown in FIG14b, the display substrate further includes a first conductive layer 41 disposed on the substrate; a first insulating layer 31 disposed on the side of the first conductive layer 41 away from the substrate 1; a semiconductor layer ACT disposed on the side of the first insulating layer 31 away from the first conductive layer 41; a second conductive layer 42 disposed on the side of the semiconductor layer ACT away from the first insulating layer 31; and a second insulating layer 32 disposed on the side of the second conductive layer 42 away from the semiconductor layer ACT. The gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both located in the semiconductor layer ACT; the first electrode T11 and the second electrode of the first transistor T1, and the first electrode T21 and the second electrode of the second transistor T2 are both located in the second conductive layer 42.

[0155] Exemplarily, the first conductive layer 41 may be provided with a single-layer structure, using materials such as Al or Cu. Alternatively, the first conductive layer 41 may be provided with a composite film structure, including a buffer layer and a main conductive layer, wherein the material of the buffer layer may be a Ti-based alloy material or a Mo-based alloy material, and the material of the main conductive layer may be a Al or Cu-based material. Alternatively, the first conductive layer 41 may be provided with a single-layer structure, using Al or Cu with Ti-based alloy material or Mo-based alloy material added thereto.

[0156] For example, as shown in FIG. 13 b or FIG. 14 b , the first insulating layer 31 may be a gate insulating layer, and the material of the gate insulating layer may generally be SiOx (x>0) material.

[0157] Exemplarily, as shown in FIG. 13b or FIG. 14b, in terms of the coverage of the gate and the reduction of capacitance, since the first insulating layer 31 as the gate insulating layer is required to cover and protect the bottom gate structure in the process, and the thickness of the first insulating layer 31 as the gate insulating layer affects the capacitance, the thickness of the first insulating layer 31 as the gate insulating layer is larger than that of the top gate structure. In addition, in terms of the requirement for Ion, the thinner the first insulating layer 31 as the gate insulating layer, the higher the Ion. Combining the above two requirements, the thickness of the first insulating layer 31 can be 300nm to 500nm. Exemplarily, as shown in FIG. 13b or FIG. 14b, the material of the second conductive layer 42 is metal.

[0158] Exemplarily, as shown in FIG. 13 b or FIG. 14 b , the second insulating layer 32 is a channel protection layer, the material of the channel protection layer can generally be SiOx (x>0) material, and the thickness of the second insulating layer 32 is not less than 100 nm.

[0159] Exemplarily, as shown in FIG. 13b or FIG. 14b, the second insulating layer 32 is a channel protection layer, and the material of the channel protection layer can generally be a composite film layer of SiN and SiOx (x>0), and the overall thickness of the second insulating layer 32 is between 200nm and 400nm. In addition, the selection of the thickness of the second insulating layer 32 is not only a requirement for the thickness coverage of the second conductive layer 42, but also a requirement for the protection of TFT characteristics, such as the thickness requirement of the SiOx (x>0) film layer to ensure that the device does not become conductive, and the use of the SiN film layer to block the influence of water vapor on the organic film layer (the water vapor barrier capability of the SiN film layer is better than that of the SiOx (x>0) film layer), etc.

[0160] In some embodiments, as shown in FIG. 13b or FIG. 14b, the pixel units 2 in the same row are electrically connected to the same gate line Gate; the gate line Gate is used as the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2; the gate line Gate is a composite film layer, including a buffer layer and a main conductive layer sequentially arranged on the base substrate 1. The material of the buffer layer can be Ti-based alloy material or Mo-based alloy material, and the material of the main conductive layer can be Al or Cu and other materials.

[0161] In some embodiments, as shown in Figures 17i, 18i and 8b, the pixel unit 2 further includes a second electrode 23, and the second electrode 23 is located on a side of the pixel electrode ITO close to the base substrate 1. The second electrode 23 is a common electrode.

[0162] In some embodiments, as shown in FIG8d, the pixel electrode ITO is a slit electrode; the common electrode is a plate electrode. The pixel electrode ITO is electrically connected to the second electrode T22 of the second transistor T2 through the third via hole via3. As shown in FIG8a and FIG8c, the third via hole via3 includes a first sub-hole via31 penetrating the planarization layer 342, and a second sub-hole via32 penetrating the metal protection layer 341. The pixel electrode ITO is electrically connected to the second electrode T22 of the second transistor T2 through the first sub-hole via31 and the second sub-hole via32 in sequence.

[0163] In addition, the embodiment of the present disclosure further provides a display device, which includes the display substrate of any one of the above embodiments. The display device can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as a limitation to the present disclosure.

[0164] In addition, an embodiment of the present disclosure further provides a method for preparing a display substrate, which is used for preparing the display substrate of any one of the above embodiments.

[0165] The method specifically includes: providing a base substrate 1; forming a plurality of pixel units 2 arranged in an array on the base substrate 1. The step of forming the pixel unit 2 at least includes: sequentially forming a pixel circuit 21 and a first electrode 22 on the base substrate 1. The pixel circuit 21 at least includes a first transistor T1 and a second transistor T2; the second electrode T12 of the first transistor T1 is electrically connected to the first electrode T21 of the second transistor T2, and the second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22. The materials of the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both metal oxide semiconductor materials.

[0166] In some embodiments, FIG. 15a to FIG. 15j are schematic diagrams of a process for preparing a display substrate shown in FIG. 5b provided in an embodiment of the present disclosure, specifically including the following steps S11 to S111, wherein:

[0167] S11, providing a substrate 1.

[0168] In this step, the base substrate 1 is a glass substrate.

[0169] S12, as shown in FIG. 15 a, a light shielding layer 50 is formed on the base substrate 1.

[0170] S13 . As shown in FIG. 15 b , a first insulating layer 31 is formed on the side of the light shielding layer 50 facing away from the base substrate 1 .

[0171] S14 , as shown in FIG. 15 c , a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .

[0172] Specifically, the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.

[0173] S15 . As shown in FIG. 15 d , a second insulating layer 32 and a first conductive layer 41 are formed on a side of the semiconductor layer ACT away from the first insulating layer 31 .

[0174] The second insulating layer 32 is a gate insulating layer, and the first conductive layer 41 includes a gate, or a gate line Gate multiplexed as a gate.

[0175] The material of the gate insulating layer and the material of the first conductive layer 41 are deposited in sequence; then, gate photolithography and etching are performed, and the gate insulating layer is etched using the gate as a mask to expose the semiconductor layer ACT and then conduct it. The conductorization process can be processed using plasma (Plasma) of gases such as He, Ar, H2, NH3 (including mixed gases).

[0176] It should be noted that the conductive second contact portion 13 b is directly connected to the conductive third contact portion 23 a .

[0177] S16. As shown in FIG. 15e, a third insulating layer 33 is continuously formed on the basis of step S15.

[0178] The material of the second insulating layer 32 is deposited, and then the intermediate dielectric layer is photolithographically processed and etched to form a first via hole Via1 to the first contact portion 13 a of the active layer and a second via hole Via2 to the fourth contact portion 23 b.

[0179] S17. As shown in FIG. 15 f , a second conductive layer 42 is formed on a side of the third insulating layer 33 facing away from the substrate 1 .

[0180] The material of the second conductive layer 42 is a metal material, and the second conductive layer 42 is electrically connected to the first contact portion 13a and the fourth contact portion 23b respectively through the first via hole Via1 and the second via hole Via2 penetrating the third insulating layer 33. The second contact portion 13b is multiplexed as the second electrode T12 of the first transistor T1, and the third contact portion 23a is multiplexed as the first electrode T21 of the second transistor T2.

[0181] S18 . As shown in FIG. 15 g , a fourth insulating layer 34 is formed on a side of the second conductive layer 42 away from the third insulating layer 33 .

[0182] The fourth insulating layer 34 may be a metal protection layer 341 and a planarization layer 342 .

[0183] The materials of the metal protection layer 341 and the planarization layer 342 are deposited in sequence; then, the planarization layer 342 is subjected to organic material photolithography to form a first sub-hole Via31.

[0184] S19. As shown in FIG. 15 h , a second electrode 23 is formed on a side of the fourth insulating layer 34 away from the third insulating layer 33 .

[0185] The second electrode 23 is a common electrode.

[0186] S110 , as shown in FIG. 15 i , forming a fifth insulating layer 35 on a side of the second electrode 23 away from the fourth insulating layer 34 .

[0187] The fifth insulating layer 35 is a passivation layer.

[0188] The material of the passivation layer is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.

[0189] S111 , as shown in FIG. 15 j , a pixel electrode ITO is formed on a side of the fifth insulating layer 35 away from the second electrode 23 .

[0190] The pixel electrode ITO is a slit electrode and has a connection portion, which is connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2) through the third via hole Via3; the auxiliary component 6 is connected to the fourth contact portion 23b through the second via hole Via2.

[0191] In some embodiments, FIG. 16a to FIG. 16j are schematic diagrams of a process for preparing a display substrate shown in FIG. 9b provided in an embodiment of the present disclosure, specifically including the following steps S21 to S211, wherein:

[0192] S21, providing a substrate 1.

[0193] In this step, the base substrate 1 is a glass substrate.

[0194] S22 . As shown in FIG. 16 a , a light shielding layer 50 is formed on the base substrate 1 .

[0195] S23 . As shown in FIG. 16 b , a first insulating layer 31 is formed on the side of the light shielding layer 50 facing away from the base substrate 1 .

[0196] S24 , as shown in FIG. 16 c , a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .

[0197] Specifically, the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.

[0198] S25 . As shown in FIG. 16 d , a second insulating layer 32 and a first conductive layer 41 are formed on a side of the semiconductor layer ACT away from the first insulating layer 31 .

[0199] The second insulating layer 32 is a gate insulating layer, and the first conductive layer 41 includes a gate, or a gate line Gate multiplexed as a gate.

[0200] The material of the gate insulating layer and the material of the first conductive layer 41 are deposited in sequence; then, gate photolithography and etching are performed, and the gate insulating layer is etched using the gate as a mask to expose the semiconductor layer ACT and then conduct it. The conductorization process can be processed using plasma (Plasma) of gases such as He, Ar, H2, NH3 (including mixed gases).

[0201] S26. As shown in FIG. 16e, a third insulating layer 33 is continuously formed on the basis of step S25.

[0202] The material of the second insulating layer 32 is deposited, and then the intermediate dielectric layer is photolithographically and etched to form a first via Via1 to the first contact portion 13a of the active layer, a fourth via Via4 to the second contact portion 13b, a fifth via Via5 to the third contact portion 23a, and a second via Via2 to the fourth contact portion 23b.

[0203] S27 . As shown in FIG. 16 f , a second conductive layer 42 is formed on a side of the third insulating layer 33 facing away from the substrate 1 .

[0204] The material of the second conductive layer 42 is a source / drain metal, in which the drain of the first transistor T1 is electrically connected to the first contact portion 13a through a first via Via1 that penetrates the third insulating layer 33. The source of the first transistor T1 is electrically connected to the drain of the second transistor T2, and is electrically connected to the second contact portion 13b and the third contact portion 23a through a fourth via Via4 and a fifth via Via5, respectively. The source of the second transistor T2 is electrically connected to the fourth contact portion 23b through a second via Via2. The auxiliary component 6 is reused as the source of the second transistor T2. The auxiliary component 6 is connected to the third via Via4 through the third via Via5.

[0205] S28 . As shown in FIG. 16 g , a fourth insulating layer 34 is formed on a side of the second conductive layer 42 away from the third insulating layer 33 .

[0206] The fourth insulating layer 34 is a planarization layer.

[0207] The material of the planarization layer is deposited, and then the organic material is photolithographically processed to form the first sub-hole Via31.

[0208] S29 . As shown in FIG. 16 h , a second electrode 23 is formed on a side of the fourth insulating layer 34 away from the third insulating layer 33 .

[0209] The second electrode 23 is a common electrode.

[0210] S210 , as shown in FIG. 16 i , forming a fifth insulating layer 35 on a side of the second electrode 23 away from the fourth insulating layer 34 .

[0211] The fifth insulating layer 35 is a passivation layer.

[0212] The material of the passivation layer is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.

[0213] S211 , as shown in FIG. 16 j , a pixel electrode ITO is formed on a side of the fifth insulating layer 35 away from the second electrode 23 .

[0214] The pixel electrode ITO is a slit electrode and has a connection portion, which is connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2) through the third via hole Via3; the auxiliary component 6 is connected to the fourth contact portion 23b through the second via hole Via2.

[0215] In some embodiments, FIG. 17a to FIG. 17i are schematic diagrams of a process for preparing a display substrate shown in FIG. 13b provided in an embodiment of the present disclosure, specifically including the following steps S31 to S310, wherein:

[0216] S31, providing a substrate 1.

[0217] In this step, the base substrate 1 is a glass substrate.

[0218] S32 , as shown in FIG. 17 a , forming a first conductive layer 41 on the base substrate 1 .

[0219] The first conductive layer 41 is a composite film layer, including a buffer layer and a main conductive layer sequentially arranged on the base substrate 1. The material of the buffer layer can be Ti alloy material or Mo alloy material, and the material of the main conductive layer can be Al or Cu.

[0220] The first conductive layer 41 includes a gate line Gate which is multiplexed as the gate of the first transistor T1 and the gate of the second transistor T2 .

[0221] S33 , as shown in FIG. 17 b , forming a first insulating layer 31 on a side of the first conductive layer 41 away from the substrate 1 .

[0222] S34 , as shown in FIG. 17 c , a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .

[0223] Specifically, the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.

[0224] The semiconductor layer ACT is conductively processed using a mask. The conductive process may be processed using plasma of gases such as He, Ar, H2, NH3 (including mixed gases) to form the first contact portion 13a and the fourth contact portion 23b of the active layer.

[0225] S35 , as shown in FIG. 17 d , forming a second conductive layer 42 on a side of the semiconductor layer ACT away from the first insulating layer 31 .

[0226] The second conductive layer 42 includes a first electrode T11 of the first transistor T1 and a second electrode T22 of the second transistor T2. The first electrode T11 of the first transistor T1 is directly connected to the first contact portion 13a, the second contact portion 13b is multiplexed as the first channel portion 13c of the first transistor T1, and the third contact portion 23a is multiplexed as the second channel portion 23c of the second transistor T2. The second contact portion 13b and the third contact portion 23a are connected as an integral structure, and the second electrode T22 of the second transistor T2 is directly connected to the fourth contact portion 23b.

[0227] In order to prevent the active layer (IGZO) from being excessively damaged by the etching solution, it is preferred to use a Cu stack and a hydrogen peroxide-based etching solution to complete the process of forming the second conductive layer 42 .

[0228] S36 . As shown in FIG. 17 e , a second insulating layer 32 is formed on a side of the second conductive layer 42 away from the first insulating layer 31 .

[0229] The second insulating layer 32 is a channel protection layer.

[0230] S37 . As shown in FIG. 17 f , a third insulating layer 33 is formed on a side of the second insulating layer 32 away from the second conductive layer 42 .

[0231] The third insulating layer 33 is a planarization layer.

[0232] The material of the planarization layer is deposited, and then the organic material is photolithographically processed to form the first sub-hole Via31.

[0233] S38 . As shown in FIG. 17 g , a second electrode 23 is formed on a side of the third insulating layer 33 that is away from the second insulating layer 32 .

[0234] The second electrode 23 is a common electrode.

[0235] S39. As shown in FIG. 17h, a fourth insulating layer 34 is formed on a side of the second electrode 23 away from the third insulating layer.

[0236] The fourth insulating layer 34 is a passivation layer.

[0237] The material of the passivation layer is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.

[0238] S310 , as shown in FIG. 17 i , a pixel electrode ITO is formed on a side of the fourth insulating layer 34 away from the second electrode 23 .

[0239] The pixel electrode ITO is a slit electrode and has a connection portion, which is connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2) through the third via hole Via3; the auxiliary component 6 is directly connected to the fourth contact portion 23b.

[0240] In some embodiments, FIG. 18a to FIG. 18i are schematic diagrams of a process for preparing a display substrate shown in FIG. 10 provided in an embodiment of the present disclosure, specifically including the following steps S41 to S410, wherein:

[0241] S41, providing a substrate 1.

[0242] In this step, the base substrate 1 is a glass substrate.

[0243] S42 , as shown in FIG. 18 a , forming a first conductive layer 41 on the base substrate 1 .

[0244] The first conductive layer 41 is a composite film layer, including a buffer layer and a main conductive layer sequentially arranged on the base substrate 1. The material of the buffer layer can be Ti alloy material or Mo alloy material, and the material of the main conductive layer can be Al or Cu.

[0245] The first conductive layer 41 includes a gate line Gate which is multiplexed as the gate of the first transistor T1 and the gate of the second transistor T2 .

[0246] S43 , as shown in FIG. 18 b , forming a first insulating layer 31 on a side of the first conductive layer 41 away from the base substrate 1 .

[0247] S44 , as shown in FIG. 18 c , a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .

[0248] Specifically, the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.

[0249] The semiconductor layer ACT is conductorized using a mask. The conductorization process can be processed using plasma (Plasma) of gases such as He, Ar, H2, NH3 (including mixed gases) to form the first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b of the active layer.

[0250] S45 , as shown in FIG. 18 d , forming a second conductive layer 42 on a side of the semiconductor layer ACT away from the first insulating layer 31 .

[0251] The second conductive layer 42 includes a first electrode T11 and a second electrode of the first transistor T1, and a first electrode T21 and a second electrode of the second transistor T2. The second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 are an integrated structure. The first electrode T11 of the first transistor T1 is directly connected to the first contact portion 13a, the second electrode T12 of the first transistor T1 is directly connected to the second contact portion 13b, the first electrode T21 of the second transistor T2 is directly connected to the third contact portion 23a, and the second electrode T22 of the second transistor T2 is directly connected to the fourth contact portion 23b.

[0252] In order to prevent the active layer (IGZO) from being excessively damaged by the etching solution, it is preferred to use a Cu stack and a hydrogen peroxide-based etching solution to complete the process of forming the second conductive layer 42 .

[0253] S46 . As shown in FIG. 18 e , a second insulating layer 32 is formed on a side of the second conductive layer 42 away from the first insulating layer 31 .

[0254] The second insulating layer 32 is a channel protection layer.

[0255] S47 . As shown in FIG. 18 f , a third insulating layer 33 is formed on a side of the second insulating layer 32 away from the second conductive layer 42 .

[0256] The third insulating layer 33 is a planarization layer.

[0257] The material of the planarization layer is deposited, and then the organic material is photolithographically processed to form the first sub-hole Via31.

[0258] S48 . As shown in FIG. 18 g , a second electrode 23 is formed on a side of the third insulating layer 33 that is away from the second insulating layer 32 .

[0259] The second electrode 23 is a common electrode.

[0260] S49. As shown in FIG. 18h, a fourth insulating layer 34 is formed on a side of the second electrode 23 away from the third insulating layer.

[0261] The fourth insulating layer 34 is a passivation layer.

[0262] The material of the passivation layer is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.

[0263] S410 , as shown in FIG. 18 i , a pixel electrode ITO is formed on a side of the fourth insulating layer 34 away from the second electrode 23 .

[0264] The pixel electrode ITO is a slit electrode and has a connection portion, which is connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2) through the third via hole Via3; the auxiliary component 6 is directly connected to the fourth contact portion 23b.

[0265] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

A display substrate comprises a base substrate, and gate lines and data lines located on the base substrate, wherein the gate lines and the data lines intersect to define a plurality of pixel units; the gate lines extend along a first direction, and the data lines extend along a second direction, and the first direction and the second direction intersect; the pixel unit comprises a first transistor and a second transistor; the active layer of the first transistor comprises a first contact portion and a second contact portion, and the active layer of the second transistor comprises a third contact portion and a fourth contact portion, the first contact portion is electrically connected to the data line, the second contact portion is electrically connected to the third contact portion, and the fourth contact portion is electrically connected to the first electrode of the pixel unit; along the second direction, the maximum spacing between the first contact portion and the gate line is not less than the maximum spacing between the fourth contact portion and the same gate line. The display substrate according to claim 1, wherein: Along the first direction, a width of the first contact portion is smaller than a width of the fourth contact portion. The display substrate according to claim 1, wherein: The orthographic projection of the first contact portion on the base substrate overlaps with the orthographic projection of the data line on the base substrate, the first contact portion includes a first part and a second part connected to each other, the first part is electrically connected to the data line, and along the first direction, the width of the first part is greater than the width of the second part. The display substrate according to claim 3, wherein: The orthographic projection of the fourth contact portion on the substrate overlaps with the orthographic projection of the gate line on the substrate, the fourth contact portion includes a third portion and a fourth portion connected to each other, the fourth portion is electrically connected to the first electrode, and along the second direction, the minimum width of the fourth portion is greater than the minimum width of the third portion. The display substrate according to claim 1, wherein: The first contact portion is electrically connected to the data line through a first via hole, and the fourth contact portion is electrically connected to the first electrode through a second via hole; along the second direction, the minimum spacing between the first via hole and the gate line is greater than the minimum spacing between the second via hole and the same gate line. The display substrate according to claim 1, wherein: The first contact portion is electrically connected to the data line through a first via hole, and the fourth contact portion is electrically connected to the first electrode through a second via hole and a third via hole; along the second direction, the minimum spacing between the first via hole and the gate line is greater than the minimum spacing between the second via hole and the same gate line; The minimum distance between the third via hole and the gate line is smaller than the minimum distance between the second via hole and the same gate line. The display substrate according to claim 6, wherein: The pixel unit further includes an auxiliary component; the auxiliary component includes a fifth portion and a sixth portion connected to each other, the fifth portion is electrically connected to the fourth contact portion through the second via hole; the sixth portion is electrically connected to the first electrode through the third via hole. The display substrate according to claim 7, wherein: The auxiliary component is arranged in the same layer as the data line, and in the first direction, the auxiliary component is arranged between two adjacent data lines at positions where they are connected to the first contact portion. The display substrate according to claim 1, wherein: The first contact portion, the second contact portion, the third contact portion and the fourth contact portion are arranged in the same layer. The display substrate according to claim 1, wherein: The active layer of the first transistor and / or the active layer of the second transistor includes a metal oxide semiconductor material. The display substrate according to claim 10, wherein: The active layers of the first transistor and the second transistor include a plurality of stacked sub-layers, and the mobility of the sub-layers away from the substrate is smaller than the mobility of the sub-layers close to the substrate. The display substrate according to claim 1, wherein: The gate of the first transistor is located on a side of the active layer of the first transistor away from the substrate; the gate of the second transistor is located on a side of the active layer of the second transistor away from the substrate; the active layer of the first transistor and the active layer of the second transistor are arranged on the same layer; The data line is multiplexed as the first electrode of the first transistor; the second contact portion is multiplexed as the second electrode of the first transistor, the third contact portion is multiplexed as the first electrode of the second transistor, and the second contact portion and the third contact portion are connected as an integrated structure. The display substrate according to claim 12, wherein: The first electrode is a pixel electrode; The orthographic projections of the second contact portion and the third contact portion connected as one body on the base substrate partially overlap with the orthographic projection of at least one pixel electrode on the base substrate. The display substrate according to claim 13, wherein: For two adjacent pixel units, the orthographic projection of the second contact portion and the third contact portion connected as one body in one of the pixel units on the base substrate partially overlaps with the orthographic projection of the other pixel unit on the base substrate. The display substrate according to claim 12, wherein: The active layer of the first transistor also includes a first channel portion arranged between the first contact portion and the second contact portion, and the active layer of the second transistor also includes a second channel portion arranged between the third contact portion and the fourth contact portion; the first channel portion, the second contact portion and the third contact portion connected as a whole, and the second channel portion The contour shape of the positive projection on the substrate is U-shaped. The display substrate according to claim 1, wherein: The gate of the first transistor and the gate of the second transistor are arranged on the same layer; the active layer of the first transistor and the active layer of the second transistor are arranged on the same layer; the first electrode and the second electrode of the first transistor are arranged on the same layer as the first electrode and the second electrode of the second transistor; the gate of the first transistor is located on the side of the active layer away from the substrate; the first electrode and the second electrode of the first transistor are located on the side of the gate away from the active layer; the data line is multiplexed as the first electrode of the first transistor; the second electrode of the first transistor and the first electrode of the second transistor are connected as an integral structure, and the second electrode of the first transistor is electrically connected to the second contact portion through a fourth via hole, and the first electrode of the second transistor is electrically connected to the third contact portion through a fifth via hole. The display substrate according to any one of claims 12 to 16, wherein: The display substrate also includes a light-shielding layer arranged near the pixel unit to the base substrate; the active layer of the first transistor also includes a first channel portion arranged between the first contact portion and the second contact portion, and the active layer of the second transistor also includes a second channel portion arranged between the third contact portion and the fourth contact portion; the orthographic projection of the light-shielding layer on the base substrate at least covers the orthographic projections of the first channel portion and the second channel portion on the base substrate. The display substrate according to claim 17, wherein: In a first direction, a first distance exists between an edge of an outline of an orthographic projection of the light shielding layer on the base substrate and an edge of an outline of an orthographic projection of the first channel portion on the base substrate; In the first direction, there is a second spacing between the contour edge of the orthographic projection of the light shielding layer on the base substrate and the contour edge of the orthographic projection of the second channel portion on the base substrate; the first spacing and / or the second spacing ranges from 4 μm to 6 μm. The display substrate according to claim 17, wherein: In the second direction, a third distance exists between an edge of an outline of an orthographic projection of the light shielding layer on the base substrate and an edge of an outline of an orthographic projection of the first channel portion on the base substrate; In the second direction, there is a fourth spacing between the contour edge of the orthographic projection of the light shielding layer on the base substrate and the contour edge of the orthographic projection of the second channel portion on the base substrate; the third spacing and / or the fourth spacing ranges from 0 to 4 μm. The display substrate according to any one of claims 1 to 16, wherein The pixel units in the same row are electrically connected to the same gate line; the gate line is used as the gate of the first transistor and the gate of the second transistor. The display substrate according to any one of claims 1 to 16, wherein A gate insulating layer is disposed on a side of the gate of the first transistor close to the active layer; the thickness of the gate insulating layer is between 10 nm and 30 nm. The display substrate according to claim 1, wherein: The gate of the first transistor and the gate of the second transistor are arranged in the same layer; the active layer of the first transistor and the active layer of the second transistor are arranged in the same layer; the first electrode and the second electrode of the first transistor are arranged in the same layer as the first electrode and the second electrode of the second transistor; the gate of the first transistor is located on the side of the active layer close to the substrate; the first electrode and the second electrode of the first transistor are located on the side of the active layer away from the gate; the data line is multiplexed as the first electrode of the first transistor; the second electrode of the first transistor and the first electrode of the second transistor are connected as an integral structure, and the second electrode of the first transistor is electrically connected to the second contact portion of the first transistor; the first electrode of the second transistor is electrically connected to the third contact portion of the second transistor. The display substrate according to claim 22, wherein The pixel units in the same row are electrically connected to the same gate line; the gate line is used as the gate of the first transistor and the gate of the second transistor; the gate line is a composite film layer, including a buffer layer and a main conductive layer sequentially arranged on the base substrate. The display substrate according to claim 22, wherein A gate insulating layer is disposed on a side of the gate of the first transistor close to the active layer; the thickness of the gate insulating layer is between 30nm and 50nm. A display device, wherein The invention comprises the display substrate according to any one of claims 1 to 24.

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