Chip testing method and system, chip, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention relates to the technical field of chips, and discloses a chip testing method and system, a chip, electronic equipment and a computer readable storage medium, and the chip testing method comprises the steps: capturing input data of a TDI pin through a first TDR register so as to input the input data to a scanning circuit, and capturing output data of the scanning circuit through a second TDR register so as to input the output data to the scanning circuit; according to the chip fault detection method and the chip fault detection device provided by the invention, the chip can be prevented from being disassembled from the circuit board for retest operation, the chip can be directly tested on the circuit board by using the chip JTAG port, the test efficiency is improved, the test time is shortened, the test cost is reduced, and the test efficiency is improved. And the chip fault detection efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip testing method, system, chip, electronic device and computer-readable storage medium. Background Art

[0002] Defective chips are inevitable during manufacturing. It is necessary to use DFT Scan Chain (Design For Test Scan Chain) technology to test the manufactured chips, eliminate defective products, and sell good products to customers.

[0003] However, after customers use the chips to make products, they may still find product-level mass production defects, and need to locate the cause of the defects. For example, it is necessary to clarify whether the product-level defects are caused by chip defects. Chips are all good products that have passed mass production test screening before leaving the factory, so this chip defect may come from the chip transportation and storage process, but it may also be because the chip mass production test is not complete, resulting in escaped chips. At this time, it is necessary to use DFT Scan Chain technology to retest the suspected defective chips.

[0004] The chip pins required for the DFT Scan circuit are reused with the functional pins. In the test plant, the chip is placed in the socket and connected to the ATE machine through the Load Board. The ATE machine inputs stimulus to the Scan circuit through these reused pins, and grabs the output of the Scan Chain from the reused pins, and compares it with the expected value to determine whether the chip is a good product. However, after the product is made, since the chip has been soldered on the product PCB board, these reused functional pins have been connected to other devices on the PCB, so the ATE machine cannot input stimulus from these pins to drive the scan chain, nor can it grab the output of the scan chain from these pins.

[0005] Currently, the chip is usually removed from the product board (heating the chip, melting the solder balls, and removing the chip). Since the solder balls are damaged during removal, the chip needs to be transported to the packaging factory for re-balling, and then transported to the testing factory and placed in the socket of the Load Board of the ATE machine for retesting, resulting in a lengthy retesting process and high costs. Summary of the invention

[0006] The embodiments of the present application provide a chip testing method, system, chip, electronic device and computer-readable storage medium to improve the efficiency of chip fault detection.

[0007] To solve the above technical problems, the present application provides the following technical solutions:

[0008] In a first aspect, an embodiment of the present application provides a chip testing method, which is applied to a chip, the chip is placed on a circuit board, the chip includes a TDI pin, a TDO pin, a scanning circuit, a first TDR register and a second TDR register, the scanning circuit is connected to the first TDR register and the second TDR register respectively, the first TDR register is connected to the TDI pin, and the second TDR register is connected to the TDO pin, the method includes:

[0009] Generate input data through the JTAG tool, where the TDI pin is used to input input data to the scanning circuit;

[0010] Capturing input data of the TDI pin through the first TDR register and inputting the input data to the scanning circuit; and capturing output data outputted by the scanning circuit through the second TDR register and outputting the output data to the TDO pin;

[0011] Through the JTAG tool, obtain the output data output by the TDO pin and compare the output data with the expected data to determine the fault status of the chip.

[0012] In some embodiments,

[0013] The chip also includes a TAP controller, the TAP controller is connected to the first TDR register and the second TDR register;

[0014] The method includes capturing input data of a TDI pin through a first TDR register and inputting the input data to a scanning circuit; and capturing output data output by the scanning circuit through a second TDR register and outputting the output data to a TDO pin, including:

[0015] Control the TAP controller to enter the Capture_DR state so that the second TDR register captures the output data output by the scanning circuit;

[0016] Control the TAP controller to enter the Shift_DR state, so that the output data stored in the second TDR register is shifted out through the TDO pin, and the input data inputted by the TDI pin is shifted into the first TDR register;

[0017] The TAP controller is controlled to enter the Update_DR state, so that the input data stored in the first TDR register is input to the scan circuit to drive the operation of the scan circuit.

[0018] In some embodiments,

[0019] The JTAG tool is used to run the SVF file, which includes multiple test vectors;

[0020] The method also includes:

[0021] The state of the TAP controller is switched cyclically in the order of Capture_DR state, Shift_DR state, and Update_DR state, where each cycle corresponds to a test vector;

[0022] Determine whether the chip test mode is ended;

[0023] If the SVF file is executed, it is determined that the chip test mode is ended;

[0024] If the SVF file is not executed completely, it is determined that the test mode of the chip is not ended, and the state of the TAP controller continues to be switched.

[0025] In some embodiments,

[0026] The chip includes a plurality of first TDR registers, each of which corresponds to an input signal of the scanning circuit, and the plurality of first TDR registers are connected in series, wherein each of the first TDR registers includes a first data flip-flop and a second data flip-flop;

[0027] After the TAP controller enters the Shift_DR state, the first data flip-flop of each first TDR register obtains and stores one bit of data from the TDI pin at each TCK clock edge;

[0028] After the TAP controller enters the Update_DR state, the second data flip-flops of all the first TDR registers obtain corresponding bit data from the corresponding first data flip-flops to obtain multiple bit data, wherein the multiple bit data are input into the scanning circuit in parallel.

[0029] In some embodiments,

[0030] The chip includes a plurality of second TDR registers, each of which corresponds to an output signal of the scanning circuit, and the plurality of second TDR registers are connected in series, wherein each of the second TDR registers includes a third data flip-flop;

[0031] After the TAP controller enters the Capture_DR state, the third data flip-flop of each second TDR register acquires and stores a bit of data from the scanning circuit;

[0032] After the TAP controller enters the Shift_DR state, the bit data stored in the third data flip-flop of each second TDR register is serially output to the TDO pin at the TCK clock edge.

[0033] In a second aspect, an embodiment of the present application provides a chip, including:

[0034] TDI pin;

[0035] TDO pin;

[0036] Scanning circuit;

[0037] TAP controller, the TAP controller is connected to the scanning circuit;

[0038] A first TDR register is connected to the TDI pin and the scanning circuit, and is used to capture input data of the TDI pin and input the input data to the scanning circuit;

[0039] The second TDR register is connected to the TDO pin and the scanning circuit, and is used for capturing output data output by the scanning circuit, and outputting the output data to the TDO pin.

[0040] In some embodiments,

[0041] The chip includes a plurality of first TDR registers, each of which corresponds to an input signal of the scanning circuit, and the plurality of first TDR registers are connected in series, wherein each of the first TDR registers includes a first data flip-flop and a second data flip-flop;

[0042] After the TAP controller enters the Shift_DR state, the first data flip-flop of each first TDR register obtains and stores one bit of data from the TDI pin at each TCK clock edge;

[0043] After the TAP controller enters the Update_DR state, the second data flip-flops of all the first TDR registers obtain corresponding bit data from the corresponding first data flip-flops to obtain multiple bit data, wherein the multiple bit data are input into the scanning circuit in parallel.

[0044] In a third aspect, an embodiment of the present application provides a chip testing system, including:

[0045] Such as the chip in the second aspect;

[0046] JTAG tool, used to test the chip.

[0047] In a fourth aspect, an embodiment of the present application provides an electronic device, including:

[0048] A processor and a memory, the processor is used to execute the executable program code in the memory, and when the executable program code is executed, the processor executes the instructions of the chip testing method of the first aspect.

[0049] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed, the chip testing method of the first aspect is implemented.

[0050] The beneficial effect of the embodiments of the present application is as follows: different from the prior art, the embodiments of the present application provide a chip testing method, the chip is placed on a circuit board, the chip includes a TDI pin, a TDO pin, a scanning circuit, a first TDR register and a second TDR register, the scanning circuit is connected to the first TDR register and the second TDR register respectively, the first TDR register is connected to the TDI pin, and the second TDR register is connected to the TDO pin, the method includes: generating input data through a JTAG tool, wherein the TDI pin is used to input input data to the scanning circuit; capturing the input data of the TDI pin through the first TDR register, and inputting the input data to the scanning circuit; and capturing the output data output by the scanning circuit through the second TDR register, and outputting the output data to the TDO pin; obtaining the output data output by the TDO pin through the JTAG tool, and comparing the output data with the expected data to determine the fault state of the chip.

[0051] The input data of the TDI pin is captured through the first TDR register to input the input data into the scanning circuit, and the output data of the scanning circuit is captured through the second TDR register to output through the TDO pin, and the output data of the TDO pin is further compared with the expected data through the JTAG tool to determine the fault state of the chip. The present application can avoid the operation of removing the chip from the circuit board for retesting, and realize chip testing directly on the circuit board using the chip JTAG port, thereby improving the efficiency of chip fault detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0053] Figure 1 is a schematic diagram of a DFT Scan circuit provided in an embodiment of the present application;

[0054] Figure 2 It is a schematic diagram of a chip test process provided by an embodiment of the present application;

[0055] Figure 3 is a schematic diagram of another chip test process provided by an embodiment of the present application;

[0056] Figure 4It is a flowchart of a chip testing method provided in an embodiment of the present application;

[0057] Figure 5 is a schematic diagram of a chip testing system provided in an embodiment of the present application;

[0058] Figure 6 It is a schematic diagram of a connection relationship between a first TDR register, a second TDR register and a chip provided in an embodiment of the present application;

[0059] Figure 7 is a schematic diagram of a TAP controller provided in an embodiment of the present application;

[0060] Figure 8 This is a schematic diagram of the overall process of a chip test provided by an embodiment of the present application;

[0061] Fig. 9 is a structural diagram of a first TDR register provided in an embodiment of the present application;

[0062] Fig. 10A is a schematic diagram of a bypass path of a first TDR register provided in an embodiment of the present application;

[0063] Fig. 10B is a schematic diagram of a Shift path of a first TDR register provided in an embodiment of the present application;

[0064] Fig. 10C is a schematic diagram of the Update path of the first TDR register provided in an embodiment of the present application;

[0065] Fig.11 is a schematic diagram of the connection relationship of multiple first TDR registers provided in an embodiment of the present application;

[0066] Fig.12 is a structural diagram of a second TDR register provided in an embodiment of the present application;

[0067] Fig.13A is a schematic diagram of a bypass path of a second TDR register provided in an embodiment of the present application;

[0068] Fig. 13B is a schematic diagram of a Capture path of a second TDR register provided in an embodiment of the present application;

[0069] Fig. 13C is a schematic diagram of a Shift path of a second TDR register provided in an embodiment of the present application;

[0070] Fig.14 is a schematic diagram of the connection relationship between two second TDR registers provided in an embodiment of the present application;

[0071] Fig.15 is a schematic diagram of the structure of a chip testing system provided in an embodiment of the present application;

[0072] Fig.16 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0073] Description of Figure Numbers:

[0074] Label name Label name 100 chip 101 First TDR register 102 Second TDR register 103 Scanning circuit 104 TAP Controller 105 Multiplexer 200 JTAG Tools 300 Chip test system 160 Electronic devices 161 processor 162 Memory DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0076] In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0077] Before describing the technical solution of the present application, the relevant technical terms are explained first.

[0078] (1) Design for Test (DFT) refers to taking test requirements into consideration during design, making integrated circuits easier to test and reducing the complexity of subsequent testing.

[0079] (2) Boundary Scan Cell (BSC) is a key component of boundary scan test technology and is mainly used for design for testability (DFT) of integrated circuits (ICs) and circuit boards. Each boundary scan cell is usually connected to an I / O pin, which can input test data from the outside into the chip and output the internal state to the outside. Multiple boundary scan cells are connected into a serial boundary scan chain (Boundary-Scan Chain), and data is transmitted through the boundary scan register (Boundary Scan Register, BSR), thereby allowing data from multiple cells to be transmitted sequentially in the boundary scan chain. Among them, the boundary scan cell selects different operating modes, such as test mode and normal operating mode, through specific control signals (such as TCK, TMS, TDI and TDO).

[0080] (3) Test Access Port (TAP) is a key component in boundary scan test technology. It is mainly used to control and access the boundary scan function inside the integrated circuit (IC) and to access the TDR register. TAP is part of the implementation of boundary scan standards (such as IEEE 1149.1), which allows the device to be tested and debugged without direct connection to the circuit pins.

[0081] (4) TAP Controller: refers to a controller used to manage and control the test access port (TAP). It is used to manage and control the operation of the test access port (TAP). A state machine is implemented inside the TAP controller, which can switch between different states according to the input of the TMS signal. The states of the TAP controller include: Test_Logic_Reset state, Run_Test_Idle state, Select_DR_Scan state, Select_IR_Scan state, Capture_DR state, Shift_IR state, Shift_DR state, etc.

[0082] (5) Data Flip-Flop (DFF), also known as D flip-flop, is a basic digital circuit element used to store a single bit of information. It receives input data and stores it when triggered by the edge of the clock signal (usually the rising edge or the falling edge). The D flip-flop is usually composed of two NAND gates or two NOR gates, and stores information through a feedback loop. When the signal at the data input end is 1, the D flip-flop stores the 1 state; when the signal at the data input end is 0, the D flip-flop stores the 0 state. In JTAG boundary scan testing, each DFF is usually connected to the input or output pin of the circuit. Through the DFF, the test system can control the flow of signals and read the state of the pin in the test mode. In the boundary scan chain, multiple DFFs are connected in sequence to form a scan chain. Through the JTAG interface, test data can be serially input into the chain in sequence and the results can be output from the chain. This enables faults to be detected without physically contacting the circuit. DFF can also be used to monitor the status of the circuit to help engineers debug and analyze. During the test, DFF can record the status of the circuit at different time points, thus providing a basis for troubleshooting.

[0083] (6) Test Data Register (TDR), which is used to store data transmitted during the boundary scan process. This data may include device status information, control instructions, or other signals that need to be tested.

[0084] The technical solution of the present application is described in detail below in conjunction with the accompanying drawings.

[0085] It is understandable that when designing a circuit, engineers will apply Design for Testability (DFT) technology to the circuit design so that corresponding test patterns can be generated at a later stage.

[0086] See also Figure 1 , Figure 1 It is a schematic diagram of a DFT Scan circuit provided in an embodiment of the present application.

[0087] like Figure 1 As shown, the chip pins and functional pins required by the DFT Scan circuit are multiplexed, for example: the test_clk of the scan circuit (scan circuit) multiplexes the functional pin gpio0, and the scan_en multiplexes the functional pin gpio1. In the test plant, the chip is placed in the socket and connected to the ATE machine through the Load Board. The ATE machine inputs the excitation signal to the scan circuit through these multiplexed pins, and captures the output of the scan chain (scan chain) from the multiplexed pins, and compares the output data with the expected value to determine whether the chip fails, that is, whether the chip is a good product. Among them, the scan circuit (scan circuit) is usually used to test and troubleshoot the circuit. It can be understood that the scan circuit is the scan chain circuit.

[0088] It is understandable that if defective chips appear in mass production, since the chips have been soldered on the product PCB board and the reused functional pins have been connected to other devices on the PCB board, the ATE machine cannot input excitation signals from these functional pins to drive the scan chain, nor can it capture the output of the scan chain from these pins.

[0089] At present, the usual practice for chip retesting is to remove the chip from the product board (heat the chip, melt the solder balls, and remove the chip). Since the solder balls are damaged during removal, the chip needs to be transported to the packaging factory for re-balling, and then transported to the testing factory and placed in the socket of the Load Board of the ATE machine for retesting.

[0090] See also Figure 2 , Figure 2 It is a schematic diagram of a chip test process provided in an embodiment of the present application.

[0091] like Figure 2 As shown, the chip testing process includes the following steps S201 to S205:

[0092] Step S201: The customer discovers a problem.

[0093] Step S202: The customer disassembles the chip.

[0094] Step S203: The packaging factory performs chip implantation.

[0095] Step S204: the test factory performs chip ATE retest.

[0096] Step S205: The chip supplier collects data for analysis and positioning.

[0097] It can be seen that the above chip testing process involves chip disassembly at the customer, ball implantation at the packaging factory, and retesting at the testing factory. The packaging factory and the testing factory also need to schedule production, and there is also logistics time in between, which makes the entire retesting process lengthy. In addition, it also involves the production costs of the packaging factory and the testing factory, resulting in high costs.

[0098] In view of this, the embodiments of the present application perform chip retesting directly on the circuit board, without the need to disassemble the chip, package and implant the ball, or ship it to a chip testing factory for retesting, thereby saving time and cost in locating mass production yield problems.

[0099] See also Figure 3 , Figure 3 It is a flowchart of another chip test provided in an embodiment of the present application.

[0100] like Figure 3 As shown, the chip test process includes the following steps S301 to S303:

[0101] Step S301: The customer discovers a problem.

[0102] Step S302: The chip supplier performs retesting on the customer's circuit board.

[0103] Step S303: The chip supplier collects data for analysis and positioning.

[0104] It can be seen that by having the chip supplier directly retest on the circuit board, the processes of chip disassembly, packaging and ball implantation, and chip transportation can be avoided, thereby reducing testing costs and improving testing efficiency.

[0105] Specifically, an embodiment of the present application provides a chip testing method for testing a chip, wherein the chip is placed on a circuit board, the chip includes a TDI pin, a TDO pin, a scanning circuit, a first TDR register and a second TDR register, the scanning circuit is respectively connected to the first TDR register and the second TDR register, the first TDR register is connected to the TDI pin, and the second TDR register is connected to the TDO pin.

[0106] See also Figure 4 , Figure 4 It is a flowchart of a chip testing method provided in an embodiment of the present application.

[0107] like Figure 4 As shown, the process of the chip testing method includes the following steps S401 to S403:

[0108] Step S401: Generate input data through a JTAG tool, wherein the TDI pin is used to input input data to a scan circuit.

[0109] Specifically, JTAG tools are a series of devices and software for testing, debugging and programming integrated circuits and circuit boards using the JTAG (Joint Test Action Group) standard.

[0110] Please refer to Figure 5 , Figure 5 It is a schematic diagram of a chip testing system provided in an embodiment of the present application.

[0111] like Figure 5 As shown, the chip testing system 300 includes: a chip 100 and a JTAG tool 200 .

[0112] The chip 100 includes a first TDR register 101 , a second TDR register 102 , a scanning circuit 103 , a TAP controller 104 and a multiplexer 105 .

[0113] Among them, the multiplexer 105, namely MUX, is used to switch the test mode of the chip. The test mode of the chip includes a mass production machine test mode and a product board retest mode. Among them, the mass production machine test mode inputs a test excitation signal to the scanning circuit through the IO pin; the product board retest mode inputs a test excitation signal to the scanning circuit through the first TDR register. Different test modes can be switched through the multiplexer.

[0114] The chip 100 further includes a JTAG port, which includes a JTAG TCK pin, a JTAG TDI pin (Test Data In, TDI), a JTAG TDO pin (Test Data Out, TDO), a JTAG TMS pin, and a TRST pin. The TCK pin is used to provide a clock, and the TMS pin is used for the state jump of the TAP controller, thereby controlling the first and second TDR registers.

[0115] The JTAG tool 200 is connected to a TDI pin, which is connected to the first TDR register 101 . The TDI pin is used to input data to the scanning circuit 103 through the first TDR register 101 .

[0116] Specifically, the JTAG tool 200 generates input data, which includes a test vector, which is a specific input signal set for testing, usually including a combination of logic high (1) and logic low (0). It can be understood that the JTAG tool can run the SVF file converted from the test vector automatically generated by the DFT circuit design tool to ensure that various possible input conditions are covered.

[0117] The JTAG tool inputs the input data into the chip through the JTAG TDI pin. Specifically, a customized program is used to convert the test vector (Scan ATE pattern) automatically generated by the DFT design tool into a standard SVF format test vector. The JTAG tool can recognize and run the SVF format test vector and transmit it through the JTAG chain, that is, the serialized test vector is input into the chip using the JTAG TDI pin.

[0118] Step S402: Capture input data of the TDI pin through the first TDR register, and input the input data to the scan circuit; and capture output data output by the scan circuit through the second TDR register, and output the output data to the TDO pin.

[0119] Specifically, the first TDR register is connected to the JTAG TDI pin, and the input data input to the JTAG TDI pin, that is, the input signal, is captured through the first TDR register to input the input signal to the scanning circuit.

[0120] After the input signal passes through the scanning circuit, the scanning circuit outputs a corresponding output signal, wherein the second TDR register 102 is connected to the scanning circuit 103, and the second TDR register 102 captures the output data output by the scanning circuit 103, that is, the output signal, and outputs the output data to the JTAG TDO pin.

[0121] Step S403: Obtain output data output by the TDO pin through the JTAG tool, and compare the output data with expected data to determine the fault status of the chip.

[0122] Specifically, the JTAG tool 200 is connected to the JTAG TDO pin to obtain the output data, i.e., the output signal, outputted by the JTAG TDO pin, and analyze whether the output data is the same as the expected data. If so, the fault state of the chip is determined to be no fault; if not, the fault state of the chip is determined to be a fault.

[0123] Specifically, the JTAG tool 200 is used to run a file in a standard SVF format, namely, an SVF file, to control the pin inputs of JTAG TCK, JTAG TDI, JTAG TMS, and JTAG TRST, and to capture the data of the JTAG TDO pin for comparison.

[0124] For example, the SVF file has the following statement:

[0125] SDR 10TDI(250)TDO(301)MASK(3FF);

[0126] Among them, SDR 10 represents a 10-bit DR register.

[0127] Among them, TDI(250) means moving in 0x250 from the TDI pin, which is binary bit 1001010000.

[0128] Among them, TDO(301) means that the expected TDO output is 0x301, that is, binary bit1100000001. The JTAG tool compares the actual sampled TDO value with the expected value.

[0129] Among them, MASK (3FF) indicates whether to compare TDO. Each bit is 1, which means that the corresponding bit needs to be compared with TDO, and 0 means no comparison.

[0130] In an embodiment of the present application, the input data of the TDI pin is captured by the first TDR register to input the input data into the scanning circuit, and the output data of the TDO pin is captured by the second TDR register, and the output data of the TDO pin is compared with the expected data through the JTAG tool to determine the fault state of the chip. The present application can avoid the operation of removing the chip from the circuit board for retesting, and realize the testing of the chip directly on the circuit board using the chip JTAG port, thereby improving the efficiency of chip fault detection.

[0131] Please refer to Figure 6 , Figure 6 It is a schematic diagram of the connection relationship between a first TDR register, a second TDR register and a chip provided in an embodiment of the present application.

[0132] like Figure 6As shown, a first TDR register is inserted into each input signal of the scan circuit, for example, the input signals edt_update, scan_en, test_clk, scan_in0, scan_in1 and other input signals of the scan chain circuit are inserted into the first TDR register, wherein the first TDR register is a control TDR register, i.e., control TDR. Among them, test_clk is the clock of the scan circuit; scan_en is the control signal of the scan circuit, 1 indicates scan shift, 0 indicates scan capture; edt_update is the control signal of the scan circuit, 1 indicates edt circuit refresh. scan_in0 refers to the input signal of the first scan chain, which is used to input test data to the first position of the first scan chain. scan_in0 can be regarded as the starting point of the data flow of the first scan chain. scan_in1 refers to the input signal of the second scan chain, which is used to input data to the first register of the second scan chain. scan_in1 can be regarded as the starting point of the data flow of the second scan chain.

[0133] And, a second TDR register is inserted into each output signal of the scanning circuit, for example, the output signals scan_out0 and scan_out1 of the scanchain circuit are inserted into the second TDR register, wherein the second TDR register is an observation TDR register, namely observe TDR.

[0134] It can be understood that each first TDR register and each second TDR register are connected in series to the JTAG chain, and a TAP controller (Tap Controller) is also connected in series to the JTAG chain, and each first TDR register and each second TDR register are controlled by the TAP controller.

[0135] Specifically, the chip further includes a TAP controller, which is connected to the first TDR register and the second TDR register and is used to control the first TDR register and the second TDR register to perform capture, shift, and update.

[0136] Please refer to Figure 7 , Figure 7 It is a schematic diagram of a TAP controller provided in an embodiment of the present application.

[0137] like Figure 7As shown, the TAP controller controls the operation of the instruction register and various data registers by issuing control signals. The controller states are divided into two columns. The states in the left column are used to control the data registers, while the states in the right column are used for the instruction registers. The TAP controller has two startup states, 7 data register control states and 7 instruction register control states.

[0138] It can be understood that when the TAP controller is in different states, the control signals for the JTAG chain are different.

[0139] In the embodiment of the present application, the TAP controller implements the signal flow of the JTAG chain through the Capture_DR state, the Shift_DR state, and the Update_DR state.

[0140] Specifically, the input data of the TDI pin is captured through the first TDR register, and the input data is input to the scanning circuit; and the output data output by the scanning circuit is captured through the second TDR register, and the output data is output to the TDO pin, including:

[0141] Control the TAP controller to enter the Capture_DR state so that the second TDR register captures the output data output by the scanning circuit;

[0142] Control the TAP controller to enter the Shift_DR state, so that the output data stored in the second TDR register is shifted out through the TDO pin, and the input data inputted by the TDI pin is shifted into the first TDR register;

[0143] The TAP controller is controlled to enter the Update_DR state, so that the input data stored in the first TDR register is input to the scan circuit to drive the operation of the scan circuit.

[0144] For example: Figure 6 As shown, when the TAP controller undergoes the Capture_DR state, output signals such as scan_out0 and scan_out1 are captured into the second TDR register.

[0145] When the TAP controller is in the Shift_DR state, input signals such as edt_update, scan_en, test_clk, scan_in0, scan_in1 are shifted into the first TDR register through the TDI pin, for example, shifted in beat by beat (1 bit is shifted in for each TCK clock) to the first TDR register. At the same time, output signals such as scan_out0 and scan_out1 stored in the second TDR register are shifted out through the TDO pin, for example, shifted out beat by beat (1 bit is shifted out for each TCK clock).

[0146] When the TAP controller is in the Update_DR state, the data Update in the first TDR register is output to the edt_update, scan_en, test_clk, scan_in0, scan_in1 and other pins, thereby driving the operation of the scan circuit.

[0147] In an embodiment of the present application, a JTAG tool is used to run an SVF file, and the SVF file includes multiple test vectors;

[0148] The method also includes:

[0149] The state of the TAP controller is switched cyclically in the order of Capture_DR state, Shift_DR state, and Update_DR state, where each cycle corresponds to a test vector;

[0150] Determine whether the chip test mode is ended;

[0151] If the SVF file is executed, it is determined that the chip test mode is ended;

[0152] If the SVF file is not executed completely, it is determined that the test mode of the chip is not ended, and the state of the TAP controller continues to be switched.

[0153] For details, please refer to Figure 8 , Figure 8 It is a schematic diagram of the overall process of a chip test provided in an embodiment of the present application.

[0154] like Figure 8 As shown, the overall process of chip testing includes the following steps S801 to S805:

[0155] start;

[0156] Step S801: configure the selection signal and the enable signal to connect the scanning circuit with the TDR.

[0157] Specifically, the chip also includes a multiplexer (MUX), which is connected to the first TDR register and the scanning circuit. The multiplexer (MUX) is a selective signal transmission element that can transmit one of multiple input signals to the output end. By selecting a control signal (such as mux_sel), it is possible to select which input signal is transmitted, thereby selecting a specific input path connected to the output.

[0158] Wherein, a selection signal is configured, and the selection signal is used to select the signal output by the first TDR register as the input signal of the scanning circuit; or, to select the IO pin as the input signal of the scanning circuit.

[0159] Specifically, the selection signal includes a mux_sel signal, which is a signal for controlling the MUX selection. By configuring the mux_sel signal, the input path of the signal can be selected to determine different signal sources. In an embodiment of the present application, the mux_sel signal is configured to select TDR as the source of the input signal.

[0160] An enable signal is configured, wherein the enable signal is used to activate the connection between the first TDR register and the scanning circuit.

[0161] Specifically, the enable signal includes an ltest_en signal, which is used to enable or disable the scan circuit. When the ltest_en signal is activated, the signal flow in the test mode is allowed, and a specific signal transmission path is activated so that data can be transmitted smoothly, for example: the connection between the first TDR register and the scan circuit is activated so that the signal can flow between the first TDR register and the scan circuit, thereby establishing a connection between the first TDR register and the scan circuit, so that the test vector can be transmitted from the TDR to the scan circuit for corresponding testing and data acquisition.

[0162] like Figure 5 As shown, the multiplexer (MUX) can open the connection between the first TDR register and the scanning circuit by configuring a selection signal, such as a mux_sel signal.

[0163] It can be understood that the ltest_en signal is an enable signal used to enable or disable the test mode. When the signal is activated, it means that the test equipment is testing, and at this time, a specific path will be opened so that the test data can be transmitted smoothly.

[0164] Step S802: Entering the Capture_DR state under the control of the TAP controller, the second TDR register captures several outputs of the scanning circuit.

[0165] Specifically, when the TAP controller is in the Capture_DR state, output signals such as scan_out0 and scan_out1 of the scan circuit are captured into the second TDR register.

[0166] Step S803: Entering the Shift_DR state under the control of the TAP controller, several outputs of the scanning circuit captured by the second TDR register are shifted out from TDO, and several inputs of the scanning circuit are shifted serially from TDI into the first TDR register.

[0167] Specifically, when the TAP controller is in the Shift_DR state, input signals such as edt_update, scan_en, test_clk, scan_in0, scan_in1 are shifted into the first TDR register through the TDI pin, and output signals such as scan_out0 and scan_out1 stored in the second TDR register are shifted out through the TDO pin.

[0168] Step S804: Entering the Update_DR state under the control of the TAP controller, the first TDR register outputs the serially shifted input in parallel to the scanning circuit, so that the scanning circuit obtains a set of input excitation signals.

[0169] Specifically, when the TAP controller experiences the Update_DR state, the data Update in the first TDR register is output to the edt_update, scan_in1, scan_in0, scan_en, test_clk and other pins, and then output to the scanning circuit in parallel, so that the scanning circuit obtains a set of input excitation signals, and the set of input excitation signals includes edt_update signal, scan_in1 signal, scan_in0 signal, scan_en signal, test_clk signal and other signals.

[0170] It can be understood that the above process is to realize serial-to-parallel conversion through the first TDR register and the JTAG TDI pin to obtain a parallel scan circuit input excitation signal; at the same time, the parallel-to-serial conversion is realized through the second TDR register and the JTAG TDO pin, so that the JTAG tool captures the output data of the scan chain.

[0171] Step S805: Determine whether the chip test mode is completed.

[0172] It can be understood that the above-mentioned TAP controller switches in the order of Capture_DR state, Shift_DR state, and Update_DR state to complete a cycle, wherein one cycle corresponds to a test vector, and each test vector includes a set of input signals and expected output signals to verify the function and performance of the device under test.

[0173] By repeating the above process, that is, the TAP controller switches in the order of Capture_DR state, Shift_DR state, and Update_DR state, a complete test plant machine test vector (scan ATE pattern) can be equivalently implemented on the product board.

[0174] It is understandable that Scan ATE pattern refers to a test vector used in automatic test equipment (ATE) for mass production testing of chips to screen out defective chips. Pattern refers to a specific test signal or data sequence that is used to stimulate the circuit and observe its response to determine whether the device is working properly. By converting the test plant machine test vector (ScanATE pattern) automatically generated by the DFT design tool into a standard SVF format test vector through a customized program and running it with the JTAG tool, the complete test plant machine test vector (scan ATE pattern) can be equivalently implemented on the product board.

[0175] Specifically, determining whether the chip test mode is terminated includes:

[0176] Determine whether the SVF file has been executed;

[0177] If the SVF file is executed, it is determined that the chip test mode is ended;

[0178] If the SVF file is not executed completely, it is determined that the test mode of the chip is not ended, and the state of the TAP controller continues to be switched.

[0179] Specifically, an SVF file is a text file format used to describe scan test processes and test vectors. It is understandable that an SVF file contains multiple instructions, test vectors, timing control, etc., where instructions include entering test mode, setting data registers, transmitting data, etc. Test vectors include actual test data, which is used to test the functions of the device under test. Timing control includes: timing settings of control signals, such as clock cycles, etc.

[0180] Among them, the SVF file includes multiple lines. In the scan test mode, one line usually represents a complete test vector. A test vector includes a set of input signals and expected output signals. The above cycle corresponds to a test vector. By executing these test vectors line by line, it is possible to systematically verify whether the behavior of the device under test meets the design expectations. The results of each line are usually compared with the expected results to determine whether the chip test has passed.

[0181] Determine whether the SVF file has been executed, including: determining whether the last line of the SVF file has been executed. If so, it is determined that the SVF file has been executed, which means that the test mode of the chip has ended; if not, it is determined that the SVF file has been executed, which means that the test mode of the chip has not ended, and it is necessary to continue switching the state of the TAP controller to execute the next round of loops until the last line of the SVF file is executed.

[0182] In the embodiment of the present application, by switching the state of the TAP controller, it is possible to perform scan chain retesting on the circuit board using only the chip JTAG port, which is beneficial to reducing the retesting cost and improving the retesting efficiency.

[0183] See also Fig. 9 , Fig. 9 It is a structural diagram of a first TDR register provided in an embodiment of the present application.

[0184] like Fig. 9 As shown, the first TDR register includes a first data flip trigger (DFF0) and a second data flip trigger (DFF1), wherein the first data flip trigger is connected to the second data flip trigger, the signal_in signal of the chip pin is input to the first TDR register, and the signal_out signal output by the first TDR register is output to the scanning circuit.

[0185] It is understandable that a data flip-flop is a flip-flop with a data input terminal, and its state is determined by the signal at the data input terminal. When the rising edge of the clock signal of the flip-flop arrives, the D flip-flop stores the signal at the data input terminal into the flip-flop, thereby realizing the storage of information.

[0186] In the embodiment of the present application, the first TDR register includes three working modes. In different working modes, the data flow mode is different, that is, each working mode corresponds to a data path one by one, for example:

[0187] The working mode of the first TDR register includes a Bypass mode, and the Bypass mode corresponds to a Bypass path.

[0188] For details, please refer to Fig. 10A , Fig. 10A It is a schematic diagram of the Bypass path of the first TDR register provided in an embodiment of the present application.

[0189] like Fig. 10A As shown, in the Bypass mode, the Bypass path is in the direction shown by the dotted line, that is, from the signal_in signal directly to the signal_out signal. For example, the mux_sel signal is configured to 0, and the multiplexer (MUX) switches the path and uses the input of the chip pin as the output, that is, the signal_in signal is directly connected to the signal_out signal, so that the first TDR register does not act on the signal_in signal, and the input of the chip pin is used as edt_update, scan_en, test_clk, scan_in0, scan_in1 and other signals.

[0190] Alternatively, the working mode of the first TDR register includes a Shift mode, and the Shift mode corresponds to a Shift path.

[0191] For details, please refer to Fig. 10B , Fig. 10B It is a schematic diagram of the Shift path of the first TDR register provided in an embodiment of the present application.

[0192] like Fig. 10B As shown, in Shift mode, the Shift path goes from SI signal to DFF0, and then from DFF0 to SO signal. For example, TDI data enters DFF0 from SI at the TCK clock edge for storage, and the original DFF0 data is output from SO to SI of the next level TDR and is stored by DFF0 of the next level control TDR.

[0193] Alternatively, the working mode of the first TDR register includes an Update mode, and the Update mode corresponds to an Update path.

[0194] For details, please refer to Fig. 10C , Fig. 10C It is a schematic diagram of the Update path of the first TDR register provided in an embodiment of the present application.

[0195] like Fig. 10C As shown in the figure, in Update mode, the Update path is from DFF0 to DFF1, and then from DFF1 to signal_out signal output to the scan circuit. In Update mode, the data of DFF0 is saved to DFF1 at the TCK clock edge, the mux_sel signal is configured to 1, and MUX connects DFF1 to signal_out.

[0196] In the embodiment of the present application, in a normal test plant ATE machine test scenario, the first TDR register works in the Bypass mode, and the chip pin provides an excitation signal to the scan circuit. In the product board DFT scan retest scenario, the first TDR register works in the shift mode and the update mode, wherein the shift mode realizes the data shifting in from TDI, and the update mode realizes DFF1 providing an excitation signal to the scan circuit.

[0197] In an embodiment of the present application, the chip includes multiple first TDR registers, each of which corresponds to an input signal of the scanning circuit, and the multiple first TDR registers are connected in series, wherein each first TDR register includes a first data flip trigger and a second data flip trigger.

[0198] After the TAP controller enters the Shift_DR state, the first data flip-flop of each first TDR register obtains and stores one bit of data from the TDI pin at each TCK clock edge;

[0199] After the TAP controller enters the Update_DR state, the second data flip-flops of all the first TDR registers obtain corresponding bit data from the corresponding first data flip-flops to obtain multiple bit data, wherein the multiple bit data are input into the scanning circuit in parallel.

[0200] Please refer to Fig.11 , Fig.11 It is a schematic diagram of the connection relationship of multiple first TDR registers provided in an embodiment of the present application.

[0201] like Fig.11 As shown, the first TDR register includes control_TDR0, control_TDR1, control_TDR2, control_TDR3 and control_TDR4, wherein control_TDR0 is connected to control_TDR1, control_TDR1 is connected to control_TDR2, control_TDR2 is connected to control_TDR3, and control_TDR3 is connected to control_TDR4.

[0202] In the Bypass mode, the chip pin provides an excitation signal to the scan circuit, that is, the signal of the chip pin is directly input to the scan circuit.

[0203] When the TAP controller is in the Shift_DR state, each TCK clock will shift in a bit of data from TDI and temporarily store it in the first data flip-flop DFF0, that is, TDI is shifted to the DFF0 register of control_TDR0, and the DFF0 register value of control_TDR0 is shifted into the DFF0 register of control_TDR1, and so on.

[0204] When the TAP controller is in the Update_DR state, data in a group of first data flip-flops DFF0 are shifted in parallel to the second data flip-flops DFF1 of the multiple first TDR registers, and are output in parallel to the scanning circuit by the second data flip-flops DFF1 of the multiple first TDR registers.

[0205] It can be understood that in the Shift mode or Update mode, the MUX performs path switching and uses the DFF1 of the control_TDR as the edt_update, scan_en, test_clk, scan_in0, scan_in1 and other signals.

[0206] Please refer to Fig.12 , Fig.12 It is a structural diagram of a second TDR register provided in an embodiment of the present application.

[0207] like Fig.12 As shown, the second TDR register includes a data trigger register (DFF), ie, a third data flip-flop.

[0208] In the embodiment of the present application, the second TDR register includes three working modes. In different working modes, the data flow mode is different, that is, each working mode corresponds to a data path one by one, for example:

[0209] The working mode of the second TDR register includes a Bypass mode, and the Bypass mode corresponds to a Bypass path.

[0210] For details, please refer to Fig.13A , Fig.13A is a schematic diagram of a bypass path of a second TDR register provided in an embodiment of the present application;

[0211] like Fig.13A As shown, in the Bypass mode, the Bypass path is in the direction shown by the dotted line, that is, directly from the signal_in signal to the signal_out signal, that is, the output of the scan circuit is output through the chip pin.

[0212] Alternatively, the operating mode of the second TDR register includes a Capture mode, and the Capture mode corresponds to a Capture path.

[0213] For details, please refer to Fig. 13B , Fig. 13B It is a schematic diagram of the Capture path of the second TDR register provided in an embodiment of the present application.

[0214] like Fig. 13B As shown in Figure 1, in Capture mode, the Capture path is from the signal_in signal to the DFF. For example, in Capture mode, the mux_sel signal is configured to 0, and the output signal from the scan circuit is captured into the DFF at the TCK clock edge.

[0215] Alternatively, the operating mode of the second TDR register includes a Shift mode, and the Shift mode corresponds to a Shift path.

[0216] For details, please refer to Fig. 13C , Fig. 13C It is a schematic diagram of the Shift path of the second TDR register provided in an embodiment of the present application.

[0217] like Fig. 13C As shown in the figure, in Shift mode, the Shift path goes from SI signal to DFF, and then from DFF to SO signal. For example, in Shift mode, the mux_sel signal is configured as 1, and the data captured in DFF is sent from SO to TDO output at the TCK clock edge. At the same time, the data captured by DFF of the previous observe_TDR is input from SI to DFF, and the data is stored by DFF.

[0218] In the embodiment of the present application, the chip includes a plurality of second TDR registers, each of which corresponds to an output signal of the scanning circuit, and the plurality of second TDR registers are connected in series, wherein each second TDR register includes a third data flip-flop;

[0219] After the TAP controller enters the Capture_DR state, the third data flip-flop of each second TDR register acquires and stores a bit of data from the scanning circuit;

[0220] After the TAP controller enters the Shift_DR state, the bit data stored in the third data flip-flop of each second TDR register is serially output to the TDO pin.

[0221] See also Fig.14 , Fig.14 It is a schematic diagram of the connection relationship between two second TDR registers provided in an embodiment of the present application.

[0222] like Fig.14 As shown, the second TDR register includes two registers, namely observe_TDR0 and observe_TDR1.

[0223] When the TAP controller is in the Capture_DR state, the output of the scan circuit is captured into the corresponding DFF register.

[0224] When the TAP controller is in the Shift_DR state, each TCK clock edge shifts 1 bit of data out of TDO, that is, the DFF register value of observe_TDR1 is shifted to the TDO output, the DFF register value of observe_TDR0 is shifted to the DFF register of observe_TDR1, and so on.

[0225] In an embodiment of the present application, the method further includes:

[0226] Through multiple second TDR registers, all register values ​​in the chip that are connected to the scan chain are captured from TDO, thereby obtaining the internal state of the chip for chip debugging.

[0227] In an embodiment of the present application, the input data of the TDI pin is captured by the first TDR register to input the input data into the scan circuit, and the output data of the scan circuit is captured by the second TDR register to be output from TDO, and the output data of the TDO pin is compared with the expected data through the JTAG tool to determine the fault state of the chip. The present application can avoid the operation of removing the chip from the circuit board for retesting, and realize the testing of the chip directly on the circuit board using the chip JTAG port, thereby improving the efficiency of chip fault detection.

[0228] The present application also provides a chip, which includes:

[0229] TDI pin; TDO pin; scanning circuit;

[0230] TAP controller, the TAP controller is connected to the scanning circuit;

[0231] A first TDR register is connected to the TDI pin and the scanning circuit, and is used to capture input data of the TDI pin and input the input data to the scanning circuit;

[0232] The second TDR register is connected to the TDO pin and the scanning circuit, and is used for capturing output data output by the scanning circuit, and outputting the output data to the TDO pin.

[0233] In the embodiments of the present application,

[0234] The chip includes a plurality of first TDR registers, each of which corresponds to an input signal of the scanning circuit, and the plurality of first TDR registers are connected in series, wherein each of the first TDR registers includes a first data flip-flop and a second data flip-flop;

[0235] After the TAP controller enters the Shift_DR state, the first data flip-flop of each first TDR register obtains and stores one bit of data from the TDI pin at each TCK clock edge;

[0236] After the TAP controller enters the Update_DR state, the second data flip-flops of all the first TDR registers obtain corresponding bit data from the corresponding first data flip-flops to obtain multiple bit data, wherein the multiple bit data are input into the scanning circuit in parallel.

[0237] In the embodiments of the present application,

[0238] The chip includes a plurality of second TDR registers, each of which corresponds to an output signal of the scanning circuit, and the plurality of second TDR registers are connected in series, wherein each of the second TDR registers includes a third data flip-flop;

[0239] After the TAP controller enters the Capture_DR state, the third data flip-flop of each second TDR register acquires and stores a bit of data from the scanning circuit;

[0240] After the TAP controller enters the Shift_DR state, the bit data stored in the third data flip-flop of each second TDR register is serially output to the TDO pin.

[0241] It should be noted that the specific content of the chip can be referred to the above-mentioned content and will not be repeated here.

[0242] Please refer to Fig.15 , Fig.15 It is a structural schematic diagram of a chip testing system provided in an embodiment of the present application.

[0243] like Fig.15 As shown, the chip testing system 300 includes a chip 100 and a JTAG tool 200 .

[0244] It should be noted that the specific contents of the chip and the JTAG tool can be referred to the above-mentioned contents and will not be repeated here.

[0245] Please refer to Fig.16 , Fig.16 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0246] like Fig.16 As shown, the electronic device 160 includes one or more processors 161 and a memory 162. Fig.16 A processor 161 is taken as an example.

[0247] The processor 161 and the memory 162 may be connected via a bus or other means. Fig.16 The example of connecting through bus is taken in the following.

[0248] The processor 161 is used to provide computing and control capabilities to control the electronic device 160 to perform corresponding tasks, for example, to control the electronic device 160 to perform the chip testing method in any one of the above method embodiments, the chip testing method is applied to a chip, the chip is placed on a circuit board, the chip includes a TDI pin, a TDO pin, a scanning circuit, a first TDR register and a second TDR register, the scanning circuit is respectively connected to the first TDR register and the second TDR register, the first TDR register is connected to the TDI pin, and the second TDR register is connected to the TDO pin, the method includes: inputting input data to the scanning circuit through the TDI pin; capturing the input data of the TDI pin through the first TDR register, and inputting the input data to the scanning circuit; and, capturing the output data output by the scanning circuit through the second TDR register, and outputting the output data to the TDO pin; obtaining the output data output by the TDO pin through the JTAG tool, and comparing the output data with the expected data to determine the fault state of the chip.

[0249] The input data of the TDI pin is captured by the first TDR register to input the input data into the scanning circuit, and the output data of the scanning circuit is captured by the second TDR register to be output from the TDO pin, and the output data of the TDO pin is compared with the expected data through the JTAG tool to determine the fault state of the chip. The present application can avoid the operation of removing the chip from the circuit board for retesting, and realize chip testing directly on the circuit board using the chip JTAG port, thereby improving the efficiency of chip fault detection.

[0250] The processor 161 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0251] The memory 162, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the chip testing method in the embodiment of the present application. The processor 161 can implement the chip testing method in any of the above method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 162. Specifically, the memory 162 may include a volatile memory (VM), such as a random access memory (RAM); the memory 162 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD) or other non-transitory solid-state storage device; the memory 162 may also include a combination of the above types of memories.

[0252] The memory 162 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 162 may optionally include a memory remotely arranged relative to the processor 161, and these remote memories may be connected to the processor 161 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0253] One or more modules are stored in the memory 162, and when executed by one or more processors 161, the chip testing method in any of the above method embodiments is executed, for example, the chip testing method described above is executed. Figure 4 The steps shown.

[0254] In the embodiment of the present application, the electronic device 160 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The electronic device 160 may also include other components for realizing device functions, which will not be described in detail here.

[0255] The embodiment of the present application also provides a non-volatile computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the chip testing method in the above embodiment. For example, the non-volatile computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0256] The embodiment of the present application also provides a non-volatile computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the chip testing method in the above embodiment. For example, the non-volatile computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0257] The embodiment of the present application also provides a computer program product, which includes one or more program codes, and the program codes are stored in a non-volatile computer-readable storage medium. The processor of the electronic device reads the program code from the non-volatile computer-readable storage medium, and the processor executes the program code to complete the method steps of the chip testing method provided in the above embodiment.

[0258] A person skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be accomplished by hardware or by hardware associated with a program code, and the program may be stored in a non-volatile computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0259] Through the description of the above implementation methods, a person of ordinary skill in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, can also be implemented by hardware. A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0260] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as mentioned above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip testing method, characterized in that: The chip is placed on a circuit board, the chip includes a TDI pin, a TDO pin, a scanning circuit, a first TDR register and a second TDR register, the scanning circuit is connected to the first TDR register and the second TDR register respectively, the first TDR register is connected to the TDI pin, and the second TDR register is connected to the TDO pin, and the method includes: Generate input data through a JTAG tool, wherein the TDI pin is used to input the input data to the scanning circuit; Capturing input data of the TDI pin through the first TDR register, and inputting the input data to the scanning circuit; and capturing output data output by the scanning circuit through the second TDR register, and outputting the output data to the TDO pin; The output data output by the TDO pin is obtained through a JTAG tool, and the output data is compared with expected data to determine the fault status of the chip.

2. The method according to claim 1, characterized in that The chip further includes a TAP controller, wherein the TAP controller is connected to the first TDR register and the second TDR register; The first TDR register is used to capture the input data of the TDI pin, and the input data is input to the scanning circuit; And, capturing output data output by the scanning circuit through the second TDR register, and outputting the output data to the TDO pin, comprising: Controlling the TAP controller to enter the Capture_DR state so that the second TDR register captures the output data output by the scanning circuit; Controlling the TAP controller to enter the Shift_DR state so that the output data stored in the second TDR register is shifted out through the TDO pin, and the input data input by the TDI pin is shifted into the first TDR register; The TAP controller is controlled to enter the Update_DR state, so that the input data stored in the first TDR register is input to the scanning circuit to drive the operation of the scanning circuit.

3. The method according to claim 2, characterized in that The JTAG tool is used to run an SVF file, wherein the SVF file includes a plurality of test vectors; The method further comprises: Cyclic switching of the state of the TAP controller in the order of the Capture_DR state, the Shift_DR state, and the Update_DR state, wherein each cycle corresponds to a test vector; Determining whether the test mode of the chip is terminated; If the SVF file is executed, it is determined that the test mode of the chip is terminated; If the SVF file is not executed completely, it is determined that the test mode of the chip is not ended, and the state of the TAP controller continues to be switched.

4. The method according to claim 2, characterized in that: The chip includes a plurality of the first TDR registers, each of the first TDR registers corresponds to an input signal of the scanning circuit, and the plurality of the first TDR registers are connected in series, wherein each of the first TDR registers includes a first data flip-flop and a second data flip-flop; After the TAP controller enters the Shift_DR state, the first data flip-flop of each of the first TDR registers acquires and stores one bit of data from the TDI pin at each TCK clock edge; After the TAP controller enters the Update_DR state, the second data flip-flops of all first TDR registers obtain corresponding bit data from the corresponding first data flip-flops to obtain multiple bit data, wherein the multiple bit data are input into the scanning circuit in parallel.

5. The method according to claim 1, characterized in that The chip includes a plurality of the second TDR registers, each of which corresponds to an output signal of the scanning circuit, and the plurality of the second TDR registers are connected in series, wherein each of the second TDR registers includes a third data flip-flop; After the TAP controller enters the Capture_DR state, the third data flip-flop of each of the second TDR registers acquires and stores a bit of data from the scanning circuit; After the TAP controller enters the Shift_DR state, the bit data stored in the third data flip-flop of each of the second TDR registers is serially output to the TDO pin at the TCK clock edge.

6. A chip, characterized in that: include: TDI pin; TDO pin; Scanning circuit; A TAP controller, the TAP controller connected to the first TDR register and the second TDR register; The first TDR register is connected to the TDI pin and the scanning circuit, and is used to capture input data of the TDI pin and input the input data to the scanning circuit; The second TDR register is connected to the TDO pin and the scanning circuit, and is used for capturing output data output by the scanning circuit, and outputting the output data to the TDO pin.

7. The chip according to claim 6, characterized in that: The chip includes a plurality of the first TDR registers, each of the first TDR registers corresponds to an input signal of the scanning circuit, and the plurality of the first TDR registers are connected in series, wherein each of the first TDR registers includes a first data flip-flop and a second data flip-flop; After the TAP controller enters the Shift_DR state, the first data flip-flop of each of the first TDR registers acquires and stores one bit of data from the TDI pin at each TCK clock edge; After the TAP controller enters the Update_DR state, the second data flip-flops of all the first TDR registers obtain corresponding bit data from the corresponding first data flip-flops to obtain multiple bit data, wherein the multiple bit data are input into the scanning circuit in parallel.

8. A chip testing system, characterized in that: include: The chip according to claim 6 or 7; The JTAG tool is used to test the chip.

9. An electronic device, characterized in that: include: A processor and a memory, wherein the processor is used to execute an executable program code in the memory, and when the executable program code is executed, the processor executes instructions of the chip testing method according to any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the chip testing method according to any one of claims 1 to 5 is implemented.

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