Curved mask layer design based on level set function

Abstract

The invention relates to a curved mask layer design based on a level set function. In some aspects, a lithographic mask is designed, the lithographic mask having a plurality of features, including curved major features. A mask layer is first accessed, the mask layer representing a vector representation of the lithographic mask. A correction field between the simulation field and the target field is then calculated. The simulated field is a field representation of a simulated result of a lithographic process using the lithographic mask, and the target field is a field representation of a target result of the lithographic process. The major feature of a mask field is modified based on the correction field, wherein the mask field is a field representation of the major feature of the lithographic mask. Finally, the major features of the mask layer are updated based on the modification to the mask field. This process may be repeated for multiple iterations, and after the last iteration, a final version of the mask layer is output.

Description

Technical Field

[0001] The present disclosure relates to lithography simulation, including curved mask layer design based on level set functions. Background Art

[0002] One step in semiconductor wafer manufacturing involves photolithography. In a typical photolithography process, a source generates light that is collected and directed by collection / illumination optics to illuminate a photolithography mask. Projection optics relay the pattern generated by the illuminated mask onto the wafer, exposing the resist on the wafer according to the illumination pattern. The patterned resist is then used in a process to make device structures on the wafer.

[0003] As integrated circuit designs become larger, denser, and more complex, there is an increasing need for computational lithography solutions for developing masks used in fabrication. Mask features are becoming smaller and less straight. For example, advanced mask writing tools can produce curved shapes. However, traditionally, lithographic shapes are represented as polygons, and tools for computational lithography are designed to use polygons. Representing curved shapes as polygons makes their simulation and correction more difficult and computationally intensive. On the other hand, many computational lithography tools are not very well suited to directly handle curved shapes. Summary of the invention

[0004] In some aspects, a lithography mask is designed based on a level set function, the lithography mask having a plurality of features, including curved primary features (e.g., curved primary features). A mask layer is first accessed, the mask layer representing a vector representation of the lithography mask. A correction field between a simulation field and a target field is then calculated. The simulation field is a field representation (e.g., a level set) of a simulated result of a lithography process using the lithography mask, and the target field is a field representation (e.g., a level set) of a target result of the lithography process. The primary features of the mask field are modified based on the correction field. The mask field is a field representation (e.g., a level set) of the primary features of the lithography mask. Finally, the primary features of the mask layer are updated based on the modifications to the mask field. This process may be repeated for multiple iterations, and after the last iteration, a final version of the mask layer (i.e., a final synthesized lithography mask) is output.

[0005] Other aspects include components, devices, systems, improvements, methods, processes, applications, computer-readable media, and other techniques related to any of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the drawings of embodiments of the present disclosure. The drawings are used to provide knowledge and understanding of the embodiments of the present disclosure, and do not limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0007] Figure 1 A flow chart illustrating the operation of a mask layer design process according to some embodiments of the present disclosure.

[0008] Figure 2 yes Figure 1 Block diagram of the layers and fields used in the mask layer design process.

[0009] Figure 3 is a flow chart of a computational lithography process according to some embodiments of the present disclosure.

[0010] Figure 4A Illustrated are multiple layers defined for a mask layer design process according to some embodiments of the present disclosure.

[0011] Figure 4B The diagram illustrates the principle of mask edge movement according to some embodiments of the present disclosure.

[0012] Figure 5 is a detailed flow chart of an iterative mask layer design process according to some embodiments of the present disclosure.

[0013] Fig. 6A The diagram shows Figure 5 A field representation (e.g., level set) of a target layer during the mask layer design process.

[0014] Figure 6B The diagram shows Figure 5 Field representation of the main features of the mask layer during the mask layer design process.

[0015] Figure 6C The diagram shows Figure 5 Field representation of the simulation layer during the mask layer design process.

[0016] Fig.6D The diagram shows Figure 5 Field representation of the correction layer during the mask layer design process.

[0017] Fig. 6E Graphical instructions Figure 5 Field representation of the main features of the corrected mask layer at the end of the mask layer design process.

[0018] Fig. 7A Illustrate the convergence trajectory of an iterative mask layer design process without applying an inertial field according to some embodiments of the present disclosure.

[0019] Figure 7B Illustrate the convergence trajectory of the iterative mask layer design process when an inertial field is applied according to some embodiments of the present disclosure.

[0020] Figure 8 Illustrated are example target layers, inner pseudo contours, and outer pseudo contours according to some embodiments of the present disclosure.

[0021] Fig. 9A Illustrates a synthesized simulated layer when the simulated layer is not initially generated according to some embodiments of the present disclosure.

[0022] Fig. 9B Illustrate a synthesized simulated layer when an initial simulated layer is covered by an inner pseudo contour according to some embodiments of the present disclosure.

[0023] Fig. 9C Illustrated is a synthesized simulated layer as an initial simulated layer intersects an inner pseudo contour and an outer pseudo contour according to some embodiments of the present disclosure.

[0024] Fig.9D Illustrated is a synthesized simulated layer when an initial simulated layer intersects an inner pseudo contour according to some embodiments of the present disclosure.

[0025] Fig.9E Illustrate a synthesized simulated layer when an initial simulated layer covers an outer pseudo contour according to some embodiments of the present disclosure.

[0026] Fig. 10A An example first clip of a contact layer is illustrated, wherein a designed mask layer exhibits overlap with a circular target layer, according to some embodiments of the present disclosure.

[0027] Fig. 10B An example second segment of a contact layer is illustrated, wherein a designed mask layer exhibits overlap with a circular target layer, according to some embodiments of the present disclosure.

[0028] Fig.11A It is for Fig. 10A Example graph of the area difference between the circular target layer and the simulated layer of the contact layer.

[0029] Fig. 11B It is for Fig. 10B Example graph of the area difference between the circular target layer and the simulated layer of the contact layer.

[0030] Fig. 12A is a table of running times and different edge placement errors (EPE) for the iterative mask layer design process presented in this paper. Fig. 10A The conventional mask layer design process for the contact layer is benchmarked.

[0031] Fig. 12B is a table of the running time and different EPEs for the iterative mask layer design process presented in this paper. Fig. 10B The conventional mask layer design process for the contact layer is benchmarked.

[0032] Fig.13 Flowcharts depicting various processes used during the design and manufacture of integrated circuits according to some embodiments of the present disclosure.

[0033] Fig.14 A diagram depicting an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0034] Aspects of the present disclosure relate to a curved mask layer design based on a level set function. A lithographic mask is used in a lithographic process to print features on a wafer. A lithographic mask contains many features, which can be classified as primary features and auxiliary features. A primary feature is a feature that is primarily responsible for producing a corresponding printed feature on a wafer. However, the primary features alone may not be sufficient to produce a printed feature of sufficient quality. Auxiliary features are auxiliary features that improve the quality of the printed feature.

[0035] As technology advances, these features become smaller and less rectangular. Mask features may be curved. In the design phase, curved mask features can be used as input to a simulation of a lithography process. The simulation predicts the outcome of the lithography process. This outcome is compared to the desired (target) outcome. The mask design is modified until the simulated outcome matches the target outcome.

[0036] To do this effectively, the computational tools used to analyze and correct these features during the design phase must be able to handle curved features. However, traditionally, mask layers and other lithography layouts are represented by polygons, and more specifically rectilinear polygons. The use of sub-resolution auxiliary features and curved main shapes makes the traditional representation based on rectilinear polygons less than ideal. Approximating curved shapes by rectilinear polygons requires a large number of vertices and curved edges can still be represented by step approximations. Even if non-rectilinear polygons are allowed, curved edges will still require polygons with a large number of sides to approximate the curve. Using these polygonal approximations to simulate and correct curved mask layers can be time consuming.

[0037] In the approach described herein, curved masks are represented by curves (rather than polygonal approximations), and design iterations of these curved masks are handled by using level set functions. Curved mask features have an edge, part or all of which is curved. These mask features can be represented by defining the location of the edge. For example, a straight edge can be represented by its vertices, and a curved edge can be represented by a parameterization of a curve. This is a vector representation of a feature, and this type of representation will be referred to as a layer. For example, a mask layer is a vector representation of a lithography mask.

[0038] However, the process of designing a mask can be challenging if it is based only on a vector representation of the mask, simulated lithography results, and target lithography results. In the approach described herein, a field representation (e.g., a level set) is used. A field representation is an (x, y) array of values ​​(fields) representing the quantity of interest. For mask features, the value at each point in the field can be the distance from the point to the edge of the mask, and the sign of the value indicates whether the point is located inside the feature. In one approach, instead of comparing the simulated results with the vector representation of the target results, the field representations of the two are compared to generate a correction field. This is returned as a field representation of the mask (mask field), and the mask field is then converted into a corresponding modification of the mask layer.

[0039] Technical advantages of the present disclosure may include, but are not limited to, the following. The approach described herein can process curved masks more quickly than conventional approaches. Due to the simple mechanism, the computational cost of this approach is lower than the computational cost of more conventional approaches. This method can also produce more consistent shapes of mask layers across different templates, thereby reducing inter-template and intra-template inconsistencies. In addition, since the mask edge movement is only affected by the difference between the level sets of the simulated results and the target results, patterns under the same geometric environment pass through the same optimization trajectory.

[0040] The approach described herein may also be more accurate than conventional approaches. When the mask edge moves in response to the difference between the simulated level set and the target level set, this results in a corresponding mask edge movement, i.e., the majority pattern as well as the minority pattern (e.g., line ends) converge to the design target in a uniform and stable manner. This approach also provides a reduction in the maximum edge placement error (EPE) at the convergence point. Furthermore, it is robust to situations where simulation results are not generated for the initial mask layer and when the lithography model causes strong crosstalk between mask edges.

[0041] In more detail, Figure 1 A flow chart illustrating the operation of a mask layer design process according to some embodiments of the present disclosure. Figure 2 yes Figure 1 Block diagram of the layers and fields used in the mask layer design process. Figure 2 The left side of the diagram shows the layers used in the mask layer design process, and Figure 2 , a field representation used in the mask layer design process is shown on the right side of . At 105, a mask layer 205 is accessed. The mask layer 205 includes a vector representation of a lithography mask. The lithography mask may include many features, including one or more curved main features. The mask layer 205 may include a parameterized curve representing the curved main features of the mask layer 205. The curved main features of the mask layer 205 may be curved. The features of the lithography mask may include auxiliary features that are not modified during the mask layer design process, that is, the auxiliary features of the mask layer 205 are fixed. The mask layer 205 may be provided as an input to a lithography model 210. The lithography model 210 may include a forward function (e.g., for predicting a wafer image) that generates a simulation layer 215 using the mask layer 205. The mask layer 205 may be converted into a mask field 235 by calculating, for example, the level sets of the main features of the mask layer 205. The simulated layer 215 obtained by the lithography model 210 may be converted into a field representation of the simulated layer 215 , ie, into a simulated field 220 , by calculating, for example, a level set function of the simulated layer 215 .

[0042] At 110, a correction field 230 between a simulation field 220 and a target field 225 is calculated. The simulation field 220 includes a field representation of a simulated result of a lithography process using a lithography mask. The target field 225 includes a field representation of a target result of the lithography process. The field representation utilized herein may be a level set representation of a corresponding layer. At 105, for example, a target layer representing a vector representation of the target result may be further received. At 110, for example, a target field 225 may be determined based on the target layer. The target layer may include curved primary features. The result of the lithography process may be one of the following: an aerial image, a latent image of a resist, a resist structure, and a device structure. The simulation of the lithography process may produce a field representation, rather than a vector representation.

[0043] At 115, the primary features of the mask field 235 are modified based on the correction field 230. The mask field 235 includes a field representation of the primary features of the lithography mask. The mask field 235, the simulation field 220, and the target field 225 may include field representations of the primary features instead of the auxiliary features. At 120, the processing device performing the mask layer design process modifies the primary features of the mask layer 205 based on the modification of the mask field 205. At 120, the modified primary features of the mask field 235 may be converted into the primary features of the mask layer 205 by applying a profile generating function with a defined threshold (e.g., equal to zero) to the modified primary features of the mask field 235.

[0044] repeat Figure 1The operations 110 to 120 are repeated for multiple iterations. The final version of the mask layer 205 is the output from the multiple iterations of the operations 110 to 120. The modification of the mask layer 205 achieved by performing the operations 105 to 120 may be incorporated as part of an inverse photolithography technology (ILT) process.

[0045] At 110, an initial correction field may be calculated by scaling the difference between the simulation field 220 and the target field 225. At 110, an inertial field may be further calculated by scaling a version of the correction field 230 calculated in the previous iteration of the operation 110. At 110, the correction field 230 may be determined by adding the inertial field to the initial correction field. In one or more embodiments, a simulation layer 215 is calculated by performing Boolean operations on the mask layer 205, the inner pseudo contour, and the outer pseudo contour, and the simulation layer is a vector representation of the simulated result. The inner pseudo contour may be generated by shrinking the target layer to an inner band. The outer pseudo contour may be generated by expanding the target layer to an outer band.

[0046] Figure 3 is a flow chart of a computational lithography process according to an embodiment of the present disclosure. In this example, the computational lithography process is used to design a lithography mask. Figure 3 The left side of FIG. 3 shows a lithography system 320, and Figure 3 The right side of FIG. 3 shows a computational lithography flow 330 for simulating the system. In the lithography system 320, a light source (not shown) generates a light distribution (illumination field 322) that is incident on a lithography mask 324 having a specific mask topology. Light from the illumination field 322 propagates through or is reflected by the lithography mask 324, thereby generating a light distribution referred to as a near field. The near field is imaged onto a resist 328 on a substrate 329 (e.g., a semiconductor wafer) by projection optics 326. The light distribution that illuminates the resist 328 is referred to as an aerial image. The aerial image exposes a resist process (e.g., including exposure, post-exposure baking (PEB) and development), which generates a three-dimensional shape (profile) in the resist 328. Terms such as light and optical are intended to include all relevant wavelengths, including ultraviolet light, deep ultraviolet light, and extreme ultraviolet light, and are not limited to only visible wavelengths.

[0047] Figure 3The right side of shows a computational lithography flow 330 of a simulated lithography system 320, including modifying the design of a lithography mask, according to an embodiment of the present disclosure. The dashed box 330 contains a simulation or modeling of the overall lithography configuration. For convenience, the individual boxes are shown as corresponding to physical components or processes, but the simulation does not have to be implemented in this manner. For example, the source model 340 represents a model of the source, and the illumination optics model 350 models the effect of the illumination optics. These models generate source illumination 355, which is an estimate of the source illumination 322 incident on the mask. However, an actual simulation may or may not use separate models 340, 350 for the source and optics. In some cases, the two may be combined into a single model or simulation that predicts the source illumination 355.

[0048] Mask model 360 models the effect of lithography mask 324 on incident illumination 322. Here, lithography mask 324 is represented by mask layer 362. Projection optics model 370 represents the effect of optics 326. Source illumination 355 is filtered by mask model 360. The resulting field is referred to as near field 365. The near field is applied to model 370 of projection optics to estimate an aerial image 375, which exposes resist 328 on wafer 329. Resist 328 is modeled by resist exposure model 380 and resist development model 382, ​​resulting in an estimate of patterned resist 388. Additional modeling may be used to predict etching, doping, deposition, or other semiconductor fabrication processes. One or more portions of mask model 360, projection optics model 370, resist exposure model 380, and / or resist development model 382 may form a Figure 2 The lithographic model 210 in FIG. The near field 365 , the aerial image 375 , and / or the patterned resist 388 may be embodiments of the simulation layer 215 .

[0049] Various results of the lithography simulation 330 may be used to modify 395 the mask layer 362. For example, the predicted near field 365 may be analyzed and then used to modify 395 the mask layer 362. The aerial image 375 and the patterned resist 388 may also be used for this purpose. In some embodiments, the mask layer 362 is modified 395 using the simulated field 220 obtained from the simulation layer 215, the target field 225, and the correction field 230.

[0050] Metrics derived from these quantities may also be used. One example is the difference between the predicted aerial image 375 and the desired aerial image. The difference between other predicted signals (e.g., near field 365) and the desired signal may also be used. The difference between the predicted position of the edges of patterned resist 388 (resist profile) and the desired position of those edges is another example. This may be referred to as edge placement error.

[0051] As another example, one measure of the quality of the patterned resist 388 is the critical dimension (CD). The CD is the size of a particular feature in the patterned resist 388. Typically, the CD is the smallest line width or space width printed in the resist 388. Thus, the CD is a measure of the resolution of the resist 388 and the lithography process. The model in the lithography simulation 330 can be used to predict the CD for a given lithography configuration. The predicted CD can be used to modify 395 the mask layer 362.

[0052] Another measure of the quality of the patterned resist 388 is defects. Examples of defects include when two printed lines that were thought to be separate merge, when a printed line that was thought to be continuous has a break, and when a printed feature that was thought to have a hole in the center is actually filled. Predicted defects and defect rates can also be used to modify 395 the mask layer 362. Other metrics can be based on the difference between the desired result and the predicted result.

[0053] In computational lithography process 330, various layouts may be represented by parametric curves rather than rectilinear polygons. For example, mask layer 362 itself includes many shapes, some or many of which may be represented by parametric curves. Source illumination 355, near field 365, and aerial image 375 may also be represented by parametric curves. These quantities are two-dimensional intensity distributions. Parametric curves may be used to represent profiles of constant intensity. Patterned resist 388 may also be represented by a parametric curve. Resist 388 itself is a three-dimensional shape. Resist 388 may be represented by profiles at different heights of resist 388. Both the simulated quantities and the desired target results shown in computational lithography process 330 may be represented by parametric curves.

[0054] Figure 4A The diagram illustrates the multiple layers defined for the mask layer design process presented in this article. Figure 4A 4. As shown in FIG. 4, three different layers may be defined—a mask layer 402 (i.e., an initial mask layer), a target layer 404 (e.g., a circular target result), and a simulation layer 406. In order to achieve a smooth shape for the curved mask, the target layer 404 may be defined to be a circular shape. The target layer 404 is fixed across the iterative mask layer design process, while the mask layer 402 and the simulation layer 406 are updated in each iteration. Arrow 408 illustrates the shortest distance from a given position of the simulation layer 406 to the target layer 404, i.e., the difference between the simulation field (e.g., the level set of the simulation layer 406) and the target field (e.g., the level set of the target layer 404). Arrow 410 illustrates the momentum of the mask edge movement, i.e., the momentum of the correction applied to the mask layer 402.

[0055] Figure 4BThe diagram illustrates the principle of mask edge movement during the mask layer design process presented herein. Mask edge movement represents the movement of mask layer 402 to updated mask layer 402' when simulation layer 406 moves to simulation layer 406' (i.e., simulation layer 406 moves closer to target layer 404). The mask edge movement at a particular location of mask layer 402 can be proportional to the shortest distance from simulation layer 406 to target layer 404. The shortest distance can be calculated by subtracting the simulation field from the target field (e.g., by subtracting the level set of simulation layer 406 from the level set of target layer 404).

[0056] Figure 5 Flowchart of an iterative mask layer design process performed during synthesis of a curved mask (e.g., a curved mask or some other type of curved mask). An initial mask layer ('layer_mask'), a circular target layer ('layer_target'), a damping factor ('damp_f'), and an inertia weight ('inert_wt') are predetermined and represent inputs to the iterative mask layer design process. At 505, the target layer is converted to a field representation (e.g., a level set) of a target layer ('lset_target'), i.e., L(target_layer)→lset_target, where L() is a function that converts a layer into a level set (e.g., a signed distance function). Fig. 6A , for level set values ​​between, for example, -50 and +50, the target field (e.g., the level set of the target layer) is shown in . At 510, the initial mask layer is converted into a field representation (e.g., the level set) of the mask layer. In one or more embodiments, only the main features of the initial mask layer ('layer_mask_MF') are converted into the level set of the main features of the mask layer ('lset_mask_MF'), i.e., L(layer_mask_MF)→lset_mask_MF. Figure 6B The mask field (ie, a level set of a mask layer with main and assist features) for level set values ​​between, for example, -50 and +50 is shown in FIG.

[0057] At 515, a simulation layer ('layer_simulation') is calculated using the current mask layer (i.e., F(layer_mask)→layer_simulation), where F() is a forward function of a lithography model used, for example, to predict wafer images. At 520, the simulation layer is converted into a field representation (e.g., level set) of the simulation layer ('lset_simulation'), i.e., L(layer_simulation)→lset_simulation. Figure 6C Example level set for a simulation layer for level set values ​​between, for example, -50 and +50 is shown in FIG.

[0058] At 525, an initial correction field is calculated. The correction field represents the difference between the field representation of the simulation layer (e.g., level set) and the field representation of the target layer (e.g., level set). The initial correction field ('lset_correction_0') is calculated as the difference between the field representation of the simulation layer (e.g., level set) and the field representation of the target layer (e.g., level set), and the calculated difference is scaled by using a damping factor (e.g., less than 1), i.e., lset_correction_0←damp_f*(lset_simulation−lset_target). At 530, a final correction field ('lset_correction') is calculated by adding the inertia field representation to the initial correction field using an inertia weight ('inertia_wt'), i.e., lset_correction←lset_correction_0+inertia_wt*lset_correction_cached. It should be noted that 'lset_correction_cached' is the correction field saved (or cached) for the next iteration. It should be noted that the correction field is not saved before the first iteration begins, i.e. the inertial field is not applied to the correction field in the first iteration. Fig.6D The difference between the level set of the simulation layer and the level set of the target layer (ie, the correction field) is shown in FIG. 5 for level set values ​​between, for example, -50 and 0.

[0059] At 535, the main features of the mask field (eg, the level set of main features of the mask layer) are updated. The level set of main features of the mask layer ('lset_mask_MF') is updated by subtracting the correction field from the level set of main features of the mask layer calculated at 510 (ie, lset_mask_MF←lset_mask_MF-lset_correction). Fig. 6E An updated level set of the mask layer with updated main features and fixed assist features for level set values ​​between, for example, -50 and +50 is shown in FIG.

[0060] At 540, the correction field is saved (or cached) for the next iteration (the next iteration of step 525), i.e., lset_correction_cached←lset_correction. At 545, the updated main features of the mask field (e.g., the level set of updated main features of the mask layer) are converted to the main features of the mask layer ('layer_mask_MF'), i.e., M(lset_mask_MF)→layer_mask_MF, where M() is a function that converts a level set to a layer. The function M() can be a contour generation function with a threshold level of, for example, zero.

[0061] At 550, the auxiliary features (fixed) of the mask layer are merged with the updated main features of the mask layer to obtain an updated mask layer, i.e., layer_mask←layer_mask_MF+layer_mask_AF. After that, steps 515 to 550 are repeated until the number of iterations reaches a predetermined value or until the simulated layer reaches the target layer within predefined limits. At 550 of the last iteration, the updated mask layer represents the final corrected mask layer, i.e., the designed curved mask.

[0062] In some embodiments, instead of using a field representation (e.g., a level set function), the layers can be directly Figure 5 In particular, instead of applying a correction field to the mask field, a correction field defined as the difference between the simulated field and the target field can be applied directly to the mask layer. In this case, the mask edge movement can be directly responsive to the difference between the simulated field and the target field, i.e., to the correction field updated during each iteration.

[0063] Figure 5 The lithography model (e.g., lithography model 210) used at 515 to generate the simulation layer from the mask layer may introduce strong crosstalk between mask edges. Strong crosstalk may lead to oscillations in the movement of the correction field (and equivalently, oscillations in the movement of the mask edge), thereby leading to a large number of iterations of the mask layer design process, that is, leading to a long running time of the mask layer design process and possible convergence failure. Fig. 7A Illustration illustrating the convergence trajectory of the iterative mask layer design process without applying an inertial field. Fig. 7A Point x0 in is the initial position in the mask search space, and trajectory 705 represents the trajectory of the position in the mask search space during the iterative mask layer design process. It can be observed that due to the strong crosstalk between the mask edges, the trajectory 705 of the position in the mask search space oscillates during the iterative mask layer design process, resulting in additional iterations required to converge to the target position (i.e., the convergence point).

[0064] To solve this convergence problem, Figure 5 The inertial field is applied during the iterative mask layer design process (e.g., at step 530 for calculating the final correction field). The inertial field prevents the movement of the mask edge from oscillating when the crosstalk level is high. The inertial field at the current iteration N can be calculated by scalar multiplication of the correction field at the previous iteration N-1 and the inertial weight (predetermined value). The correction field at the current iteration is updated as:

[0065] lset_correction[N]=damp_f*(lset_sim_contour[N]–lset_target)+lset_inertia_field[N], (1)

[0066] And the inertia field at the current iteration is calculated as follows:

[0067] lset_inertia_field[N] = inertia_wt * lset_correction[N-1]. (2)

[0068] Figure 7B Graphical instructions Figure 5 Convergence trajectory of the iterative mask layer design process when applying the inertial field. Figure 7B The point x0 in is the initial position in the mask search space, and the trajectory 710 is Figure 5 The trajectory of the positions in the mask search space during the iterative mask layer design process of . Figure 7B Observe that due to the vector 715 of the difference level set direction (i.e., the direction of the difference between the level set of the simulation layer and the level set of the target layer) and the vector 720 of the direction of the inertial field, the direction of the combined vector 725 is positioned directly towards the target location. Figure 5 The trajectory 710 of positions in the mask search space during the iterative mask layer design process does not oscillate, resulting in fewer iterations for converging to the target position.

[0069] exist Figure 5 During the iterative mask layer design process of , the mask edge movement is driven by the difference between the level set of the simulation layer and the level set of the target layer. However, in some cases, at step 515, the initial mask layer may not generate a simulation layer, resulting in no mask edge movement. In order to handle the "no simulation layer" situation, the concept of "pseudo contour" is introduced herein. Specifically, two types of pseudo contours are defined - inner pseudo contour and outer pseudo contour. Figure 8 An example circular target layer 802, an inner pseudo contour 804, and an outer pseudo contour 806 are illustrated. To calculate the inner pseudo contour 804 and the outer pseudo contour 806, an inner band 808 and an outer band 810 are defined. The inner band 808 is the gap between the inner pseudo contour 804 and the circular target layer 802, and the outer band 810 is the gap between the outer pseudo contour 806 and the circular target layer 802. The inner pseudo contour 804 may then be calculated by shrinking the circular target layer 802 to the inner band 808, and the outer pseudo contour 806 may then be calculated by expanding the circular target layer 802 to the outer band 810.

[0070] The final pseudo contour is synthesized by performing Boolean operations on the inner pseudo contour 804, the outer pseudo contour 806, and the simulation layer (if any), as defined below:

[0071] Final pseudo contour = [(simulation layer OR inner pseudo contour) AND outer pseudo contour]. (3)

[0072] exist Figures 9A to 9E The different shapes of the final pseudo contour synthesized using the inner pseudo contour and the outer pseudo contour are illustrated in FIG. The final pseudo contour synthesized by applying the operation of equation (3) may be referred to herein as Figure 5 The term “synthesized analog layers” rather than “analog layers” are used in the iterative mask layer design process.

[0073] Fig. 9A The diagram illustrates a synthesized simulated layer when no simulated layer is initially generated from an initial mask layer. The target layer 902, inner pseudo contour 904, and outer pseudo contour 906 are predetermined and pre-calculated. The synthesized simulated layer 908 is generated using the inner pseudo contour 904 and the outer pseudo contour 906 as given by equation (3). Fig. 9A The arrow 910 in the figure illustrates that Figure 5 The mask edge moves with full outward momentum during the iterative mask layer design process, which converges towards the target layer 902 in response to the synthesized simulated layer 908 .

[0074] Fig. 9B The diagram illustrates the synthesized simulated layer when the initial simulated layer is covered by the inner pseudo contour. The target layer 912, the inner pseudo contour 914 and the outer pseudo contour 916 are predetermined and pre-calculated. Fig. 9B As shown in , the initial simulated layer 915 generated from the initial mask layer is completely covered by the inner pseudo contour 914. The inner pseudo contour 914, the outer pseudo contour 916, and the initial simulated layer 915 are used to generate a synthesized simulated layer 918 as given by equation (3). Fig. 9B The arrow 920 in the figure illustrates that Figure 5 The mask edge moves with full outward momentum during the iterative mask layer design process, in response to the synthesized simulated layer 918 converging toward the target layer 912 .

[0075] Fig. 9C The diagram illustrates the synthesized simulated layer when the initial simulated layer intersects the inner pseudo contour and the outer pseudo contour. The target layer 922, the inner pseudo contour 924 and the outer pseudo contour 926 are predetermined and pre-calculated. Fig. 9C As shown in , the initial simulated layer 925 generated from the initial mask layer intersects both the inner pseudo contour 924 and the outer pseudo contour 926. The synthesized simulated layer 928 is generated using the inner pseudo contour 924, the outer pseudo contour 926, and the initial simulated layer 925, as given by equation (3). Fig. 9C As shown in FIG. 9 , the synthesized simulated layer 928 intersects the target layer 922. Arrow 929 illustrates the inward momentum of the mask edge movement, and arrow 930 illustrates the inward momentum of the mask edge movement. Figure 5 The outward momentum of the mask edge movement during the iterative mask layer design process of FIG. Both the inward momentum and the outward momentum are responsive to the corresponding convergence of the synthesized simulated layer 928 toward the target layer 922.

[0076] Fig.9D The diagram illustrates the synthesized simulated layer when the initial simulated layer intersects the inner pseudo contour. The target layer 932, the inner pseudo contour 934 and the outer pseudo contour 936 are predetermined and pre-calculated. Fig.9D , the initial simulated layer 935 generated from the initial mask layer intersects the inner pseudo contour 934 but does not intersect the outer pseudo contour 936. The inner pseudo contour 934, the outer pseudo contour 936, and the initial simulated contour 935 are used to generate a synthesized simulated layer 938, as given by equation (3). Fig.9D The arrow 940 in the figure illustrates that Figure 5 The total outward momentum of the mask edge movement during the iterative mask layer design process is in response to the convergence of the synthesized simulated layer 938 toward the target layer 932. However, it should be noted that the strength of the outward momentum is not uniform across different locations of the synthesized simulated layer 938 because the synthesized simulated layer 938 is closer to the target layer 932 at some locations than at some other locations.

[0077] Fig.9E The diagram illustrates the synthesized simulation layer when the initial simulation layer covers the outer pseudo contour. The target layer 942, the inner pseudo contour 944 and the outer pseudo contour 946 are predetermined and pre-calculated. Fig.9E , the initial simulated layer 945 generated from the initial mask layer completely covers the outer pseudo contour 946. The inner pseudo contour 944, the outer pseudo contour 946, and the initial simulated layer 945 are used to generate a synthesized simulated layer 948, as given by equation (3). Fig.9E The arrow 950 in the figure illustrates that Figure 5 The full inward momentum of the mask edge movement during the iterative mask layer design process in response to the convergence of the synthesized simulated layer 948 towards the target layer 942.

[0078] A pair of segments of the contact layer were used to prototype and test the iterative mask layer design process presented herein. Fig. 10A The diagram illustrates a fragment of a contact layer 1000, where the designed main features of the mask layer 1002 show overlap with the fixed assist features of the circular target layer 1004, the simulation layer 1006, and the mask layer 1008. Fig. 10A It is observed that the simulation layer 1006 for different patterns substantially overlaps the circular target layer 1004, thereby confirming the convergence of the iterative mask layer design process presented herein for different mask patterns. Fig. 10B The diagram illustrates a fragment of a contact layer 1010 in which the designed main features of a mask layer 1012 show overlap with fixed assist features of a circular target layer 1014, a simulation layer 1016, and a mask layer 1018. Fig. 10BIt is observed that the simulation layer 1016 substantially overlaps the circular target layer 1014 for different patterns, thereby confirming the convergence of the iterative mask layer design process presented herein for different mask patterns.

[0079] To evaluate the convergence stability, the area difference between the target layer and the simulated layer is measured as a function of the iteration number of the iterative mask layer design process presented in this paper. Fig.11A It is for Fig. 10A An example graph 1102 of the area difference between a circular target layer 1004 and a simulated layer 1006 of a segment of a contact layer 1000 . Fig. 11B It is for Fig. 10B Example graph 1104 of the area difference between a circular target layer 1014 and a simulated layer 1016 for a segment of the contact layer 1010. In both cases, the area difference decays monotonically when increasing the number of iterations of the presented mask layer design process.

[0080] The iterative mask layer design process presented herein (also referred to herein as a "level set solver") is benchmarked herein against several conventional mask synthesis solutions, namely, a first ILT (Inverse Lithography Technology) algorithm, a second ILT algorithm, a third ILT algorithm, and an OPC (Optical Proximity Correction) algorithm. Fig. 10A Comparison of the operating time (ie, turnaround time (TAT)), maximum EPE, minimum EPE and average absolute EPE of the fragments of the contact layer 1000 is shown in FIG. Fig. 12A Displayed in and targeted at Fig. 10B The fragment of the contact layer 1010 is Fig. 12B It can be observed that in both cases, the “Level Set Solver” presented herein outperforms conventional mask synthesis solutions in terms of runtime (ie, speed) and average absolute EPE (ie, convergence accuracy).

[0081] Fig.13 The diagram illustrates a set of example processes 1300 used during the design, verification and fabrication of a manufactured article (e.g., an integrated circuit) to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term 'EDA' denotes the term 'electronic design automation'. These processes begin with forming a product concept 1310 using information provided by a designer, transforming this information to form a manufactured article using a set of EDA processes 1312. When the design is finally completed, the design is taped out 1334, at which time the artwork (e.g., geometric pattern) of the integrated circuit is sent to a fabrication facility to produce a mask set, which is then used to fabricate the integrated circuit. After tape-out, semiconductor die are fabricated 1336 and packaging and assembly processes 1338 are performed to produce a finished integrated circuit 1340.

[0082] The specification of a circuit or electronic structure can range from low-level transistor material layout to a high-level description language. The high-level representation can be used to design circuits and systems using a hardware description language ('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic-level register transfer level ('RTL') description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of representation as a more detailed description adds more useful detail to the design description, for example, more detail for the modules that contain the description. The lower level of representation as a more detailed description can be computer-generated, derived from a design library, or formed by another design automation process. An example of a specification language for specifying a more detailed description of a lower-level representation language is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each representation level is enabled for use by the corresponding system of that layer (e.g., a formal verification system). The design process can use Fig.13 The process is described as being enabled by an EDA product (or EDA system).

[0083] During system design 1314, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or code line), and reduced cost. The design can be partitioned into different types of modules or components at this stage.

[0084] During logic design and functional verification 1316, modules or components in a circuit are specified in one or more description languages ​​and the functional accuracy of the specifications is checked. The components of the circuit can be checked to generate outputs that match the requirements of the specifications of the designed circuit or system. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, special component systems called 'emulators' or 'prototyping systems' are used to accelerate functional verification.

[0085] During synthesis and test design 1318, the HDL code is transformed into a netlist. In some embodiments, the netlist can be a graph structure where the edges of the graph structure represent components of the circuit and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical manufacturing objects that can be used by EDA products to verify that the integrated circuit is executed according to the specified design when manufactured. The netlist can optimize the target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0086] During netlist verification 1320, the netlist may be checked for compliance of timing constraints and correspondence of HDL code. During design planning 1322, an overall floor plan of the integrated circuit may be constructed and analyzed for timing and top-level routing.

[0087] During layout or physical implementation 1324, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connecting circuit components through multiple conductors) occur, and selection of cells from a library may be performed to enable specific logic functions. As used herein, the term 'cell' may specify a group of transistors, other components, and interconnections that provide Boolean logic functions (e.g., "and", "or", "not", "exclusive or") or storage functions (e.g., flip-flops or latches). As used herein, a circuit 'block' may refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components and are enabled both as physical structures and in simulations. Parameters (e.g., size) are specified for selected cells (based on 'standard cells') and may be accessed in a database for use by EDA products.

[0088] During analysis and extraction 1326, circuit functionality is verified at the layout level, which permits improvements to the layout design. During physical verification 1328, the layout design is checked to ensure that manufacturing constraints (e.g., DRC constraints, electrical constraints, lithography constraints) are correct and that the circuit system functionality matches the HDL design specifications. During resolution enhancement 1330, the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0089] During tape-out, data is formed for use in producing lithography masks (after applying lithography enhancements where appropriate).During mask data preparation 1332, the 'tape-out' data is used to produce lithography masks, which are used to produce finished integrated circuits.

[0090] Computer systems (e.g. Fig.14 The storage subsystem of the computer system 1400) may be used to store programs and data structures used by some or all of the EDA products described herein, as well as cells for the library and products for physical and logical design that use the library.

[0091] Fig.14 An example machine of a computer system 1400 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0092] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0093] The example computer system 1400 includes a processing device 1402, a main memory 1404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 1406 (e.g., flash memory, static random access memory (SRAM)), and a data storage device 1418, which communicate with each other via a bus 1430.

[0094] The processing device 1402 represents one or more processors (e.g., microprocessors, central processing units, etc.). More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 1402 may also be one or more special purpose processing devices (e.g., application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc.). The processing device 1402 may be configured to execute instructions 1426 for performing the operations and steps discussed herein.

[0095] The computer system 1400 may further include a network interface device 1408 that communicates via a network 1420. The computer system 1400 may also include a video display unit 1410 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1412 (e.g., a keyboard), a cursor control device 1414 (e.g., a mouse), a graphics processing unit 1422, a signal generating device 1416 (e.g., a speaker), a graphics processing unit 1422, a video processing unit 1428, and an audio processing unit 1432.

[0096] The data storage device 1418 may include a machine-readable storage medium 1424 (also referred to as a non-transitory computer-readable medium) having stored thereon one or more sets of instructions 1426 or software embodying any one or more of the methodologies or functions described herein. The instructions 1426 may also reside completely or at least partially within the main memory 1402 and / or the processing device 1400 during execution thereof by the computer system 1404, the main memory 1404 and the processing device 1402 also constituting machine-readable storage media.

[0097] In some embodiments, instructions 1426 include instructions to implement functionality corresponding to the present disclosure. Although machine-readable storage medium 1424 is shown as a single medium in an exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated cache memory and server) storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine and processing device 1402 to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0098] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to those skilled in the art. An algorithm may be a sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0099] It should be remembered, however, that all of these terms and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated as apparent from the present disclosure, it should be understood that throughout this specification, specific terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0100] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may include a computer that is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as but not limited to any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0101] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0102] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a program according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0103] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific exemplary embodiments of the present disclosure. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the figures and similar elements are labeled with similar numbers. Therefore, the present disclosure and the drawings should be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method comprising: accessing a mask layer, the mask layer comprising a vector representation of a lithography mask, the lithography mask comprising a plurality of features including a curved primary feature; calculating a correction field between a simulated field and a target field, wherein the simulated field comprises a field representation of a simulated result of a lithography process using the lithography mask and the target field comprises a field representation of a target result of the lithography process; modifying the primary features of a mask field based on the correction field, wherein the mask field comprises a field representation of the primary features of the lithography mask; and The main features of the mask layer are modified by processing means based on the modification of the mask field. 2 . The method of claim 1 , wherein the mask layer comprises a parameterized curve representing the curved primary feature. The method of claim 1 , wherein the curved primary feature is curvilinear. The method of claim 1 , wherein the field representation comprises a level set representation.

5. The method of claim 1, wherein the result of the lithography process is one of: an aerial image, a latent image in resist, a resist structure, and a device structure.

6. The method of claim 1 , wherein calculating the correction field comprises: calculating an initial correction field by scaling the difference between the simulated field and the target field; calculating an inertial field by scaling a version of the correction field calculated in a previous iteration of a plurality of iterations of the method; and The correction field is determined by adding the inertial field to the initial correction field.

7. The method according to claim 1, further comprising: generating an inner pseudo contour by scaling down a target layer to an inner band, wherein the target layer includes a vector representation of the target result; generating an outer pseudo contour by enlarging the target layer to an outer band; and A simulation layer is calculated by performing Boolean operations on the mask layer, the inner pseudo contour, and the outer pseudo contour, wherein the simulation layer includes a vector representation of the simulated result.

8. The method according to claim 1, further comprising: The mask layer is converted into the mask field by computing level sets of the principal features of the mask layer.

9. The method according to claim 1, further comprising: The modified primary features of the mask field are converted into the primary features of the mask layer by applying a profile generating function with a defined threshold to the modified primary features of the mask field.

10. The method according to claim 1, further comprising: receiving a target layer, the target layer comprising a vector representation of the target result; and The target field is determined according to the target layer. The method of claim 10 , wherein the target layer comprises a curved primary feature.

12. The method of claim 1, wherein the plurality of features of the photolithographic mask include assist features, and the method does not modify the assist features.

13. The method of claim 12, wherein the mask field, the simulation field, and the target field include field representations of the primary features but not the auxiliary features.

14. The method of claim 1, wherein the simulation of the lithography process produces a field representation rather than a vector representation.

15. The method of claim 1, wherein modifying the mask layer is incorporated as part of an Inverse Lithography Technology (ILT) process.

16. The method of claim 1, wherein the method is repeated for a plurality of iterations, the method further comprising: A final version of the mask layer from the plurality of iterations is output.

17. A system comprising: a memory storing instructions; a processing device coupled to the memory and configured to execute the instructions, which when executed cause the processing device to: accessing a mask layer, the mask layer comprising a vector representation of a lithography mask, the lithography mask comprising a plurality of features including a curved main feature, running a simulation of a lithography process using the lithography mask to generate simulated results of the lithography process, calculating a correction field between a simulated field and a target field, wherein the simulated field comprises a field representation of the simulated result and the target field comprises a field representation of a target result of the lithographic process, modifying the primary features of a mask field based on the correction field, wherein the mask field comprises a field representation of the primary features of the lithography mask, and The primary features of the mask layer are modified based on the modification of the mask field.

18. The system of claim 17, wherein the instructions, when executed, further cause the processing device to: receiving a target layer, the target layer comprising a vector representation of the target result; and The target field is determined based on the target layer, wherein the target layer contains curved primary features, and wherein, the plurality of features of the photolithographic mask include assist features that are not modified, the mask field, the simulation field, and the target field include field representations of the primary features but not the auxiliary features, The simulation of the lithographic process produces a field representation rather than a vector representation, and Modifying the mask layer is incorporated as part of the Inverse Lithography Technology (ILT) process.

19. A non-transitory computer-readable medium comprising stored instructions that, when executed by a processing device, cause the processing device to: accessing a mask layer, the mask layer comprising a vector representation of a lithography mask, the lithography mask comprising a curved primary feature; calculating a correction field between a simulated field and a target field, wherein the simulated field comprises a field representation of a simulated result of a lithography process using the lithography mask and the target field comprises a field representation of a target result of the lithography process; modifying a mask field based on the correction field, wherein the mask field comprises a field representation of the lithography mask; and The mask layer is modified based on the modification of the mask field.

20. The non-transitory computer readable medium of claim 19, wherein the instructions further cause the processing device to: calculating an initial correction field by scaling the difference between the simulated field and the target field; calculating an inertial field by scaling a previously calculated version of the correction field; and The correction field is determined by adding the inertial field to the initial correction field.

Images