Emergency backup dual-redundancy broadband digital servo system

Abstract

An emergency backup dual-redundancy broadband digital servo system comprises two emergency backup control redundancies with the same module configuration, and the dual redundancies are electrically connected through two redundancy data interaction modules and a dual-redundancy synchronization signal module. Each of the two redundancies comprises an ADin module, a bus driving module, an FPGA module, a DSP module, a DAout module and a power amplification module. The FPGA module of the redundancy 1 and the FPGA module of the redundancy 2 are electrically connected through two redundancy data interaction modules, and the DSP module of the redundancy 1 and the DSP module of the redundancy 2 are electrically connected through a dual-redundancy synchronization signal module; two redundancies are connected through the two data interaction modules and the redundancy synchronization signal module, so that the redundancy and hardware architecture based on the backup system realizes acquisition of signals between the redundancies and rapid operation of servo control instructions, and the frequency response technical index requirements of a main paddle digital servo loop are met.

Description

Technical Field

[0001] The invention belongs to the field of backup systems for fly-by-wire flight control systems, and in particular is an emergency backup dual-redundancy wideband digital servo system. Background Art

[0002] When the main flight control fails, the emergency backup control system needs to implement the backup flight control function. Combined with the redundancy architecture and hardware architecture of the main flight control, the emergency backup and the main flight control need to be completely dissimilar. The project development requires the backup flight control function and the main propeller servo drive function to be integrated and implemented in the same product. Based on the redundancy and hardware architecture of the backup system, how to achieve the acquisition of redundancy signals and the rapid calculation of servo control instructions to meet the technical indicator requirements of the main propeller digital servo loop frequency response (8Hz) is a problem that the present invention needs to solve. Summary of the invention

[0003] In view of this, the present invention provides an emergency backup dual-redundancy wideband digital servo system to solve the above problem.

[0004] The technical solution adopted by the present invention is: an emergency backup dual-redundancy wideband digital servo system, comprising a first emergency backup control redundancy and a second emergency backup control redundancy with the same module configuration, characterized in that: the first emergency backup control redundancy and the second emergency backup control redundancy are electrically connected through two redundancy data interaction modules and a dual-redundancy synchronization signal module; The first emergency backup control redundancy and the second emergency backup control redundancy both include an ADin module, a bus driver module, an FPGA module, a DSP module, a DAout module and a power amplifier module; the FPGA module is electrically connected to the ADin module, the bus driver module, the DSP module and the DAout module respectively; the DAout_a module is electrically connected to the power amplifier module; the FPGA module of the first emergency backup control redundancy and the FPGA module in the second emergency backup control redundancy are electrically connected through two redundancy data interaction modules, and the DSP module of the first emergency backup control redundancy and the DSP module in the second emergency backup control redundancy are electrically connected through a dual-redundancy synchronization signal module; The ADin module is used to collect RVDT signals and LVDT signals and transmit them to the FPGA module; The bus driver module is used to collect atmospheric engine signals and inertial measurement signals and transmit them to the FPGA module; The FPGA module is used to complete the acquisition and output of analog signals and bus signals and the data interaction between the two redundancies; The DSP module is used for voting and command operation of the signal source between the two redundancies, and the synchronization signal between the two redundancies; The DAout module is used to output the servo control instruction to the power amplifier module; The power amplification module is used to convert the servo control instruction into a servo valve driving signal.

[0005] Further, the two redundancy data interaction modules include a first redundancy data interaction module and a second redundancy data interaction module, wherein the first redundancy data interaction module includes an FPGA_a module U1_a and a bus driver module U2_a arranged in the first emergency backup control redundancy, a bus signal transceiver crossover area J1, and an FPGA_b module U1_b and a bus driver module U2_b arranged in the second emergency backup control redundancy; The K1 pin of the FPGA_a module U1_a in the first emergency backup control redundancy is connected to the 3 pin of the bus driver module U2_a through the transmission channel TX1_a, and the K2 pin of the FPGA_a module U1_a is connected to the 2 pin of the bus driver module U2_a through the receiving channel RX1_a; The 5th pin of the bus driver module U2_a is connected to the 1st pin of the bus signal transceiver cross area J1 through the forward signal line TX1+_a of the transmission channel, and the 6th pin of the bus driver module U2_a is connected to the 2nd pin of the bus signal transceiver cross area J1 through the reverse signal line TX1-_a of the transmission channel; the 8th pin of the bus driver module U2_a is connected to the 3rd pin of the bus signal transceiver cross area J1 through the forward signal line RX1+_a of the receiving channel, and the 7th pin of the bus driver module U2_a is connected to the 4th pin of the bus signal transceiver cross area J1 through the reverse signal line RX1-_a of the receiving channel; a resistor R1_a is connected between the 8th pin and the 7th pin of the bus driver module U2_a; Pin 1 and Pin 2 of the bus signal receiving and transmitting crossover area J1 are respectively connected to Pin 8 and Pin 7 of the bus driver module U2_b, and a resistor R1_b is connected in parallel between Pin 8 and Pin 7 of the line driver module U2_b; Pin 3 and Pin 4 of the bus signal receiving and transmitting crossover area J1 are respectively connected to Pin 5 and Pin 6 of the bus driver module U2_b; Pin 3 and Pin 2 of the bus driver module U2_b are respectively connected to Pin K1 and Pin K2 of the FPGA_b module U1_b set in the second emergency backup control redundancy.

[0006] Further, the second data interaction module includes an FPGA_a module U1_a and a bus driver module U3_a arranged in the first emergency backup control redundancy, a bus signal transceiver crossover area J1, and an FPGA_b module U1_b and a bus driver module U3_b arranged in the second emergency backup control redundancy; In the first emergency backup control redundancy, the K6 pin of the FPGA_a module U1_a is connected to the 3 pin of the bus driver module U3_a through the transmission channel TX2_a, and the J6 pin of the FPGA_a module U1_a is connected to the 2 pin of the bus driver module U3_a through the receiving channel RX2_a; The 5th pin of the bus driver module U3_a is connected to the 5th pin of the bus signal transceiver cross area J1 through the forward signal line TX2+_a of the transmission channel, and the 6th pin of the bus driver module U3_a is connected to the 6th pin of the bus signal transceiver cross area J1 through the reverse signal line TX2-_a of the transmission channel; the 8th pin of the bus driver module U3_a is connected to the 7th pin of the bus signal transceiver cross area J1 through the forward signal line RX2+_a of the receiving channel, and the 7th pin of the bus driver module U3_a is connected to the 8th pin of the bus signal transceiver cross area J1 through the reverse signal line RX2-_a of the receiving channel; a resistor R2_a is connected between the 8th pin and the 7th pin of the bus driver module U3_a; Pin 5 and pin 6 of the bus signal receiving and transmitting crossover area J1 are respectively connected to pin 8 and pin 7 of the bus driver module U3_b, and a resistor R2_b is connected in parallel between pin 8 and pin 7 of the line driver module U3_b; pin 7 and pin 8 of the bus signal receiving and transmitting crossover area J1 are respectively connected to pin 5 and pin 6 of the bus driver module U3_b; pin 3 and pin 2 of the bus driver module U3_b are respectively connected to pin K6 and pin J6 of the FPGA_b module U1_b set in the second emergency backup control redundancy.

[0007] Furthermore, the period of the first data interaction module is configured to be 12.5 ms; and the period of the second data interaction module is configured to be 2.5 ms.

[0008] Further, the dual-redundancy synchronization signal module includes a DSP_a module U4_a and a level conversion_a module U5_a arranged in the first emergency backup control redundancy, a synchronization signal crossover area J2, and a DSP_b module U4_b and a level conversion_b module U5_b arranged in the second emergency backup control redundancy; The L12 pin of the DSP_a module U4_a is connected to the 36 pin of the level conversion module U5_a, for receiving the synchronization signal in the second emergency backup control margin; the J12 pin of the DSP_a module U4_a is connected to the 47 pin of the level conversion module U5_a, for outputting the synchronization signal to the second emergency backup control margin; Pin 1 of the level conversion module U5_a is connected to +5V power supply, and pin 24 is grounded; pin 13 of the level conversion module U5_a is connected to pin 10 of the synchronization signal cross section J2, and pin 2 of the level conversion module U5_a is connected to pin 9 of the synchronization signal cross section J2; The L12 pin of the DSP_b module U4_b is connected to the 36 pin of the level conversion_b module U5_b, for receiving the synchronization signal in the first emergency backup control margin; the J12 pin of the DSP_b module U4_b is connected to the 47 pin of the level conversion_b module U5_b, for outputting the synchronization signal to the first emergency backup control margin; Pin 1 of the level conversion module U5_b is connected to a +5V power supply and pin 24 is grounded; pin 13 of the level conversion module U5_b is connected to pin 9 of the synchronization signal crossing area J2, and pin 2 of the level conversion module U5_b is connected to pin 10 of the synchronization signal crossing area J2.

[0009] Furthermore, the synchronization of the dual-redundancy synchronization signal module is divided into power-on initial synchronization and periodic synchronization. The maximum waiting time for the power-on initial synchronization is 500ms, the maximum waiting time for the periodic synchronization is 50μs, and the synchronization period is 12.5ms.

[0010] The beneficial effect of the present invention is that two redundancies are connected through two data interaction modules and a redundancy synchronization signal module, so that the acquisition of signals between redundancies and the rapid calculation of servo control instructions are realized based on the redundancy and hardware architecture of the backup system, meeting the technical index requirements of the frequency response of the main propeller digital servo loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of redundancy cross-linking of emergency backup control system; Figure 2 It is a functional module block diagram of the present invention; Figure 3 It is a circuit connection diagram of the redundancy data interaction module; Figure 4 This is a circuit connection diagram of the redundancy synchronization signal module. DETAILED DESCRIPTION

[0012] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0013] like Figure 1 As shown, an emergency backup dual-redundancy wideband digital servo system includes two emergency backup control redundancies, namely a first emergency backup control redundancy and a second emergency backup control redundancy. For the convenience of description, they are referred to as redundancy 1 and redundancy 2 in the following. Redundancy 1 and redundancy 2 are electrically connected through two redundancy data interaction modules and a dual-redundancy synchronization signal module.

[0014] In one embodiment, Figure 2As shown, the configuration structure of each module in Redundancy 1 and Redundancy 2 is the same. It should be noted that "_a" represents the device in Redundancy 1, and "_b" represents the device in Redundancy 2. Now take Redundancy 1 as an example to explain the structure: Redundancy 1 includes an ADin_a module, a bus driver_a module, an FPGA_a module, a DSP_a module, a DAout_a module, and a power amplifier module. The FPGA_a module is electrically connected to the ADin_a module, the bus driver_a module, the DSP_a module, and the DAout_a module. The DAout_a module is electrically connected to the power amplifier module.

[0015] The ADin_a module is used to collect RVDT signals and LVDT signals and transmit them to the FPGA_a module. Specifically, the ADin_a module uses an A / D conversion chip to collect analog signal rod displacement RVDT signals and actuator position feedback LVDT signals, and the A / D conversion chip then inputs the collection results to the FPGA_a module for collection.

[0016] The bus driver_a module is used to collect the atmospheric engine signal and the inertial measurement signal and transmit them to the FPGA_a module. Specifically, the bus driver_a module uses the bus driver to drive the conversion of the bus signal atmospheric engine signal and the inertial measurement signal, and then inputs them to FPGA_a for collection.

[0017] The FPGA_a module is used to complete the acquisition and output of analog signals and bus signals, as well as the data exchange between the two redundancies. The FPGA_a module also exchanges data with the DSP_a module. Specifically, the FPGA_a module completes the acquisition of analog signals and bus signals through the ADin_a module and the bus driver_a module, and transmits the collected signals to the outside through the DAout_a module to transmit servo control instructions. The FPGA_a module exchanges data with the DSP_a, and at the same time controls the interactive transmission of instructions between the two redundancies.

[0018] The DSP_a module is used for the voting and instruction operation of the signal source between the two redundancies, as well as the synchronization signal between the two redundancies. Specifically, the DSP_a module completes the voting of the input signal source between the two redundancies, the voting of the control instruction output, the control instruction operation, the servo loop servo control instruction operation, and the function of realizing the synchronization signal between the two redundancies.

[0019] The DAout_a module uses a D / A conversion chip to output servo control instructions to the power amplifier circuit.

[0020] The power amplifier module uses a power operational amplifier to convert the servo control command into a servo valve drive signal.

[0021] The module configuration structure in the emergency backup control redundancy b is consistent with that in the emergency backup control redundancy a, including an ADin_b module, a bus driver_b module, an FPGA_b module, a DSP_b module, a DAout_b module and a power amplifier module.

[0022] In the emergency backup control redundancy a and the emergency backup control redundancy b, there is a redundancy synchronization function module in the electrical signal connection between the FPGA_a module and the FPGA_b module. The redundancy data interaction function module is used to obtain the data information of its redundancy and redundancy management. There is a redundancy synchronization function module in the electrical signal connection between the DSP_a module and the DSP_b module. For the emergency backup system, the performance of the components of each redundancy will not be exactly the same, resulting in different startup times and operating rhythms of the two redundancies. In order to achieve synchronous operation between the two redundancies of the emergency backup system and realize the real-time data interaction, it is necessary to synchronize the two redundancies, so a dual redundancy synchronization signal module is set.

[0023] For the present invention, the most important thing is how to achieve synchronization between the two redundancies. In order to achieve the frequency response requirements of the digital servo loop, two sets of data interaction channels are configured, one set is used for cross-acquisition of external loop data (first redundancy data interaction module), and the cycle is set to 12.5ms; the other set is used for cross-acquisition of data of the internal digital servo loop (second redundancy data interaction module), and the cycle is set to 2.5ms. Different interaction cycles are adopted to achieve the index requirements of the high frequency response of the servo loop. The redundancy data interaction module is now described in detail, as follows: The two redundant data interaction modules have the same hardware composition, which are divided into a first data interaction module and a second data interaction module. Figure 3 A detailed description is now given.

[0024] Since the two redundancy data interaction modules connect two redundancies, "_a" in the device represents redundancy 1 and "_b" represents redundancy 2.

[0025] In one embodiment, the first data interaction module includes an FPGA_a module U1_a, a bus driver module U2_a, a bus signal transceiver crossover area J1, a bus driver module U2_b, and an FPGA_b module U1_b.

[0026] The K1 pin of the FPGA_a module U1_a is connected to the 3 pin of the bus driver module U2_a through the transmission channel TX1_a, and the K2 pin of the FPGA_a module U1_a is connected to the 2 pin of the bus driver module U2_a through the receiving channel RX1_a; Pin 5 of the bus driver module U2_a is connected to pin 1 of the bus signal transceiver cross section J1 through the forward signal line TX1+_a of the transmission channel, and pin 6 of the bus driver module U2_a is connected to pin 2 of the bus signal transceiver cross section J1 through the reverse signal line TX1-_a of the transmission channel. Pin 8 of the bus driver module U2_a is connected to pin 3 of the bus signal transceiver cross section J1 through the forward signal line RX1+_a of the receiving channel, and pin 7 of the bus driver module U2_a is connected to pin 4 of the bus signal transceiver cross section J1 through the reverse signal line RX1-_a of the receiving channel. A resistor R1_a is connected between pins 8 and 7 of the bus driver module U2_a; Pins 1 and 2 of the bus signal receiving and transmitting crossover area J1 are connected to pins 8 and 7 of the bus driver module U2_b, respectively. A resistor R1_b is connected in parallel between pins 8 and 7 of the line driver module U2_b. Pins 3 and 4 of the bus signal receiving and transmitting crossover area J1 are connected to pins 5 and 6 of the bus driver module U2_b, respectively. Pins 3 and 2 of the bus driver module U2_b are connected to pins K1 and K2 of the FPGA_b module U1_b, respectively.

[0027] The specific implementation function of the first data interaction module is to obtain flight control law data. The communication cycle is set to 12.5ms. The first data interaction module sends data information to Redundancy 2 through the sending channel TX1_a. The data information includes the signal data of Redundancy 1, i.e., RVDT, atmospheric engine, inertial measurement, voting results, and control law operation results. The receiving channel RX1_a in the first data interaction module receives the data information sent by Redundancy 2. The data information includes the signal source of Redundancy 2, i.e., RVDT, atmospheric engine, inertial measurement data, voting results, and control law operation results.

[0028] In one embodiment, the second data interaction module includes an FPGA_a module U1_a, a bus driver module U3_a, a bus signal transceiver crossover area J1, a bus driver module U3_b, and an FPGA_b module U1_b.

[0029] The K6 pin of the FPGA_a module U1_a is connected to the 3 pin of the bus driver module U3_a through the transmission channel TX2_a, and the J6 pin of the FPGA_a module U1_a is connected to the 2 pin of the bus driver module U3_a through the receiving channel RX2_a; The 5th pin of the bus driver module U3_a is connected to the 5th pin of the bus signal transceiver cross section J1 through the forward signal line TX2+_a of the transmission channel, and the 6th pin of the bus driver module U3_a is connected to the 6th pin of the bus signal transceiver cross section J1 through the reverse signal line TX2-_a of the transmission channel. The 8th pin of the bus driver module U3_a is connected to the 7th pin of the bus signal transceiver cross section J1 through the forward signal line RX2+_a of the receiving channel, and the 7th pin of the bus driver module U3_a is connected to the 8th pin of the bus signal transceiver cross section J1 through the reverse signal line RX2-_a of the receiving channel. A resistor R2_a is connected between the 8th and 7th pins of the bus driver module U3_a; The 5th and 6th pins of the bus signal receiving and transmitting cross area J1 are connected to the 8th and 7th pins of the bus driver module U3_b respectively, and a resistor R2_b is connected in parallel between the 8th and 7th pins of the line driver module U3_b. The 7th and 8th pins of the bus signal receiving and transmitting cross area J1 are connected to the 5th and 6th pins of the bus driver module U3_b respectively. The 3rd and 2nd pins of the bus driver module U3_b are connected to the K6th and J6th pins of the FPGA_b module U1_b respectively.

[0030] The specific implementation function of the second data interaction module is: used for acquiring digital servo loop data. The communication cycle is set to 2.5ms. The sending channel TX2_a in the second data interaction module sends data information to Redundancy 2, and the data information includes the data of the servo position feedback sensor LVDT of the signal source of Redundancy 1 and the operation result of the servo loop control instruction. The receiving channel RX2_a in the second data interaction module receives the data information sent by Redundancy 2, and the data information includes the data of the servo position feedback sensor LVDT of the signal source of Redundancy 2 and the operation result of the servo loop control instruction.

[0031] The hardware composition of data interaction channel 1 and data interaction channel 2 is the same, and the data interaction period of bus configuration is different. The first data interaction module is configured with 12.5ms; the second data interaction module is configured with 2.5ms. The implementation function of the bus signal transceiver crossover area J1 in the redundancy data interaction circuit is to realize the connection between the sending of redundancy 1 bus signal and the receiving of redundancy 2 bus signal, and the connection between the receiving of redundancy 1 bus signal and the sending of redundancy 2 bus signal.

[0032] In the present invention, the implementation function of the dual-redundancy synchronization signal module is: each redundancy configuration hardware synchronization signal sends and receives the synchronization signal of the other redundancy, and the synchronization signal arrives within the specified time, indicating that the synchronization is normal. The synchronization of this scheme is divided into power-on initial synchronization and periodic synchronization. The maximum waiting time for power-on initial synchronization is 500ms, the maximum waiting time for periodic synchronization is 50μs, and the synchronization cycle is 12.5ms.

[0033] In one embodiment, Figure 4As shown, the dual-redundancy synchronization signal module includes a DSP_a module U4_a, a level conversion_a module U5_a, a synchronization signal crossover area J2, a level conversion_b module U5_b, and a DSP_b module U4_b. Similarly, since two dual-redundancy synchronization signal modules are connected to two redundancies, "_a" in the device represents redundancy 1, and "_b" represents redundancy 2.

[0034] The L12 pin of the DSP_a module U4_a is connected to the 36 pin of the level conversion module U5_a, for receiving the synchronization signal of the redundancy 2; the J12 pin of the DSP_a module U4_a is connected to the 47 pin of the level conversion module U5_a, for outputting the synchronization signal to the redundancy 2; Pin 1 of the level conversion module U5_a is connected to the +5V power supply and pin 24 is connected to the ground.

[0035] Pin 13 of the level conversion module U5_a is connected to pin 10 of the synchronization signal crossing area J2, and pin 2 of the level conversion module U5_a is connected to pin 9 of the synchronization signal crossing area J2.

[0036] The L12 pin of the DSP_b module U4_b is connected to the 36 pin of the level conversion module U5_b, for receiving the synchronization signal of the redundancy 1; the J12 pin of the DSP_b module U4_b is connected to the 47 pin of the level conversion module U5_b, for outputting the synchronization signal to the redundancy 1; Pin 1 of the level conversion module U5_b is connected to the +5V power supply and pin 24 is connected to the ground.

[0037] Pin 13 of the level conversion module U5_b is connected to pin 9 of the synchronization signal crossing area J2, and pin 2 of the level conversion module U5_b is connected to pin 10 of the synchronization signal crossing area J2.

[0038] The implementation function of the synchronization signal crossing area J2 is to realize that the synchronization signal output by redundancy 1 is connected to the receiving of the synchronization signal of redundancy 2, and the receiving of the synchronization signal of redundancy 1 is connected to the output of the synchronization signal of redundancy 2.

[0039] In the present invention, the chip model of the FPGA module U1 is XC6SLX75-3FGG484I; The chip model of the bus driver module U2 used in the first data interaction module and the bus driver module U3 used in the second data interaction module is MAX3490ESA; The chip model of DSP module U4 is TMS320F28335-176ZJZ; The chip model of the level conversion module U5 in the dual-redundancy synchronization signal module is JC 54ALVC164245H; Resistors R1 and R2 are RMK1608KB121FPB chip resistors.

[0040] The time parameters involved in the present invention, such as 500ms, 50μs, 12.5ms, and 2.5ms, are set and implemented by the emergency backup system flight control software.

[0041] The functional division of each redundancy in this emergency backup control system is as follows: the FPGA module completes the acquisition and solution of the signal source, and the data interaction interface between the redundancy is realized in the FPGA interface. In order to ensure the frequency response requirements of the digital servo loop, the data interaction between the redundancy is realized by two sets of bus transceivers, one set is used for the cross-acquisition of control law data, and the cycle is set to 12.5ms; the other set is used for the cross-acquisition of digital servo loop data, and the cycle is set to 2.5ms. The digital signal processor DSP module establishes the synchronization signal between the two redundancies, completes the operation of the control law and the operation of the servo control instructions; the data line between the FPGA module and the DSP module is transmitted interactively. The FPGA module outputs the servo control instruction to the D / A conversion unit. After the servo control instruction is power-amplified, the servo drive instruction is sent to the servo valve to realize the servo drive function under the backup function.

[0042] After environmental tests, ground joint tests and on-board verification, the present invention can achieve the technical index requirements of the broadband digital servo loop of the emergency backup system.

Claims

1. An emergency backup dual-redundancy broadband digital servo system, comprising a first emergency backup control redundancy and a second emergency backup control redundancy with the same module configuration, characterized in that: The first emergency backup control redundancy and the second emergency backup control redundancy are electrically connected via two redundancy data interaction modules and a dual-redundancy synchronization signal module; The first emergency backup control redundancy and the second emergency backup control redundancy both include an ADin module, a bus driver module, an FPGA module, a DSP module, a DAout module and a power amplifier module; the FPGA module is electrically connected to the ADin module, the bus driver module, the DSP module and the DAout module respectively; the DAout_a module is electrically connected to the power amplifier module; the FPGA module of the first emergency backup control redundancy and the FPGA module in the second emergency backup control redundancy are electrically connected through two redundancy data interaction modules, and the DSP module of the first emergency backup control redundancy and the DSP module in the second emergency backup control redundancy are electrically connected through a dual-redundancy synchronization signal module; The ADin module is used to collect RVDT signals and LVDT signals and transmit them to the FPGA module; The bus driver module is used to collect atmospheric engine signals and inertial measurement signals and transmit them to the FPGA module; The FPGA module is used to complete the acquisition and output of analog signals and bus signals and the data interaction between the two redundancies; The DSP module is used for voting and command operation of the signal source between the two redundancies, and the synchronization signal between the two redundancies; The DAout module is used to output the servo control instruction to the power amplifier module; The power amplification module is used to convert the servo control instruction into a servo valve driving signal.

2. An emergency backup dual-redundancy broadband digital servo system as claimed in claim 1, characterized in that: The two redundancy data interaction modules include a first redundancy data interaction module and a second redundancy data interaction module, wherein the first redundancy data interaction module includes an FPGA_a module U1_a and a bus driver module U2_a arranged in the first emergency backup control redundancy, a bus signal transceiver crossover area J1, and an FPGA_b module U1_b and a bus driver module U2_b arranged in the second emergency backup control redundancy; The K1 pin of the FPGA_a module U1_a in the first emergency backup control redundancy is connected to the 3 pin of the bus driver module U2_a through the transmission channel TX1_a, and the K2 pin of the FPGA_a module U1_a is connected to the 2 pin of the bus driver module U2_a through the receiving channel RX1_a; The 5th pin of the bus driver module U2_a is connected to the 1st pin of the bus signal transceiver cross area J1 through the forward signal line TX1+_a of the transmission channel, and the 6th pin of the bus driver module U2_a is connected to the 2nd pin of the bus signal transceiver cross area J1 through the reverse signal line TX1-_a of the transmission channel; the 8th pin of the bus driver module U2_a is connected to the 3rd pin of the bus signal transceiver cross area J1 through the forward signal line RX1+_a of the receiving channel, and the 7th pin of the bus driver module U2_a is connected to the 4th pin of the bus signal transceiver cross area J1 through the reverse signal line RX1-_a of the receiving channel; a resistor R1_a is connected between the 8th pin and the 7th pin of the bus driver module U2_a; Pins 1 and 2 of the bus signal receiving and transmitting crossover area J1 are connected to pins 8 and 7 of the bus driver module U2_b respectively, and a resistor R1_b is connected in parallel between pins 8 and 7 of the line driver module U2_b; Pins 3 and 4 of the bus signal receiving and transmitting crossover area J1 are respectively connected to pins 5 and 6 of the bus driver module U2_b; pins 3 and 2 of the bus driver module U2_b are respectively connected to pins K1 and K2 of the FPGA_b module U1_b set in the second emergency backup control redundancy.

3. An emergency backup dual-redundancy broadband digital servo system as claimed in claim 2, characterized in that: The second data interaction module includes an FPGA_a module U1_a and a bus driver module U3_a arranged in the first emergency backup control redundancy, a bus signal transceiver crossover area J1, and an FPGA_b module U1_b and a bus driver module U3_b arranged in the second emergency backup control redundancy; In the first emergency backup control redundancy, the K6 pin of the FPGA_a module U1_a is connected to the 3 pin of the bus driver module U3_a through the transmission channel TX2_a, and the J6 pin of the FPGA_a module U1_a is connected to the 2 pin of the bus driver module U3_a through the receiving channel RX2_a; The 5th pin of the bus driver module U3_a is connected to the 5th pin of the bus signal transceiver cross area J1 through the forward signal line TX2+_a of the transmission channel, and the 6th pin of the bus driver module U3_a is connected to the 6th pin of the bus signal transceiver cross area J1 through the reverse signal line TX2-_a of the transmission channel; the 8th pin of the bus driver module U3_a is connected to the 7th pin of the bus signal transceiver cross area J1 through the forward signal line RX2+_a of the receiving channel, and the 7th pin of the bus driver module U3_a is connected to the 8th pin of the bus signal transceiver cross area J1 through the reverse signal line RX2-_a of the receiving channel; a resistor R2_a is connected between the 8th pin and the 7th pin of the bus driver module U3_a; Pin 5 and pin 6 of the bus signal receiving and transmitting crossover area J1 are respectively connected to pin 8 and pin 7 of the bus driver module U3_b, and a resistor R2_b is connected in parallel between pin 8 and pin 7 of the line driver module U3_b; pin 7 and pin 8 of the bus signal receiving and transmitting crossover area J1 are respectively connected to pin 5 and pin 6 of the bus driver module U3_b; pin 3 and pin 2 of the bus driver module U3_b are respectively connected to pin K6 and pin J6 of the FPGA_b module U1_b set in the second emergency backup control redundancy.

4. An emergency backup dual-redundancy broadband digital servo system as claimed in claim 2, characterized in that: The period of the first data interaction module is configured to be 12.5 ms; the period of the second data interaction module is configured to be 2.5 ms.

5. The emergency backup dual-redundancy broadband digital servo system according to claim 1, characterized in that: The dual-redundancy synchronization signal module includes a DSP_a module U4_a and a level conversion_a module U5_a arranged in the first emergency backup control redundancy, a synchronization signal crossing area J2, and a DSP_b module U4_b and a level conversion_b module U5_b arranged in the second emergency backup control redundancy; The L12 pin of the DSP_a module U4_a is connected to the 36 pin of the level conversion module U5_a, for receiving the synchronization signal in the second emergency backup control margin; the J12 pin of the DSP_a module U4_a is connected to the 47 pin of the level conversion module U5_a, for outputting the synchronization signal to the second emergency backup control margin; Pin 1 of the level conversion module U5_a is connected to +5V power supply, and pin 24 is grounded; pin 13 of the level conversion module U5_a is connected to pin 10 of the synchronization signal cross section J2, and pin 2 of the level conversion module U5_a is connected to pin 9 of the synchronization signal cross section J2; The L12 pin of the DSP_b module U4_b is connected to the 36 pin of the level conversion_b module U5_b, for receiving the synchronization signal in the first emergency backup control margin; The J12 pin of the DSP_b module U4_b is connected to the 47 pin of the level conversion_b module U5_b, and is used to output a synchronization signal to the first emergency backup control margin; The level conversion module U5_b has pin 1 connected to a +5V power supply and pin 24 connected to ground; Pin 13 of the level conversion module U5_b is connected to pin 9 of the synchronization signal crossing area J2, and pin 2 of the level conversion module U5_b is connected to pin 10 of the synchronization signal crossing area J2.

6. An emergency backup dual-redundancy broadband digital servo system as claimed in claim 5, characterized in that: The synchronization of the dual-redundancy synchronization signal module is divided into power-on initial synchronization and periodic synchronization. The maximum waiting time of the power-on initial synchronization is 500ms, the maximum waiting time of the periodic synchronization is 50μs, and the synchronization period is 12.5ms.

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