A bandgap reference circuit with an ultra-low power band start-up circuit suitable for high temperature conditions

Abstract

The application discloses a band-gap reference circuit with a starting circuit suitable for high-temperature conditions, comprising a control circuit module, a starting core circuit unit, a leakage compensation circuit unit and a band-gap reference circuit module; the control circuit module is used for establishing a starting identification signal based on an enable signal; the starting core circuit unit is used for providing a starting temporary current to the band-gap reference circuit module according to the starting identification signal, so that the band-gap reference circuit module gets rid of the degenerate electric state of zero current; the leakage compensation circuit unit is used for generating a corresponding mirror leakage current when there is a leakage situation in the starting core circuit unit, so as to maintain the balance state of the band-gap reference circuit module; and the band-gap reference circuit module is used for generating and outputting a reference voltage based on an input power supply and the starting identification signal. In the application, the starting core circuit unit and the leakage compensation circuit unit can guarantee that the ultra-low-power band-gap reference can be normally started at high temperature and good working performance is maintained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a bandgap reference circuit with an ultra-low-power starting circuit suitable for high-temperature conditions. BACKGROUND

[0002] A bandgap reference source is a chip internal reference voltage source that can generate a stable voltage independent of temperature changes and voltage fluctuations, and is widely used in ADC, DAC, LDO, etc. circuits to provide a reference voltage for comparison, thereby ensuring the high precision and stability of the overall circuit. In recent years, with the rise of wearable electronic devices, the demand for static power consumption of electronic systems is becoming higher and higher. As a core component of electronic systems, the bandgap reference also hopes to have low energy consumption while ensuring stability, so as to prolong the battery life of the device.

[0003] In a bandgap reference circuit, the circuit usually has two working states, the first being the normal working state, and the second being the state in which the circuit has no current. For the second case, a starting circuit needs to be added to help the circuit get out of the abnormal working state. The most common starting circuit is to make the circuit get out of the state of no current when the circuit is just started, and the starting circuit is usually turned off after the circuit has current and is working normally, so as to reduce the power consumption of the circuit. In the prior art, the starting circuit usually forms a current sink through a MOS transistor and is connected to the output terminal of the bandgap reference operational amplifier. By pulling down the output terminal of the operational amplifier, a temporary current is injected to start the circuit, and the transistor is turned off after the operational amplifier is started. Ideally, the transistor will not affect the core circuit of the bandgap reference after being turned off, and the output voltage of the bandgap reference operational amplifier is determined by the core circuit of the bandgap itself. However, in fact, the MOS transistor will have a picoampere level of leakage current at high temperature. This size of leakage current will not affect the performance of the circuit at high temperature for circuits with power consumption of microampere level and above, but for circuits with power consumption of nanoampere level, it will cause serious mismatch of the operational amplifier, gain reduction, etc., thereby affecting the output voltage or current of the bandgap reference, and further affecting the precision and stability of the bandgap reference source.

[0004] Therefore, it is urgent to design a starting circuit that can ensure the normal starting of an ultra-low-power bandgap reference at high temperature and maintain the performance, so as to meet the working requirements of the bandgap reference circuit. SUMMARY

[0005] The present application provides a bandgap reference circuit with an ultra-low-power starting circuit suitable for high-temperature conditions, which solves the technical problem that the existing starting circuit based on the bandgap reference circuit design cannot ensure the normal starting of an ultra-low-power bandgap reference at high temperature and maintain the good working performance of the bandgap reference.

[0006] The application provides a bandgap reference circuit with an ultra-low power consumption band starting circuit suitable for high-temperature conditions, comprising: a control circuit module, a starting circuit module and a bandgap reference circuit module; the starting circuit module is composed of a starting core circuit unit and a leakage compensation circuit unit;

[0007] The control circuit module is connected with the starting circuit module, and is used for establishing a starting identification signal of the starting core circuit unit based on an enable signal and sending the starting identification signal to the starting core circuit unit;

[0008] The starting core circuit unit is connected with the bandgap reference circuit module, and is used for providing a starting temporary current to the bandgap reference circuit module according to the starting identification signal, so that the bandgap reference circuit module is out of the degenerate state of zero current;

[0009] The leakage compensation circuit unit is connected with the starting circuit module and the bandgap reference circuit module respectively, and is used for generating a corresponding mirror leakage current when there is leakage in the starting core circuit unit, so as to maintain the balance state of the bandgap reference circuit module;

[0010] The bandgap reference circuit module is used for generating and outputting a reference voltage based on an input power supply and the starting identification signal.

[0011] Further, the starting core circuit unit is composed of a PMOS tube Mp2, an NMOS tube Mn1 and an NMOS tube Mn2;

[0012] The gate of the PMOS tube Mp2 is connected with the gate of the NMOS tube Mn1 and the first end of the bandgap reference circuit module respectively, the drain of the PMOS tube Mp2 is connected with the first end of the control circuit module, and the source of the PMOS tube Mp2 is connected with the second end of the control circuit module, the drain of the NMOS tube Mn1 and the gate of the NMOS tube Mn2 respectively;

[0013] The gate of the NMOS tube Mn1 is connected with the first end of the bandgap reference circuit module, the drain of the NMOS tube Mn1 is connected with the gate of the NMOS tube Mn2 and the second end of the control circuit module respectively, and the source of the NMOS tube Mn1 is grounded;

[0014] The gate of the NMOS tube Mn2 is connected with the second end of the control circuit module and the first end of the leakage compensation circuit unit respectively, the drain of the NMOS tube Mn2 is connected with the second end of the bandgap reference circuit module, and the source of the NMOS tube Mn2 is grounded.

[0015] Further, the leakage compensation circuit unit comprises an NMOS tube Mn3 and a resistor Res2;

[0016] The drain of the NMOS tube Mn3 is connected with one end of the resistor Res2, and the source of the NMOS tube Mn3 is grounded.

[0017] The other end of the resistor Res2 is connected with the third end of the bandgap reference circuit module.

[0018] Further, the first end of the leakage compensation circuit unit is specifically the gate of the NMOS tube Mn3.

[0019] Further, the control circuit module is composed of an inverter INV1, an inverter INV2, a PMOS tube Mp1 and an NMOS tube Mn4.

[0020] The input end of the inverter INV1 is connected with an enable signal, and the output end of the inverter INV1 is connected with the input end of the inverter INV2.

[0021] The gate of the PMOS tube Mp1 is connected with the output end of the inverter INV1, and the drain of the PMOS tube Mp1 is connected with an input power supply.

[0022] The gate of the NMOS tube Mn4 is connected with the output end of the inverter INV2, and the source of the NMOS tube Mn4 is grounded.

[0023] Further, the first end of the control circuit module is specifically the source of the PMOS tube Mp1, and the second end of the control circuit module is specifically the drain of the NMOS tube Mn4.

[0024] Further, the bandgap reference circuit module is composed of a PMOS tube Mp3, a PMOS tube Mp4, a PMOS tube Mp5, a PMOS tube Mp6, a resistor Res1, a bipolar transistor Bipolar1, a bipolar transistor Bipolar2 and an amplifier AMP.

[0025] The gate of the PMOS tube Mp3 is connected with the gate of the PMOS tube Mp4 and the first output end of the amplifier AMP respectively, the drain of the PMOS tube Mp3 is connected with an input power supply, and the source of the PMOS tube Mp3 is connected with the drain of the PMOS tube Mp5.

[0026] The gate of the PMOS tube Mp4 is connected with the first output end of the amplifier AMP, the drain of the PMOS tube Mp4 is connected with an input power supply, and the source of the PMOS tube Mp4 is connected with the drain of the PMOS tube Mp6.

[0027] The gate of the PMOS tube Mp5 is connected with the gate of the PMOS tube Mp6, and the source of the PMOS tube Mp5 is connected with the positive input end of the amplifier AMP and one end of the resistor Res1 respectively;

[0028] The source of the PMOS tube Mp6 is connected with the negative input end of the amplifier AMP, the base of the triode Bipolar2 and the collector of the triode Bipolar2 respectively.

[0029] One end of the resistor Res1 is connected with the positive input end of the amplifier AMP, and the other end of the resistor Res1 is connected with the base and the collector of the triode Bipolar1 respectively.

[0030] The emitter of the triode Bipolar1 is grounded.

[0031] The base of the triode Bipolar2 is connected with the collector of the triode Bipolar2 and the negative input end of the amplifier AMP respectively, and the emitter of the triode Bipolar2 is grounded.

[0032] Further, the first end of the bandgap reference circuit module is specifically the negative input end of the amplifier AMP, the second end of the bandgap reference circuit module is specifically the first output end of the amplifier AMP, and the third end of the bandgap reference circuit module is specifically the second output end of the amplifier AMP.

[0033] Further, the amplifier AMP is composed of an NMOS tube Man1, an NMOS tube Man2, an NMOS tube Man3, an NMOS tube Man4, an NMOS tube Man5, an NMOS tube Man6, an NMOS tube Man7, a PMOS tube Map1, a PMOS tube Map2, a PMOS tube Map3, a PMOS tube Map4 and a PMOS tube Map5.

[0034] Among them, the NMOS tube Man1 and the NMOS tube Man2 constitute an input pair of the amplifier AMP, the PMOS tube Map1 and the PMOS tube Map2 constitute a current mirror load of the amplifier AMP, and the NMOS tube Man4 and the PMOS tube Map5 constitute a mirror current branch of the current mirror load of the amplifier AMP.

[0035] Further, the first output end of the amplifier AMP is specifically the output end of the mirror current branch of the current mirror load, and the second output end of the amplifier AMP is specifically the output end of the current mirror load.

[0036] From the above technical solutions, it can be seen that the present application has the following advantages:

[0037] The application provides a band-gap reference circuit with an ultra-low-power starting circuit suitable for high-temperature conditions, which comprises a control circuit module, a starting circuit module and a band-gap reference circuit module; the starting circuit module is composed of a starting core circuit unit and a leakage compensation circuit unit;

[0038] The control circuit module is connected with the starting circuit module, and is used for establishing a starting identification signal of the starting core circuit unit based on an enable signal and sending the starting identification signal to the starting core circuit unit; the starting core circuit unit is connected with the band-gap reference circuit module, and is used for providing a starting temporary current to the band-gap reference circuit module according to the starting identification signal, so that the band-gap reference circuit module is out of the degenerate state of zero current; the leakage compensation circuit unit is connected with the starting circuit module and the band-gap reference circuit module respectively, and is used for generating a corresponding mirror leakage current when there is leakage in the starting core circuit unit, so as to maintain the balance state of the band-gap reference circuit module; and the band-gap reference circuit module is used for generating and outputting a reference voltage based on an input power supply and the starting identification signal.

[0039] In the application, the starting core circuit unit provides a temporary current for the band-gap reference circuit, avoids the band-gap reference circuit from falling into a deadlock state, and at the same time, when there is leakage in the starting core circuit unit, the leakage compensation circuit unit provides a mirror leakage current to the band-gap reference circuit module, so that the two output branches of the band-gap reference circuit module leak the same current, and the band-gap reference circuit module is still in a working balance state, thereby ensuring that the ultra-low-power band-gap reference can be normally started at high temperature and maintain good working performance, and the technical problem that the starting circuit based on the existing band-gap reference circuit design cannot ensure that the ultra-low-power band-gap reference is normally started at high temperature and maintains good working performance of the band-gap reference is solved. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0041] Figure 1 A module connection schematic diagram of the band-gap reference circuit with the ultra-low-power starting circuit suitable for high-temperature conditions is provided for the application;

[0042] Figure 2 A specific circuit connection schematic diagram of the band-gap reference circuit with the ultra-low-power starting circuit suitable for high-temperature conditions is provided for the application;

[0043] Figure 3The starting circuit and the ultra-low power band gap reference circuit diagram provided by the application do not consider the leakage of MOS tube;

[0044] Figure 4 The amplifier AMP circuit diagram of the band gap reference circuit module provided by the application. DETAILED DESCRIPTION

[0045] The embodiment of the application provides a band gap reference circuit of an ultra-low power band starting circuit suitable for high temperature conditions, and the technical problem that an existing starting circuit based on a band gap reference circuit design is difficult to ensure that an ultra-low power band gap reference is normally started under high temperature conditions and good working performance of the band gap reference is maintained.

[0046] In order to make the application purpose, features and advantages of the application more obvious and easy to understand, the technical solutions in the embodiments of the application will be clearly and completely described below in combination with the drawings in the embodiments of the application. Obviously, the following described embodiments are only a part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0047] In the description of the application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0048] Unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected, it can be mechanical connection, or electrical connection, it can be directly connected, or indirectly connected through intermediate medium, it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0049] Please refer to Figures 1-4 An embodiment of the band gap reference circuit of the ultra-low power band starting circuit suitable for high temperature conditions provided by the application comprises: a control circuit module, a starting circuit module and a band gap reference circuit module; the starting circuit module is composed of a starting core circuit unit and a leakage compensation circuit (leakage elimination circuit) unit;

[0050] The control circuit module is connected with the starting circuit module, and is used for establishing a starting identification signal of the starting core circuit unit based on the enable signal Ven and sending the starting identification signal to the starting core circuit unit;

[0051] The starting core circuit unit is connected with the band gap reference circuit module, and is used for providing a starting temporary current to the band gap reference circuit module according to the starting identification signal, so that the band gap reference circuit module is out of the degenerate state of zero current;

[0052] The leakage compensation circuit unit is connected with the starting circuit module and the band gap reference circuit module respectively, and is used for generating a corresponding mirror leakage current when there is a leakage in the starting core circuit unit, so as to maintain the balance state of the band gap reference circuit module;

[0053] The band gap reference circuit module is used for generating and outputting a reference voltage based on the input power supply voltage Vdd and the starting identification signal.

[0054] Specifically, when the enable signal Ven is low, the starting identification signal is a non-starting signal, and the starting core circuit unit will not provide a starting temporary current to the band gap reference circuit module, at this time, the band gap reference circuit module is in a non-working state; and when the enable signal is high, the starting identification signal is a starting signal, and the starting core circuit unit will provide a starting temporary current to the band gap reference circuit module, so that the band gap reference circuit module is out of the degenerate state of zero current, at this time, the band gap reference circuit module is in a working state, thereby outputting a reference voltage;

[0055] When the band gap reference circuit module is working, the starting core circuit unit will extract a little current from the band gap reference circuit module to form a leakage current, which will seriously affect the performance of the band gap reference under high temperature conditions; the leakage compensation circuit unit is arranged between the starting core circuit unit and the band gap reference circuit module to generate a corresponding mirror leakage current, so that the band gap reference circuit module is still in a balanced state and will not cause imbalance of its work, thereby ensuring that the band gap reference circuit module is still in a good working state and ensuring the working performance of the band gap reference circuit module under high temperature conditions.

[0056] Please refer to Figure 1 , Figure 2 and Figure 4 , the following further describes the specific circuit structure of the band gap reference circuit of the ultra-low power consumption band starting circuit provided by the application.

[0057] The control circuit module is composed of an inverter INV1, an inverter INV2, a PMOS tube Mp1 and an NMOS tube Mn4; an input end of the inverter INV1 is connected to the enable signal, an output end of the inverter INV1 is connected to an input end of the inverter INV2; a gate of the PMOS tube Mp1 is connected to the output end of the inverter INV1, a drain of the PMOS tube Mp1 is connected to the input power supply Vdd; a gate of the NMOS tube Mn4 is connected to an output end of the inverter INV2, a source of the NMOS tube Mn4 is grounded. The first end of the control circuit module is specifically a source of the PMOS tube Mp1, and the second end of the control circuit module is specifically a drain of the NMOS tube Mn4.

[0058] It can be understood that when the enable signal Ven is low, the output signal Ven_B of the inverter INV1 is high, and the output signal Ven_S of the inverter INV2 is low, thereby establishing the start signal; on the contrary, when the enable signal Ven is high, the output signal Ven_B of the inverter INV1 is low, and the output signal Ven_S of the inverter INV2 is high, thereby establishing the non-start signal, and finally the control circuit module delivers the start identification signal to the start core circuit unit through Mp1 and Mn4 according to the enable signal.

[0059] Further, the start core circuit unit is composed of a PMOS tube Mp2, an NMOS tube Mn1 and an NMOS tube Mn2; a gate of the PMOS tube Mp2 is connected to a gate of the NMOS tube Mn1 and the first end of the bandgap reference circuit module, a drain of the PMOS tube Mp2 is connected to the first end of the control circuit module, a source of the PMOS tube Mp2 is connected to the second end of the control circuit module, a drain of the NMOS tube Mn1 and a gate of the NMOS tube Mn2; the gate of the NMOS tube Mn1 is connected to the first end of the bandgap reference circuit module, the drain of the NMOS tube Mn1 is connected to the gate of the NMOS tube Mn2 and the second end of the control circuit module, and the source of the NMOS tube Mn1 is grounded; the gate of the NMOS tube Mn2 is connected to the second end of the control circuit module, the drain of the NMOS tube Mn2 is connected to the second end of the bandgap reference circuit module, and the source of the NMOS tube Mn2 is grounded.

[0060] The start core circuit unit adjusts the working state of the transistor in the start core circuit unit according to the start identification signal output by the first end and the second end of the control circuit module; when the start identification signal is the non-start signal, the transistors in the start core circuit unit are all in the off state; when the start identification signal is the start signal, the transistor Mn2 in the start core circuit unit is turned on, thereby providing a temporary current to the second end of the bandgap reference circuit module, so that the bandgap reference circuit module gets rid of the degenerate point of zero current.

[0061] Further, the bandgap reference circuit module is composed of a PMOS transistor Mp3, a PMOS transistor Mp4, a PMOS transistor Mp5, a PMOS transistor Mp6, a resistor Res1, a bipolar transistor Bipolar1, a bipolar transistor Bipolar2 and an amplifier AMP;

[0062] The gate of the PMOS transistor Mp3 is connected to the gate of the PMOS transistor Mp4 and the first output terminal of the amplifier AMP respectively, the drain of the PMOS transistor Mp3 is connected to an input power supply Vdd, and the source of the PMOS transistor Mp3 is connected to the drain of the PMOS transistor Mp5; the gate of the PMOS transistor Mp4 is connected to the first output terminal of the amplifier AMP, the drain of the PMOS transistor Mp4 is connected to the input power supply Vdd, and the source of the PMOS transistor Mp4 is connected to the drain of the PMOS transistor Mp6; the gate of the PMOS transistor Mp5 is connected to the gate of the PMOS transistor Mp6, and the source of the PMOS transistor Mp5 is connected to the positive input terminal of the amplifier AMP and one end of the resistor Res1 respectively; the source of the PMOS transistor Mp6 is connected to the negative input terminal of the amplifier AMP, the base of the bipolar transistor Bipolar2 and the collector of the bipolar transistor Bipolar2 respectively; one end of the resistor Res1 is connected to the positive input terminal of the amplifier AMP, and the other end of the resistor Res1 is connected to the base and the collector of the bipolar transistor Bipolar1 respectively; the emitter of the bipolar transistor Bipolar1 is grounded; the base of the bipolar transistor Bipolar2 is connected to the collector of the bipolar transistor Bipolar2 and the negative input terminal of the amplifier AMP respectively, and the emitter of the bipolar transistor Bipolar2 is grounded.

[0063] The first terminal of the bandgap reference circuit module is specifically the negative input terminal of the amplifier AMP, the second terminal of the bandgap reference circuit module is specifically the first output terminal of the amplifier AMP, and the third terminal of the bandgap reference circuit module is specifically the second output terminal of the amplifier AMP.

[0064] Please refer to Figure 4 The amplifier AMP is composed of an NMOS transistor Man1, an NMOS transistor Man2, an NMOS transistor Man3, an NMOS transistor Man4, an NMOS transistor Man5, an NMOS transistor Man6, an NMOS transistor Man7, a PMOS transistor Map1, a PMOS transistor Map2, a PMOS transistor Map3, a PMOS transistor Map4 and a PMOS transistor Map5; wherein the NMOS transistor Man1 and the NMOS transistor Man2 form an input pair of the amplifier AMP, the PMOS transistor Map1 and the PMOS transistor Map2 form a current mirror load of the amplifier AMP, and the NMOS transistor Man4 and the PMOS transistor Map5 form a mirror current branch of the current mirror load of the amplifier AMP. Specifically, the first output terminal of the amplifier AMP is an output terminal (i.e. a node B) of the mirror current branch, and the second output terminal of the amplifier AMP is an output terminal (i.e. a node C) of the current mirror load. Figure 4In the figure, Vin+ represents the input signal of the positive input terminal of the amplifier AMP, and Vin- represents the input signal of the negative input terminal of the amplifier AMP.

[0065] Please refer to Figure 2 and Figure 4 The working principle of the start-up core circuit module is as follows:

[0066] 1) When the enable signal Ven is low, the output signal Ven_B of the inverter INV1 is high, and the output signal Ven_S of the inverter INV2 is low. At this time, the gate voltage of the PMOS transistor Mp1 is high, and the PMOS transistor Mp1 is in the closed state, that is, there is no current flowing through the branch where the PMOS transistor Mp1 is located, and the PMOS transistor Mp2 is in the closed state. The gate voltage of the NMOS transistor Mn4 is high, and the NMOS transistor Mn4 is in the on state, but it pulls down the gate voltages of the NMOS transistors Mn2 and Mn3. At this time, the transistors Mn2 and Mn3 are in the closed state.

[0067] At the same time, when the enable signal Ven is low, in the amplifier AMP of the bandgap reference circuit module, the first voltage signal EN_B is low, and the second voltage signal EN_S is high. Then the gate voltages of the NMOS transistors Man5, Man6 and Man7 are high, and the gate voltages of the PMOS transistors Map3 and Map4 are low. At this time, the switch transistors Map3, Map4, Man5, Man6 and Man7 in the amplifier AMP are in the on state, and the entire amplifier AMP does not work at this time, and the output voltage of the first output terminal (i.e. node B) of the amplifier AMP is pulled to the input power supply voltage Vdd by the switch transistor Map4. Therefore, the entire bandgap reference circuit module is in the non-working state.

[0068] 2) When the enable signal Ven is high, the output signal Ven_B of the inverter INV1 is low, and the output signal Ven_S of the inverter INV2 is high. At this time, except for the PMOS transistor Mp2, the remaining switch transistors of the start-up core circuit module are in the closed state.

[0069] When the enable signal is high, PMOS transistor Mp2 is turned on. If the bandgap reference circuit module is in an abnormal working state at this time, i.e. the bandgap reference circuit is locked in the degenerate point state of zero current, the current of the bandgap reference circuit module is 0, the transistor Bipolar2 is not turned on, the gate voltages of PMOS transistor Mp2 and NMOS transistor Mn1 are detected as low, and then the drain-source voltage of PMOS transistor Mp2 (which is also the gate voltage of NMOS transistor Mn2, i.e. the voltage of node A) is pulled high, so that NMOS transistor Mn2 is turned on. After NMOS transistor Mn2 is turned on, the drain-source voltage of NMOS transistor Mn2 (which is also the gate voltage of PMOS transistors MP3 and MP4) is pulled low, so that PMOS transistors Mp3 and Mp4 are turned on, and the bandgap reference circuit module starts to have a temporary current, thereby getting rid of the degenerate point of zero current. After the bandgap reference circuit module is started slowly, the transistor Bipolar2 is turned on, and the gate voltages of PMOS transistor Mp2 and NMOS transistor Mn1 are high. The pull-down capability of NMOS transistor Mn1 is designed to be stronger than the pull-up capability of PMOS transistor Mp2, so that when NMOS transistor Mn1 is turned on, the gate voltage of NMOS transistor Mn2 is pulled low, and then NMOS transistor Mn2 does not work. Therefore, the starting core circuit unit does not affect the bandgap reference circuit module, and the bandgap reference circuit module can work in a normal state due to the existence of the starting core circuit unit.

[0070] Based on Figure 2 and Figure 4 It can be seen that the key transistor of the bandgap reference circuit module having a temporary current is Mn2, the gate of which is connected to the output end of an inverter composed of Mp2 and Mn1, and the drain of which is connected to the first output end of the amplifier AMP in the bandgap reference circuit module. After NMOS transistor Mn2 is turned on, PMOS transistors Mp3 and Mp4 in the bandgap reference circuit module are turned on, so that the bandgap reference circuit module starts to have a temporary current.

[0071] Therefore, the starting core circuit module provided by the present application can ensure that the bandgap reference circuit can get rid of the degenerate point working state of zero current when the enable signal is high, and is suitable for the design of an ultra-low power consumption bandgap reference circuit. Meanwhile, the starting core circuit module of the present application has small design difficulty and extremely small power consumption, which meets the needs of the design of an ultra-low power consumption bandgap reference circuit.

[0072] In order to further illustrate the technical effect that the bandgap reference circuit of the ultra-low power consumption band starting circuit suitable for high-temperature conditions provided by the present application can also maintain good working performance under high-temperature conditions, please refer to Figure 3 , Figure 3 The figure shows the starting circuit and the ultra-low power consumption bandgap reference circuit designed by the present application without considering the leakage of MOS transistors.

[0073] Figure 3 The circuit also consists of a control circuit module, a startup core circuit unit, and a bandgap reference circuit module. The control circuit module consists of inverters INV1 and INV2, PMOS transistor Mp1, and NMOS transistor Mn4. The startup core circuit unit consists of PMOS transistors Mp2, NMOS transistors Mn1, and NMOS transistor Mn2. The bandgap reference circuit module consists of PMOS transistors Mp3, Mp4, Mp5, and Mp6, resistor Res1, transistors Bipolar1 and Bipolar2, and amplifier AMP.

[0074] exist Figure 3 In the bandgap reference circuit module, when the bandgap reference circuit module is working normally, the gate voltage of NMOS transistor Mn2 is low. Ideally, the drain current flowing through it should be zero. However, due to the existence of leakage current, NMOS transistor Mn2 will draw a small amount of current from amplifier AMP. This current may be in the pA range. For a bandgap reference circuit design with power consumption in the nA range, it is not negligible and may affect the working performance of the bandgap reference circuit. That is, the circuit of amplifier AMP will suffer from severe mismatch due to this leakage current, thereby reducing the working gain and output accuracy of the bandgap reference circuit.

[0075] Based on this, the present invention designs a corresponding leakage current compensation circuit unit to eliminate or compensate for the impact of this leakage current. Please refer to [link / reference]. Figure 1 The leakage current compensation circuit unit includes an NMOS transistor Mn3 and a resistor Res2. The drain of NMOS transistor Mn3 is connected to one end of resistor Res2, and the source of NMOS transistor Mn3 is grounded. The other end of resistor Res2 is connected to the third terminal of the bandgap reference circuit module. Specifically, the first terminal of the leakage current compensation circuit unit is the gate of NMOS transistor Mn3, and the gate of NMOS transistor Mn3 is connected to the gate of Mn2. Furthermore, transistors Mn2 and Mn3 need to use the same size structure during the design process.

[0076] Therefore, when the NMOS transistor Mn2 of the starting core circuit unit exists a leakage current, the NMOS transistor Mn3 of the leakage compensation circuit unit synchronously generates a mirror leakage current existing in the NMOS transistor Mn2, the branch of the transistor Mn2 of the starting core circuit unit is connected with the branch of the output end of the amplifier AMP (i.e. the branch where the node B is located), and the branch of the transistor Mn3 of the leakage compensation circuit unit is connected with the mirror output branch of the amplifier (i.e. the branch where the node C is located), so that, even if the transistor of the starting core circuit unit exists a leakage phenomenon, the amplifier AMP is still in a balanced state due to the same current leakage of the two branches (i.e. the branches where the nodes B and C are located) of the amplifier AMP, and the unbalance of the amplifier AMP is not caused, so that the good working performance of the ultra-low power bandgap reference circuit at high temperature is ensured, and the problem that the circuit performance of the ultra-low power bandgap reference circuit is affected due to the leakage of the MOS transistor at high temperature is avoided.

[0077] In the leakage compensation circuit unit of the application, the main function of the transistor Mn3 is to mirror the leakage current, and the function of the large resistor Res1 is to provide a temporary current of the bandgap reference core circuit module when the bandgap reference core circuit module is just started, which is still determined by the Mn2 of the starting core circuit unit, if the two currents simultaneously pull down the voltage between the two ends of the amplifier AMP, the circuit may be oscillated when it is just started, at this time, the voltage at the first output end of the amplifier AMP is pulled down earlier than the output voltage at the mirror end due to the existence of the large resistor of the leakage compensation circuit unit when the circuit is just started.

[0078] The bandgap reference circuit of the ultra-low power band starting circuit suitable for high temperature conditions has the following advantages:

[0079] 1. The starting core circuit adopts a low-power design and has low design difficulty, the MOS transistor of the starting core circuit provides a temporary current for the bandgap reference circuit, avoids the bandgap reference circuit from being in a deadlock state, and meets the starting requirement of the ultra-low power bandgap reference.

[0080] 2. When the transistor of the starting core circuit unit exists a leakage phenomenon, the leakage compensation circuit unit provides a mirror leakage current for the bandgap reference circuit module, the two output branches of the amplifier of the bandgap reference circuit module simultaneously leak the same current, the bandgap reference circuit module is still in a working balanced state, so that the ultra-low power bandgap reference can be normally started at high temperature, and the existence of the leakage compensation circuit unit does not affect the related performance of the bandgap reference, so that the bandgap reference keeps good working performance.

[0081] The above-described and above-embodied examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or some technical features therein can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A bandgap reference circuit with an ultra-low power consumption and a startup circuit suitable for high-temperature conditions, characterized in that, include: Control circuit module, startup circuit module, and bandgap reference circuit module; The startup circuit module consists of a startup core circuit unit and a leakage current compensation circuit unit. The control circuit module is connected to the startup circuit module and is used to establish a startup identifier signal for the startup core circuit unit based on the enable signal, and send the startup identifier signal to the startup core circuit unit. The startup core circuit unit is connected to the bandgap reference circuit module and is used to provide a startup temporary current to the bandgap reference circuit module according to the startup identification signal, so that the bandgap reference circuit module gets rid of the zero-current degenerate electrical state. The leakage current compensation circuit unit is connected to the startup circuit module and the bandgap reference circuit module respectively. It is used to generate a corresponding mirror leakage current when there is leakage in the startup core circuit unit, thereby maintaining the balance state of the bandgap reference circuit module. The bandgap reference circuit module is used to generate and output a reference voltage based on the input power supply and the start-up flag signal; The startup core circuit unit is composed of PMOS transistor Mp2, NMOS transistor Mn1 and NMOS transistor Mn2; The gate of the PMOS transistor Mp2 is connected to the gate of the NMOS transistor Mn1 and the first terminal of the bandgap reference circuit module, respectively. The drain of the PMOS transistor Mp2 is connected to the first terminal of the control circuit module, and the source of the PMOS transistor Mp2 is connected to the second terminal of the control circuit module, the drain of the NMOS transistor Mn1, and the gate of the NMOS transistor Mn2, respectively. The gate of the NMOS transistor Mn1 is connected to the first terminal of the bandgap reference circuit module, the drain of the NMOS transistor Mn1 is connected to the gate of the NMOS transistor Mn2 and the second terminal of the control circuit module, and the source of the NMOS transistor Mn1 is grounded. The gate of the NMOS transistor Mn2 is connected to the second terminal of the control circuit module and the first terminal of the leakage compensation circuit unit, respectively. The drain of the NMOS transistor Mn2 is connected to the second terminal of the bandgap reference circuit module, and the source of the NMOS transistor Mn2 is grounded. The leakage current compensation circuit unit includes an NMOS transistor Mn3 and a resistor Res2; The drain of the NMOS transistor Mn3 is connected to one end of the resistor Res2, and the source of the NMOS transistor Mn3 is grounded. The other end of the resistor Res2 is connected to the third end of the bandgap reference circuit module.

2. The ultra-low power bandgap reference circuit with startup circuit according to claim 1, characterized in that, The first terminal of the leakage current compensation circuit unit is specifically the gate of the NMOS transistor Mn3.

3. The ultra-low power bandgap reference circuit with startup circuit according to claim 1, characterized in that, The control circuit module consists of inverter INV1, inverter INV2, PMOS transistor Mp1, and NMOS transistor Mn4. An enable signal is connected to the input of inverter INV1, and the output of inverter INV1 is connected to the input of inverter INV2. The gate of the PMOS transistor Mp1 is connected to the output terminal of the inverter INV1, and the drain of the PMOS transistor Mp1 is connected to the input power supply. The gate of the NMOS transistor Mn4 is connected to the output terminal of the inverter INV2, and the source of the NMOS transistor Mn4 is grounded.

4. The ultra-low power bandgap reference circuit with startup circuit according to claim 3, characterized in that, The first terminal of the control circuit module is specifically the source of the PMOS transistor Mp1, and the second terminal of the control circuit module is specifically the drain of the NMOS transistor Mn4.

5. The ultra-low power bandgap reference circuit with startup circuit according to claim 2, characterized in that, The bandgap reference circuit module consists of PMOS transistors Mp3, Mp4, Mp5, and Mp6, resistor Res1, transistors Bipolar1 and Bipolar2, and amplifier AMP. The gate of the PMOS transistor Mp3 is connected to the gate of the PMOS transistor Mp4 and the first output terminal of the amplifier AMP, respectively. The drain of the PMOS transistor Mp3 is connected to the input power supply, and the source of the PMOS transistor Mp3 is connected to the drain of the PMOS transistor Mp5. The gate of the PMOS transistor Mp4 is connected to the first output terminal of the amplifier AMP, the drain of the PMOS transistor Mp4 is connected to the input power supply, and the source of the PMOS transistor Mp4 is connected to the drain of the PMOS transistor Mp6. The gate of the PMOS transistor Mp5 is connected to the gate of the PMOS transistor Mp6, and the source of the PMOS transistor Mp5 is connected to the positive input terminal of the amplifier AMP and one end of the resistor Res1, respectively. The source of the PMOS transistor Mp6 is connected to the inverting input terminal of the amplifier AMP, the base of the bipolar transistor 2, and the collector, respectively. One end of the resistor Res1 is connected to the positive input terminal of the amplifier AMP, and the other end of the resistor Res1 is connected to the base and collector of the transistor Bipolar1 respectively. The emitter of the bipolar transistor 1 is grounded; The base of the transistor Bipolar2 is connected to its collector and the inverting input of the amplifier AMP, respectively, and the emitter of the transistor Bipolar2 is grounded.

6. The ultra-low power bandgap reference circuit with startup circuit according to claim 5, characterized in that, The first terminal of the bandgap reference circuit module is specifically the inverting input terminal of the amplifier AMP, the second terminal of the bandgap reference circuit module is specifically the first output terminal of the amplifier AMP, and the third terminal of the bandgap reference circuit module is specifically the second output terminal of the amplifier AMP.

7. The ultra-low power bandgap reference circuit with startup circuit according to claim 6, characterized in that, The amplifier AMP consists of NMOS transistors Man1, Man2, Man3, Man4, Man5, Man6, and Man7, and PMOS transistors Map1, Map2, Map3, Map4, and Map5. Among them, NMOS transistors Man1 and Man2 form the input pair of amplifier AMP, PMOS transistors Map1 and Map2 form the current mirror load of amplifier AMP, and NMOS transistors Man4 and Map5 form the current mirror load of amplifier AMP to mirror the current branch.

8. The ultra-low power bandgap reference circuit with startup circuit according to claim 7, characterized in that, The first output terminal of the amplifier AMP is specifically the output terminal of the current mirror load mirror current branch; the second output terminal of the amplifier AMP is specifically the output terminal of the current mirror load.

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