A fast ca train method for LPDDR5

Abstract

The present invention provides a fast CA training method for LPDDR5. The method comprises: sending three sets of data to a CA in Command Bus Training Mode and receiving return results from the DQ signal lines; determining the relationship between each bit in the CA signal and the clock signal based on the received results; and adjusting the delay of the CA signal based on the relationship between each bit in the CA signal and the clock signal. By continuously sending three sets of data and using the return values to determine the positional relationship between the CA signal and the clock signal, the present invention determines whether left or right shifting is required when finding the left and right boundaries of each bit in the CA signal, thereby reducing time consumption. By using left or right shift control signals, different positional relationships are classified as the same, simplifying the process.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fast CAP train method for LPDDR5. Background Art

[0002] When the control signal (ca), chip select signal (cs), and clock signal (ck) are transmitted between the physical layer (phy) and the storage particles, due to the existence of delay errors and the different delays between them, the clock signal (ck) may not be able to sample the correct control signal (ca), thus affecting normal operation. The impact of delay is more obvious at high speeds. Ideally, the positional relationship of the control signal (ca), chip select signal (cs), and clock signal (ck) received by the particle is as follows: Figure 2 As shown in the figure, the rising and falling edges of the clock signal (ck) are aligned with the middle of the control signal (ca) edge. This ensures that the clock signal (ck) samples the correct and stable control signal (ca). However, in actual applications, the transmission of signals in the line will inevitably cause delays. When there is a delay, the position relationship between the clock signal (ck) and the control signal (ca) may be as follows when it reaches the particle: Figure 3 As shown, the edge of the clock signal (ck) coincides with the edge of the control signal (ca), causing the clock signal (ck) to sample unstable data. Furthermore, because the control signal (ca) consists of seven bits, each with its own routing and varying delays, the clock signal (ck) can sample erroneous data. At high speeds, the edge width of the control signal (ca) and the period of the clock signal (ck) are shorter, making the impact of these varying delays even greater. Delays introduced by these routings and other external factors are unavoidable and unpredictable. To mitigate these delays, additional controllable delays, ca_delay[i] (i ranges from 0 to 6) and ck_delay, are added before the signal reaches the particle. Finding the optimal values for ca_delay[i] and ck_delay is called ca training. Without ca training, there's no guarantee that the particle will receive the correct command.

[0003] Current technology for finding the left and right boundaries of the control signal (ca) relies on iterating through combinations of ca_delay[i] and ck_delay values. This lacks knowledge of the positional relationship between the control signal (ca) and the clock signal (ck), making it difficult to determine whether the control signal (ca) needs to be shifted left or right relative to the clock signal (ck), resulting in a significant time consumption. Furthermore, the control signal (ca) consists of seven bits, and the positions of different bits vary. Therefore, each bit of the control signal (ca) may need to be shifted left or right. The adjustable range between ca_delay and ck_delay is limited, making it difficult to find the boundary. Furthermore, ck_delay is closely related to the chip select signal (cs) and cannot be adjusted arbitrarily, further complicating training. Summary of the Invention

[0004] The purpose of this invention is to provide a fast ca train method for LPDDR5. This method sends three sets of commands to the particles. The rising or falling edge of the clock signal will sample the CA and feedback the result through the DQ. The return value is used to determine the positional relationship between the control signal and the clock signal, so as to determine whether to shift left or right when finding the left and right boundaries of each bit of the control signal, thereby reducing the time spent. After determining the positional relationship, different positional relationships can be classified as the same by shifting the control signal left or right ( Figure 6 , Figure 7 The location situation is classified as Figure 5 ), thus simplifying the process. When the positional relationship between the control signal and the clock signal is poor, and the conditions for finding both the left and right boundaries cannot be met, the positional relationship can be used to determine which boundary can be found and the other can be discarded, reducing unnecessary work.

[0005] A method for fast ca train for LPDDR5, comprising:

[0006] Send three sets of data to the CA of the Command Bus Training Mode particle and receive the return results of the DQ signal line respectively;

[0007] Determine the relationship between each bit in the CA signal and the clock signal based on the received results;

[0008] The delay of the CA signal is adjusted according to the relationship between each bit in the CA signal and the clock signal.

[0009] Preferably, the sending of three sets of data to the CA of the Command Bus Training Mode particle and receiving return results from the DQ signal lines respectively include:

[0010] After the first data: 0, 7f, 0, 7f, is sent out and the data receiving end receives the corresponding result, the second data: 0, 0, 7f, 0 is sent;

[0011] After the second data is sent out and the data receiving end receives the corresponding result, the third data is sent: 7f, 0, 7f, 7f.

[0012] Preferably, determining the relationship between each bit in the CA signal and the clock signal according to the received result includes:

[0013] If the received result is 0, 1, 1, it means that the rising edge of the clock signal is in the middle of the control signal;

[0014] If the received result is 1, 0, 0, it means that the rising edge of the clock signal is to the left of the left boundary of the control signal;

[0015] If the received result is 1, 0, 1, it means that the rising edge of the clock signal is to the right of the right boundary of the control signal.

[0016] Preferably, adjusting the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal includes:

[0017] The delay of the control signal is pre-adjusted so that the rising edge of the clock signal is in the middle of the control signal;

[0018] Coarsely adjust the delay of the control signal to quickly find the approximate position of the control signal boundary

[0019] Fine-tune the delay of the control signal to find the precise position boundary of the control signal

[0020] Preferably, the delay of the pre-adjusted control signal so that the rising edge of the clock signal is exactly in the middle of the control signal comprises:

[0021] When it is detected that the rising edge of the clock signal is to the right of the right boundary of the control signal, the control signal is shifted right by half a clock cycle;

[0022] When it is detected that the rising edge of the clock signal is to the left of the left boundary of the control signal, the control signal is shifted left by half a clock cycle.

[0023] Preferably, the delay of the control signal to find the left boundary of the control signal includes:

[0024] Increase the value of the control signal delay to shift the control signal to the right and find the left boundary;

[0025] Each time the control signal delay value is changed, data is sent until the value at the data receiving end changes from 1 to 0;

[0026] When the value of a bit at the data receiving end changes from 1 to 0, it means that the left boundary of the control signal of this bit has been found;

[0027] Stop increasing the delay value of the corresponding control signal, and continue to increase the delay value of the control signal for the bit where no jump occurs, until the control signals of all bits find the left boundary.

[0028] Preferably, the delay of the control signal to find the right boundary of the control signal includes:

[0029] Increase the control signal delay value to shift the control signal to the left and find the right boundary;

[0030] Each time the control signal delay value is changed, it is sent once until the value at the data receiving end changes from 1 to 0;

[0031] When the value of a bit at the data receiving end changes from 1 to 0, it means that the right boundary of the control signal of this bit has been found;

[0032] Reduce the control signal delay value until all bits transition.

[0033] Preferably, it also includes:

[0034] First, use a larger step size a to roughly adjust the control signal delay, and then use a smaller step size b to fine-tune the control signal delay;

[0035] If a jump occurs after adding n*a, the control signal is delayed back to (dly_init+(n-1)*a);

[0036] Use a step size b that is smaller than a for adjustment. If a jump occurs after adding m*b, the control signal delay for finding the left boundary is (initial delay + (n-1)*a + m*b).

[0037] A system for fast CA train for LPDDR5, comprising:

[0038] The data sending module is used to send three sets of data to the CA of the Command Bus Training Mode particle and receive the return results of the DQ signal line respectively;

[0039] The data receiving module is used to determine the relationship between each bit in the CA signal and the clock signal based on the received results;

[0040] The data processing module is used to adjust the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal.

[0041] An electronic device comprises: a chip, a processor and a memory, wherein the memory is used to store computer program code, the computer program code comprises computer instructions, and when the chip executes the computer instructions, the electronic device executes a method for fast ca train of LPDDR5.

[0042] The beneficial effects of the present invention are: 1. The present invention determines the positional relationship between the control signal and the clock signal through the return value, thereby determining whether left shift or right shift is required when finding the left and right boundaries of each bit of ca, reducing time spent, clarifying the adjustment direction, saving simulation time, and improving work efficiency; 2. The present invention combines coarse adjustment and fine adjustment, which can not only reduce the number of adjustments and save time, but also ensure the adjustment accuracy and improve accuracy; 3. The present invention adjusts the control signal bit by bit to ensure that the control signal has the largest edge width and improves stability; 4. The present invention has strong flexibility, and various positional relationships between the bits of the control signal and various positional relationships between the control signal and the clock signal can be flexibly handled. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0045] Figure 1 A flow chart of a method for fast ca train for LPDDR5 of the present invention;

[0046] Figure 2 This is a schematic diagram of the clock signal sampling control signal under ideal conditions of the present invention;

[0047] Figure 3 Schematic diagram of the clock signal sampling control signal in the actual situation of the present invention;

[0048] Figure 4 This is a schematic diagram of sending three sets of data to particles according to the present invention;

[0049] Figure 5 This is a schematic diagram of the rising edge of the clock signal of the present invention being in the middle of the control signal;

[0050] Figure 6 This is a schematic diagram of the rising edge of the clock signal of the present invention approaching the right boundary of the control signal;

[0051] Figure 7 Schematic diagram of the rising edge of the clock signal of the present invention approaching the left boundary of the control signal;

[0052] Figure 8 Schematic diagram of the positional relationship among the clock signal, chip select signal and control signal of the present invention;

[0053] Figure 9 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0054] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0055] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0056] In addition, the descriptions of "first", "second", etc. in the present invention are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0057] Current technology for finding the left and right boundaries of the control signal (ca) relies on iterating through combinations of ca_delay[i] and ck_delay values. This lacks knowledge of the positional relationship between the control signal (ca) and the clock signal (ck), making it difficult to determine whether the control signal (ca) needs to be shifted left or right relative to the clock signal (ck), resulting in a significant time consumption. Furthermore, the control signal (ca) consists of seven bits, and the positions of different bits vary. Therefore, each bit of the control signal (ca) may need to be shifted left or right. The adjustable range between ca_delay and ck_delay is limited, making it difficult to find the boundary. Furthermore, ck_delay is closely related to the chip select signal (cs) and cannot be adjusted arbitrarily, further complicating training.

[0058] The present invention determines the positional relationship between the control signal and the clock signal through the return value, thereby determining whether left shift or right shift is required when finding the left and right boundaries of each bit of CA, reducing time spent, clarifying the adjustment direction, saving simulation time, and improving work efficiency; the present invention combines coarse adjustment and fine adjustment, which can not only reduce the number of adjustments and save time, but also ensure adjustment precision and improve accuracy; the present invention adjusts the control signal bit by bit to ensure that the control signal has the maximum edge width and improves stability; the present invention has strong flexibility and can flexibly handle various positional relationships between the bits of the control signal and various positional relationships between the control signal and the clock signal.

[0059] Example 1

[0060] A fast ca train method for lpddr5, reference Figure 1 ,include:

[0061] S100, sends three sets of data to the CA of the Command Bus Training Mode particle and receives the return results of the DQ signal line respectively;

[0062] The physical layer (Phy) is the lowest layer in the OSI model of computer networks, primarily responsible for providing the physical connection and transmission media for data transmission. The physical layer specifies the mechanical, electrical, functional, and regulatory characteristics required to establish, maintain, and dismantle physical links, ensuring that raw data can be transmitted across various physical media. The physical layer provides a reliable transmission environment for data communication between devices, shielding against differences in physical devices and transmission media. This allows the upper-level data link layer to focus solely on its protocols and services, without having to consider the specific transmission media.

[0063] Storage particles usually refer to memory particles, primarily used in dynamic random access memory (DRAM). Memory particles are composed of millions of capacitors and transistors and are used to store data. These particles are packaged together to form memory particles, which are an important component of computer memory.

[0064] In the embodiment of the present invention, the physical layer sends three different groups of data to the storage particles, and then the data receiving end receives feedback results for determining the positional relationship between the control signal and the clock signal.

[0065] S200, determining the relationship between each bit in the CA signal and the clock signal based on the received result;

[0066] The received results generally fall into three categories, corresponding to the positional relationships between the three control signals and the clock signal. The present invention can quickly and accurately determine the positional relationship between the control signal and the clock signal based on the received results.

[0067] S300 , adjusting the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal.

[0068] With the positional relationship between the control signal and the clock signal, we can proceed to the next step, which is to adjust the control signal delay so that the middle of the control signal edge is aligned with the rising edge or falling edge of the clock signal.

[0069] Preferably, S100, sending three sets of data to the CA of the Command Bus Training Mode particle and receiving return results from the DQ signal lines respectively include:

[0070] After the first data: 0, 7f, 0, 7f, is sent out and the data receiving end receives the corresponding result, the second data: 0, 0, 7f, 0 is sent;

[0071] After the second data is sent out and the data receiving end receives the corresponding result, the third data is sent: 7f, 0, 7f, 7f.

[0072] In the embodiment of the present invention, specifically, a first set of data is sent to the particle CA, and the data receiving end receives the corresponding result;

[0073] sending a second line pattern;

[0074] After the second line pattern is sent out and the data receiving end receives the corresponding result, the third line pattern is sent.

[0075] A total of three data points are sent to the storage chip, and the control signal for each data point consists of four consecutive bits, either 7f or 0. The first data point is 0, 7f, 0, 7f; the second data point is 0, 0, 7f, 0; and the third data point is 7f, 0, 7f, 7f. After the first data point is sent and the corresponding result is received by the data receiver, the next data point is sent. After the three data points are sent, the positional relationship between each bit of the control signal and the clock signal can be determined by combining the data from the three data receivers.

[0076] Preferably, reference Figure 5 , Figure 6 and Figure 7 S200, judging the relationship between each bit in the CA signal and the clock signal according to the received result includes:

[0077] If the received result is 0, 1, 1, it means that the rising edge of the clock signal is in the middle of the control signal;

[0078] If the received result is 0, 1, 1, it means that the rising edge of the clock signal is in the middle of the left and right boundaries of the control signal, and each bit of the data receiving end corresponds to the control signal. If the result of dq[i] three times is 0, 1, 1, then finding the two boundaries of the control signal only requires shifting the control signal left and right.

[0079] If the received result is 1, 0, 0, it means that the rising edge of the clock signal is to the left of the left boundary of the control signal;

[0080] If the received result is 1, 0, 0, it means that the rising edge of the clock signal corresponds to the left of the left boundary of the control signal. If the three results of dq[i] are 1, 0, 0 respectively, then the control signal needs to be shifted left to find both boundaries of the control signal.

[0081] If the received result is 1, 0, 1, it means that the rising edge of the clock signal is close to the right of the right boundary of the control signal.

[0082] If the received results are 1, 0, and 1, it means that the rising edge of the clock signal corresponds to the right of the right boundary of the control signal. If the three results of dq[i] are 1, 0, and 1 respectively, then the control signal needs to be shifted right to find both boundaries of the control signal.

[0083] In an embodiment of the present invention, the result received by the data receiving end can be used to determine the approximate positional relationship between the boundary of the control signal and the rising edge of the clock signal, and then the control signal delay can be changed based on the determined positional relationship to achieve the purpose of aligning the middle of the control signal with the rising edge of the clock signal. This overcomes the technical problem in the prior art of relying on traversing the difference between ca_delay and ck_delay, being in an unaware state of the positional relationship between the control signal and the clock signal, and having difficulty in determining whether the control signal needs to be shifted left or right relative to the clock signal, which takes a long time. The present invention can accurately determine the positional relationship between the control signal and the clock signal, and then make corresponding improvements to the positional relationship between the control signal and the clock signal, which can save adjustment time and eliminates the need to traverse the entire signal, greatly improving work efficiency.

[0084] Preferably, in S300, adjusting the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal includes:

[0085] S310, pre-adjusting the delay of the control signal so that the rising edge of the clock signal is in the middle of the control signal;

[0086] In order to reduce the amount of code, in the latter two cases, the control signal will be shifted left or right by two ui (half a clock signal cycle) to change the control signal edge to the middle close to the rising edge or falling edge of the clock signal.

[0087] S320, coarsely adjusting the delay of the control signal to quickly find the approximate position of the control signal boundary;

[0088] S330 , coarsely and finely adjust the delay of the control signal to find the boundary of the control signal.

[0089] When the delay of the control signal is adjusted to be close to the rising edge or falling edge of the clock signal, fine adjustment should be started so that the middle of the control signal is exactly aligned with the rising edge or falling edge of the clock signal.

[0090] The delay of the coarse control signal can find the approximate location of the CA boundary more quickly;

[0091] The delay of the fine-tuning control signal can ensure accuracy based on the coarse-tuning.

[0092] Combining coarse adjustment and fine adjustment can improve speed and ensure accuracy.

[0093] Preferably, in S310, pre-adjusting the delay of the control signal so that the rising edge of the clock signal is exactly in the middle of the control signal includes:

[0094] S311, when it is detected that the rising edge of the clock signal is to the right of the right boundary of the control signal, the control signal is shifted right by half a clock cycle;

[0095] The clock cycle, also known as the oscillation period, is defined as the inverse of the clock frequency. It is the most basic and smallest unit of time in a computer. During one clock cycle, the CPU only completes one basic action. The clock cycle represents the maximum frequency at which the SDRAM can operate; a smaller clock cycle means a higher operating frequency.

[0096] S312 , when it is detected that the rising edge of the clock signal is close to the left of the left boundary of the control signal, the control signal is shifted left by half a clock cycle.

[0097] Preferably, reference Figure 8 S320, delaying the control signal to find the left boundary of the control signal includes:

[0098] S321, increasing the delay value of the control signal to shift the control signal to the right, and finding the left boundary;

[0099] Increasing the control signal delay moves the control signal to the right, so that the left boundary of the control signal is closer to the rising edge of the clock signal. When the left boundary of the control signal is close to the rising edge of the clock signal, reduce the delay value until the return value jumps, indicating that the left boundary of the control signal has been found.

[0100] S322, each time the control signal delay value is changed, data is sent once until the value at the data receiving end changes from 1 to 0;

[0101] The value of each change in the control signal delay can be set relatively large first, and then coarse adjustment is performed, and then the data receiving end is checked for any jump. If it has, the result of the last coarse adjustment is returned to, and the value of each change in the control signal delay is reduced, and fine adjustment is performed, and then the data receiving end is checked for any jump. This is repeated until a jump occurs at the data receiving end. This indicates that the current control signal delay value represents the distance between the left boundary of the control signal and the rising edge of the clock signal. The present invention first searches for a larger range, and then slowly narrows the range until the accurate delay value is found, thereby determining how far the left boundary of the control signal is from the clock signal.

[0102] S323, when the value of a certain bit at the data receiving end changes from 1 to 0, it indicates that the left boundary of the control signal of this bit has been found;

[0103] The number of bits in a control signal depends on the number of states it needs to represent. In communication systems, control signals are typically represented by different symbols (symbols). The number of states each symbol can represent determines the number of bits required. In this embodiment of the present invention, the control signal consists of seven bits, originating from different lines. Because each line has a different route, the delay varies, which can easily lead to inaccurate clock signal sampling. Therefore, it is necessary to identify the boundaries of each bit of the control signal and then align them.

[0104] S324: Stop increasing the delay value of the corresponding control signal, and continue increasing the delay value of the control signal for the bit where no transition occurs, until the control signal of all bits finds the left boundary.

[0105] After determining the positional relationship between each bit of ca and ck and classifying it as the first case, the value of ca_delay[i] is adjusted and a new pattern is sent. First, the value of ca_delay[i] is increased to shift ca rightward, searching for the left boundary. Each time the value of ca_delay[i] is changed, the pattern is sent again until the value of dq[i] changes from 1 to 0. When the dq value of a bit changes from 1 to 0, indicating that the left boundary of ca for that bit has been found, the corresponding ca_delay[i] is stopped from being increased. The incrementing process continues for the remaining bits that have not transitioned until the left boundary of ca for all bits has been found.

[0106] Preferably, in S320, delaying the control signal to find the right boundary of the control signal includes:

[0107] S325, increasing the delay value of the control signal to shift the control signal to the left, and finding the right boundary;

[0108] Before finding the right boundary of the control signal, the control signal is first shifted left as a whole by (3 / 4)*half a clock cycle, and then the right boundary is found according to the method for finding the left boundary.

[0109] S326, each time the value of the control signal delay is changed, it is sent once until the value at the data receiving end changes from 1 to 0;

[0110] The data receiving end (DQ) is used for data transmission and is bidirectional, serving as both data input and output. The DQ pins are used for data read and write operations. During a read operation, the memory chip transmits stored data to the motherboard or other processing unit via the DQ pins. During a write operation, the processing unit writes data to the memory chip via the DQ pins. To ensure accurate data transmission, one or more DQS (Data Strobe) pins are typically used to synchronize data on the DQ pins. The DQS pin provides a clock signal during data transmission, ensuring that data is read or written at the correct time.

[0111] S327, when the value of a certain bit at the data receiving end changes from 1 to 0, it indicates that the right boundary of the control signal of this bit has been found;

[0112] S328: Reduce the value of the control signal delay until all bits are transitioned.

[0113] Then start looking for the right edge. First, shift ca left by (3 / 4) * half the ck period. Then, similar to the method for finding the left edge, start decreasing the value of ca_delay[i] until all bits transition.

[0114] Record the ca_delay[i] value of each bit when the left and right boundaries are found, and take the average of the corresponding bits to get the final result.

[0115] Preferably, it also includes:

[0116] First, use a larger step size a to roughly adjust the control signal delay, and then use a smaller step size b to fine-tune the control signal delay;

[0117] In embodiments of the present invention, the delay of a control signal can be adjusted using a calibration delay circuit. This can extend the signal transmission time. A calibration delay circuit is a circuit with a specific delay time that delays the input signal for a period of time before outputting it. By adjusting the delay time of the delay circuit, the signal delay can be controlled. Delay circuits typically use signals such as clocks to control the delay time.

[0118] If a jump occurs after adding n*a, the control signal is delayed back to (dly_init+(n-1)*a);

[0119] Use a step size b that is smaller than a for adjustment. If a jump occurs after adding m*b, the control signal delay for finding the left boundary is (initial delay + (n-1)*a + m*b).

[0120] This method allows for coarse adjustments before fine-tuning when finding the boundary, further saving simulation time. For example, assuming the initial ca_delay is dly_init, adjust ca_delay using a larger step size a. If a jump occurs after increasing it by n*a, adjust ca_delay back to (dly_init + (n-1)*a) and then use a smaller step size b. If a jump occurs after increasing it by m*b, the final ca_delay for the left boundary is (dly_init + (n-1)*a + m*b).

[0121] Example 2

[0122] A system for fast CA train for LPDDR5, comprising:

[0123] The data sending module is used to send three sets of data to the CA of the Command Bus Training Mode particle and receive the return results of the DQ signal line respectively;

[0124] The data receiving module is used to determine the relationship between each bit in the CA signal and the clock signal based on the received results;

[0125] The data processing module is used to adjust the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal.

[0126] Example 3

[0127] An electronic device includes: a chip, a processor and a memory, wherein the memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a method for fast ca train of LPDDR5.

[0128] refer to Figure 9 The electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, which may include various interfaces, transmission lines, or buses, etc., but this is not limited in the present embodiment. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, such as connection via various interfaces, transmission lines, buses, etc.

[0129] The processor 21 may be one or more graphics processing units (GPUs). If the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Alternatively, the processor 21 may be a processor group consisting of multiple GPUs, with the multiple processors coupled to each other via one or more buses. Alternatively, the processor may be another type of processor, and this is not limited in this embodiment of the present invention.

[0130] The memory 22 can be used to store computer program instructions and various computer program codes, including program codes for executing the embodiments of the present invention. Optionally, the memory includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), and is used for related instructions and data.

[0131] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 can be independent devices or an integrated device.

[0132] The present invention determines the positional relationship between the control signal and the clock signal through the return value, thereby determining whether left shift or right shift is required when finding the left and right boundaries of each bit of CA, reducing time spent, clarifying the adjustment direction, saving simulation time, and improving work efficiency; the present invention combines coarse adjustment and fine adjustment, which can not only reduce the number of adjustments and save time, but also ensure adjustment precision and improve accuracy; the present invention adjusts the control signal bit by bit to ensure that the control signal has the maximum edge width and improve stability; the present invention has strong flexibility and can flexibly handle various positional relationships between the bits of the control signal and various positional relationships between the control signal and the clock signal.

[0133] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is intended to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for fast ca train of lpddr5, characterized in that include: Send three sets of data to the CA of the Command Bus Training Mode particle and receive the return results of the DQ signal line respectively; Determine the relationship between each bit in the CA signal and the clock signal based on the received results; Adjust the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal; The sending of three sets of data to the CA of the Command Bus Training Mode particle and receiving the return results of the DQ signal lines respectively include: After the first data: 0, 7f, 0, 7f, is sent out and the data receiving end receives the corresponding result, the second data: 0, 0, 7f, 0 is sent; After the second data is sent out and the data receiving end receives the corresponding result, the third data is sent: 7f, 0, 7f, 7f; Determining the relationship between each bit in the CA signal and the clock signal according to the received result includes: If the received result is 0, 1, 1, it means that the rising edge of the clock signal is in the middle of the control signal; If the received result is 1, 0, 0, it means that the rising edge of the clock signal is to the left of the left boundary of the control signal; If the received result is 1, 0, 1, it means that the rising edge of the clock signal is to the right of the right boundary of the control signal; The adjusting the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal includes: The delay of the control signal is pre-adjusted so that the rising edge of the clock signal is in the middle of the control signal; Coarsely adjust the delay of the control signal to quickly find the approximate position of the control signal boundary Fine-tune the delay of the control signal to find the precise position boundary of the control signal; The delay of the control signal to find the left boundary of the control signal includes: Increase the value of the control signal delay to shift the control signal to the right and find the left boundary; Each time the control signal delay value is changed, data is sent until the value at the data receiving end changes from 1 to 0; When the value of a bit at the data receiving end changes from 1 to 0, it means that the left boundary of the control signal of this bit has been found; Stop increasing the delay value of the corresponding control signal. Continue increasing the delay value of the control signal for the bit that has not jumped until the control signal of all bits finds the left boundary. The delay of the fine-tuning control signal to find the right boundary of the control signal includes: Increase the value of the control signal delay to shift the control signal to the left and find the right boundary; Each time the control signal delay value is changed, it is sent once until the value at the data receiving end changes from 1 to 0; When the value of a bit at the data receiving end changes from 1 to 0, it means that the right boundary of the control signal of this bit has been found; Reduce the control signal delay value until all bits transition. First, use a larger step size a to roughly adjust the control signal delay, and then use a smaller step size b to fine-tune the control signal delay; If a jump occurs after adding n*a, the control signal is delayed back to: dly_init+(n-1)*a; Use a step size b that is smaller than a for adjustment. If a jump occurs after adding m*b, the control signal delay of the left boundary is finally found to be: initial delay + (n-1)*a + m*b.

2. A method for fast ca train for LPDDR5 according to claim 1, characterized in that The delay of the coarse adjustment control signal so that the rising edge of the clock signal is exactly in the middle of the control signal includes: When it is detected that the rising edge of the clock signal is to the right of the right boundary of the control signal, the control signal is shifted right by half a clock cycle; When it is detected that the rising edge of the clock signal is close to the left of the left boundary of the control signal, the control signal is shifted left by half a clock cycle.

3. A system for fast ca train of LPDDR5, applied to the method for fast ca train of LPDDR5 according to any one of claims 1-2, characterized in that: include: The data sending module is used to send three sets of data to the CA of the Command Bus Training Mode particle and receive the return results of the DQ signal line respectively; The data receiving module is used to determine the relationship between each bit in the CA signal and the clock signal based on the received results; The data processing module is used to adjust the delay of the CA signal according to the relationship between each bit in the CA signal and the clock signal.

4. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program code, wherein the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a method for fast CA train for LPDDR5 as described in any one of claims 1 to 2.

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