Chip power consumption control method and device, electronic equipment, storage medium and program product

Abstract

The invention relates to a chip power consumption control method and device, electronic equipment, a storage medium and a program product. The method comprises the steps that at least two power consumption candidate values are obtained through at least two power consumption management modules of a target chip, each power consumption management module in the at least two power consumption management modules outputs one power consumption candidate value, and the at least two power consumption management modules comprise temperature control modules; the at least two power consumption candidate values comprise a first power consumption candidate value output by the temperature control module; determining target power consumption of the target chip according to the at least two power consumption candidate values; determining a target frequency and a target voltage of the target chip according to the target power consumption and the actual power consumption of the target chip; and adjusting the frequency of the target chip according to the target frequency, and adjusting the voltage of the target chip according to the target voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a chip power consumption control method, a chip power consumption control device, an electronic device, a computer-readable storage medium, and a computer program product. Background Art

[0002] With the development of technology in the fields of electronic consumer products, graphics cards, servers, etc., higher requirements are placed on the power consumption and temperature control of chips. In related technologies, power consumption control and temperature control are usually regarded as two independent technical problems, and their respective solutions are developed.

[0003] In terms of power consumption control, technology development is mainly focused on reducing power consumption by dynamically adjusting the voltage and frequency of the processor, a technology called DVFS (Dynamic Voltage and Frequency Scaling). In terms of temperature control, technology development focuses on maintaining the chip within a safe operating temperature range through various heat dissipation technologies.

[0004] However, power consumption control solutions and temperature control solutions often require independent control logic and hardware support, which increases system complexity and reduces control efficiency. Summary of the invention

[0005] The present disclosure provides a chip power consumption control technology solution.

[0006] According to one aspect of the present disclosure, a chip power consumption control method is provided, comprising:

[0007] Obtaining at least two power consumption candidate values ​​through at least two power consumption management modules of the target chip, wherein each of the at least two power consumption management modules outputs a power consumption candidate value respectively, the at least two power consumption management modules include a temperature control module, and the at least two power consumption candidate values ​​include a first power consumption candidate value output by the temperature control module;

[0008] Determining the target power consumption of the target chip according to the at least two candidate power consumption values;

[0009] Determining a target frequency and a target voltage of the target chip according to the target power consumption and the actual power consumption of the target chip;

[0010] The frequency of the target chip is adjusted according to the target frequency, and the voltage of the target chip is adjusted according to the target voltage.

[0011] In a possible implementation manner, obtaining at least two candidate power consumption values ​​through at least two power consumption management modules of the target chip includes:

[0012] The first power consumption candidate value is determined by the temperature control module according to the current temperature of the target chip and the corresponding relationship between temperature and power consumption.

[0013] In a possible implementation, the at least two power consumption management modules include a performance state management module;

[0014] The obtaining at least two candidate power consumption values ​​through at least two power consumption management modules of the target chip includes:

[0015] Determining, by the performance state management module, a target performance state level of the target chip according to information about a current workload of a processor in the target chip;

[0016] According to the target performance state level, a second power consumption candidate value is determined.

[0017] In a possible implementation, the at least two power consumption management modules include an overclocking management module;

[0018] The obtaining at least two candidate power consumption values ​​through at least two power consumption management modules of the target chip includes:

[0019] A third power consumption candidate value input by a user is obtained through the overclocking management module.

[0020] In a possible implementation manner, determining the target power consumption of the target chip according to the at least two candidate power consumption values ​​includes:

[0021] In the case where a preset overclocking operation condition is met, determining the third power consumption candidate value as the target power consumption of the target chip;

[0022] or,

[0023] In the case where the preset overclocking operation condition is not met, determining the minimum value of the at least two candidate power consumption values ​​as the target power consumption of the target chip;

[0024] The preset overclocking operation condition includes: the candidate power consumption values ​​output by each power consumption management module except the overclocking management module in the at least two power consumption management modules are all preset maximum power consumption values.

[0025] In a possible implementation manner, determining the target power consumption of the target chip according to the at least two candidate power consumption values ​​includes:

[0026] The minimum value of the at least two candidate power consumption values ​​is determined as the target power consumption of the target chip.

[0027] In a possible implementation manner, determining the target frequency and target voltage of the target chip according to the target power consumption and the actual power consumption of the target chip includes:

[0028] Determining a target frequency of the target chip according to the target power consumption and the actual power consumption of the target chip;

[0029] The target voltage of the target chip is determined according to the target frequency and the corresponding relationship between frequency and voltage.

[0030] In a possible implementation manner, determining the target frequency of the target chip according to the target power consumption and the actual power consumption of the target chip includes:

[0031] Determining a power consumption difference according to the target power consumption and the actual power consumption of the target chip;

[0032] The target frequency of the target chip is determined according to the power consumption difference by a proportional-integral-differential controller.

[0033] According to one aspect of the present disclosure, a chip power consumption control device is provided, comprising:

[0034] An obtaining module, configured to obtain at least two power consumption candidate values ​​through at least two power consumption management modules of a target chip, wherein each of the at least two power consumption management modules outputs a power consumption candidate value respectively, the at least two power consumption management modules include a temperature control module, and the at least two power consumption candidate values ​​include a first power consumption candidate value output by the temperature control module;

[0035] A first determining module, configured to determine a target power consumption of the target chip according to the at least two candidate power consumption values;

[0036] A second determining module, used to determine a target frequency and a target voltage of the target chip according to the target power consumption and the actual power consumption of the target chip;

[0037] The adjustment module is used to adjust the frequency of the target chip according to the target frequency, and to adjust the voltage of the target chip according to the target voltage.

[0038] In a possible implementation, the obtaining module is used to:

[0039] The first power consumption candidate value is determined by the temperature control module according to the current temperature of the target chip and the corresponding relationship between temperature and power consumption.

[0040] In a possible implementation, the at least two power consumption management modules include a performance state management module;

[0041] The acquisition module is used for:

[0042] Determining, by the performance state management module, a target performance state level of the target chip according to information about a current workload of a processor in the target chip;

[0043] According to the target performance state level, a second power consumption candidate value is determined.

[0044] In a possible implementation, the at least two power consumption management modules include an overclocking management module;

[0045] The acquisition module is used for:

[0046] A third power consumption candidate value input by a user is obtained through the overclocking management module.

[0047] In a possible implementation manner, the first determining module is used to:

[0048] In the case where a preset overclocking operation condition is met, determining the third power consumption candidate value as the target power consumption of the target chip;

[0049] or,

[0050] In the case where the preset overclocking operation condition is not met, determining the minimum value of the at least two candidate power consumption values ​​as the target power consumption of the target chip;

[0051] The preset overclocking operation condition includes: the candidate power consumption values ​​output by each power consumption management module except the overclocking management module in the at least two power consumption management modules are all preset maximum power consumption values.

[0052] In a possible implementation manner, the first determining module is used to:

[0053] The minimum value of the at least two candidate power consumption values ​​is determined as the target power consumption of the target chip.

[0054] In a possible implementation manner, the second determining module is used to:

[0055] Determining a target frequency of the target chip according to the target power consumption and the actual power consumption of the target chip;

[0056] The target voltage of the target chip is determined according to the target frequency and the corresponding relationship between frequency and voltage.

[0057] In a possible implementation manner, the second determining module is used to:

[0058] Determining a power consumption difference according to the target power consumption and the actual power consumption of the target chip;

[0059] The target frequency of the target chip is determined according to the power consumption difference by a proportional-integral-differential controller.

[0060] According to one aspect of the present disclosure, an electronic device is provided, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0061] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0062] According to one aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0063] In the embodiment of the present disclosure, at least two power consumption candidate values ​​are obtained through at least two power consumption management modules of the target chip, wherein each of the at least two power consumption management modules outputs a power consumption candidate value respectively, the at least two power consumption management modules include a temperature control module, and the at least two power consumption candidate values ​​include a first power consumption candidate value output by the temperature control module, and the target power consumption of the target chip is determined according to the at least two power consumption candidate values, and the target frequency and target voltage of the target chip are determined according to the target power consumption and the actual power consumption of the target chip, and the frequency of the target chip is adjusted according to the target frequency, and the voltage of the target chip is adjusted according to the target voltage, thereby unifying the power consumption control and temperature control, and integrating multiple power consumption management functions into a unified power consumption control module (that is, a unified target power consumption is determined based on the output of multiple power consumption management modules, and the frequency and voltage of the target chip are controlled based on the unified target power consumption), simplifying the complexity of software implementation, thereby reducing the difficulty of development. This integrated method not only improves the stability of the system, but also reduces the performance fluctuation caused by inconsistent coordination between multiple independent control modules, making the entire system more efficient and reliable in power consumption management. In addition, in the embodiment of the present disclosure, it is only necessary to determine the target power consumption based on at least two power consumption candidate values ​​output by at least two power consumption management modules, without calculating the complex static power consumption and dynamic power consumption of the chip. Therefore, there is no need to consider complex parameters such as the internal leakage current of the transistor, the manufacturing process of the chip, and the load capacitance, thereby further improving the efficiency of the chip power consumption control.

[0064] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

[0065] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0067] Figure 1 A schematic diagram showing a voltage-frequency (VF) curve used in a chip power consumption control method in the related art.

[0068] Figure 2 A schematic diagram showing a temperature-frequency (TF) curve used in a chip temperature control method in the related art.

[0069] Figure 3 A flow chart of a chip power consumption control method provided by an embodiment of the present disclosure is shown.

[0070] Figure 4 A schematic diagram of a temperature-power consumption (TP) curve used by a temperature control module in a chip power consumption control method provided in an embodiment of the present disclosure is shown.

[0071] Figure 5 A schematic diagram showing an application scenario of the chip power consumption control method provided by an embodiment of the present disclosure.

[0072] Figure 6 A block diagram of a chip power consumption control device provided by an embodiment of the present disclosure is shown.

[0073] Figure 7 A block diagram of an electronic device 1900 provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0074] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0075] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0076] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0077] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0078] DVFS (Dynamic Voltage and Frequency Scaling) is an efficient energy management technology that can be used to reduce the energy consumption of processors and computing devices. DVFS technology can achieve energy saving and thermal management by dynamically adjusting the voltage and frequency of the processor to adapt to different workload requirements. There is a close relationship between voltage and frequency. Generally, increasing the frequency of the processor will lead to an increase in voltage to ensure that the circuit can work normally at a higher frequency; conversely, reducing the frequency allows the voltage to be reduced.

[0079] The technical features of DVFS include:

[0080] Dynamic Adjustment: DVFS is dynamic and can adjust voltage and frequency in real time based on the processor workload, reducing voltage and frequency to save energy when the load is low, and increasing voltage and frequency to provide higher performance when the load increases.

[0081] Significant energy-saving effect: In CMOS (Complementary Metal-Oxide-Semiconductor) circuits, power consumption is mainly composed of dynamic power consumption and static power consumption. Dynamic power consumption is proportional to the square of the voltage and the frequency, and static power consumption is proportional to the voltage. Therefore, by reducing the voltage and frequency through DVFS technology, power consumption can be effectively reduced, extending battery life or reducing the electricity bill of the data center.

[0082] Thermal management: By reducing voltage and frequency, devices can generate less heat, prevent overheating, and reduce cooling requirements. This is especially important for portable devices and large-scale data centers.

[0083] DVFS technology is widely used in various computing devices, including mobile devices, embedded systems, data center servers, etc. By dynamically managing the voltage and frequency of the processor, DVFS technology can achieve significant energy saving while ensuring performance, which is especially important in areas where energy efficiency needs to be optimized.

[0084] In summary, DVFS technology is an efficient energy management technology that achieves energy saving and thermal management by dynamically adjusting the voltage and frequency of the processor to adapt to different workload requirements. Its implementation requires the collaboration of software and hardware and faces certain technical challenges. However, with the continuous advancement of technology and the expansion of application scenarios, DVFS technology will play an important role in more fields.

[0085] In the related art, chip power consumption control and temperature control methods are usually implemented based on DVFS technology, but these two goals are managed separately.

[0086] In the related art, in order to achieve the control of the chip power consumption target P_Target, the software will calculate and find the voltage and frequency that make the chip power consumption equal to P_Target based on the voltage-frequency (VF) curve of the actual operation of the chip, and then control the hardware to output the corresponding voltage V and control the chip to run the corresponding frequency F. Figure 1 A schematic diagram showing a voltage-frequency (VF) curve used in a chip power consumption control method in the related art. Figure 1 In the figure, the horizontal axis is voltage in mV, and the vertical axis is frequency in MHz. The power consumption of a chip is usually divided into two parts: static power consumption and dynamic power consumption. Among them, static power consumption refers to the power consumption generated by the internal leakage current of the transistor when the chip is powered on but no dynamic operation (such as signal flipping) is performed. Static power consumption is related to factors such as the chip's power supply voltage, manufacturing process, temperature, etc., but has nothing to do with the signal flipping frequency. The calculation formula is P_static=V_dd×I_leak, where V_dd is the chip's power supply voltage and I_leak is the leakage current. Dynamic power consumption refers to the power consumption generated when the chip is performing dynamic operations, such as signal flipping. The calculation formula is P_switch=C_L×V_dd^2×F, where C_L is the total load capacitance of the circuit, V_dd is the power supply voltage, and F is the flipping frequency of the signal. The total power consumption P_Target of all chips is equal to the sum of dynamic power consumption and static power consumption, that is, P_Target=P_switch+P_static=C_L×V_dd^2×F+V_dd×I_leak. The software needs to solve the corresponding voltage and frequency based on the known VF curve and the above equation.

[0087] In addition, in the related art, chip temperature control usually adopts a segmented control strategy. When the temperature is low and the system fan is adjustable, the NT curve between the fan speed N and the chip temperature T is used for control. When the temperature is low, the fan speed is reduced to reduce noise; when the temperature is high, the fan speed is increased to reduce the chip temperature. If the fan speed has reached the maximum value, but the chip temperature is still too high, the TF curve between the chip temperature T and the chip frequency F is usually used for control. Figure 2 FIG. 1 is a schematic diagram showing a temperature-frequency (TF) curve used in a chip temperature control method in the related art. Figure 2 In the figure, the horizontal axis is temperature in °C, and the vertical axis is frequency in MHz. Figure 2 In the TF curve shown, when the chip temperature is between 85°C and 90°C, the chip's operating frequency will decrease at a fixed slope; in the range of 90°C to 96°C, the downward slope will be higher. After reaching the minimum operating frequency of the chip, it will remain at this minimum frequency. If the chip temperature continues to rise, the system will be powered off and the chip will stop working.

[0088] The chip power consumption control and temperature control solutions in the related art have the following defects:

[0089] First, in the related art, power consumption control and temperature control are performed separately. When power consumption control and temperature control are effective at the same time, the system needs to perform complex arbitration to determine which control strategy should be executed first. This complex judgment process makes system control difficult.

[0090] Second, the implementation of temperature control usually relies on the temperature-frequency (TF) curve, but this approach has limitations because it cannot adapt to the process and leakage characteristics of different chips. Since the process and leakage current of different chips in the same product line may vary, their power consumption will be different even at the same operating frequency. Therefore, when the temperature reaches a certain threshold, the unified temperature-frequency curve cannot accurately control the power consumption of all chips, resulting in significant differences in the effect and behavior of temperature control between different chips.

[0091] Third, in addition to power consumption control and temperature control, other chip power consumption control functions are also included. These functions are independent of each other, which increases the complexity of control. Each function attempts to control the operating frequency of the chip, but there is no unified framework to coordinate these different control requirements. This decentralized control method not only increases the complexity of system design, but may also affect the overall performance and efficiency.

[0092] Fourth, the implementation of power consumption control in related technologies needs to consider multiple complex parameters, including chip leakage current, manufacturing process, load capacitance, and temperature. The complexity of these parameters lies in the fact that they are not only interdependent, but also may change over time and environmental conditions. Therefore, accurate control of power consumption requires real-time monitoring and dynamic adjustment of these parameters, which places higher requirements on both software and hardware, and also increases the difficulty of system design.

[0093] In order to solve the technical problems similar to those described above, the embodiment of the present disclosure provides a chip power consumption control method, wherein at least two power consumption candidate values ​​are obtained through at least two power consumption management modules of a target chip, wherein each of the at least two power consumption management modules outputs a power consumption candidate value respectively, the at least two power consumption management modules include a temperature control module, and the at least two power consumption candidate values ​​include a first power consumption candidate value output by the temperature control module, and the target power consumption of the target chip is determined according to the at least two power consumption candidate values, and the target frequency and target voltage of the target chip are determined according to the target power consumption and the actual power consumption of the target chip, and the frequency of the target chip is adjusted according to the target frequency, and the voltage of the target chip is adjusted according to the target voltage, thereby unifying the power consumption control and temperature control, and integrating multiple power consumption management functions into a unified power consumption control module (that is, a unified target power consumption is determined based on the outputs of multiple power consumption management modules, and the frequency and voltage of the target chip are controlled based on the unified target power consumption), simplifying the complexity of software implementation, thereby reducing the difficulty of development. This integrated method not only improves the stability of the system, but also reduces the performance fluctuations caused by inconsistent coordination between multiple independent control modules, making the entire system more efficient and reliable in power consumption management. In addition, in the embodiment of the present disclosure, it is only necessary to determine the target power consumption based on at least two power consumption candidate values ​​output by at least two power consumption management modules, without calculating the complex static power consumption and dynamic power consumption of the chip. Therefore, there is no need to consider complex parameters such as the internal leakage current of the transistor, the manufacturing process of the chip, and the load capacitance, thereby further improving the efficiency of the chip power consumption control.

[0094] The chip power consumption control method provided by the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0095] Figure 3A flow chart of a chip power consumption control method provided by an embodiment of the present disclosure is shown. In one possible implementation, the execution subject of the chip power consumption control method may be a chip power consumption control device. For example, the chip power consumption control method may be executed by a terminal device or a server or other electronic device. The terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device or a wearable device. In some possible implementations, the chip power consumption control method may be implemented by a processor calling computer-readable instructions stored in a memory. For example Figure 3 As shown, the chip power consumption control method includes steps S31 to S34.

[0096] In step S31, at least two power consumption candidate values ​​are obtained through at least two power consumption management modules of the target chip, wherein each of the at least two power consumption management modules outputs a power consumption candidate value respectively, the at least two power consumption management modules include a temperature control module, and the at least two power consumption candidate values ​​include a first power consumption candidate value output by the temperature control module.

[0097] In step S32, the target power consumption of the target chip is determined according to the at least two candidate power consumption values.

[0098] In step S33, the target frequency and target voltage of the target chip are determined according to the target power consumption and the actual power consumption of the target chip.

[0099] In step S34, the frequency of the target chip is adjusted according to the target frequency, and the voltage of the target chip is adjusted according to the target voltage.

[0100] In the embodiments of the present disclosure, the target chip may be any chip with power consumption control requirements. For example, the target chip may be a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), a SoC (System on a Chip), an ASIC (Application-Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), an MCU (Microcontroller Unit), etc., which are not limited here.

[0101] In the embodiment of the present disclosure, the power consumption management module may represent a module for controlling and optimizing the power consumption of a chip. In the embodiment of the present disclosure, at least two power consumption management modules may be managed in a unified manner, and at least two power consumption management modules may output power consumption candidate values ​​respectively. For example, at least two power consumption management modules may output power consumption candidate values ​​to the target power consumption determination module respectively.

[0102] In an embodiment of the present disclosure, the power consumption management module may include a temperature control module, and the power consumption candidate value output by the temperature control module may be a first power consumption candidate value. The temperature control module may monitor the temperature of the target chip and may adjust the output power consumption candidate value according to the current temperature and the corresponding relationship between the temperature and the power consumption.

[0103] In a possible implementation, obtaining at least two power consumption candidate values ​​through at least two power consumption management modules of the target chip includes: determining the first power consumption candidate value according to the current temperature of the target chip and the correspondence between temperature and power consumption through the temperature control module.

[0104] In this implementation, the temperature control module may use a temperature-power consumption (TP) curve to determine the power consumption limit at a specific temperature. The temperature-power consumption (TP) curve may define the corresponding relationship between temperature and power consumption. When the temperature of the target chip increases, power consumption needs to be reduced to prevent overheating and possible damage. The temperature-power consumption (TP) curve may set different power consumption limits according to different stages of temperature.

[0105] In this implementation, the first power consumption candidate value may represent a power consumption candidate value output by the temperature control module. The first power consumption candidate value may be used together with power consumption candidate values ​​generated by other power consumption management modules to determine the target power consumption of the target chip.

[0106] Figure 4 FIG. 1 is a schematic diagram showing a temperature-power consumption (TP) curve used by a temperature control module in a chip power consumption control method provided by an embodiment of the present disclosure. Figure 4 For example, when the temperature of the target chip reaches 85°C, the temperature control module can reduce the first power consumption candidate value according to the temperature-power consumption (TP) curve. If the temperature further rises to 99°C, the temperature control module can further reduce the first power consumption candidate value, for example, reducing the first power consumption candidate value to 40% of the original power consumption. It should be noted that the value of 40% here is only used as an example, and the actual percentage can be determined according to the specific design of the temperature-power consumption (TP) curve and the thermal characteristics of the chip.

[0107] The temperature control module can protect the target chip from overheating while maintaining its performance as much as possible. By dynamically adjusting the first power consumption candidate value, the target chip can operate more stably under different temperature conditions, thereby extending its service life and improving reliability.

[0108] In a possible implementation, the power consumption management module may further include a performance state management module and / or an overclocking management module.

[0109] In one possible implementation, the at least two power consumption management modules include a performance state management module; the at least two power consumption candidate values ​​are obtained through the at least two power consumption management modules of the target chip, including: determining the target performance state level of the target chip according to the current workload information of the processor in the target chip through the performance state management module; and determining a second power consumption candidate value according to the target performance state level.

[0110] In this implementation, the performance state management module can collect information about the current workload of the processor (such as a CPU or a GPU), for example, by monitoring the utilization of the processor. The utilization refers to the proportion of time that the processor executes tasks within a certain period of time, which reflects the busyness of the processor.

[0111] Based on the information of the current workload of the processor, the performance state management module can determine a suitable performance state level, namely the target performance state level. The performance state (P-states) level is a set of predefined performance levels, and each performance state level has its specific voltage and frequency settings. The performance state levels can be numbered, such as P0, P1, P2, etc. Among them, P0 can be the highest performance state level, providing the maximum frequency and voltage to achieve the best performance. P1, P2, P3, etc. can represent gradually decreasing performance state levels, and the corresponding frequency and voltage will also be reduced to reduce energy consumption.

[0112] In this implementation, if the utilization of the processor is high, the performance state management module may select a higher performance state level to provide sufficient processing power to meet the workload requirements. Conversely, if the utilization of the processor is low, the performance state management module may select a lower performance state level to reduce power consumption and save energy.

[0113] After determining the target performance state level, the performance state management module can calculate a second power consumption candidate value according to the target performance state level. The second power consumption candidate value can represent the power consumption level that the target chip should maintain under the selected performance state (i.e., the target performance state level). The second power consumption candidate value can take into account the voltage and frequency settings under the target performance state level, as well as the expected workload requirements.

[0114] The second power consumption candidate value can be used together with the power consumption candidate values ​​generated by other power consumption management modules (such as temperature control modules) to determine the target power consumption of the target chip. The system can select the minimum value among these power consumption candidate values, or can determine the final target power consumption according to other strategies.

[0115] By adopting this implementation, the performance state management module allows the target chip to flexibly adjust its performance and power consumption according to the actual workload requirements, thereby achieving energy efficiency optimization while ensuring performance. This implementation is particularly suitable for application scenarios where workloads change frequently, such as mobile devices, servers, and high-performance computing systems.

[0116] In a possible implementation, the at least two power consumption management modules include an overclocking management module; the at least two power consumption candidate values ​​are obtained through the at least two power consumption management modules of the target chip, including: obtaining a third power consumption candidate value input by the user through the overclocking management module.

[0117] In this implementation, the overclocking management module is a component of power management, which allows users to adjust the performance and power consumption of the target chip according to specific needs. Among them, the overclocking management module is a module dedicated to handling overclocking operations. Overclocking refers to increasing the operating frequency of the processor to obtain higher performance than the original design. This is usually to obtain better performance in a specific application or task.

[0118] The overclocking management module may allow the user to input a power consumption target value, which is referred to as the third power consumption candidate value in this implementation. Users may set this value based on their personal preferences for performance and power consumption, or based on the needs of a specific application. In the overclocking management module, some conditions or restrictions may be set to ensure that the overclocking operation does not cause damage to the target chip. These conditions may include the temperature of the target chip, voltage stability, system cooling capacity, etc.

[0119] The third power consumption candidate value input by the user through the overclocking management module can be used as the target power consumption of the target chip in the overclocking state. The third power consumption candidate value will be considered together with the power consumption candidate values ​​provided by other power consumption management modules (such as the temperature control module and the performance state management module).

[0120] In this way, the OC Management module provides users with a flexible way to increase chip performance while still maintaining control over power consumption. This approach allows users to make trade-offs between performance and power consumption to meet their specific needs.

[0121] In some cases, if users find that the heat dissipation function of the chip is not as expected, they may choose to set a lower third power consumption candidate value to avoid system instability or damage due to overheating. For example, based on the evaluation of the heat dissipation capability of the target chip, the user may set a lower third power consumption candidate value through the overclocking management module. By setting a lower third power consumption candidate value, the user can reduce the heat generated by the target chip under high load, thereby reducing the risk of overheating.

[0122] In this way, the setting of the third power consumption candidate value not only takes into account the need for performance improvement, but also the heat dissipation capacity of the chip and the long-term stability of the system. This method helps to achieve safer and more reliable overclocking operations in different usage scenarios and environmental conditions.

[0123] In some application scenarios, the overclocking management module may also be called a chip boost module, etc., which is not limited here.

[0124] In one possible implementation, determining the target power consumption of the target chip based on the at least two power consumption candidate values ​​includes: when a preset overclocking operation condition is met, determining the third power consumption candidate value as the target power consumption of the target chip; or, when the preset overclocking operation condition is not met, determining the minimum value of the at least two power consumption candidate values ​​as the target power consumption of the target chip; wherein the preset overclocking operation condition includes: the power consumption candidate values ​​output by each power consumption management module among the at least two power consumption management modules except the overclocking management module are all preset maximum power consumption values.

[0125] In this implementation, the preset overclocking operation condition can be used to determine whether the target chip can be overclocked in a safe state. The preset overclocking operation condition can be: the power consumption candidate values ​​output by each power consumption management module except the overclocking management module are all preset maximum power consumption values. That is, when the power consumption candidate values ​​output by each power consumption management module except the overclocking management module are all preset maximum power consumption values, it can be determined that the target chip can be overclocked in a safe state.

[0126] If the preset overclocking operation condition is met, the third power consumption candidate value provided by the overclocking management module can be used as the target power consumption of the target chip. That is, in the overclocking state, the target chip can operate according to the power consumption candidate value set by the user to achieve higher performance.

[0127] If the preset overclocking operating condition is not met, the minimum value can be selected from at least two power consumption candidate values ​​as the target power consumption of the target chip, thereby ensuring that the chip operates within a safe temperature range and avoiding overheating.

[0128] In one example, the at least two power consumption management modules include a temperature control module, a performance state management module, and an overclocking management module, and the at least two power consumption candidate values ​​include a first power consumption candidate value output by the temperature control module, a second power consumption candidate value output by the performance state management module, and a third power consumption candidate value output by the overclocking management module. The preset overclocking operation condition includes: the first power consumption candidate value is the maximum power consumption value corresponding to the temperature control module, and the second power consumption candidate value is the maximum power consumption value corresponding to the performance state management module. In this example, when the preset overclocking operation condition is met, the third power consumption candidate value is determined as the target power consumption of the target chip; when the preset overclocking operation condition is not met, the minimum value among the first power consumption candidate value, the second power consumption candidate value, and the third power consumption candidate value is determined as the target power consumption of the target chip.

[0129] In this implementation, the user can input the third power consumption candidate value through the overclocking management module, and the system can determine whether to adopt this value based on the preset overclocking operating conditions and real-time data. This design allows the user to control the performance of the target chip to a certain extent, while also providing necessary protection measures to prevent potential damage. The chip power consumption control strategy provided by this implementation can ensure the stability and security of the system while providing high performance.

[0130] In a possible implementation, the power consumption management module may further include a workload prediction module. The workload prediction module may analyze historical and real-time workload data, predict future power consumption requirements, and output corresponding power consumption candidate values.

[0131] In a possible implementation, the power consumption management module may further include an adaptive power consumption limitation module, which may dynamically adjust the power consumption limitation according to the current energy state of the system and user preferences.

[0132] In a possible implementation, the power consumption management module may further include a network activity management module. The network activity management module may adjust the candidate power consumption value according to the network activity level, for example, lower the candidate power consumption value when the network is idle.

[0133] In a possible implementation manner, determining the target power consumption of the target chip according to the at least two power consumption candidate values ​​includes: determining a minimum value of the at least two power consumption candidate values ​​as the target power consumption of the target chip.

[0134] In this implementation, the strategy for determining the target power consumption of the target chip is conservative, aiming to ensure that the target chip can operate safely under various operating conditions while saving energy as much as possible.

[0135] In this implementation, the various power consumption candidate values ​​can be compared to determine which value is the smallest. This smallest value is considered to be the safest and most energy-efficient power consumption level. The system can set the smallest power consumption candidate value as the target power consumption of the target chip. That is, regardless of the power consumption values ​​recommended by other power consumption management modules, the target chip will operate at this lowest power consumption value to avoid exceeding the safety limit set by any single power consumption management module.

[0136] By selecting the smallest power consumption candidate value, it is ensured to remain stable under all monitoring conditions, allowing safe operation even under the most stringent conditions. In addition, this implementation helps save energy.

[0137] In the embodiment of the present disclosure, the actual power consumption of the target chip can be collected by the power consumption collection module, wherein the actual power consumption can represent the current power consumption level of the target chip.

[0138] In a possible implementation, determining the target frequency and target voltage of the target chip based on the target power consumption and the actual power consumption of the target chip includes: determining the target frequency of the target chip based on the target power consumption and the actual power consumption of the target chip; and determining the target voltage of the target chip based on the target frequency and the correspondence between frequency and voltage.

[0139] In this implementation, the target frequency can be calculated based on the target power consumption and the actual power consumption of the target chip. Specifically, the power consumption difference, that is, the difference between the target power consumption and the actual power consumption, can be calculated, and the target frequency can be calculated based on the power consumption difference.

[0140] After the target frequency is determined, the target voltage can be determined based on the correspondence between frequency and voltage. For example, the voltage-frequency curve of the target chip can be determined based on the physical characteristics and design parameters of the target chip. The voltage-frequency curve can define the voltage required by the target chip at different frequencies.

[0141] As an example of this implementation method, determining the target frequency of the target chip based on the target power consumption and the actual power consumption of the target chip includes: determining a power consumption difference based on the target power consumption and the actual power consumption of the target chip; and determining the target frequency of the target chip based on the power consumption difference through a proportional-integral-differential controller.

[0142] In one example, a proportional-integral-derivative controller can be configured based on Calculate the target frequency at the kth time step. P represents the proportionality coefficient, e(k) represents the power consumption difference between the target power consumption and the actual power consumption of the target chip at the kth time step; K I represents the integral coefficient, e(i) represents the power consumption difference between the target power consumption and the actual power consumption of the target chip at the i-th time step, represents the sum of all power consumption differences from the 0th time step to the kth time step, and represents the integral of the power consumption difference; K D represents the differential coefficient, and e(k-1) represents the power consumption difference at the k-1th time step.

[0143] In one example, after the PID controller calculates the target frequency of the target chip, the DVFS module can adjust the frequency and voltage of the target chip according to the target frequency and the voltage-frequency curve.

[0144] The chip power consumption control method provided by the embodiment of the present disclosure can be applied to the fields of electronic consumer products (such as mobile devices such as smart phones and tablet computers), graphics cards, servers, and other occasions that require real-time management and optimization of chip output power consumption and product input power consumption. The chip power consumption control method provided by the embodiment of the present disclosure can adapt to different workload requirements by dynamically adjusting voltage and frequency to achieve energy saving and thermal management, and is particularly suitable for computing-intensive and power-sensitive devices that have high requirements for energy efficiency and performance stability.

[0145] The chip power consumption control method provided by the embodiment of the present disclosure is described below through a specific application scenario. Figure 5 A schematic diagram showing an application scenario of the chip power consumption control method provided by an embodiment of the present disclosure. Figure 5 As shown, in this application scenario, the power consumption management module of the target chip may include a temperature control module, a performance state management module, and an overclocking management module. The temperature control module, the performance state management module, and the overclocking management module may be connected to the power consumption control module, respectively. The power consumption control module may include a target power consumption determination module, a power consumption acquisition module, a PID controller, and a DVFS module.

[0146] Among them, the temperature control module can determine the first power consumption candidate value according to the current temperature of the target chip and the corresponding relationship between the temperature and the power consumption, and can send the first power consumption candidate value to the target power consumption determination module. The performance state management module can determine the target performance state level of the target chip according to the information of the current workload of the processor in the target chip, determine the second power consumption candidate value according to the target performance state level and the corresponding relationship between the performance state level and the power consumption, and can send the second power consumption candidate value to the target power consumption determination module. The overclocking management module can obtain the third power consumption candidate value input by the user, and can send the third power consumption candidate value to the target power consumption determination module.

[0147] The target power consumption determination module can determine the target power consumption of the target chip according to the first power consumption candidate value from the temperature control module, the second power consumption candidate value from the performance state management module, and the third power consumption candidate value from the overclocking management module. For example, if the preset overclocking operation condition is met, the third power consumption candidate value can be determined as the target power consumption of the target chip; if the preset overclocking operation condition is not met, the minimum value among the first power consumption candidate value, the second power consumption candidate value, and the third power consumption candidate value can be determined as the target power consumption of the target chip. The preset overclocking operation condition includes: the first power consumption candidate value is the maximum power consumption value corresponding to the temperature control module, and the second power consumption candidate value is the maximum power consumption value corresponding to the performance state management module.

[0148] The power consumption acquisition module can acquire the actual power consumption of the target chip.

[0149] The target power consumption and actual power consumption of the target chip can be sent to the PID controller. The PID controller can determine the target frequency of the target chip based on the target power consumption and actual power consumption of the target chip, and send the target frequency to the DVFS module. The DVFS module can adjust the frequency and voltage of the target chip based on the target frequency.

[0150] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0151] In addition, the present disclosure also provides a chip power consumption control device, an electronic device, a computer-readable storage medium, and a computer program product, all of which can be used to implement any chip power consumption control method provided by the present disclosure. The corresponding technical solutions and technical effects can be found in the corresponding records in the method part and will not be repeated here.

[0152] Figure 6FIG. 2 is a block diagram of a chip power consumption control device provided by an embodiment of the present disclosure. Figure 6 As shown, the chip power consumption control device includes:

[0153] An obtaining module 61 is configured to obtain at least two power consumption candidate values ​​through at least two power consumption management modules of a target chip, wherein each of the at least two power consumption management modules outputs a power consumption candidate value respectively, the at least two power consumption management modules include a temperature control module, and the at least two power consumption candidate values ​​include a first power consumption candidate value output by the temperature control module;

[0154] A first determining module 62, configured to determine a target power consumption of the target chip according to the at least two candidate power consumption values;

[0155] A second determining module 63, configured to determine a target frequency and a target voltage of the target chip according to the target power consumption and the actual power consumption of the target chip;

[0156] The adjustment module 64 is used to adjust the frequency of the target chip according to the target frequency, and to adjust the voltage of the target chip according to the target voltage.

[0157] In a possible implementation, the obtaining module 61 is used to:

[0158] The first power consumption candidate value is determined by the temperature control module according to the current temperature of the target chip and the corresponding relationship between temperature and power consumption.

[0159] In a possible implementation, the at least two power consumption management modules include a performance state management module;

[0160] The obtaining module 61 is used for:

[0161] Determining, by the performance state management module, a target performance state level of the target chip according to information about a current workload of a processor in the target chip;

[0162] According to the target performance state level, a second power consumption candidate value is determined.

[0163] In a possible implementation, the at least two power consumption management modules include an overclocking management module;

[0164] The obtaining module 61 is used for:

[0165] A third power consumption candidate value input by a user is obtained through the overclocking management module.

[0166] In a possible implementation, the first determining module 62 is configured to:

[0167] In the case where a preset overclocking operation condition is met, determining the third power consumption candidate value as the target power consumption of the target chip;

[0168] or,

[0169] In the case where the preset overclocking operation condition is not met, determining the minimum value of the at least two candidate power consumption values ​​as the target power consumption of the target chip;

[0170] The preset overclocking operation condition includes: the candidate power consumption values ​​output by each power consumption management module except the overclocking management module in the at least two power consumption management modules are all preset maximum power consumption values.

[0171] In a possible implementation, the first determining module 62 is configured to:

[0172] The minimum value of the at least two candidate power consumption values ​​is determined as the target power consumption of the target chip.

[0173] In a possible implementation, the second determining module 63 is used to:

[0174] Determining a target frequency of the target chip according to the target power consumption and the actual power consumption of the target chip;

[0175] The target voltage of the target chip is determined according to the target frequency and the corresponding relationship between frequency and voltage.

[0176] In a possible implementation, the second determining module 63 is used to:

[0177] Determining a power consumption difference according to the target power consumption and the actual power consumption of the target chip;

[0178] The target frequency of the target chip is determined according to the power consumption difference by a proportional-integral-differential controller.

[0179] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. Its specific implementation and technical effects can refer to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0180] The present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above method is implemented. The computer-readable storage medium may be a non-volatile computer-readable storage medium, or may be a volatile computer-readable storage medium.

[0181] The embodiment of the present disclosure further provides a computer program, including a computer-readable code. When the computer-readable code is executed in an electronic device, a processor in the electronic device executes the above method.

[0182] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in an electronic device, a processor in the electronic device executes the above method.

[0183] An embodiment of the present disclosure also provides an electronic device, comprising: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to call the executable instructions stored in the memory to execute the above method.

[0184] The electronic device may be provided as a terminal, a server, or a device in other forms.

[0185] Figure 7 1 is a block diagram of an electronic device 1900 provided in an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a terminal or a server. Figure 7 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0186] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (MacOS X TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or similar.

[0187] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0188] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0189] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0190] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0191] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0192] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0193] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0194] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0195] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0196] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0197] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0198] If the technical solution of the embodiments of the present disclosure involves personal information, the product using the technical solution of the embodiments of the present disclosure has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of the embodiments of the present disclosure involves sensitive personal information, the product using the technical solution of the embodiments of the present disclosure has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the requirement of "explicit consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to collect his or her personal information; or on the device for processing personal information, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0199] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A chip power consumption control method, characterized in that: include: Obtaining at least two power consumption candidate values ​​through at least two power consumption management modules of the target chip, wherein each of the at least two power consumption management modules outputs a power consumption candidate value respectively, the at least two power consumption management modules include a temperature control module, and the at least two power consumption candidate values ​​include a first power consumption candidate value output by the temperature control module; Determining the target power consumption of the target chip according to the at least two candidate power consumption values; Determining a target frequency and a target voltage of the target chip according to the target power consumption and the actual power consumption of the target chip; The frequency of the target chip is adjusted according to the target frequency, and the voltage of the target chip is adjusted according to the target voltage.

2. The method according to claim 1, characterized in that The obtaining at least two candidate power consumption values ​​through at least two power consumption management modules of the target chip includes: The first power consumption candidate value is determined by the temperature control module according to the current temperature of the target chip and the corresponding relationship between temperature and power consumption.

3. The method according to claim 1, characterized in that: The at least two power consumption management modules include a performance state management module; The obtaining at least two candidate power consumption values ​​through at least two power consumption management modules of the target chip includes: Determining, by the performance state management module, a target performance state level of the target chip according to information about a current workload of a processor in the target chip; According to the target performance state level, a second power consumption candidate value is determined.

4. The method according to claim 1, characterized in that: The at least two power consumption management modules include an overclocking management module; The obtaining at least two candidate power consumption values ​​through at least two power consumption management modules of the target chip includes: A third power consumption candidate value input by a user is obtained through the overclocking management module.

5. The method according to claim 4, characterized in that The step of determining the target power consumption of the target chip according to the at least two candidate power consumption values ​​includes: In the case where a preset overclocking operation condition is met, determining the third power consumption candidate value as the target power consumption of the target chip; or, In the case where the preset overclocking operation condition is not met, determining the minimum value of the at least two candidate power consumption values ​​as the target power consumption of the target chip; The preset overclocking operation condition includes: the candidate power consumption values ​​output by each power consumption management module except the overclocking management module in the at least two power consumption management modules are all preset maximum power consumption values.

6. The method according to any one of claims 1 to 4, characterized in that The step of determining the target power consumption of the target chip according to the at least two candidate power consumption values ​​includes: The minimum value of the at least two candidate power consumption values ​​is determined as the target power consumption of the target chip.

7. The method according to any one of claims 1 to 4, characterized in that The step of determining a target frequency and a target voltage of the target chip according to the target power consumption and the actual power consumption of the target chip comprises: Determining a target frequency of the target chip according to the target power consumption and the actual power consumption of the target chip; The target voltage of the target chip is determined according to the target frequency and the corresponding relationship between frequency and voltage.

8. The method according to claim 7, characterized in that The step of determining the target frequency of the target chip according to the target power consumption and the actual power consumption of the target chip comprises: Determining a power consumption difference according to the target power consumption and the actual power consumption of the target chip; The target frequency of the target chip is determined according to the power consumption difference by a proportional-integral-differential controller.

9. A chip power consumption control device, characterized in that: include: An obtaining module, configured to obtain at least two power consumption candidate values ​​through at least two power consumption management modules of a target chip, wherein each of the at least two power consumption management modules outputs a power consumption candidate value respectively, the at least two power consumption management modules include a temperature control module, and the at least two power consumption candidate values ​​include a first power consumption candidate value output by the temperature control module; A first determining module, configured to determine a target power consumption of the target chip according to the at least two candidate power consumption values; A second determining module, used to determine a target frequency and a target voltage of the target chip according to the target power consumption and the actual power consumption of the target chip; The adjustment module is used to adjust the frequency of the target chip according to the target frequency, and to adjust the voltage of the target chip according to the target voltage.

10. An electronic device, characterized in that: include: one or more processors; a memory for storing executable instructions; The one or more processors are configured to call the executable instructions stored in the memory to execute the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

12. A computer program product comprising computer readable code, or a non-volatile computer readable storage medium carrying computer readable code, characterized in that: When the computer readable code is executed in an electronic device, a processor in the electronic device executes the method according to any one of claims 1 to 8.

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