Electronic device

Abstract

The invention provides an electronic device. The electronic device includes: a display layer; and a sensor layer disposed on the display layer and defining a sensing area and a peripheral area adjacent to the sensing area, in which the sensor layer includes: first electrodes extending in a first direction and arranged in a second direction crossing the first direction; a second electrode extending in the second direction and arranged in the first direction; a third electrode extending in the first direction and electrically insulated from the first electrode; a fourth electrode extending in the second direction and electrically insulated from the second electrode; first traces electrically connected to the first electrodes, respectively, in which the plurality of first traces overlap the peripheral region; and a sub-trace electrically connected to a portion of the first trace and overlapping the sensing area.

Description

Technical Field

[0001] The present disclosure relates to electronic devices capable of detecting pen input. Background Art

[0002] Multimedia electronic devices such as televisions, mobile phones, tablet computers, laptop computers, navigators, and game consoles include display devices for visual output. In addition to traditional input methods such as buttons, keyboards, and mice, these devices typically include a sensor layer that enables touch-based input for intuitive and convenient control. The sensor layer detects touch or pressure from the user. There is an increasing demand for pen input that provides precise touch input for users who are accustomed to using writing tools or specific applications such as sketching or drawing applications. Summary of the invention

[0003] The present disclosure provides an electronic device capable of detecting pen input and featuring a reduced peripheral area.

[0004] An embodiment of the present invention provides an electronic device, which includes: a display layer configured to display an image; and a sensor layer disposed on the display layer and defining a sensing area and a peripheral area adjacent to the sensing area, wherein the sensor layer includes: a plurality of first electrodes extending in a first direction and arranged in a second direction intersecting the first direction; a plurality of second electrodes extending in a second direction and arranged in the first direction; a third electrode extending in the first direction and electrically insulated from the first electrode; a fourth electrode extending in the second direction and electrically insulated from the second electrode; a plurality of first traces electrically connected to the first electrodes, respectively, wherein the plurality of first traces overlap with the peripheral area; and a sub-trace electrically connected to a portion of the first trace and overlapping with the sensing area.

[0005] The first trace and the sub trace are disposed on different layers from each other.

[0006] Each of the first electrode and the second electrode and each of the third electrode and the fourth electrode are provided on different layers from each other.

[0007] The sensor layer further includes: a first insulating layer covering the third electrode and the fourth electrode; and a second insulating layer disposed on the first insulating layer, wherein the second insulating layer covers the first electrode and the second electrode.

[0008] The sensor layer further includes a base layer disposed below the first insulating layer, each of the first traces is disposed on the first insulating layer, and the sub-traces are disposed on the base layer.

[0009] The sub-trace overlaps the first electrode.

[0010] The sensor layer also includes: a base layer disposed below the first insulating layer; and a third insulating layer disposed between the base layer and the first insulating layer, wherein each of the first traces is disposed on the first insulating layer, and the sub-traces are disposed on the base layer between the base layer and the third insulating layer.

[0011] The sub-trace overlaps at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode.

[0012] The sensor layer further includes a plurality of dummy patterns overlapping the first electrode and the second electrode.

[0013] The sub-traces are arranged between the dummy patterns on the plane.

[0014] The third electrode includes a plurality of first auxiliary electrodes extending in the first direction and arranged in the second direction, and the fourth electrode includes a plurality of second auxiliary electrodes extending in the second direction and arranged in the first direction, wherein a first coupling capacitor is arranged between a first electrode in the first electrodes and a first auxiliary electrode in the first auxiliary electrodes, and a second coupling capacitor is arranged between a second electrode in the second electrodes and a second auxiliary electrode in the second auxiliary electrodes.

[0015] The sub-trace is disposed in a plane between the first auxiliary electrode and the second auxiliary electrode.

[0016] Each of the second auxiliary electrodes includes a 2-1st auxiliary electrode and a 2-2nd auxiliary electrode spaced apart from each other in the second direction, and the sub-trace is disposed between the 2-1st auxiliary electrode and the 2-2nd auxiliary electrode on a plane.

[0017] Each of the first electrodes includes: a first main electrode electrically connected to the sub-trace; and a first sub-electrode electrically insulated from the sub-trace.

[0018] The sub-trace overlaps two or more of the first sub-electrodes.

[0019] At least one of the first sub-electrodes is disposed between the first main electrode and the two or more first sub-electrodes overlapping the sub-trace.

[0020] Each of the sub-trace and the first main electrode is provided in plural, and the first main electrode is provided at an uppermost end of the first electrode in the second direction.

[0021] The first traces include: a plurality of 1-1th traces connected to a first end of each of the first electrodes; and a plurality of 1-2th traces connected to a second end of each of the first electrodes opposite to the first end in the first direction.

[0022] The first electrodes include: a 1-1th electrode connected to a 1-1th trace; and a 1-2th electrode connected to a 1-2th trace.

[0023] The sub-traces include: a first sub-trace electrically connected to a portion of the 1-1th trace; and a second sub-trace electrically connected to a portion of the 1-2th trace.

[0024] The first sub-trace and the second sub-trace are spaced apart from each other in the first direction.

[0025] The electronic device further includes: a plurality of second traces electrically connected to the second electrodes; a third trace electrically connected to the third electrodes; and a fourth trace electrically connected to the fourth electrodes.

[0026] The first and third traces are spaced apart from each other with the first and third electrodes therebetween, and the second and fourth traces are spaced apart from each other with the second and fourth electrodes therebetween.

[0027] The third trace overlaps the sub-trace.

[0028] A contact hole is provided in the sensor layer, through which the first trace and the sub-trace are connected to each other.

[0029] The contact hole overlaps the peripheral region.

[0030] The electronic device also includes a sensor driver configured to drive the sensor layer and operate in a first mode for sensing a touch input and a second mode for sensing a pen input.

[0031] An embodiment of the present invention provides an electronic device, which includes: a sensor layer, including a plurality of first electrodes, a plurality of second electrodes, a plurality of first auxiliary electrodes, a plurality of second auxiliary electrodes and a plurality of traces; and a sensor driver, configured to drive the sensor layer and operate in a first mode of sensing touch input and a second mode of sensing pen input, wherein a first coupling capacitor is arranged between a first electrode among the plurality of first electrodes and a first auxiliary electrode among the first auxiliary electrodes, and a second coupling capacitor is arranged between a second electrode among the plurality of second electrodes and a second auxiliary electrode among the second auxiliary electrodes, wherein the trace includes: a plurality of first traces, respectively electrically connected to the first electrodes; and a sub-trace, overlapping with a portion of the plurality of first electrodes and configured to electrically connect a portion of the first trace to the sensor driver.

[0032] The first trace and the sub trace are disposed on different layers from each other.

[0033] The sensor layer further includes: a first insulating layer covering the first auxiliary electrode and the second auxiliary electrode; and a second insulating layer disposed on the first insulating layer and covering the first electrode and the second electrode.

[0034] The sensor layer further includes a base layer disposed below the first insulating layer, each of the first traces is disposed on the first insulating layer, and the sub-traces are disposed on the base layer.

[0035] The sensor layer defines a sensing region and a peripheral region adjacent to the sensing region, and the first electrode, the second electrode, the first auxiliary electrode, and the second auxiliary electrode overlap the sensing region, and the first trace overlaps the peripheral region.

[0036] A first portion of the sub-trace overlaps the sensing area, and a second portion of the sub-trace overlaps the peripheral area.

[0037] A contact hole is provided in the sensor layer, the first trace and the sub trace are connected to each other through the contact hole, and the contact hole overlaps the peripheral area.

[0038] An embodiment of the present invention provides an electronic device, which includes: a display layer configured to display an image; a sensor layer disposed on the display layer and defining a sensing area and a peripheral area adjacent to the sensing area; and a sensor driver configured to apply a signal to the sensor layer, wherein the sensor layer includes: a plurality of first electrodes extending in a first direction and arranged in a second direction intersecting the first direction; a plurality of second electrodes extending in the second direction and arranged in the first direction; and a first trace connected to at least one of the first electrodes to transmit a signal to the first electrode, wherein the first trace includes: a first portion connected to the first electrode, overlapping the peripheral area, and extending in the second direction; and a second portion connected to the sensor driver, overlapping the sensing area, and extending in the second direction.

[0039] The sensor layer further includes a pad portion connected to the sensor driver, the first portion is disposed between the first electrode and the second portion, and the second portion is disposed between the first portion and the pad portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In the attached picture:

[0041] Figure 1A is a perspective view of an electronic device according to an embodiment of the inventive concept;

[0042] Figure 1B is a rear perspective view of an electronic device according to an embodiment of the inventive concept;

[0043] Figure 2 is a perspective view of an electronic device according to an embodiment of the inventive concept;

[0044] Figure 3 is a perspective view of an electronic device according to an embodiment of the inventive concept;

[0045] Figure 4 is a cross-sectional view of an electronic device according to an embodiment of the inventive concept;

[0046] Figure 5A is a cross-sectional view of an electronic device according to an embodiment of the inventive concept;

[0047] Figure 5B is a cross-sectional view of an electronic device according to an embodiment of the inventive concept;

[0048] Figure 6 is a schematic cross-sectional view of a display panel according to an embodiment of the inventive concept;

[0049] Figure 7 is a view for explaining an operation of an electronic device according to an embodiment of the inventive concept;

[0050] Figure 8 is a cross-sectional view of a display panel according to an embodiment of the inventive concept;

[0051] Fig. 9 is a plan view of a sensor layer according to an embodiment of the present inventive concept;

[0052] Fig.10 yes Fig. 9 An enlarged view of the area AA';

[0053] Fig.11A is a plan view showing a first conductive layer of a sensing unit according to an embodiment of the inventive concept;

[0054] Fig. 11B is a plan view showing a second conductive layer of a sensing unit according to an embodiment of the inventive concept;

[0055] Fig.12 is a sensor layer according to an embodiment of the present inventive concept along Fig.11A and Fig. 11B A cross-sectional view taken along line II' in each of the figures;

[0056] Fig.13 yes Fig.11A An enlarged view of the region DD';

[0057] Fig.14 yes Fig. 9 An enlarged view of region BB';

[0058] Fig.15Ais a plan view showing a first conductive layer of a sensing unit according to an embodiment of the inventive concept;

[0059] Fig. 15B is a plan view showing a second conductive layer of a sensing unit according to an embodiment of the inventive concept;

[0060] Fig.16A is a plan view showing a first conductive layer according to another embodiment of the inventive concept;

[0061] Fig. 16B is an enlarged plan view of a sensing unit according to another embodiment of the inventive concept;

[0062] Fig.17A is a sensor layer according to an embodiment of the present inventive concept along Fig.15A and Fig. 15B A cross-sectional view taken along line II-II' in each of the figures;

[0063] Fig. 17B is a sensor layer according to another embodiment of the present invention. Fig.15A and Fig. 15B A cross-sectional view taken along line II-II' in each of the figures;

[0064] Fig.18A yes Fig.15A An enlarged view of region EE';

[0065] Fig.18B According to another embodiment of the present invention Fig.15A An enlarged view of region EE';

[0066] Fig.19A yes Fig. 9 An enlarged view of the region CC';

[0067] Fig.19B is a sensor layer according to an embodiment of the present invention along Fig.19A A cross-sectional view taken along line III-III';

[0068] Fig.19C is a sensor layer according to another embodiment of the present invention. Fig.19A A cross-sectional view taken along line III-III';

[0069] Fig.19D is a sensor layer according to another embodiment of the present invention. Fig.19A A cross-sectional view taken along line III-III';

[0070] Fig. 20A is a plan view showing a portion of a sensor layer according to an embodiment of the present inventive concept;

[0071] Fig. 20B is a plan view showing a portion of a sensor layer according to another embodiment of the present invention;

[0072] Fig. 20C is a plan view showing a portion of a sensor layer according to another embodiment of the present invention;

[0073] Fig.21A and Fig. 21B is a view for explaining a second mode of embodiment according to the inventive concept; and

[0074] Fig.22A and Fig. 22B is a view for explaining a second mode of embodiment according to the inventive concept. DETAILED DESCRIPTION

[0075] As shown in the accompanying drawings and described in detail herein, the inventive concept can be implemented in various modified embodiments. However, this is not to limit the inventive concept to these specific embodiments. It should be understood that the inventive concept encompasses all modifications, equivalents and substitutions that fall within the scope and spirit of the inventive concept.

[0076] In this specification, it will also be understood that when a component (or region, layer, portion) is referred to as being "on," "connected to" or "coupled to" another component, it may be directly disposed on the other component, directly connected / coupled to the other component, or an intervening third component may also be present.

[0077] Throughout the specification, the same reference numerals may refer to the same elements. In addition, in the drawings, the thickness, ratio, and size of components may be exaggerated for the purpose of clear description.

[0078] The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0079] It will be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one component from other components. For example, an element referred to as a first element in an embodiment may be referred to as a second element in another embodiment. Unless otherwise specified, terms in the singular may include plural forms.

[0080] In addition, relative positions of components shown in the drawings are described using “under,” “below,” “over,” “upper,” etc. These terms may be used as relative concepts and are described relative to the directions depicted in the drawings.

[0081] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the inventive concept belongs. In addition, terms, such as terms in commonly used dictionaries, are to be interpreted as having a meaning consistent with their meaning in the context of the relevant technology.

[0082] The meaning of “include” or “comprise” is to list properties, fixed numbers, steps, operations, elements, parts or their combinations, but not to exclude other properties, fixed numbers, steps, operations, elements, parts or their combinations.

[0083] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0084] Figure 1A is a perspective view of an electronic device according to an embodiment of the inventive concept. Figure 1B is a rear perspective view of an electronic device according to an embodiment of the inventive concept.

[0085] refer to Figure 1A and Figure 1B , the electronic device 1000 may be a device activated according to an electrical signal. For example, the electronic device 1000 may display an image and sense an input applied from the outside. In other words, the electronic device 1000 may display an image and detect an external input. The external input may be an input by a user. The user's input may include various types of external inputs such as a part of the user's body, a pen PN, light, heat, or pressure.

[0086] The electronic device 1000 may include a first display panel DP1 and a second display panel DP2. The first display panel DP1 and the second display panel DP2 may be separate panels separated from each other. The first display panel DP1 may be a main display panel, and the second display panel DP2 may be an auxiliary display panel or an external display panel.

[0087] The display surface IS of the first display panel DP1 may be divided into a first display portion DA1-F and a non-display area NDA. The first display portion DA1-F may be an area in which a first image IM1a is displayed. A user views the first image IM1a through the first display portion DA1-F. The non-display area NDA may be arranged around the first display portion DA1-F.

[0088] The second display panel DP2 may include a second display portion DA2-F. The surface area of ​​the second display panel DP2 may be smaller than that of the first display panel DP1. The surface area of ​​the first display portion DA1-F may be larger than that of the second display portion DA2-F to match the size of the first display panel DP1 and the size of the second display panel DP2.

[0089] In a state where the electronic device 1000 is unfolded, the first display portion DA1-F may have a plane substantially parallel to the first direction DR1 and the second direction DR2. The thickness direction of the electronic device 1000 may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Therefore, the front surface (or top surface) and the rear surface (or bottom surface) of each of the components constituting the electronic device 1000 may be defined based on the third direction DR3.

[0090] The first display panel DP1 or the first display portion DA1-F may include a folding area FA that can be folded and unfolded and a plurality of non-folding areas NFA1 and NFA2 spaced apart from each other, wherein the folding area FA is between the plurality of non-folding areas NFA1 and NFA2. The second display panel DP2 may overlap one of the plurality of non-folding areas NFA1 and NFA2. For example, the second display panel DP2 may overlap the first non-folding area NFA1.

[0091] The display direction of the first image IM1a displayed on a portion of the first display panel DP1 (e.g., the first non-folding area NFA1) and the display direction of the second image IM2a displayed on the second display panel DP2 may be opposite to each other. For example, the first image IM1a may be displayed in a third direction DR3, and the second image IM2a may be displayed in a fourth direction DR4 opposite to the third direction DR3.

[0092] In an embodiment of the present inventive concept, the folding area FA may be bent relative to a folding axis extending in a direction parallel to the long side of the electronic device 1000 (e.g., in a direction parallel to the second direction DR2). When the electronic device 1000 is folded, the folding area FA may have a predetermined curvature and a radius of curvature. For example, when the electronic device 1000 is folded, the folding area FA may have a specific curvature and a radius of curvature. The electronic device 1000 may be folded inward (folded inwardly) so that the first non-folding area NFA1 and the second non-folding area NFA2 face each other and the first display portion DA1-F is not exposed to the outside.

[0093] In an embodiment of the inventive concept, the electronic device 1000 may be folded outward (folded outward) so that the first display portion DA1-F is exposed to the outside. In an embodiment of the inventive concept, the electronic device 1000 may be foldable inwardly and outwardly in an unfolded state, but is not limited thereto.

[0094] exist Figure 1A, an example of setting one folding area FA in the electronic device 1000 is shown, but it is not limited thereto. For example, the electronic device 1000 may include multiple folding axes and multiple folding areas corresponding thereto, and the electronic device 1000 may be folded inwardly or outwardly in each of the multiple folding areas in the unfolded state.

[0095] According to an embodiment of the inventive concept, at least one of the first display panel DP1 and the second display panel DP2 may sense the input of the pen PN even without including a digitizer. Since the digitizer for sensing the pen PN is omitted, an increase in thickness, weight, and flexibility of the electronic device 1000 due to the digitizer may not occur. Therefore, not only the first display panel DP1 but also the second display panel DP2 may be designed to sense the pen PN.

[0096] Figure 2 is a perspective view of an electronic device according to an embodiment of the inventive concept. Figure 3 is a perspective view of an electronic device according to an embodiment of the inventive concept.

[0097] Figure 2 An example is shown in which the electronic device 1000 - 1 is a mobile phone and the electronic device 1000 - 1 may include a display panel DP. Figure 3 An example is shown in which the electronic device 1000 - 2 is a laptop computer and the electronic device 1000 - 2 may include a display panel DP.

[0098] In an embodiment of the inventive concept, the display panel DP may sense an input applied from the outside. The external input may be an input of a user. The input of the user may include, for example, a part of the user's body, a pen PN (see Figure 1A ), various types of external inputs such as light, heat or pressure.

[0099] According to an embodiment of the inventive concept, even if the display panel DP does not include a digitizer, the display panel DP can sense the input of the pen PN. Since the digitizer for sensing the pen PN is omitted, the increase in thickness, weight, and flexibility of the electronic device 1000-1 or 1000-2 due to the digitizer may not occur.

[0100] exist Figure 1A In the example, a foldable electronic device 1000 may be shown, and Figure 2 In the embodiment, a bar-type electronic device 1000-1 may be shown as an example. However, the present disclosure to be described below is not limited thereto. For example, the description provided below may be applied to various electronic devices such as a rollable electronic device, a slidable electronic device, and a stretchable electronic device.

[0101] Figure 4is a cross-sectional view of an electronic device 1000 according to an embodiment of the inventive concept. Figure 4 The cross-sectional view shown in FIG. 1 may be a diagram showing an electronic device 1000 including Figure 1A 000 is a cross-sectional view of a portion of the first display panel DP1 of the electronic device 1000 shown in FIG.

[0102] refer to Figure 4 , the electronic device 1000 may include a first display panel DP1, an upper functional layer and a lower functional layer. The upper functional layer may include a component disposed above the first display panel DP1, and the lower functional layer may include a component disposed below the first display panel DP1.

[0103] The first display panel DP1 may be configured to generate an image and sense an external input. For example, the first display panel DP1 may include a display layer 100 (see Figure 6 ) and sensor layer 200 (see Figure 6 ).

[0104] The upper functional layer may include a protective layer PL, a window WD, an impact absorbing layer DL, and first, second, and third adhesive layers PSA1, PSA2, and PSA3. The components included in the upper functional layer are not limited to the components described above. At least some of the components described above may be omitted, and other components may be added.

[0105] The protection layer PL may protect components disposed under the protection layer PL. The protection layer PL may have a thickness of 60 micrometers to 70 micrometers (eg, about 65 micrometers), but the thickness of the protection layer PL is not limited thereto.

[0106] A hard coating layer, an anti-fingerprint layer, etc. may be additionally provided on the protective layer PL to improve properties such as chemical resistance and wear resistance. For example, the hard coating layer may be a functional layer for improving the use characteristics of the electronic device 1000, and may be applied on the protective layer PL. For example, anti-fingerprint properties, anti-pollution properties, and anti-scratch properties may be improved by the hard coating layer. The thickness of the hard coating layer may be about 5 microns, but is not particularly limited thereto.

[0107] The window WD may be disposed under the protective layer PL. The first adhesive layer PSA1 may be disposed between the window WD and the protective layer PL. The first adhesive layer PSA1 may be in direct contact with the window WD and the protective layer PL. The first adhesive layer PSA1 may have a thickness of 30 to 40 microns (e.g., about 35 microns), and the thickness of the first adhesive layer PSA1 is not limited thereto. In an embodiment of the inventive concept, a frame pattern may be disposed between the first adhesive layer PSA1 and the protective layer PL.

[0108] The window WD may include an optically transparent insulating material. For example, the window WD may include a glass substrate or a synthetic resin film. The window WD may have a single-layer structure or a multi-layer structure. For example, the window WD may include a plurality of plastic films bonded to each other by using an adhesive, or may include a glass substrate and a plastic film bonded to each other by using an adhesive. When the window WD is a glass substrate, the window WD may have a thickness of 80 microns or less, and may have a thickness of, for example, about 30 microns, but the thickness of the window WD is not limited thereto.

[0109] The impact absorbing layer DL may be disposed below the window WD. The second adhesive layer PSA2 may be disposed between the window WD and the impact absorbing layer DL. The second adhesive layer PSA2 may be in direct contact with the window WD and the impact absorbing layer DL. The second adhesive layer PSA2 may have a thickness of 70 to 80 microns (e.g., about 75 microns), and the thickness of the second adhesive layer PSA2 is not limited thereto.

[0110] The impact absorbing layer DL may protect the first display panel DP1 by absorbing the impact applied to the first display panel DP1. The impact absorbing layer DL may be a stretch film. For example, the impact absorbing layer DL may include a flexible plastic material. The flexible plastic material may be a synthetic resin film. For example, the impact absorbing layer DL may include a flexible plastic material such as polyimide or polyethylene terephthalate. The impact absorbing layer DL may have a thickness of 18 to 28 microns (e.g., about 23 microns), but the thickness of the impact absorbing layer DL is not limited thereto. In an embodiment of the inventive concept, the impact absorbing layer DL may be omitted.

[0111] The third adhesive layer PSA3 may be disposed between the impact absorbing layer DL and the first display panel DP1. The third adhesive layer PSA3 may be in direct contact with the impact absorbing layer DL and the first display panel DP1. The third adhesive layer PSA3 may have a thickness of 45 micrometers to 55 micrometers (eg, about 50 micrometers), and the thickness of the third adhesive layer PSA3 is not limited thereto.

[0112] The lower functional layer may include a protective film PF, a plate PLT, a cover layer CVL, a shielding layer MMP, a lower sheet CUS, an insulating film PET, and step compensation members ARS1, ARS2, and ARS3, and a fourth adhesive layer PSA4, a fifth adhesive layer PSA5, and a sixth adhesive layer PSA6. The components included in the lower functional layer are not limited to the components described above. At least part of the components described above may be omitted, and other components may be added.

[0113] The protective film PF may be coupled to the rear surface of the first display panel DP1 through the fourth adhesive layer PSA4. For example, the fourth adhesive layer PSA4 may be in direct contact with the protective film PF and the first display panel DP1. The fourth adhesive layer PSA4 may have a thickness of 20 micrometers to 30 micrometers (e.g., about 25 micrometers), and the thickness of the fourth adhesive layer PSA4 is not limited thereto.

[0114] The protective film PF may prevent scratches occurring on the rear surface of the first display panel DP1 during the process of manufacturing the first display panel DP1. The protective film PF may be a colored polyimide film. For example, the protective film PF may be an opaque yellow film, but is not limited thereto. The protective film PF may have a thickness of 45 micrometers to 55 micrometers (e.g., about 50 micrometers), but the thickness of the protective film PF is not limited thereto.

[0115] The plate PLT may be disposed under the protective film PF. The fifth adhesive layer PSA5 may be disposed between the plate PLT and the protective film PF. The fifth adhesive layer PSA5 may bond the plate PLT to the protective film PF. The fifth adhesive layer PSA5 may have a thickness of 11 micrometers to 21 micrometers (e.g., about 16 micrometers), and the thickness of the fifth adhesive layer PSA5 is not limited thereto.

[0116] The plate PLT may include carbon fiber reinforced plastic (CFRP), metal or metal alloy. The plate PLT may support a component disposed thereon. The opening PH may be formed or disposed in a portion of the plate PLT. For example, the plate PLT may include openings PH, each of the openings PH having a shape that passes from the top surface of the plate PLT to the bottom surface of the plate PLT. The opening PH may be in an area overlapping with the folding area FA. When viewed on a plane (for example, in a third direction DR3 or in the thickness direction of the plate PLT), the opening PH may overlap with the folding area FA. Portions of the plate PLT may be more easily deformed due to the opening PH. The plate PLT may have a thickness of 160 to 180 microns (for example, about 170 microns), but the thickness of the plate PLT is not limited thereto.

[0117] The cover layer CVL may be attached to the plate PLT. The cover layer CVL may cover the opening PH of the plate PLT. Therefore, the cover layer CVL may prevent foreign matter from being introduced into the opening PH. The cover layer CVL may include thermoplastic polyurethane, but is not particularly limited thereto. The cover layer CVL may have a thickness of 11 to 21 microns (e.g., about 16 microns), but the thickness of the cover layer CVL is not limited thereto.

[0118] The shielding layer MMP may be disposed below the plate PLT and the cover layer CVL. The sixth adhesive layer PSA6 may be disposed between the shielding layer MMP and the plate PLT. The sixth adhesive layer PSA6 may bond the shielding layer MMP to the plate PLT. The sixth adhesive layer PSA6 may have a thickness of 15 to 25 microns (e.g., about 20 microns), and the thickness of the sixth adhesive layer PSA6 is not limited thereto.

[0119] The shielding layer MMP may include magnetic metal powder. The shielding layer MMP may be a ferrite sheet, a magnetic metal powder layer, a magnetic layer, a magnetic circuit layer, or a magnetic path layer. The shielding layer MMP may shield the magnetic field passing through the first display panel DP1. For example, the shielding layer MMP may guide the direction of the transmitted magnetic field in different directions. Therefore, the magnetic field reaching the shielding layer MMP may be shielded without leaking to the outside (e.g., leaking to the lower side of the shielding layer MMP). The shielding layer MMP may have a thickness of 53 to 63 microns (e.g., about 58 microns), but the thickness of the shielding layer MMP is not limited thereto.

[0120] The lower sheet CUS may be disposed below the shielding layer MMP. The lower sheet CUS may reflect the magnetic field toward the shielding layer MMP. The lower sheet CUS may include a metal or a metal alloy. For example, the lower sheet CUS may include aluminum, copper, or a copper alloy. The lower sheet CUS may have a thickness of 15 to 25 microns (e.g., about 20 microns), but the thickness of the lower sheet CUS is not limited thereto.

[0121] The insulating film PET may be disposed under the lower sheet CUS. The insulating film PET may include polyethylene terephthalate, but is not particularly limited thereto. The insulating film PET may prevent static electricity from being introduced. For example, the insulating film PET may prevent electrical interference between a component disposed on the insulating film PET and a component disposed under the insulating film PET. The thickness of the insulating film PET may be 3 micrometers to 9 micrometers, for example, about 6 micrometers, but the thickness of the insulating film PET is not limited thereto.

[0122] The step compensation members ARS1, ARS2, and ARS3 may include a first step compensation member ARS1 attached to the insulating film PET, a second step compensation member ARS2 attached to the shielding layer MMP, and a third step compensation member ARS3 attached to the shielding layer MMP. The thickness of each of the first step compensation member ARS1, the second step compensation member ARS2, and the third step compensation member ARS3 may be variously set according to the product structure or the component arrangement relationship. For example, the thickness of the first step compensation member ARS1 may be about 90 microns, the thickness of the second step compensation member ARS2 may be about 87 microns, and the thickness of the third step compensation member ARS3 may be about 187 microns, but is not particularly limited thereto.

[0123] In addition, in an embodiment of the present inventive concept, each of the sixth adhesive layer PSA6, the shielding layer MMP, the lower sheet CUS, and the insulating film PET may have a structure that is separated in the region overlapping the folding area FA to form an empty space. For example, each of the sixth adhesive layer PSA6, the shielding layer MMP, the lower sheet CUS, and the insulating film PET may be divided into two parts spaced apart from each other at the region overlapping the folding area FA, with a predetermined gap therebetween. The gap may be 0.6 mm to 1.7 mm, but is not particularly limited thereto.

[0124] Figure 5A is a cross-sectional view of an electronic device according to an embodiment of the inventive concept.

[0125] refer to Figure 5A , the electronic device 1000-1 may include a display panel DP, an upper functional layer, and a lower functional layer. The upper functional layer may include a window WDa, an adhesive layer OCA, and an anti-reflection layer POL, and the lower functional layer may include a protective film PFa, a first lower layer CSL, a shielding layer MMP, and a second lower layer CUSa, a fingerprint sensor FOD, and a cover layer F-CL. The components included in each of the upper functional layer and the lower functional layer are not limited to the components described above. At least part of the components described above may be omitted, and other components may be added.

[0126] The window WDa may include an optically transparent insulating material. For example, the window WDa may include a glass substrate or a synthetic resin film, and may have a multilayer structure or a single-layer structure. For example, the window WDa may be a glass substrate, and in this case, the thickness of the window WDa may be 0.43 mm to 0.53 mm, for example, about 0.48 mm, but the thickness of the window WDa is not limited thereto.

[0127] The anti-reflection layer POL may be disposed under the window WDa. The adhesive layer OCA may be disposed between the anti-reflection layer POL and the window WDa. The thickness of the adhesive layer OCA may be 0.10 mm to 0.20 mm, for example, about 0.15 mm, but the thickness of the adhesive layer OCA is not limited thereto.

[0128] The anti-reflection layer POL can reduce the reflectivity of external light incident from the outside of the electronic device 1000-1. The anti-reflection layer POL may include a stretchable synthetic resin film. For example, the anti-reflection layer POL can be implemented by dyeing an iodine compound to a polyvinyl alcohol film (PVA film). However, this is only an example, and the material forming the anti-reflection layer POL is not limited thereto. The anti-reflection layer POL may have a thickness of 50 microns to 60 microns (e.g., about 55 microns), and the thickness of the anti-reflection layer POL is not limited thereto.

[0129] In an embodiment of the present inventive concept, the anti-reflection layer POL may be omitted. Alternatively, the anti-reflection layer POL may be embedded in the display panel DP. In this case, the anti-reflection layer POL may include a partition wall layer that blocks light and a plurality of color filters, or may include an optical layer that prevents reflection and a partition wall layer that blocks light.

[0130] The protection film PFa may be coupled to the rear surface of the display panel DP. The protection film PFa may have a thickness of 83 micrometers to 93 micrometers (eg, about 88 micrometers), but the thickness of the protection film PFa is not limited thereto.

[0131] The first lower layer CSL may be disposed under the protective film PFa. The first lower layer CSL may have a multi-layer structure. For example, the first lower layer CSL may include an embossed sheet and a buffer layer. The embossed sheet may absorb light passing through the display panel DP. In addition, the embossed sheet may include an embossed pattern to prevent bubbles from being generated when the first lower layer CSL is attached to the protective film PFa. The buffer layer may protect the display panel DP from impact transmitted from the bottom of the display panel DP. The impact resistance of the electronic device 1000-1 may be improved by the buffer layer.

[0132] An opening may be formed in the first lower layer CSL, and the fingerprint sensor FOD may be disposed in the opening. In this case, the first lower layer CSL may include a first portion and a second portion separated from each other by the opening. The fingerprint sensor FOD may be attached to the protective film PFa. In an embodiment of the present inventive concept, the fingerprint sensor FOD may be omitted.

[0133] The shielding layer MMP may be disposed below the first lower layer CSL. The shielding layer MMP may shield the magnetic field passing through the display panel DP. Therefore, the magnetic field reaching the shielding layer MMP may be shielded from leaking to the outside, for example, to the lower side of the shielding layer MMP. The shielding layer MMP may have a thickness of 20 micrometers to 30 micrometers (for example, about 25 micrometers), but the thickness of the shielding layer MMP is not limited thereto.

[0134] The second lower layer CUSa may be disposed below the shielding layer MMP. The second lower layer CUSa may include a metal or a metal alloy. For example, the second lower layer CUSa may include aluminum, copper, or a copper alloy. The second lower layer CUSa may have a thickness of 7 to 17 microns (e.g., about 12 microns), and the thickness of the second lower layer CUSa is not limited thereto.

[0135] An opening corresponding to the area in which the fingerprint sensor FOD is disposed may be formed in the shielding layer MMP and the second lower layer CUSa. The covering layer F-CL may be disposed in the opening in the shielding layer MMP and the second lower layer CUSa, and may cover the opening in the first lower layer CSL. In other words, the covering layer F-CL may be attached to the first lower layer CSL and may cover the fingerprint sensor FOD. In an embodiment, the covering layer F-CL may include a first covering layer MMP-1 and a second covering layer CUS-1, wherein the first covering layer MMP-1 includes the same material as the shielding layer MMP, and the second covering layer CUS-1 includes the same material as the second lower layer CUSa. The first covering layer MMP-1 is disposed on the second covering layer CUS-1 and is positioned closer to the opening in the first lower layer CSL than the second covering layer CUS-1.

[0136] Figure 5B is a cross-sectional view of an electronic device according to an embodiment of the present invention. Figure 5B In the description of Figure 5A Similar components are given like reference numerals, and thus, detailed description thereof will be omitted.

[0137] refer to Figure 5B , the electronic device 1000-1a may not include the cover layer F-CL (see Figure 5A ). The fingerprint sensor FOD may be covered by a sensing circuit board C-FPC that controls the operation of the fingerprint sensor FOD.

[0138] An opening corresponding to the area in which the fingerprint sensor FOD is disposed may be disposed in the shielding layer MMP and the second lower layer CUSa. The sensing circuit board C-FPC may be disposed in the opening disposed in the shielding layer MMP and the second lower layer CUSa, and may cover the opening disposed in the first lower layer CSL. For example, the sensing circuit board C-FPC may overlap with the fingerprint sensor FOD and may be connected to the first lower layer CSL.

[0139] Figure 6 is a schematic cross-sectional view of a display panel according to an embodiment of the inventive concept.

[0140] refer to Figure 6 , the display panel DP may include a display layer 100 and a sensor layer 200 .

[0141] The display layer 100 may be configured to generate an image. The display layer 100 may be an emissive display layer. For example, the display layer 100 may be an organic light-emitting display layer, an inorganic light-emitting display layer, an organic-organic light-emitting display layer, a quantum dot display layer, a micro-light-emitting diode (LED) display layer, or a nano-LED display layer. The display layer 100 may include a base layer 110, a circuit layer 120, a light-emitting element layer 130, and an encapsulation layer 140.

[0142] The base layer 110 may be a member providing a base surface on which the circuit layer 120 is disposed. The base layer 110 may have a single layer structure or a multilayer structure. The base layer 110 may be a glass substrate, a metal substrate, a silicon substrate, or a polymer substrate, but is not particularly limited thereto.

[0143] The circuit layer 120 may be disposed on the base layer 110. The circuit layer 120 may be in direct contact with the base layer 110. The circuit layer 120 may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the base layer 110 in a manner such as coating or vapor deposition, and then the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a plurality of photolithography processes.

[0144] The light emitting element layer 130 may be disposed on the circuit layer 120. The light emitting element layer 130 may be in direct contact with the circuit layer 120. The light emitting element layer 130 may include a light emitting element. For example, the light emitting element layer 130 may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0145] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may also be disposed on the circuit layer 120. The encapsulation layer 140 may protect the light emitting element layer 130 from foreign substances such as moisture, oxygen, and dust particles.

[0146] The sensor layer 200 may be disposed on the display layer 100. For example, the sensor layer 200 may be disposed on the encapsulation layer 140. The sensor layer 200 may sense an external input applied from the outside. The sensor layer 200 may be an integrated sensor continuously formed during a process of manufacturing the display layer 100, or the sensor layer 200 may be an external sensor attached to the display layer 100. The sensor layer 200 may be referred to as a sensor, an input sensor layer, an input sensing panel, or an electronic device for sensing input coordinates.

[0147] According to an embodiment of the inventive concept, the sensor layer 200 can sense input from both a passive input source such as a user's body and an input device that generates a magnetic field at a specific resonant frequency. The input device can be a pen, such as an input pen, a magnetic pen, a stylus pen, or an electromagnetic resonance pen.

[0148] Figure 7 is a view for explaining an operation of an electronic device according to an embodiment of the inventive concept.

[0149] refer to Figure 7 , the electronic device 1000 includes a display layer 100, a sensor layer 200, a display driver 100C, a sensor driver 200C, a main driver 1000C and a power supply circuit 1000P.

[0150] The sensor layer 200 may sense a first input 2000 or a second input 3000 applied from the outside. Each of the first input 2000 and the second input 3000 may be an input from an input unit capable of providing a capacitance change of the sensor layer 200, or an input from an input unit capable of inducing an induced current in the sensor layer 200. For example, the first input 2000 may be an input from a passive input unit such as a user's body. The second input 3000 may be an input using a pen PN or a radio frequency integrated circuit (RFIC) tag. For example, the pen PN may be a passive pen or an active pen.

[0151] In an embodiment of the inventive concept, the pen PN may be a device that generates a magnetic field having a predetermined resonant frequency. The pen PN may be configured to send an output signal based on electromagnetic resonance. The pen PN may also be referred to as an input device, an input pen, a magnetic pen, a stylus pen, or an electromagnetic resonance pen.

[0152] The pen PN may include an RLC resonant circuit, and the RLC resonant circuit may include an inductor L and a capacitor C. In an embodiment of the present inventive concept, the RLC resonant circuit may be a variable resonant circuit whose resonant frequency varies. In this case, the inductor L may be a variable inductor, and / or the capacitor C may be a variable capacitor, but is not particularly limited thereto.

[0153] The inductor L can generate a current by generating a magnetic field in the sensor layer 200. However, the embodiments of the present inventive concept are not particularly limited to this. For example, when the pen PN is operated as an active type, it can generate a current even if the pen PN does not receive a magnetic field from the outside. The generated current can be transferred to the capacitor C. The capacitor C can charge the current input from the inductor L and discharge the charged current to the inductor L. Thereafter, the inductor L can emit a magnetic field at a resonant frequency. The induced current can flow in the sensor layer 200 due to the magnetic field emitted by the pen PN, and the induced current can be sent to the sensor driver 200C as a received signal (or a sensing signal, a signal, etc.).

[0154] The main driver 1000C may control the overall operation of the electronic device 1000. For example, the main driver 1000C may control the operation of the display driver 100C and the sensor driver 200C. The main driver 1000C may include at least one microprocessor and may also include a graphics controller. The main driver 1000C may be an application processor, a central processing unit, or a main processor.

[0155] The display driver 100C may control the display layer 100. The display driver 100C may receive image data and control signals from the main driver 1000C. The control signals may include various signals. For example, the control signals may include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock signal, and a data enable signal.

[0156] The sensor driver 200C may control the sensor layer 200. The sensor driver 200C may receive a control signal from the main driver 1000C. The control signal may include a clock signal of the sensor driver 200C. In addition, the control signal may also include a mode determination signal that determines a driving mode of the sensor driver 200C and the sensor layer 200.

[0157] The sensor driver 200C may be implemented as an integrated circuit (IC) and electrically connected to the sensor layer 200. For example, the sensor driver 200C may be directly mounted on the display panel in a predetermined area, or mounted on a separate printed circuit board using a chip on film (COF) method and electrically connected to the sensor layer 200.

[0158] The sensor driver 200C and the sensor layer 200 may selectively operate in a first mode or a second mode. For example, the first mode may be a mode for sensing a touch input (e.g., the first input 2000). The second mode may be a mode for sensing an input of a pen PN (e.g., the second input 3000). The first mode may be a touch sensing mode, and the second mode may be a pen sensing mode.

[0159] The switch between the first mode and the second mode can be implemented in various ways. For example, the sensor driver 200C and the sensor layer 200 operate in a time-division manner in the first mode and the second mode, allowing it to sense the first input 2000 and the second input 3000. Optionally, the switch between the first mode and the second mode can occur based on the user's selection or a specific action. Activating or deactivating a specific application can also trigger a switch from one mode to another. Optionally, when the sensor driver 200C and the sensor layer 200 sense the first input 2000 while alternating between the first mode and the second mode, the sensor driver 200C and the sensor layer 200 can remain in the first mode, and when sensing the second input 3000, the sensor driver 200C and the sensor layer 200 can remain in the second mode.

[0160] The sensor driver 200C may calculate input coordinate information based on the signal received from the sensor layer 200, and provide a coordinate signal having the coordinate information to the main driver 1000C. The main driver 1000C may perform an operation corresponding to the user input based on the coordinate signal. For example, the main driver 1000C may operate the display driver 100C to display a new application image on the display layer 100.

[0161] The power supply circuit 1000P may include a power management integrated circuit (PMIC). The power supply circuit 1000P may generate a plurality of driving voltages for driving the display layer 100, the sensor layer 200, the display driver 100C, and the sensor driver 200C. For example, the plurality of driving voltages may include a gate high voltage, a gate low voltage, a first driving voltage (e.g., an ELVSS voltage), a second driving voltage (e.g., an ELVDD voltage), an initialization voltage, etc., but is not particularly limited thereto.

[0162] Figure 8 is a cross-sectional view of a display panel according to an embodiment of the inventive concept.

[0163] refer to Figure 8 , at least one buffer layer BFL is disposed on the top surface of the base layer 110. The buffer layer BFL may improve the bonding force between the base layer 110 and the semiconductor pattern. The buffer layer BFL may be provided as a multilayer. Optionally, the display layer 100 may further include a barrier layer. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked.

[0164] A semiconductor pattern including a source region SC, an active region AL, a drain region DR, and a connection signal line SCL may be disposed on the buffer layer BFL. Each of the semiconductor patterns may include polycrystalline silicon. However, each of the semiconductor patterns is not limited thereto and may include amorphous silicon, low temperature polycrystalline silicon, or an oxide semiconductor.

[0165] Figure 8 Some semiconductor patterns are shown; however, additional semiconductor patterns may be provided in other regions. The semiconductor patterns may be arranged across pixels according to specific rules. The semiconductor patterns may have different electrical characteristics depending on whether the semiconductor patterns are doped. The semiconductor pattern may include a first region including a source region SC, a drain region DR, and a connection signal line SCL having high conductivity, and a second region including an active region AL having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a doped region doped with a P-type dopant, and the N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region or may be doped at a concentration lower than that of the first region.

[0166] The conductivity of the first region may be greater than that of the second region and may be used as an electrode or a signal line. The second region may correspond to the active area AL (or channel) of the transistor 100PC. In other words, a portion of the semiconductor pattern (e.g., the active area AL) may be the active area AL of the transistor 100PC, other portions of the semiconductor pattern (e.g., the source region SC and the drain region DR) may be the source region SC or the drain region DR of the transistor 100PC, and another portion of the semiconductor pattern (e.g., the connection signal line SCL) may be a connection electrode or a connection signal line SCL.

[0167] Each of the pixels may have an equivalent circuit including seven transistors, one capacitor, and a light emitting element, and the equivalent circuit diagram of the pixel may be modified in various forms. Figure 8 , one transistor 100PC and a light emitting element 100PE provided in a pixel are shown as an example.

[0168] The source region SC, the active region AL, and the drain region DR of the transistor 100PC may be formed of a semiconductor pattern. The source region SC and the drain region DR may extend from the active region AL in opposite directions in a cross section. Figure 8 A portion of a connection signal line SCL formed of a semiconductor pattern is shown. The connection signal line SCL may be connected to a drain region DR of the transistor 100PC on a plane.

[0169] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap with a plurality of pixels in common and may cover a semiconductor pattern. The first insulating layer 10 may include an inorganic layer and / or an organic layer and have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may include a single-layer silicon oxide layer. The insulating layer of the circuit layer 120 to be described later and the first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the materials described above, but is not limited thereto.

[0170] The gate GT of the transistor 100PC is disposed on the first insulating layer 10. The gate GT may be part of a metal pattern. The gate GT overlaps with the active area AL. The gate GT may be used as a mask in a process of doping or reducing the semiconductor pattern.

[0171] The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate electrode GT. The second insulating layer 20 may overlap with the pixel in common. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the second insulating layer 20 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0172] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may have a single layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0173] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 passing through the first insulating layer 10 to the third insulating layer 30.

[0174] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single silicon oxide layer. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0175] The second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0176] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the second connection electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0177] The light emitting element layer 130 may be disposed on the circuit layer 120. The light emitting element layer 130 may include a light emitting element 100PE. For example, the light emitting element layer 130 may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED. Hereinafter, the light emitting element 100PE is described as an example of an organic light emitting element, but is not particularly limited thereto.

[0178] The light emitting element 100PE may include a first electrode AE, an emission layer EL, and a second electrode CE.

[0179] The first electrode AE ​​may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connection electrode CNE2 through a contact hole CNT-3 passing through the sixth insulating layer 60.

[0180] The pixel defining layer 70 may be disposed on the sixth insulating layer 60 to cover a portion of the first electrode AE. An opening 70-OP is defined in the pixel defining layer 70. The opening 70-OP of the pixel defining layer 70 exposes at least a portion of the first electrode AE.

[0181] The first display part DA1-F (see Figure 1A ) may include an emission region PXA and a non-emission region NPXA adjacent to the emission region PXA. The non-emission region NPXA may surround the emission region PXA. In this embodiment, the emission region PXA may correspond to a portion of the first electrode AE ​​exposed by the opening 70-OP.

[0182] The emission layer EL may be disposed on the first electrode AE. The emission layer EL may be disposed in a region corresponding to the opening 70-OP. In other words, the emission layer EL may be separated for each of the pixels. When the emission layer EL is separated for each of the pixels, each of the emission layers EL may emit light having at least one of blue, red, and green. However, embodiments of the inventive concept are not limited thereto. For example, the emission layer EL may be commonly disposed to be connected to the pixel. In this case, the emission layer EL may provide blue light or white light.

[0183] The second electrode CE may be disposed on the emission layer EL. The second electrode CE may have an integral shape and may be commonly disposed throughout a plurality of pixels.

[0184] In an embodiment of the present inventive concept, a hole control layer may be disposed between the first electrode AE ​​and the emission layer EL. The hole control layer may be commonly disposed in the emission region PXA and the non-emission region NPXA. The hole control layer may include a hole transport layer and may further include a hole injection layer. The electron control layer may be disposed between the emission layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer. The hole control layer and the electron control layer may be commonly disposed in the pixel by using an open mask or an inkjet process.

[0185] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may include an inorganic layer, an organic layer, and an inorganic layer stacked sequentially, but the layers constituting the encapsulation layer 140 are not limited thereto. The inorganic layer may protect the light emitting element layer 130 from moisture and oxygen, and the organic layer may protect the light emitting element layer 130 from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include an acrylic-based organic layer, but embodiments of the inventive concept are not limited thereto.

[0186] The sensor layer 200 may include a sensor base layer (or base layer) 201 , a first conductive layer 202 , a sensor insulating layer (or first insulating layer) 203 , a second conductive layer 204 , and a cover insulating layer (or second insulating layer) 205 .

[0187] The sensor base layer 201 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the sensor base layer 201 may be an organic layer including epoxy resin, acrylic resin, or imide-based resin. The sensor base layer 201 may have a single-layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3.

[0188] Each of the first conductive layer 202 and the second conductive layer 204 may have a single layer structure or a multilayer structure in which a plurality of layers are stacked in the third direction DR3. Figure 8 204 are shown in the figure, but are not limited thereto. For example, a third conductive layer and a fourth conductive layer may be provided, which are spaced apart from each other in the third direction DR3 and have an insulating layer therebetween. In particular, at least one of the third conductive layer and the fourth conductive layer may be provided under the display layer 100.

[0189] Each of the first conductive layer 202 and the second conductive layer 204, each having a single-layer structure, may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire, graphene, etc.

[0190] Each of the first conductive layer 202 and the second conductive layer 204, each having a multi-layer structure, may include a metal layer. The metal layer may have a three-layer structure of titanium / aluminum / titanium. The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0191] At least one of the sensor insulating layer 203 and the cover insulating layer 205 may include an inorganic layer. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0192] At least one of the sensor insulating layer 203 and the cover insulating layer 205 may include an organic layer. The organic layer may include at least one of acrylic-based resin, methacrylic-based resin, polyisoprene-based resin, vinyl-based resin, epoxy-based resin, polyurethane-based resin, cellulose-based resin, siloxane-based resin, polyimide-based resin, polyamide-based resin, and perylene-based resin.

[0193] Fig. 9 is a plan view of a sensor layer according to an embodiment of the inventive concept. Fig.10 yes Fig. 9 For example, Fig.10 is an enlarged plan view of a sensing unit SU according to an embodiment of the inventive concept. Fig.11A is a plan view illustrating a first conductive layer of a sensing unit according to an embodiment of the inventive concept. Fig. 11B is a plan view illustrating a second conductive layer of a sensing unit according to an embodiment of the inventive concept. Fig.12 is a sensor layer according to an embodiment of the present inventive concept along Fig.11A and Fig. 11B A cross-sectional view taken along line II' in each of the FIGS. Fig.13 yes Fig.11A Magnified view of region DD'.

[0194] refer to Fig. 9, the sensor layer 200 may include a sensing region 200A sensing an external input and a peripheral region 200NA adjacent to the sensing region 200A.

[0195] The sensor layer 200 may include a plurality of first electrodes 210, a plurality of second electrodes 220, a plurality of third electrodes 230, and a plurality of fourth electrodes 240. The plurality of first electrodes 210, the plurality of second electrodes 220, the plurality of third electrodes 230, and the plurality of fourth electrodes 240 may be disposed in the sensing region 200A. The first electrodes 210 and the third electrodes 230 may be electrically insulated from each other, and the second electrodes 220 and the fourth electrodes 240 may be electrically insulated from each other.

[0196] The sensor layer 200 may include a plurality of traces TL connected to the first electrode 210, the second electrode 220, the third electrode 230, and the fourth electrode 240. The trace TL may include a plurality of first traces 210t connected to the first electrode 210, a plurality of second traces 220t connected to the second electrode 220, a plurality of third traces 230t connected to the third electrode 230, a plurality of fourth traces 240rt1 and a fifth trace 240rt2 connected to the fourth electrode 240, and a sub-trace ST connected to at least a portion of the first trace 210t. The first trace 210t, the second trace 220t, the third trace 230t, and the fourth trace 240rt1 may be disposed in the peripheral area 200NA, a portion of the sub-trace ST may be disposed in the sensing area 200A, and the remaining portion of the sub-trace ST may be disposed in the peripheral area 200NA. The sub-trace ST may be disposed in plurality. Details on the sub-trace ST will be described later.

[0197] Each of the first electrodes 210 may cross the second electrode 220 in a plane. The first electrodes 210 may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The second electrodes 220 may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. Fig.10 ) may be a region where one of the first electrodes 210 and one of the second electrodes 220 cross each other.

[0198] exist Fig. 9 , 10 first electrodes 210 and 6 second electrodes 220 may be illustrated as an example, and 60 sensing units SU may be illustrated as an example. However, the number of the first electrodes 210 and the number of the second electrodes 220 are not limited thereto.

[0199] refer to Figure 8 and Fig. 9One or more of the plurality of first electrodes 210, the plurality of second electrodes 220, the plurality of third electrodes 230, and the plurality of fourth electrodes 240 described above may be arranged in Figure 8 . The signal line connected to the electrode disposed under the base layer 110 of the display layer 100 may also be disposed under the base layer 110 of the display layer 100. In an embodiment of the inventive concept, a plurality of first electrodes 210, a plurality of second electrodes 220, a plurality of third electrodes 230, and a plurality of fourth electrodes 240 may be disposed as four conductive layers disposed on different layers from each other. For example, a plurality of first electrodes 210 may be formed by a first conductive layer 202 disposed on a base layer 201 of the sensor layer 200, a plurality of second electrodes 220 may be formed by a second conductive layer 204 disposed on the first conductive layer 202, a plurality of third electrodes 230 may be formed by a third conductive layer disposed on the second conductive layer 204, and a plurality of fourth electrodes 240 may be formed by a fourth conductive layer disposed on the third conductive layer.

[0200] refer to Fig. 9 and Fig.10 Each of the first electrodes 210 may include first separation electrodes 210dv1 and 210dv2. The first electrodes 210 may extend along the first direction DR1 and may be spaced apart from each other in the second direction DR2. The first separation electrodes 210dv1 and 210dv2 may have shapes symmetrical to each other with respect to a line extending in the first direction DR1.

[0201] Each of the second electrodes 220 may include second separation electrodes 220dv1 and 220dv2. The second separation electrodes 220dv1 and 220dv2 may extend along the second direction DR2 and may be spaced apart from each other in the first direction DR1. The second separation electrodes 220dv1 and 220dv2 may have shapes symmetrical to each other with respect to a line extending in the second direction DR2.

[0202] refer to Fig.10 , Fig.11A , Fig. 11B and Fig.12 , each of the first separation electrodes 210dv1 and 210dv2 may include a sensing pattern 211 and a bridge pattern 212. The sensing pattern 211 and the bridge pattern 212 may be disposed on different layers, and the sensing pattern 211 and the bridge pattern 212 may be electrically connected to each other through a first contact CNa. For example, the bridge pattern 212 may be included in the first conductive layer 202SU, and the sensing pattern 211 and the second separation electrodes 220dv1 and 220dv2 may be included in the second conductive layer 204SU. The first conductive layer 202SU may be included in Figure 8The first conductive layer 202, and the second conductive layer 204SU may include Figure 8 In the second conductive layer 204.

[0203] The third electrodes 230 may be arranged along the second direction DR2, and the third electrodes 230 may extend along the first direction DR1. In an embodiment of the inventive concept, each of the third electrodes 230 may include first auxiliary electrodes 230s1, 230s2, and 230s3 connected in parallel. The first auxiliary electrodes 230s1, 230s2, and 230s3 may be referred to as a 1-1st auxiliary electrode 230s1, a 1-2nd auxiliary electrode 230s2, and a 1-3rd auxiliary electrode 230s3.

[0204] The wiring directions of the 1-1 auxiliary electrode 230s1, the 1-2 auxiliary electrode 230s2, and the 1-3 auxiliary electrode 230s3 may be different from each other. Fig. 9 , three third electrodes 230 may be illustrated, and three 1-1th auxiliary electrodes 230s1, five 1-2th auxiliary electrodes 230s2, and two 1-3th auxiliary electrodes 230s3 respectively included in the three third electrodes 230 may be illustrated as an example.

[0205] In the present specification, different wiring directions may mean that the connection positions between the electrode and the trace are different from each other. In other words, changing the wiring direction means that the connection points between the electrode and the trace are different from each other. For example, the connection positions of the third trace 230t electrically connected to each of the 1-1 auxiliary electrode 230s1, the 1-2 auxiliary electrode 230s2, and the 1-3 auxiliary electrode 230s3 may be different from each other. The connection position of the third trace 230t electrically connected to each of the 1-1 auxiliary electrode 230s1, the 1-2 auxiliary electrode 230s2, and the 1-3 auxiliary electrode 230s3 may be at the right end of the 1-1 auxiliary electrode 230s1 and the 1-3 auxiliary electrode 230s3 or may be at the left end of the 1-2 auxiliary electrode 230s2.

[0206] In another embodiment of the present inventive concept, the sensor layer 200 may include one third electrode 230. In this case, the third electrode 230 may include ten first auxiliary electrodes 230s1, 230s2, and 230s3 connected in parallel. Fig. 9 The number of the first auxiliary electrodes 230s1, 230s2, and 230s3 shown in FIG. 2 is not limited to the example shown.

[0207] Each of the fourth electrodes 240 may extend in the second direction DR2, and the fourth electrodes 240 may be spaced apart from each other in the first direction DR1. In an embodiment of the present inventive concept, the fourth electrode 240 may include a plurality of second auxiliary electrodes 240s connected in parallel, respectively. The number of the second auxiliary electrodes 240s included in each of the fourth electrodes 240 may vary. For example, when the number of the second auxiliary electrodes 240s included in each of the fourth electrodes 240 increases, the resistance of each of the fourth electrodes 240 may decrease, thereby improving power efficiency and improving sensing sensitivity. On the other hand, when the number of the second auxiliary electrodes 240s included in each of the fourth electrodes 240 decreases, the annular coil pattern formed by the fourth electrode 240 may be designed into a wider variety of configurations.

[0208] although Fig. 9 An example is shown in which one fourth electrode 240 includes two second auxiliary electrodes 240s, but the present disclosure is not particularly limited thereto. The second auxiliary electrodes 240s may be arranged to correspond one to one with the second electrodes 220. Therefore, one sensing unit SU may include a portion of one second auxiliary electrode 240s.

[0209] A coupling capacitor may be formed between one second electrode 220 and one second auxiliary electrode 240s. In this case, the induced current generated during pen sensing may be transmitted from the second auxiliary electrode 240s to the second electrode 220 via the coupling capacitor. In other words, the second auxiliary electrode 240s may supplement the current from the second electrode 220 to the sensor driver 200C (see Figure 7 ) transmitted. Therefore, when the phase of the signal induced in the second auxiliary electrode 240s matches the phase of the signal induced in the second electrode 220, the best effect can be achieved. Therefore, the center of the second electrode 220 in the second direction DR2 and the center of the second auxiliary electrode 240s in the second direction DR2 can overlap with each other. In addition, the center of each of the second electrodes 220 in the first direction DR1 and the center of each of the second auxiliary electrodes 240s in the first direction DR1 can also overlap with each other.

[0210] In an embodiment of the present inventive concept, since one fourth electrode 240 includes two second auxiliary electrodes 240s, one fourth electrode 240 may correspond to (overlap) two second electrodes 220. Therefore, the number of second electrodes 220 included in the sensor layer 200 may be greater than the number of fourth electrodes 240. For example, the number of second electrodes 220 may be the same as the product of the number of fourth electrodes 240 included in the sensor layer 200 and the number of second auxiliary electrodes 240s included in each of the fourth electrodes 240. Fig. 9, the number of the second electrodes 220 may be six, the number of the fourth electrodes 240 may be three, and the number of the second auxiliary electrodes 240s included in each of the fourth electrodes 240 may be two.

[0211] In an embodiment of the present inventive concept, when each of the third electrodes 230 includes the first auxiliary electrodes 230s1, 230s2, and 230s3 connected in parallel, the surface area of ​​one third electrode 230 can be increased. In addition, the resistance of each of the third electrodes 230 can be reduced to improve the second input 3000 (see Figure 7 )’s sensing sensitivity.

[0212] A coupling capacitor may be formed between one of the first electrodes 210 and one of the first auxiliary electrodes 230s1, 230s2, and 230s3. In this case, the induced current generated during pen sensing may be transmitted from the first auxiliary electrode 230s1, 230s2, or 230s3 to the first electrode 210 via the coupling capacitor. In other words, the first auxiliary electrode 230s1, 230s2, or 230s3 may supplement the current from the first electrode 210 to the sensor driver 200C (see Figure 7 ) transmitted. Therefore, when the phase of the signal induced in the first auxiliary electrode 230s1, 230s2 or 230s3 matches the phase of the signal induced in the first electrode 210, the best effect can be achieved. Therefore, the center of each of the first electrodes 210 in the first direction DR1 and the center of the first auxiliary electrode 230s1, 230s2 or 230s3 in the first direction DR1 may overlap with each other. In addition, the center of the first electrode 210 in the second direction DR2 and the center of the first auxiliary electrode 230s1, 230s2 or 230s3 in the second direction DR2 may also overlap with each other.

[0213] refer to Fig. 9 , Fig.11A and Fig. 11B, each of the first auxiliary electrodes 230s1, 230s2, and 230s3 included in the third electrode 230 may include a 3-1st pattern 231, a 3-2nd pattern 232, and a 3-3rd pattern 233. The 3-2nd pattern 232 and the 3-3rd pattern 233 may be disposed on the same layer, and the 3-1st pattern 231 may be disposed on a layer different from the layer on which the 3-2nd pattern 232 and the 3-3rd pattern 233 are disposed. The 3-1st pattern 231 and the 3-2nd pattern 232 may be electrically connected to each other through a third contact point CNc, and the 3-1st pattern 231 and the 3-3rd pattern 233 may be electrically connected through a fourth contact point CNd. The 3-2nd pattern 232 and the 3-3rd pattern 233 may be included in the first conductive layer 202SU, and the 3-1st pattern 231 may be included in the second conductive layer 204SU.

[0214] In an embodiment of the present inventive concept, a portion of the 3-2nd pattern 232 may overlap the sensing pattern 211 of each of the first separation electrodes 210dv1 and 210dv2. Thus, a coupling capacitor may be disposed or formed between the first electrode 210 and the third electrode 230.

[0215] refer to Fig. 9 , Fig.11A and Fig. 11B , each of the second auxiliary electrodes 240s included in the fourth electrode 240 may include a 4-1st pattern 241 and a 4-2nd pattern 242. The 4-1st pattern 241 and the 4-2nd pattern 242 may be disposed on different layers, and the 4-1st pattern 241 and the 4-2nd pattern 242 may be electrically connected to each other through a second contact point CNb. The 4-1st pattern 241 may be included in the first conductive layer 202SU, and the 4-2nd pattern 242 may be included in the second conductive layer 204SU.

[0216] In an embodiment of the present inventive concept, a portion of the 4-1st pattern 241 may overlap a portion of each of the second separation electrodes 220dv1 and 220dv2 . Thus, a coupling capacitor may be disposed or formed between the second electrode 220 and the fourth electrode 240 .

[0217] In an embodiment of the inventive concept, the first conductive layer 202SU may further include dummy patterns DMP. Each of the dummy patterns DMP may be electrically floating or electrically grounded. In an embodiment of the inventive concept, the dummy patterns DMP may be omitted.

[0218] The sensor layer 200 may further include a plurality of first pads PD1 and a plurality of second pads PD2, wherein the first pads PD1 correspond one-to-one to the first traces 210t disposed in the peripheral area 200NA and are electrically connected to each other, and the second pads PD2 correspond one-to-one to the second traces 220t disposed in the peripheral area 200NA. A portion of the first pads PD1 may be directly connected to the sub-trace ST. For example, the first pads PD1 may be connected to the first trace 210t via the sub-trace ST. For example, the sensor driver 200C (see Figure 7 ) can be connected to the first trace 210t through the sub-trace ST.

[0219] The first trace 210t may correspond to the first electrode 210 one by one and be electrically connected to the first electrode 210. Two first separation electrodes 210dv1 and 210dv2 included in one first electrode 210 may be connected to one of the first traces 210t. Each of the first traces 210t may include a plurality of branches to be connected to the two first separation electrodes 210dv1 and 210dv2. In an embodiment of the inventive concept, the two first separation electrodes 210dv1 and 210dv2 may be connected to each other within the sensing area 200A.

[0220] The second trace 220t may correspond to each of the second electrodes 220 one by one and be electrically connected to each of the second electrodes 220. Two second separation electrodes 220dv1 and 220dv2 included in one second electrode 220 may be connected to one of the second traces 220t. Each of the second traces 220t may include a plurality of branches to be connected to the two second separation electrodes 220dv1 and 220dv2. In an embodiment of the inventive concept, the two second separation electrodes 220dv1 and 220dv2 may be connected to each other within the sensing area 200A.

[0221] The sensor layer 200 may also include a third pad PD3, a plurality of fourth pads PD4, and a fifth pad PD5, wherein the third pad PD3 corresponds one-to-one to and is connected to a third trace 230t set in the peripheral area 200NA, a plurality of fourth pads PD4 are connected to one end (e.g., the first end) and the other end (e.g., the second end) of the fourth trace 240rt1, and the fifth pad PD5 corresponds one-to-one to and is connected to the fifth trace 240rt2.

[0222] The third traces 230t may be spaced apart from each other with the sensing region 200A therebetween. The third traces 230t may be electrically connected to at least one of the first auxiliary electrodes 230s1, 230s2, and 230s3. For example, one end of each of the first auxiliary electrodes 230s1, 230s2, and 230s3 may be connected to the third trace 230t.

[0223] The fourth trace 240rt1 may be electrically connected to at least one of the second auxiliary electrodes 240s. In an embodiment of the inventive concept, the fourth trace 240rt1 may be electrically connected to all of the second auxiliary electrodes 240s. For example, the fourth trace 240rt1 may be electrically connected to all of the fourth electrodes 240. The fourth trace 240rt1 may include a first line portion 241t extending in the first direction DR1 and electrically connected to the fourth electrode 240, a second line portion 242t extending from a first end of the first line portion 241t in the second direction DR2, and a third line portion 243t extending from a second end of the first line portion 241t in the second direction DR2. The first line portion 241t may extend along the top of the sensing region 200A.

[0224] In an embodiment of the inventive concept, the resistance of both the second wire portion 242t and the third wire portion 243t may be substantially equal to the resistance of one quarter of the resistance of a single electrode of the fourth electrode 240. Therefore, the second wire portion 242t and the third wire portion 243t serve as the fourth electrode 240, and the fourth electrode 240 is disposed in the peripheral area 200NA. For example, each of one of the second wire portion 242t and the third wire portion 243t and one of the fourth electrodes 240 may form a coil. Therefore, a pen disposed in an area adjacent to the peripheral area 200NA may be fully charged by a loop including the second wire portion 242t or the third wire portion 243t.

[0225] In an embodiment of the present inventive concept, in order to adjust the resistance of the second line portion 242t and the resistance of the third line portion 243t, the width of each of the second line portion 242t and the third line portion 243t in the first direction DR1 may be adjusted. However, this is only an example, and the first line portion 241t, the second line portion 242t, and the third line portion 243t may have substantially the same width. The fourth pad PD4 may be connected to each of the second line portion 242t and the third line portion 243t.

[0226] The fifth traces 240rt2 may be connected to the fourth electrodes 240 to correspond to each other one by one. For example, the number of the fifth traces 240rt2 may correspond to the number of the fourth electrodes 240. Fig. 9 , three fifth traces 240rt2 are shown as an example.

[0227] In an embodiment of the present inventive concept, the fifth trace 240rt2 and the fifth pad PD5 may be omitted, and the charging driving mode for charging the pen may be omitted. In this case, the sensor layer 200 may sense input from an active pen capable of emitting a magnetic field even if no magnetic field is provided from the sensor layer 200.

[0228] refer to Fig.13 , the dummy pattern DMP may have a grid structure. The dummy pattern DMP may include a plurality of grid lines. Each of the plurality of grid lines may have a straight line shape extending in a predetermined direction, and the plurality of grid lines may be connected to each other. An opening in which no grid line is provided may be provided or formed in each of the dummy patterns DMP. Fig. 9 Each of the first electrode 210 , the second electrode 220 , the third electrode 230 , and the fourth electrode 240 shown in FIG. 2 may have a mesh structure.

[0229] exist Fig.13 In the embodiment, the dummy pattern DMP may include grid lines extending along a first crossing direction CDR1 crossing the first direction DR1 and the second direction DR2, and grid lines extending along a second crossing direction CDR2 crossing the first crossing direction CDR1. However, the direction in which the grid lines constituting the dummy pattern DMP extend is not particularly limited to Fig.13 For example, the dummy pattern DMP may include only grid lines extending in the first direction DR1 and the second direction DR2, or grid lines extending in the first direction DR1, the second direction DR2, the first cross direction CDR1, and the second cross direction CDR2. In other words, the grid structure of the dummy pattern DMP may be modified to a different configuration.

[0230] The dummy patterns DMP may be separated from each other by a predetermined distance in the first crossing direction CDR1. The space in which the dummy patterns DMP are spaced apart from each other may be designated as a dummy opening DOP. The distance between the dummy patterns DMP in the first crossing direction CDR1 may be a first distance d1. In addition, the width of the dummy hole DMH formed by the dummy pattern DMP may be a first width w1. The dummy pattern DMP may be provided to prevent the first electrode 210 (see Fig.10 ) and the second electrode 220 (see Fig.10 ) is visible from the outside. For example, the dummy pattern DMP may be disposed adjacent to the first electrode 210 (see Fig.10 ) and the second electrode 220 (see Fig.10 ) in the overlapping area.

[0231] like Fig.13As shown in , the first distance d1 is shown to be greater than the first width w1, but the first distance d1 may be less than the first width w1. The dummy opening DOP may be a portion where no electrode is provided and may be visible from the outside. Therefore, when the first distance d1 decreases, the portion of the dummy opening DOP visible from the outside may decrease.

[0232] exist Fig.13 , the cutting line CL is shown as a straight line along the second crossing direction CDR2, but the cutting line CL is not limited thereto and may be arranged in a zigzag pattern along the second crossing direction CDR2. By combining the zigzag side surface for the dummy pattern DMP, the first electrode 210 (see Fig.10 ) and the second electrode 220 (see Fig.10 ) The occurrence of a phenomenon that is visible from the outside due to reflection caused by external light.

[0233] Fig.14 yes Fig. 9 Magnified view of region BB'. Fig.14 is an enlarged plan view of a sensing unit SUa according to an embodiment of the inventive concept. Fig.15A is a plan view illustrating a first conductive layer of a sensing unit according to an embodiment of the inventive concept. Fig. 15B is a plan view illustrating a second conductive layer of a sensing unit according to an embodiment of the inventive concept. Fig.16A is a plan view illustrating a first conductive layer according to another embodiment of the inventive concept. Fig. 16B is an enlarged plan view of one sensing unit according to another embodiment of the inventive concept. Fig.17A is a sensor layer according to an embodiment of the present inventive concept along Fig.15A and Fig. 15B A cross-sectional view taken along line II-II' in each of the figures. Fig. 17B is a sensor layer according to another embodiment of the present invention. Fig.15A and Fig. 15B A cross-sectional view taken along line II-II' in each of the figures. Fig.18A yes Fig.15A An enlarged view of area EE'. Fig.18B According to another embodiment of the present invention Fig.15A The first conductive layer 202SUa may be substantially Fig.11A The first conductive layer 202SU is the same as the first conductive layer 202SU, and the second conductive layer 204SUa can be substantially the same as Fig. 11B Hereinafter, contents repeated with the above description will be omitted.

[0234] refer to Fig. 9 , Fig.14 , Fig.15A and Fig. 15B , the sub-trace ST may be disposed in the sensing area 200A on a plane. For example, a first portion of the sub-trace ST may be disposed in the sensing area 200A, and a second portion of the sub-trace ST may be disposed in the peripheral area 200NA. According to an embodiment of the inventive concept, the sub-trace ST may overlap with the first electrode 210 on a plane. For example, the sub-trace ST may overlap with the sensing pattern 211 of the first electrode 210 on a plane. The present disclosure is not limited thereto, and the sub-trace ST may not overlap with the sensing pattern 211 on a plane, and may overlap with the second partition electrode 220dv1. In addition, the sub-trace ST may overlap with the 3-1st pattern 231 of the third electrode 230 on a plane, and may not overlap with the 3-2nd pattern 232 of the third electrode 230 on a plane. In an embodiment, when the 3-1st pattern 231 is omitted, the sub-trace ST may not overlap with the 3-1st pattern 231 and the 3-2nd pattern 232 on a plane.

[0235] refer to Fig.15A , Fig. 15B and Fig.17A , the sub-trace ST may be disposed on the sensor base layer 201. The sub-trace ST may be disposed on the same layer as the bridge pattern 212 and the 4-1st pattern 241. The sub-trace ST, the bridge pattern 212, and the 4-1st pattern 241 may be disposed on the sensor base layer 201. The sub-trace ST, the bridge pattern 212, and the 4-1st pattern 241 may be disposed on the sensor base layer 201. The sub-trace ST, the bridge pattern 212, and the 4-1st pattern 241 may be covered by the sensor insulating layer 203. However, the present disclosure is not limited thereto, and the sub-trace ST may be disposed on the same layer as the 3-2nd pattern 232 and the dummy pattern DMPa. Therefore, the sub-trace ST may not overlap with the bridge pattern 212, the 4-1st pattern 241, the 3-2nd pattern 232, and the dummy pattern DMPa on a plane.

[0236] The sub-trace ST may include a first portion P1 disposed between the dummy patterns DMPa, and a second portion P2 disposed between the 4-1st pattern 241 and the 3-2nd pattern 232. The first portion P1 may be inclined, and the second portion P2 may be straight. Fig.15A , the width of the sub-trace ST is shown as being constant, but the widths of the first portion P1 and the second portion P2 may be different. For example, the width of the first portion P1 disposed between the dummy patterns DMPa may be freely adjusted based on the area from which the dummy pattern DMPa is removed. However, because the sizes of the 4-1st pattern 241 and the 3-2nd pattern 232 cannot be freely adjusted, the second portion P2 may maintain a certain width or greater. Therefore, the width of the first portion P1 may be greater than the width of the second portion P2. Fig. 17B, the sensor layer 200a may further include a sub-insulating layer (or third insulating layer) 206. The sub-insulating layer 206 may be disposed between the sensor insulating layer 203 and the sensor base layer 201. According to an embodiment of the inventive concept, the sub-trace STc may be disposed on the sensor base layer 201 and covered by the sub-insulating layer 206. The present disclosure is not limited thereto, and the sensor layer 200a may further include a plurality of insulating layers between the sensor insulating layer 203 and the sensor base layer 201. The sub-trace STc may be disposed on one of the plurality of insulating layers.

[0237] Reference together Fig. 9 and Fig. 17B , the sub-trace STc may overlap in plane with at least one of the first electrode 210, the plurality of second electrodes 220, the plurality of third electrodes 230, and the plurality of fourth electrodes 240. For example, the sub-trace STc may overlap in plane with the bridge pattern 212 of the first electrode 210, the second separation electrodes 220dv1 and 220dv2 of the second electrode 220, and the 4-2nd pattern 242 of the fourth electrode 240. However, since the sub-trace STc is disposed on a layer different from the layer on which each of the first electrode 210, the plurality of second electrodes 220, the plurality of third electrodes 230, and the plurality of fourth electrodes 240 is disposed, the sub-trace STc may overlap in plane with all of the first electrode 210, the plurality of second electrodes 220, the plurality of third electrodes 230, and the plurality of fourth electrodes 240.

[0238] refer to Fig.15A and Fig.18A , the sub-trace ST may be disposed between the dummy patterns DMPa. The dummy patterns DMPa may be spaced apart from each other by a predetermined distance. The sub-trace ST may be arranged in a space where the dummy patterns DMPa are spaced apart from each other. The space where the dummy patterns DMPa are spaced apart from each other may be a dummy opening DOPa. The distance between the dummy patterns DMPa in the first crossing direction CDR1 may be a second distance d2. The second distance d2 may be greater than another sensing unit SU (see Fig.10 ) in the first distance d1 of the virtual opening DOP (see Fig.13 In other words, the dummy opening DOPa can be formed by removing the dummy pattern DMP (see Fig.10 ) part.

[0239] The sub-trace lines ST may be disposed on the first auxiliary electrodes 230s1, 230s2, and 230s3 (see Fig. 9 ) and the second auxiliary electrode 240s (see Fig. 9). For example, the sub-trace line ST may be disposed between the 3-2 pattern 232 of the first auxiliary electrodes 230s1, 230s2, and 230s3 and the 4-1 pattern 241 of the second auxiliary electrode 240s. The position at which the sub-trace line ST is disposed is not limited to Fig.15A For example, the sub-trace ST may be disposed between the dummy pattern DMPa and the 3-2nd pattern 232. In other words, the sub-trace ST may be disposed in a space in the first conductive layer 202SUa that does not overlap with other components.

[0240] refer to Fig.18B , the width of the sub-trace STd can be greater than Fig.18A . For example, the sub-trace STd may be disposed adjacent to the dummy pattern DMPa. When the dummy opening DOPb is minimized, the portion of the dummy opening DOPb visible from the outside may be reduced. In addition, increasing the width of the sub-trace STd may result in a reduction in the resistance of the sub-trace STd, thereby improving power efficiency and improving sensing sensitivity.

[0241] The first cutting line CL1 and the second cutting line CL2 may be provided in the dummy opening DOPb. After the sub-trace line STd and the dummy pattern DMPa are provided as one body, the sub-trace line STd and the dummy pattern DMPa may be separated from each other by the first cutting line CL1 and the second cutting line CL2. The width of the sub-trace line STd may be freely changed by the first cutting line CL1 and the second cutting line CL2. Therefore, the second distance d2a by which the dummy patterns DMPa are spaced from each other may be less than Fig.18A The second distance d2 is shown in .

[0242] refer to Fig.16A , the second auxiliary electrode 240s (see Fig. 9 ) may be spaced apart from each other in the second direction DR2. For example, the 4-1st patterns 241a may be separated from each other and spaced apart from each other. The sub-trace line STa may be disposed at a position where the 4-1st patterns 241a are separated from each other. The area where the sub-trace line STa is disposed is not limited to Fig.16A The sub-trace STa may be disposed in a space passing through other elements disposed on the first conductive layer 202SUb.

[0243] refer to Fig. 16B, in the sensing unit SUb, the sub-trace STb may not overlap with the first electrode 210 and the second electrode 220. For example, the sub-trace STb may be disposed between the sensing pattern 211 and the second separation electrode 220dv2 on a plane. Since the sub-trace STb is disposed to avoid overlapping with the first electrode 210 and the second electrode 220, the sub-trace STb helps to minimize signal noise caused by the sub-trace STb during sensing of the first electrode 210 and the second electrode 220. In addition, since the dummy pattern DMPa is disposed between the sub-trace STb and the 3-2 pattern 232, the coupling gap occurring between the sub-trace STb and the 3-2 pattern 232 may be reduced. Fig.19A yes Fig. 9 For example, Fig.19A is an enlarged plan view of a first trace 210 t and a sub-trace ST according to an embodiment of the inventive concept. Fig.19B According to an embodiment of the present invention, Fig.19A A cross-sectional view of the sensor layer taken along line III-III'. Fig.19C According to another embodiment of the present invention, Fig.19A A cross-sectional view of the sensor layer taken along line III-III'. Fig.19D According to another embodiment of the present invention, Fig.19A A cross-sectional view of the sensor layer taken along line III-III'.

[0244] refer to Fig.19A and Fig.19B , the first trace 210t and the sub-trace ST may be disposed on different layers. The first trace 210t may be disposed on the sensor insulating layer 203, and the sub-trace ST may be disposed on the sensor base layer 201. According to an embodiment of the inventive concept, a contact hole CNT-T may be formed in the sensor insulating layer 203 of the sensor layer 200. The sub-trace ST may be connected to the first trace 210t through the contact hole CNT-T passing through the sensor insulating layer 203. The contact hole CNT-T may be formed in the peripheral area 200NA. However, the present disclosure is not limited thereto, and the first trace 210t and the sub-trace ST may be disposed on the same layer and connected to each other without the contact hole CNT-T.

[0245] refer to Fig.19C, the sensor layer 200a may further include a sub-insulating layer (or third insulating layer) 206. The sub-insulating layer 206 may be disposed between the sensor insulating layer 203 and the sensor base layer 201. According to an embodiment of the inventive concept, the sub-trace STc may be disposed on the sensor base layer 201 and covered by the sub-insulating layer 206. In this case, the sub-trace STc is sandwiched between the sensor base layer 201 and the sub-insulating layer 206. The present disclosure is not limited thereto, and the sensor layer 200a may further include a plurality of insulating layers between the sensor insulating layer 203 and the sensor base layer 201. The sub-trace STc may be disposed on one of the plurality of insulating layers.

[0246] The sub-trace STc may be connected to the first trace 210t through the first contact hole CNT-T1 passing through the sensor insulating layer 203 and the second contact hole CNT-T2 passing through the sub-insulating layer 206. For example, the connection electrode CNE-T disposed on the sub-insulating layer 206 may be connected to the first trace 210t through the first contact hole CNT-T1, and may be connected to the sub-trace STc through the second contact hole CNT-T2. In other words, the sub-trace STc may be connected to the first trace 210t through the first contact hole CNT-T1, the connection electrode CNE-T, and the second contact hole CNT-T2.

[0247] refer to Figures 9 to 19C , the sensor layer 200 may include a sub-trace ST connected to some of the first traces 210t. The sub-trace ST may be arranged to overlap the sensing region 200A. The first trace 210t connected to the sub-trace ST may not be disposed in the peripheral region 200NA adjacent to the sensing region 200A in the direction opposite to the first direction DR1. Therefore, the surface area of ​​the peripheral region 200NA may be reduced, and the size of the electronic device 1000 (see Figure 1A ) of the display surface IS (see Figure 1A ) is formed by the non-display area NDA (see Figure 1A ) The surface area occupied by the electronic device 1000 is reduced. In other words, an electronic device 1000 including a narrow frame can be provided.

[0248] refer to Fig.19D , the first trace 210t may include a multi-layer structure. For example, the first trace 210t may include an upper trace 210t-U and a lower trace 210t-D. The lower trace 210t-D may be disposed on the sensor base layer 201, and the upper trace 210t-U may be disposed on the sensor insulating layer 203. The upper trace 210t-U may be electrically connected to the lower trace 210t-D through a contact hole CNT-Ta passing through the sensor insulating layer 203. Since the first trace 210t has a double-layer structure, the resistance of the first trace 210t may be reduced, the power efficiency may be improved, and the sensing sensitivity may be improved.

[0249] Sub-trace ST may extend from lower trace 210t-D. For example, sub-trace ST may be integrated with lower trace 210t-D. Upper trace 210t-U may not be disposed in an area overlapping with sub-trace ST. Sub-trace ST may be integrated with lower trace 210t-D, and therefore, a separate contact hole may not be required. Therefore, simplification of the formation process of sub-trace ST is achieved, and the need for a separate contact hole is eliminated, thereby preventing the resistance of sub-trace ST from increasing.

[0250] Fig. 20A is a plan view illustrating a portion of a sensor layer according to an embodiment of the inventive concept. Fig. 20A Only the first electrode 210 , the second electrode 220 , the third electrode 230 , and the fourth electrode 240 , the first trace 210 t , and the sub-trace ST are shown. Fig. 20B and Fig. 20C is a plan view showing a portion of a sensor layer according to another embodiment of the present inventive concept. Descriptions overlapping with those given above will be omitted.

[0251] refer to Fig. 20A , the first electrode 210 may include a first main electrode 210-M electrically connected to the sub-trace ST and a first sub-electrode 210-S electrically insulated from the sub-trace ST. The first main electrode 210-M may be connected to the sensor driver 200C through the first trace 210t and the sub-trace ST (see Figure 7 ), and the first sub-electrode 210-S may be connected to the sensor driver 200C through the first trace 210t (see Figure 7 ).

[0252] The sub-trace ST may overlap the sensing region 200A. For example, the sub-trace ST may overlap the first sub-electrode 210-S of the first electrode 210 disposed in the sensing region 200A. A plurality of first sub-electrodes 210-S may be disposed. The sub-trace ST may overlap two or more first sub-electrodes 210-S.

[0253] The first trace 210t may include a plurality of 1-1th traces 210t-1 connected to one end (e.g., the first end) of the first electrode 210 and a plurality of 1-2th traces 210t-2 connected to the other end (e.g., the second end) of the first electrode 210. In this embodiment, one end of the first electrode 210 may be a portion corresponding to an end of the first electrode 210 in a direction opposite to the first direction DR1, and the other end of the first electrode 210 may be a portion corresponding to an end of the first electrode 210 in the first direction DR1. The 1-1th trace 210t-1 and the 1-2th trace 210t-2 may be spaced apart from each other in the first direction DR1. Fig. 20A, the number of each of the 1-1th trace 210t-1 and the 1-2th trace 210t-2 is shown as 5, but the number of each of the 1-1th trace 210t-1 and the 1-2th trace 210t-2 is not limited thereto.

[0254] The sub-trace ST may be provided in plurality, and the first main electrode 210-M may be provided in plurality to correspond to the number of the sub-trace ST. According to an embodiment of the inventive concept, the first main electrode 210-M may be provided at the uppermost end of the first electrode 210 in the second direction DR2. However, the inventive concept is not limited thereto, and the first main electrode 210-M may be provided near the central portion of the first electrode 210.

[0255] According to an embodiment of the inventive concept, at least one first sub-electrode 210-S may be disposed between the first main electrode 210-M and the first sub-electrode 210-S overlapping the sub-trace ST. At least one first sub-electrode 210-S may be disposed between the first main electrode 210-M disposed at the lowermost end of the first main electrode 210-M in the second direction DR2 and the first sub-electrode 210-S disposed at the uppermost end of the first sub-electrode 210-S in the second direction DR2. When the at least one first sub-electrode 210-S is a first sub-electrode located in the center (also referred to as a first central sub-electrode 210-S), the first central sub-electrode 210-S may be disposed in four. However, the present disclosure is not limited thereto, and the number of the first central sub-electrodes 210-S may be set to five or more.

[0256] Fig. 20B is a plan view showing a portion of a sensor layer 200 b according to another embodiment of the present invention.

[0257] refer to Fig. 20B , the first trace 210ta may include a plurality of 1-1 traces 210t-1a connected to one end (e.g., the first end) of the first electrode 210 and a plurality of 1-2 traces 210t-2a connected to the other end (e.g., the second end) of the first electrode 210. The 1-1 trace 210t-1a and the 1-2 trace 210t-2a may be electrically connected to the first electrode 210, respectively. In an embodiment of the inventive concept, one first electrode 210 may be connected to the 1-1 trace 210t-1a or the 1-2 trace 210t-2a through one connection point. In this case, the first electrode 210 may further include a first separation electrode 210dv1 and 210dv2 (see Fig.10 )'s additional bridging pattern.

[0258] Fig. 20Cis a plan view showing a portion of a sensor layer 200 c according to another embodiment of the present invention.

[0259] refer to Fig. 20C , the first trace 210tb may include a plurality of 1-1 traces 210t-1b connected to one end (e.g., the first end) of the first electrode 210 and a plurality of 1-2 traces 210t-2b connected to the other end (e.g., the second end) of the first electrode 210. The 1-1 trace 210t-1b and the 1-2 trace 210t-2b may be spaced apart from each other in the first direction DR1. Fig. 20C , the number of the 1-1th traces 210t-1b is 5, and the number of the 1-2th traces 210t-2b is 4, but the number of each of the 1-1th traces 210t-1b and the 1-2th traces 210t-2b is not limited thereto.

[0260] The first electrode 210 may include a 1-1 electrode 210-1 connected to a 1-1 trace 210t-1b and a 1-2 electrode 210-2 connected to a 1-2 trace 210t-2b. The 1-1 electrode 210-1 may be connected to the sensor driver 200C through the 1-1 trace 210t-1b (see Figure 7 ), and the 1-2 electrode 210-2 may be connected to the sensor driver 200C through the 1-2 trace 210t-2b (see Figure 7 ). The number of each of the 1-1st electrode 210-1 and the 1-2nd electrode 210-2 may be the same as the number of each of the 1-1st trace 210t-1b and the 1-2nd trace 210t-2b. The arrangement of the 1-1st electrode 210-1 and the 1-2nd electrode 210-2 is not limited to the arrangement shown.

[0261] The sub-trace STc may include a first sub-trace ST1 and a second sub-trace ST2. The first sub-trace ST1 may be electrically connected to at least a portion of the 1-1th trace 210t-1b, and the second sub-trace ST2 may be electrically connected to at least a portion of the 1-2th trace 210t-2b. Fig. 20C , the first sub-trace ST1 may be electrically connected to all five 1-1 traces 210t-1b, and the second sub-trace ST2 may be electrically connected to two 1-2 traces 210t-2b of the four 1-2 traces 210t-2b. However, the present disclosure is not limited thereto, and the first sub-trace ST1 may be electrically connected to a portion of the five 1-1 traces 210t-1b, and the second sub-trace ST2 may be electrically connected to all four 1-2 traces 210t-2b.

[0262] The 1-1th electrode 210-1 may be connected to the sensor driver 200C through the 1-1th trace 210t-1b and the first sub-trace ST1 (see Figure 7 ), and the 1-2 electrode 210-2 may be connected to the sensor driver 200C through the 1-2 trace 210t-2b (see Figure 7 ), or connected to the sensor driver 200C through the 1-2 trace 210t-2b and the second sub-trace ST2 (see Figure 7 ).

[0263] The first sub-trace ST1 and the second sub-trace ST2 may be disposed in the sensing region 200A. The first sub-trace ST1 and the second sub-trace ST2 may overlap the first electrode 210 on a plane. An initial portion of the first sub-trace ST1, where the first sub-trace ST1 begins to overlap the sensing region 200A, may overlap the 1-2 electrode 210-2. In addition, a portion of the first sub-trace ST1 extending in a direction opposite to the second direction DR2 may overlap the 1-1 electrode 210-1. An initial portion of the second sub-trace ST2, where the second sub-trace ST2 begins to overlap the sensing region 200A, may overlap the 1-1 electrode 210-1. In addition, a portion of the second sub-trace ST2 extending in a direction opposite to the second direction DR2 may overlap the 1-2 electrode 210-2.

[0264] The first electrode 210 may be disposed between the 1-1 electrode 210-1 connected to the first sub-trace ST1 and the 1-2 electrode 210-2 overlapping the first sub-trace ST1. In addition, the first electrode 210 may be disposed between the 1-2 electrode 210-2 connected to the second sub-trace ST2 and the 1-1 electrode 210-1 overlapping the second sub-trace ST2. For example, a plurality of 1-2 electrodes 210-2 may be disposed between the 1-1 electrode 210-1 disposed at the lowermost end of the 1-1 electrode 210-1 connected to the first sub-trace ST1 in the second direction DR2 and the 1-2 electrode 210-2 disposed at the uppermost end of the 1-2 electrode 210-2 overlapping the first sub-trace ST1 in the second direction DR2. In addition, a plurality of 1-1 electrodes 210-1 (for example, four 1-1 electrodes 210-1) may be disposed between a 1-2 electrode 210-2 disposed at a lowermost end of the 1-2 electrode 210-2 connected to the second sub-trace ST2 in the second direction DR2 and a 1-1 electrode 210-1 disposed at an uppermost end of the 1-1 electrode 210-1 overlapping the second sub-trace ST2 in the second direction DR2. The first sub-trace ST1 and the second sub-trace ST2 may be spaced apart from each other in the first direction DR1.

[0265] The first sub-trace ST1 may overlap with the 1-2 electrode 210-2 disposed in the sensing region 200A. The 1-1 trace 210t-1b connected to the first sub-trace ST1 may not be disposed adjacent to the peripheral region 200NA in a direction opposite to the first direction DR1 with respect to the peripheral region 200NA adjacent to the first sub-trace ST1 overlapping with the 1-2 electrode 210-2. A portion of the 1-1 trace 210t-1b may not be disposed at the lower left end of the peripheral region 200NA where a plurality of lines are disposed, and therefore, the occurrence of a bottleneck phenomenon due to the plurality of lines may be reduced.

[0266] Fig.21A and Fig. 21B is a view for explaining a second mode of embodiment according to the inventive concept.

[0267] Fig.21A is a view showing a state in which the pen PN according to an embodiment of the inventive concept moves on the sensor layer 200 ′ in directions ①, ②, and ③, and Fig. 21B It is shown that when the input is sensed by the pen PN, the sensor driver 200C (see Figure 7 ) is a graph obtained by calculating input coordinate information from the signal received from the sensor layer 200'.

[0268] Fig.21A A portion of a sensor layer 200 ′ according to an embodiment of the inventive concept is shown. Fig.21A Only the first electrode 210 ′, the second electrode 220 , the third electrode 230 , and the fourth electrode 240 , the first trace 210 t ′, and the sub-trace ST′ are shown.

[0269] The first trace 210t' may include a plurality of 1-1 traces 210t-1' connected to one end (e.g., the first end) of the first electrode 210' and a plurality of 1-2 traces 210t-2' connected to the other end (e.g., the second end) of the first electrode 210'. The first electrode 210' may include a first main electrode 210-M' electrically connected to the sub-trace ST' and a first sub-electrode 210-S' electrically insulated from the sub-trace ST'.

[0270] At least one first sub-electrode 210-S' may be disposed between the first main electrode 210-M' disposed at the lowermost end of the first main electrode 210-M' in the second direction DR2 and the first sub-electrode 210-S' disposed at the uppermost end of the first sub-electrode 210-S' in the second direction DR2. When at least one first sub-electrode 210-S' is a first central sub-electrode 210-S', the number of first central sub-electrodes 210-S' may be set to three or less. In addition, the number of first sub-electrodes 210-S' connected to the 1-2 trace 210t-2' may be greater than the number of first central sub-electrodes 210-S'. For example, the number of first sub-electrodes 210-S' connected to the 1-2 trace 210t-2' may be at least one more than the number of first central sub-electrodes 210-S'.

[0271] The pen PN may move on the sensor layer 200' in a direction opposite to the second direction DR2. For example, the pen PN may move on the sensor layer 200' in directions ①, ②, and ③. When the sensor layer 200' senses input from the pen PN moving in directions ①, ②, and ③, the sensor driver 200C (see Figure 7 ) can calculate coordinate information based on the signal received from the sensor layer 200'.

[0272] refer to Fig. 21B When the pen PN moves in directions ①, ②, and ③, the sensor driver 200C (see Figure 7 ) may adjust the coordinate information based on the signal received from the sensor layer 200' according to the embodiment. The reference line may be a coordinate value that must be calculated when the pen PN moves in each of the directions ①, ②, and ③. For example, when the pen PN moves in each of the directions ①, ②, and ③, it can be observed that the accuracy of the calculated coordinate value increases as the graph based on the value approaches the reference line.

[0273] The first comparison graph G1' is a graph based on the coordinate values ​​when the pen PN moves in direction ①. The second comparison graph G2' is a graph based on the coordinate values ​​when the pen PN moves in direction ②. The third comparison graph G3' is a graph based on the coordinate values ​​when the pen PN moves in direction ③. It can be observed that when the pen PN moves in directions ① and ②, the coordinate values ​​of the first comparison graph G1' and the second comparison graph G2' gradually become distorted. In particular, in the third comparison graph G3', it is observed that when the pen PN moves in direction ③, when the x value is between 10 and 15, the y coordinate value moves rapidly away from the reference line.

[0274] Fig.22A and Fig. 22Bis a view for explaining a second mode of embodiment according to the inventive concept.

[0275] Fig.22A is a view showing a state in which the pen PN according to an embodiment of the inventive concept moves in directions ①, ②, and ③ on the sensor layer 200, and Fig. 22B It is shown that when the input is sensed by the pen PN, the sensor driver 200C (see Figure 7 ) is a graph obtained by calculating input coordinate information from a signal received from the sensor layer 200.

[0276] Fig.22A A portion of a sensor layer 200 according to an embodiment of the inventive concept is shown. Fig.22A The sensor layer 200 shown in FIG. Fig. 20A The sensor layer 200 ′ shown in FIG. 2 is identical.

[0277] refer to Fig.22A , at least one first sub-electrode 210-S may be disposed between the first main electrode 210-M disposed at the lowermost end of the first main electrode 210-M in the second direction DR2 and the first sub-electrode 210-S disposed at the uppermost end of the first sub-electrode 210-S in the second direction DR2. Optionally, there may be five or more first central sub-electrodes 210-S. In addition, the number of first sub-electrodes 210-S connected to the 1-2nd trace 210t-2 may be greater than the number of first central sub-electrodes 210-S. For example, the number of first sub-electrodes 210-S connected to the 1-2nd trace 210t-2 may be at least one more than the number of first central sub-electrodes 210-S.

[0278] The pen PN can move in directions ①, ②, and ③ on the sensor layer 200. Fig. 22B When the pen PN moves in directions ①, ②, and ③ on the sensor layer 200, the sensor driver 200C (see Figure 7 ) can adjust the coordinate information calculated based on the signal received from the sensor layer 200 according to the embodiment.

[0279] The first graph G1 is a graph based on coordinate values ​​when the pen PN moves in direction ①. The second graph G2 is a graph based on coordinate values ​​when the pen PN moves in direction ②. The third graph G3 is a graph based on coordinate values ​​when the pen PN moves in direction ③. It can be observed that when the pen PN moves in directions ①, ②, and ③, the coordinate values ​​of the first graph G1, the second graph G2, and the third graph G3 are calculated to be almost the same as the reference line.

[0280] For example, refer to FIG. 21A to FIG. 22B, it can be observed that when the number of the first central sub-electrodes 210 -S is set to 4 or more, when the sensor layer 200 senses the input of the pen PN, the precise coordinates are calculated.

[0281] According to an embodiment of the present invention, the sensor layer may include a sub-trace electrically connected to the first trace and overlapping the sensing area. The first trace connected to the sub-trace may not be disposed in a peripheral area adjacent to the sensing area overlapping the sub-trace. Therefore, the surface area of ​​the peripheral area can be reduced, and the surface area occupied by the non-display area on the display screen of the electronic device can be reduced. In other words, an electronic device that implements a narrow frame can be provided.

[0282] It will be apparent to those skilled in the art that various modifications and deviations may be made to the inventive concept. Therefore, it is intended that the inventive concept cover any modifications and deviations that fall within the scope of the appended claims and their equivalents.

Claims

1. Electronic equipment, including: A display layer configured to display an image; as well as a sensor layer disposed on the display layer and defining a sensing area and a peripheral area adjacent to the sensing area, Wherein, the sensor layer comprises: a plurality of first electrodes extending in a first direction and arranged in a second direction intersecting the first direction; a plurality of second electrodes extending in the second direction and arranged in the first direction; a third electrode extending in the first direction and electrically insulated from the first electrode; a fourth electrode extending in the second direction and electrically insulated from the second electrode; a plurality of first traces electrically connected to the first electrodes, respectively, wherein the plurality of first traces overlap the peripheral area; and A sub-trace is electrically connected to a portion of the first trace and overlaps the sensing area.

2. The electronic device according to claim 1, wherein: The first trace and the sub-trace are disposed on different layers from each other.

3. The electronic device according to claim 2, wherein: Each of the first electrode and the second electrode and each of the third electrode and the fourth electrode are disposed on different layers from each other.

4. The electronic device according to claim 3, wherein: The sensor layer further comprises: a first insulating layer, covering the third electrode and the fourth electrode; and A second insulating layer is disposed on the first insulating layer, wherein the second insulating layer covers the first electrode and the second electrode.

5. The electronic device according to claim 4, wherein: The sensor layer further comprises a base layer disposed below the first insulating layer, Each of the first traces is disposed on the first insulating layer, and The sub-traces are disposed on the base layer.

6. The electronic device according to claim 5, wherein: The sub-trace overlaps the first electrode.

7. The electronic device according to claim 4, wherein: The sensor layer further comprises: a base layer, disposed below the first insulating layer; and a third insulating layer, disposed between the base layer and the first insulating layer, wherein each of the first traces is disposed on the first insulating layer, and The sub-trace is disposed on the base layer between the base layer and the third insulating layer.

8. The electronic device according to claim 7, wherein: The sub-trace overlaps at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode.

9. The electronic device according to claim 1, wherein: The sensor layer further includes a plurality of dummy patterns overlapping the first electrode and the second electrode.

10. The electronic device according to claim 9, wherein: The sub-traces are disposed between the dummy patterns on a plane.

11. The electronic device according to claim 1, wherein: The third electrode includes a plurality of first auxiliary electrodes extending in the first direction and arranged in the second direction, and the fourth electrode includes a plurality of second auxiliary electrodes extending in the second direction and arranged in the first direction, A first coupling capacitor is provided between one of the first electrodes and one of the first auxiliary electrodes, and A second coupling capacitor is provided between one of the second electrodes and one of the second auxiliary electrodes.

12. The electronic device according to claim 11, wherein: The sub-trace is disposed in a plane between the first auxiliary electrode and the second auxiliary electrode.

13. The electronic device according to claim 11, wherein: each of the second auxiliary electrodes includes a 2-1 auxiliary electrode and a 2-2 auxiliary electrode spaced apart from each other in the second direction, and The sub-trace is disposed between the 2-1st auxiliary electrode and the 2-2nd auxiliary electrode on a plane.

14. The electronic device according to claim 1, wherein: Each of the first electrodes comprises: a first main electrode electrically connected to the sub-trace; and The first sub-electrode is electrically insulated from the sub-trace.

15. The electronic device according to claim 14, wherein: The sub-trace overlaps two or more of the first sub-electrodes.

16. The electronic device according to claim 15, wherein: At least one of the first sub-electrodes is disposed between the first main electrode and the two or more first sub-electrodes overlapping the sub-trace.

17. The electronic device according to claim 14, wherein: Each of the sub-traces and the first main electrode is provided in plurality, and The first main electrode is disposed at an uppermost end of the first electrode in the second direction.

18. The electronic device according to claim 1, wherein: The first trace comprises: a plurality of 1-1th traces connected to a first end of each of the first electrodes; and A plurality of 1-2 trace lines are connected to a second end of each of the first electrodes opposite to the first end in the first direction.

19. The electronic device according to claim 18, wherein: The first electrode comprises: A 1-1th electrode connected to the 1-1th trace; and The 1-2nd electrode is connected to the 1-2nd trace.

20. The electronic device according to claim 18, wherein: The sub-traces include: a first sub-trace electrically connected to a portion of the 1-1th trace; and A second sub-trace is electrically connected to a portion of the 1-2th trace.

21. The electronic device according to claim 20, wherein: The first sub-trace and the second sub-trace are spaced apart from each other in the first direction.

22. The electronic device according to claim 1, further comprising: a plurality of second traces electrically connected to the second electrode; a third trace electrically connected to the third electrode; as well as A fourth trace is electrically connected to the fourth electrode.

23. The electronic device according to claim 22, wherein: The first trace and the third trace are spaced apart from each other, wherein the first electrode and the third electrode are between the first trace and the third trace, and The second trace and the fourth trace are spaced apart from each other, wherein the second electrode and the fourth electrode are between the second trace and the fourth trace.

24. The electronic device according to claim 22, wherein: The third trace overlaps the sub-trace.

25. The electronic device according to claim 1, wherein: A contact hole is provided in the sensor layer, and the first trace and the sub-trace are connected to each other through the contact hole.

26. The electronic device according to claim 25, wherein: The contact hole overlaps the peripheral region. 27 . The electronic device of claim 1 , further comprising a sensor driver configured to drive the sensor layer and operate in a first mode of sensing a touch input and a second mode of sensing a pen input.

28. Electronic equipment, including: a sensor layer including a plurality of first electrodes, a plurality of second electrodes, a plurality of first auxiliary electrodes, a plurality of second auxiliary electrodes, and a plurality of traces; as well as a sensor driver configured to drive the sensor layer and operate in a first mode for sensing a touch input and a second mode for sensing a pen input, A first coupling capacitor is provided between one of the plurality of first electrodes and one of the first auxiliary electrodes, and A second coupling capacitor is provided between one of the plurality of second electrodes and one of the second auxiliary electrodes. Wherein, the trace includes: a plurality of first traces electrically connected to the first electrodes respectively; and A sub-trace overlaps a portion of the plurality of first electrodes and is configured to electrically connect a portion of the first trace to the sensor driver.

29. The electronic device according to claim 28, wherein: The first trace and the sub-trace are disposed on different layers from each other.

30. The electronic device according to claim 29, wherein: The sensor layer further comprises: a first insulating layer, covering the first auxiliary electrode and the second auxiliary electrode; and The second insulating layer is disposed on the first insulating layer and covers the first electrode and the second electrode.

31. The electronic device according to claim 30, wherein: The sensor layer further comprises a base layer disposed below the first insulating layer, Each of the first traces is disposed on the first insulating layer, and The sub-traces are disposed on the base layer.

32. The electronic device according to claim 28, wherein: The sensor layer defines a sensing region and a peripheral region adjacent to the sensing region, and The first electrode, the second electrode, the first auxiliary electrode, and the second auxiliary electrode overlap the sensing area, and the first trace overlaps the peripheral area.

33. The electronic device according to claim 32, wherein: A first portion of the sub-trace overlaps the sensing region, and a second portion of the sub-trace overlaps the peripheral region.

34. The electronic device according to claim 33, wherein: A contact hole is provided in the sensor layer, the first trace and the sub-trace are connected to each other through the contact hole, and The contact hole overlaps the peripheral region.

35. Electronic equipment, including: A display layer configured to display an image; a sensor layer disposed on the display layer and defining a sensing area and a peripheral area adjacent to the sensing area; as well as a sensor driver configured to apply a signal to the sensor layer, Wherein, the sensor layer comprises: a plurality of first electrodes extending in a first direction and arranged in a second direction intersecting the first direction; a plurality of second electrodes extending in the second direction and arranged in the first direction; and a first trace connected to at least one of the first electrodes to transmit the signal to the first electrode, Wherein, the first trace comprises: a first portion connected to the first electrode, overlapping the peripheral region, and extending in the second direction; and A second portion is connected to the sensor driver, overlaps the sensing area, and extends in the second direction.

36. The electronic device according to claim 35, wherein: The sensor layer also includes a pad portion connected to the sensor driver, The first portion is disposed between the first electrode and the second portion, and The second portion is disposed between the first portion and the pad portion.

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