Data storage method, storage device and electronic equipment

Abstract

The invention provides a data storage method, a storage device and electronic equipment, relates to the technical field of storage, and aims at improving the address distribution capability and improving the data writing efficiency. The method comprises the following steps: receiving a plurality of write requests, wherein each write request carries data to be written; for any write request, generating a plurality of target addresses of a plurality of write requests according to the write request and the use information of at least three kinds of data management in the memory; the at least three data managements comprise three or more of a plurality of data blocks, a plurality of data pieces, a plurality of data rows and a plurality of data addresses, the use information comprises the size and occupation condition of various data managements in the memory, the target address comprises at least three levels of addresses, the first level of address is a target data block, and the second level of address is a target data row. The second-level address is a target data piece / target data row, and the third-level address is a target data address; and writing the plurality of to-be-written data carried by the plurality of write requests into address spaces corresponding to the plurality of target addresses.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a data storage method, a storage device and an electronic device. Background Art

[0002] At present, when a network processor (NP) forwards and processes a message, the message it forwards and processes is cached by the NP. Figure 1 As shown, NP includes: reassembly block (RB) and input buffer (IB). Among them, RB includes cell link list manager (CLLM) and reassembly controller (RC), and RC includes first input first output (FIFO) storage module. Specifically, after receiving the message, RC reassembles the control signal in the message (including source address, destination address, transmission protocol and message length, etc.), and sends a write request for applying for a write address to CLLM, and temporarily stores the data part in the message in the FIFO storage module; CLLM generates a write address according to the write request and sends the write address to RC. CLLM can only generate one write address at the same time. After receiving the write address, RC reads the data part from the FIFO storage module and writes the data part into the storage space indicated by the above write address in IB through the bus.

[0003] However, since CLLM can only generate one write address at the same time and has low address allocation capability, IB can only support one bus write, which reduces the efficiency of data writing. Summary of the invention

[0004] The present application provides a data storage method, a storage device and an electronic device, which relate to the field of storage technology and are used to improve the address allocation capability while improving the data writing efficiency.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, a data storage method is provided, the data storage method is applied to a storage device, the storage device includes a memory, and the method includes: receiving multiple write requests, each write request carries data to be written; for any one of the multiple write requests, generating multiple target addresses of the multiple write requests according to the write request and usage information of at least three types of data management in the memory; the at least three types of data management include three or more of multiple data blocks, multiple data slices, multiple data rows and multiple data addresses, the usage information includes the size and occupancy of various data management in the memory, and the target address includes at least three levels of addresses, wherein the first level address is a target data block in the multiple data blocks, the second level address is a target data slice / target data row in the multiple data slices / multiple data rows, and the third level address is a target data address in the multiple data addresses. Write the multiple data to be written carried by the multiple write requests into the address space corresponding to the multiple target addresses.

[0007] In the technical solution provided by the present application, after receiving multiple write requests, multiple target addresses of the multiple write requests are generated according to the write requests and usage information of at least three types of data management in the memory, thereby improving the address allocation capability. After obtaining the multiple target addresses, the multiple data to be written carried by the multiple write requests are written into the address space corresponding to the multiple target addresses, so that the memory can support multiple write requests at the same time, thereby improving the data writing efficiency. On the other hand, the data is directly stored in the storage device without having to enter other storage spaces for temporary storage, thereby reducing the movement of data and reducing power consumption.

[0008] In a possible implementation of the first aspect, at least three types of data management include multiple data blocks, multiple data slices, and multiple data addresses, each data block includes multiple data slices, each data slice includes multiple data addresses, and multiple target addresses are generated according to write requests and usage information, including: generating a target data block and a first-level address according to the size of the data, the size of the data block, and the occupancy of multiple data blocks; generating a target data slice and a second-level address according to the occupancy of multiple data slices included in the target data block; generating a third-level address according to the occupancy of multiple data addresses included in the target data slice, thereby generating a target address. In the above possible implementation, three levels of target addresses are generated step by step according to the occupancy of data blocks, data slices, and data addresses, which improves the efficiency of address generation at each level, while improving the balance of the three types of data management, and further improving the address allocation capability.

[0009] In a possible implementation of the first aspect, at least three types of data management include multiple data blocks, multiple data slices, multiple data rows, and multiple data addresses, each data block includes multiple data slices, each data slice includes multiple data rows, and each data row includes multiple data addresses. Multiple target addresses are generated according to write requests and usage information, including: generating a target data block and a first-level address according to the size of the data, the size of the data block, and the occupancy of multiple data blocks; generating a target data slice and a second-level address according to the occupancy of multiple data slices included in the target data block; generating a target data row and a third-level address according to the occupancy of multiple data rows included in the target data slice; generating a fourth-level address according to the occupancy of multiple data addresses included in the target data row, thereby generating a target address. In the above possible implementation, four levels of target addresses are generated level by level according to the occupancy of data blocks, data slices, data rows, and data addresses, and data is stored using more levels of target addresses, thereby improving the stability and reliability of data storage.

[0010] In a possible implementation of the first aspect, the method further includes: deleting multiple data stored in the multiple data addresses, and releasing the use lock permissions of the multiple data addresses. In the above possible implementation, the utilization rate of the multiple data addresses is improved.

[0011] In a possible implementation of the first aspect, the multiple write requests come from multiple buses respectively, and the width of the bus is the product of the size of the data block and the number of the data blocks. In the above possible implementation, the size consistency of the stored data is guaranteed, and the storage efficiency is improved.

[0012] In a possible implementation of the first aspect, the number of data rows included in any data slice is greater than or equal to the number of buses. In the above possible implementation, there are enough data rows to support multiple write requests, thereby improving the success rate of data writing.

[0013] In a possible implementation manner of the first aspect, the number of the multiple data addresses included in any one data row is equal to the size of the data row.

[0014] In a second aspect, a storage device is provided, which includes a coupled controller and a memory, the memory is used to store data, and the controller is used to: receive multiple write requests, each write request carries data to be written; for any one of the multiple write requests, generate multiple target addresses of the multiple write requests according to the write request and usage information of at least three types of data management in the memory; the at least three types of data management include three or more of multiple data blocks, multiple data slices, multiple data rows and multiple data addresses, the usage information includes the size and occupancy of various data management in the memory, the target address includes at least three levels of addresses, wherein the first level address is a target data block among the multiple data blocks, the second level address is a target data slice / target data row among the multiple data slices / multiple data rows, and the third level address is a target data address among the multiple data addresses; write the multiple data to be written carried by the multiple write requests into the address space corresponding to the multiple target addresses.

[0015] In a possible implementation of the second aspect, at least three types of data management include multiple data blocks, multiple data slices and multiple data addresses, each data block includes multiple data slices, and each data slice includes multiple data addresses. The controller is specifically used to: generate a target data block and a first-level address according to the size of the data, the size of the data block and the occupancy of multiple data blocks; generate a target data slice and a second-level address according to the occupancy of multiple data slices included in the target data block; generate a third-level address according to the occupancy of multiple data addresses included in the target data slice, thereby generating a target address.

[0016] In a possible implementation of the second aspect, at least three types of data management include multiple data blocks, multiple data slices, multiple data rows and multiple data addresses, each data block includes multiple data slices, each data slice includes multiple data rows, and each data row includes multiple data addresses. The controller is specifically used to: generate a target data block and a first-level address according to the size of the data, the size of the data block and the occupancy of multiple data blocks; generate a target data slice and a second-level address according to the occupancy of multiple data slices included in the target data block; generate a target data row and a third-level address according to the occupancy of multiple data rows included in the target data slice; generate a fourth-level address according to the occupancy of multiple data addresses included in the target data row, thereby generating a target address.

[0017] In a possible implementation manner of the second aspect, the controller is further used to: delete multiple data stored in multiple data addresses, and release usage lock permissions of the multiple data addresses.

[0018] In a possible implementation manner of the second aspect, the multiple write requests come from multiple buses respectively, and the width of the bus is the product of the size of the data block and the number of the data blocks.

[0019] In a possible implementation manner of the second aspect, the number of the multiple data rows included in any data slice is greater than or equal to the number of buses.

[0020] In a possible implementation manner of the second aspect, the number of the multiple data addresses included in any data row is equal to the size of the data row.

[0021] According to a third aspect, an electronic device is provided, comprising a processor and a storage device, wherein the storage device executes the data storage method provided in the first aspect or any possible implementation of the first aspect, and the processor is used to process data in the storage device.

[0022] In another aspect of the present application, a computer-readable storage medium is provided, which includes computer instructions. When the computer instructions are executed on a storage device, the storage device executes the data storage method provided by the first aspect or any possible implementation of the first aspect.

[0023] In another aspect of the present application, a computer program product comprising instructions is provided. When the computer program product is executed on a computer device, the computer device executes the data storage method provided in the first aspect or any possible implementation of the first aspect.

[0024] It can be understood that the storage device, electronic device, computer-readable storage medium and computer program product provided above can be used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the structure of a network processor NP;

[0026] Figure 2 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of the structure of another electronic device provided in an embodiment of the present application;

[0028] Figure 4 A flowchart of a data storage method provided in an embodiment of the present application;

[0029] Figure 5 A flowchart of another data storage method provided in an embodiment of the present application;

[0030] Figure 6 A flowchart of another data storage method provided in an embodiment of the present application;

[0031] Figure 7 A schematic diagram of the structure of a storage device IB provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In this application, "at least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple. In addition, the embodiments of the present application use words such as "first" and "second" to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0033] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0034] An embodiment of the present application provides a data storage method, which can be applied to a storage device, which may include a memory, and the data storage method includes: receiving multiple write requests, each write request carrying data to be written; for any one of the multiple write requests, generating multiple target addresses of the multiple write requests according to the write request and usage information of at least three types of data management in the memory; the at least three types of data management include three or more of multiple data blocks, multiple data slices, multiple data rows and multiple data addresses, the usage information includes the size and occupancy of various data management in the memory, the target address includes at least three levels of addresses, wherein the first level address is a target data block among the multiple data blocks, the second level address is a target data slice / target data row among the multiple data slices / multiple data rows, and the third level address is a target data address among the multiple data addresses; writing the multiple data to be written carried by the multiple write requests into the address space corresponding to the multiple target addresses. After receiving multiple write requests, this solution generates multiple target addresses for the multiple write requests based on the write requests and usage information of at least three types of data management in the memory, thereby improving the address allocation capability. After obtaining the multiple target addresses, the multiple data to be written carried by the multiple write requests are written into the address space corresponding to the multiple target addresses, so that the memory can support multiple write requests at the same time, thereby improving the data writing efficiency. On the other hand, the data is directly stored in the storage device without having to enter other storage spaces for temporary storage, thereby reducing data movement and reducing power consumption.

[0035] The storage device provided in the embodiments of the present application can be applied to electronic devices, which may include terminal devices, which may include but are not limited to personal computers, server computers, routers, switches, mobile devices (such as mobile phones, tablet computers, media players, etc.), wearable devices, vehicle-mounted devices, consumer terminal devices, mobile robots and drones, etc.

[0036] Combine the following Figure 2 The structure of the electronic device is introduced and described. For example, Figure 2 The electronic device 20 may include a processor 210, a bus 220, a storage device 230, and a communication interface 240. The processor 210, the storage device 230, and the communication interface 240 are connected via the bus 220.

[0037] It should be understood that in this embodiment, the processor 210 can be a (central processing unit, CPU), and the processor chip 210 can also be other general-purpose processors, digital signal processors (digital signal processing, DSP), (application-specific integrated circuit, ASIC), field-programmable gate arrays (field-programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor, etc. The processor 210 can also be a graphics processing unit (graphics processing unit, GPU), a neural network processing unit (neural network processing unit, NPU), a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the present application. In an embodiment of the present application, the processor 210 can be a network processor (network processor, NP).

[0038] The communication interface 240 is used to implement communication between the electronic device 20 and an external device or component.

[0039] The bus 220 may include a path for transmitting information between the above components (such as the processor 210 and the storage device 230). In addition to the data bus, the bus 220 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are marked as bus 220 in the figure. The bus 220 may be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 220 can be divided into an address bus, a data bus, a control bus, etc. Among them, the data bus may include a write data bus and a read data bus.

[0040] As an example, the electronic device 20 may include multiple processors. The processor may be a multi-core (multi-CPU) processor. The processor here may refer to one or more devices, circuits, and / or computing units for processing data (such as computer program instructions).

[0041] It is worth mentioning that Figure 2 In the example, an electronic device 20 including a processor 210 and a storage device 230 is taken as an example. Here, the processor 210 and the storage device 230 are respectively used to indicate a type of device or equipment. In a specific embodiment, the number of each type of device or equipment can be determined according to business requirements.

[0042] The storage device 230 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0043] In the embodiment of the present application, the storage device 230 may also be an input buffer (IB). Figure 3 As shown, the storage device 230 may include a controller 01 and a memory 02 .

[0044] The controller 01 may be used to receive information input by a peripheral device, for example, the peripheral device may include a bus 220. The information may include a write request, and the write request carries data to be written. The controller 01 is also used to generate a target address of the write request according to the write request and usage information of at least three types of data management, wherein the at least three types of data management include three or more of a plurality of data blocks, a plurality of data slices, a plurality of data rows, and a plurality of data addresses, the usage information includes the size and occupancy of various data managements in the memory 02, and the target address includes at least three levels of addresses, wherein the first level address is a target data block in a plurality of data blocks, the second level address is a target data slice / target data row in a plurality of data slices / a plurality of data rows, and the third level address is a target data address in a plurality of data addresses. Optionally, the controller 01 may further include at least three equalization units, and the at least three equalization units may be used to record the occupancy of at least three types of data management. The controller may further include at least three write distribution schedulers, and the at least three write distribution schedulers are used to support the controller 01 to generate a target address of the write request according to the write request and usage information of at least three types of data management.

[0045] The memory 02 can be used to store data information.

[0046] In practical applications, the processor 210 and the storage device 230 may be integrated on one chip, which may be referred to as a processor chip.

[0047] Combine the following Figure 2 and Figure 3 The electronic device shown in the figure introduces and illustrates the data storage method provided by the embodiment of the present application.

[0048] Figure 4 A schematic diagram of a data storage method provided in an embodiment of the present application, the method comprising:

[0049] S401: receiving multiple write requests, each of which carries data to be written.

[0050] Specifically, the storage device in the electronic device receives multiple write requests. For example, the controller in the storage device receives multiple write requests. The electronic device may be the above-mentioned Figure 2 or Figure 3 The electronic device 20 shown in FIG. 1 may be the controller Figure 3 Controller 01 shown in .

[0051] Wherein, the multiple write requests may come from multiple buses respectively, and the bus may include the above-mentioned Figure 2 or Figure 3 The bus 220 shown in FIG. 2 , specifically, multiple buses 220 send multiple write requests to the controller 01 respectively.

[0052] S402: For any one of the multiple write requests, generate multiple target addresses of the multiple write requests according to the write request and usage information of at least three types of data management in the memory; the at least three types of data management include three or more of multiple data blocks, multiple data slices, multiple data rows and multiple data addresses, the usage information includes the size and occupancy of various data management in the memory, and the target address includes at least three levels of addresses, wherein the first level address is a target data block among the multiple data blocks, the second level address is a target data slice / target data row among the multiple data slices / multiple data rows, and the third level address is a target data address among the multiple data addresses.

[0053] Specifically, the controller 01 may be configured to generate multiple target addresses of multiple write requests according to the write request and at least three types of usage information of data management.

[0054] The at least three data managements may include three data managements, or more than three data managements. For example, the at least three data managements may include four management layers. The following two embodiments illustrate different situations of the at least three data managements.

[0055] In a first possible embodiment, the at least three types of data management include three types of data management.

[0056] Exemplarily, the three types of data management include multiple data blocks whose identification information can be represented as C0 to Cn, multiple data slices whose identification information can be represented as S0 to Sm, and multiple data addresses whose identification information can be represented as A0 to Ag. Each of the multiple data blocks includes multiple data slices, and each of the multiple data slices includes multiple data addresses. n, m, and g are all positive integers.

[0057] Optionally, the three types of data management may also include data blocks, data rows and data addresses, or data slices, data rows and data addresses, which are not specifically limited in the embodiments of the present application.

[0058] In a second possible embodiment, the at least three data managements include four data managements.

[0059] Exemplarily, the four types of data management include multiple data blocks whose identification information can be represented as C0 to Cn, multiple data slices whose identification information can be represented as S0 to Sm, multiple data rows whose identification information can be represented as B0 to Bk, and multiple data addresses whose identification information can be represented as A0 to Ag. Each data block includes multiple data slices, each data slice includes multiple data rows, and each data row includes multiple data addresses. k is a positive integer.

[0060] Among them, a data block can also be called a data block unit (chunk), and multiple data blocks can also be called first-level management; a data slice can also be called a data slice unit (slice), and multiple data slices can also be called second-level management; a data row can also be called a data bank unit (bank), and multiple data rows can also be called third-level management; multiple data addresses can also be called fourth-level management.

[0061] In addition, the usage information also includes the occupancy status of data management, and the occupancy status includes occupied data management or unoccupied data management. For example, in the above-mentioned second possible embodiment, the occupancy status of at least three types of data management includes the occupancy status of multiple data blocks, the occupancy status of multiple data slices, the occupancy status of multiple data rows, and the occupancy status of multiple data addresses. Among them, the occupancy status of multiple data blocks includes occupied data blocks and unoccupied data blocks, the occupancy status of multiple data slices includes occupied data slices and unoccupied data slices, the occupancy status of multiple data rows includes occupied data rows and unoccupied data rows, and the occupancy status of multiple data addresses includes occupied data addresses and unoccupied data addresses. In actual applications, the controller can record the occupancy status of various data managements through different balancing units, and determine the data blocks, data slices, data rows or data addresses that need to be processed for this write request based on the occupancy status of various data managements, thereby quickly generating the target address.

[0062] Secondly, the usage information includes the size of data management, that is, the usage information includes the size of the data block, for example, the size of the data block can be 128 bytes or 64 bytes, which can be set according to actual needs or the experience of relevant staff, and this application does not make specific restrictions. The size of the data block can also be called the granularity of the data block or the management granularity of the data block.

[0063] Optionally, for the data to be written carried in any write request, the number of target addresses corresponding to the data is related to the size of the data and the size of the data block. For example, the size of the data block is 128 bytes and the size of the data is 256 bytes, that is, it is necessary to write data of 2 data blocks to the memory 02, and the data corresponds to 2 target addresses. For ease of understanding, the following embodiments all take the case where the size of the data is smaller than the size of the data block as an example, that is, for the data to be written carried in any write request, the data corresponds to one target address as an example.

[0064] In a possible embodiment, the width of the bus is the product of the size of the data block and the number of data blocks. For example, when the multiple data blocks include 8 data blocks and the size of the data block is 64 bytes, the width of the bus can be 512 bytes. The specific width of the bus can be set according to actual needs or the experience of relevant staff, and this application does not make specific restrictions on this. In this embodiment, the size consistency of the stored data is guaranteed, and the storage efficiency is improved.

[0065] In a possible embodiment, the number of multiple data rows included in any data slice is greater than or equal to the number of buses. For example, when the electronic device includes 4 buses, the number of data rows may be greater than or equal to 4, for example, the number of data rows may be 5. In this embodiment, there are enough data rows to support multiple write requests, thereby improving the success rate of data writing.

[0066] In practical applications, the number of multiple data addresses included in any data row is equal to the size of the data row. For example, if the size of the data row is 4 bytes, the data row includes 4 addresses.

[0067] Optionally, the target address may include three-level addresses, or may include addresses of more than three levels. The number of levels of the target address is equal to the number of at least three types of data management. For example, when there are three types of data management, the target address includes three-level addresses, and the target address includes (first-level address, second-level address, third-level address); when there are four types of data management, the target address includes four-level addresses, and the target address includes (first-level address, second-level address, third-level address, fourth-level address).

[0068] The specific process of determining the target address in the first and second embodiments above is described below.

[0069] In the first possible embodiment described above, the at least three types of data management may include three types of data management.

[0070] For example, Figure 5 As shown, step S402 specifically includes: step S4021: generating a target data block C0 and a first-level address C0 according to the size of the data, the size of the data block and the occupancy of multiple data blocks (i.e., balancing the selection of data blocks for this write operation according to the occupancy of multiple data blocks, for example, a data block with less resource occupancy can be selected as the data block for this write operation (less resource occupancy means: fewer data slices, data rows or data addresses are used)).

[0071] Step S402 specifically also includes step S4022: generating a target data slice S0 and a second-level address S0 according to the occupancy status of multiple data slices included in the target data block C0 (i.e., balancing the selection of data slices for this write operation according to the occupancy status of multiple data slices; for example, a data slice with less resource occupancy can be selected as the data slice for this write operation (less resource occupancy means: fewer data rows or data addresses are used)).

[0072] Step S402 specifically includes step S4023: generating a third-level address A0 according to the occupation of multiple data addresses included in the target data slice S0, thereby generating a target address (for example, an unused data address among the multiple data addresses can be selected as the data address of this write operation). Wherein, the target address is (C0, S0, A0).

[0073] In this embodiment, the controller 01 generates three levels of target addresses step by step according to the occupancy of data blocks, data slices and data addresses, thereby improving the efficiency of address generation at each level and improving the balance of the three types of data management; further, when there are multiple write requests, the controller 01 can simultaneously generate multiple target addresses for multiple write requests, thereby improving the address allocation capability; in addition, the data to be written in multiple write requests is written into the address space corresponding to the multiple target addresses, thereby improving the data writing efficiency. On the other hand, the data is directly stored in the storage device and is not temporarily stored in the processor 210, thereby reducing the storage pressure of the processor 210, while reducing the movement of data and reducing power consumption.

[0074] In the second possible embodiment described above, the at least three types of data management may include four management layers.

[0075] For example, Figure 6 As shown, step S402 specifically includes step S4021 and step S4022 in the first embodiment, and step S402 specifically also includes step S4024: generating a target data row B0 and a third-level address B0 according to the occupancy of multiple data rows included in the target data slice S0 (i.e., balancing the selection of data rows for this write operation according to the occupancy of multiple data rows, for example, data rows with less resource occupancy can be selected as the data rows for this write operation (less resource occupancy means: fewer data addresses are used)).

[0076] Step S402 specifically includes step S4025: generating a fourth-level address A0 according to the occupation of multiple data addresses included in the target data row B0, thereby generating a target address, wherein the target address is (C0, S0, B0, A0).

[0077] In this embodiment, the controller 01 generates four levels of target addresses step by step according to the occupancy of data blocks, data slices, data rows and data addresses, and uses more levels of target addresses to store data, thereby improving the stability and reliability of data storage.

[0078] In a possible embodiment, for any two write requests among the multiple write requests, the process of generating two target addresses of the two write requests are independent of each other.

[0079] In practical applications, the controller 01 may include a chunk dispatcher for write (CDW), a slice dispatcher for write (SDW), and an address dispatcher for write (ADW). CDW may be used to execute the above step S4021, SDW may be used to execute the above step S4022, and ADW may be used to execute the above step S4023 or step S4025. Optionally, the controller 01 may also include a bank dispatcher for write (BDW), and BDW may be used to execute the above step S4024.

[0080] Since the controller 01 can record the occupancy of various data management through different balancing units. In practical applications, the controller 01 may include a data block balancing unit (chunk load balance, CLB), a data slice balancing unit (slice load balance, SLB), and a data address balancing unit (address load balance, ALB). Among them, CLB can be used to record the occupancy of multiple data blocks, SLB can be used to record the occupancy of data slices, and ALB can be used to record the occupancy of data addresses. Optionally, the controller 01 may also include a data row balancing unit (bank load balance, BLB), which can be used to record the occupancy of data rows. Among them, the occupancy status can also be called resource occupancy status.

[0081] In a possible embodiment, each data slice corresponds to one SDW and one SLB, each data row corresponds to one BDW and one BLB, and multiple data addresses in each data row correspond to one ADW and one ALB.

[0082] Furthermore, the data storage method provided in the embodiment of the present application also includes step S403.

[0083] S403: Writing the multiple data to be written carried by the multiple write requests into the address space corresponding to the multiple target addresses.

[0084] Specifically, for multiple data to be written, the multiple data to be written can be written into the address spaces corresponding to multiple target addresses in the memory through multiple buses, that is, the multiple data to be written can be written into the address spaces corresponding to multiple target addresses through multiple buses at the same time. The memory can be the above Figure 3 Memory 02 shown in .

[0085] In a possible embodiment, the method provided in the embodiment of the present application further includes: deleting the multiple data stored in the multiple data addresses, and releasing the use lock permissions of the multiple data addresses, that is, reclaiming the multiple data addresses. In this embodiment, the utilization rate of the multiple data addresses is improved.

[0086] For ease of understanding, Figure 7 The storage device shown introduces and illustrates the data storage method provided in the embodiment of the present application. Figure 7 A data storage device is provided in an embodiment of the present application. The data storage device may include an IB70. The IB includes a controller 701 and a memory 702. Figure 7 The memory 702 is not shown. Figure 7 There are four data management examples including at least three types of data management.

[0087] Among them, the four types of data management include multiple data blocks C0 to Cn, each data block includes multiple data slices S0 to Sm, each data slice includes multiple data rows B0 to Bk, and each data row includes multiple data addresses A0 to Ag. n, m, k and g are all positive integers greater than or equal to 0, and n is greater than m, m is greater than k, and k is greater than g. The controller 701 includes a data block write distribution scheduler CDW, a data slice write distribution scheduler SDW, a data row write distribution scheduler BDW and a data address write distribution scheduler ADW. The controller 701 may also include a data block balancing unit CLB, a data slice balancing unit SLB, a data row balancing unit BLB and a data address balancing unit ALB. Among them, each balancing unit is used to record the occupancy of various data managements. Specifically, S701, the data block write distribution scheduler CDW receives multiple write requests, each of which carries data to be written; S702, the data block write distribution scheduler CDW generates the target data block C0 and the first-level address C0 according to the size of the data, the size of the data block and the occupancy of the data blocks C0 to Cn recorded in the CLB; S703, the data slice write distribution scheduler SDW generates the target data slice S0 and the second-level address S0 according to the occupancy of S0 to Sm included in the target data block C0 (recorded by the SLB); S704, the data row write distribution scheduler BDW generates the target data row B0 and the third-level address B0 according to the occupancy of B0 to Bk included in the target data slice S0 (recorded by the BLB); S705, the data row write distribution scheduler ADW generates the fourth-level address A0 according to the occupancy of A0 to Ag included in the target data row B0 (recorded by the ALB). Among them, the target address includes (C0, S0, B0, A0). Figure 7 In the example, the size of data is smaller than the size of the data block.

[0088] In the data storage method provided by the embodiment of the present application and the technical solution provided by the present application, after receiving multiple write requests, multiple target addresses of the multiple write requests are generated according to the write requests and usage information of at least three types of data management in the memory, thereby improving the address allocation capability. After obtaining the multiple target addresses, the multiple data to be written carried by the multiple write requests are written into the address space corresponding to the multiple target addresses, so that the memory can support multiple write requests at the same time, thereby improving the data writing efficiency. On the other hand, the data directly enters the storage device for storage without entering other storage spaces for temporary storage, thereby reducing the movement of data and reducing power consumption.

[0089] It is understandable that, in order to realize the above functions, the controller 01 includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in conjunction with the data processing method steps of each example described in the embodiments herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0090] The embodiment of the present application can divide the controller 01 into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0091] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, which will not be repeated here. The storage device 230 provided in the embodiment of the present application is used to perform the corresponding functions in the above embodiment, so it can achieve the same effect as the above control method.

[0092] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0093] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0094] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for the device to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks or optical disks.

[0095] Another aspect of the present application provides an electronic device, which includes a processor and a storage device, the storage device is used to execute the relevant steps in the above method embodiment, and the storage device can be the above Figure 3 The storage device 230 provided in the embodiment of the present invention is used for processing the data stored in the storage device.

[0096] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A data storage method, characterized in that: The data storage method is applied to a storage device, the storage device includes a memory, and the method includes: Receive multiple write requests, each write request carries data to be written; For any one of the multiple write requests, multiple target addresses of the multiple write requests are generated according to the write request and usage information of at least three types of data management in the memory; the at least three types of data management include three or more of multiple data blocks, multiple data slices, multiple data rows and multiple data addresses, the usage information includes the size and occupancy of various data management in the memory, and the target address includes at least three levels of addresses, wherein the first level address is a target data block among the multiple data blocks, the second level address is a target data slice / target data row among the multiple data slices / the multiple data rows, and the third level address is a target data address among the multiple data addresses; The multiple data to be written carried by the multiple write requests are written into the address space corresponding to the multiple target addresses.

2. The method according to claim 1, characterized in that The at least three types of data management include the multiple data blocks, the multiple data slices, and the multiple data addresses, each data block includes multiple data slices, each data slice includes multiple data addresses, and generating the multiple target addresses according to the write request and the usage information includes: Generate a target data block and a first-level address according to the size of the data, the size of the data block and the occupancy of the multiple data blocks; Generate a target data slice and a second-level address according to the occupancy status of multiple data slices included in the target data block; A third-level address is generated according to the occupation status of multiple data addresses included in the target data slice, thereby generating a target address.

3. The method according to claim 1, characterized in that The at least three types of data management include the multiple data blocks, the multiple data slices, the multiple data rows and the multiple data addresses, each data block includes multiple data slices, each data slice includes multiple data rows, each data row includes multiple data addresses, and the multiple target addresses are generated according to the write request and the usage information, including: Generate a target data block and a first-level address according to the size of the data, the size of the data block and the occupancy of the multiple data blocks; Generate a target data slice and a second-level address according to the occupancy status of multiple data slices included in the target data block; Generate a target data row and a third-level address according to the occupancy status of multiple data rows included in the target data slice; A fourth-level address is generated according to the occupation status of multiple data addresses included in the target data row, thereby generating a target address.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: The multiple data stored in the multiple data addresses are deleted, and the use lock permissions of the multiple data addresses are released.

5. The method according to any one of claims 1 to 4, characterized in that: The multiple write requests come from multiple buses respectively, and the width of the bus is the product of the size of the data block and the number of the data blocks.

6. The method according to claim 5, characterized in that The number of the multiple data rows included in any one data slice is greater than or equal to the number of the buses.

7. The method according to any one of claims 1 to 6, characterized in that: The number of the multiple data addresses included in any one data row is equal to the size of the data row.

8. A storage device, characterized in that: The device comprises a coupled controller and a memory, the memory being configured to store data, the controller being configured to: Receive multiple write requests, each write request carries data to be written; For any one of the multiple write requests, multiple target addresses of the multiple write requests are generated according to the write request and usage information of at least three types of data management in the memory; the at least three types of data management include three or more of multiple data blocks, multiple data slices, multiple data rows and multiple data addresses, the usage information includes the size and occupancy of various data management in the memory, and the target address includes at least three levels of addresses, wherein the first level address is a target data block among the multiple data blocks, the second level address is a target data slice / target data row among the multiple data slices / the multiple data rows, and the third level address is a target data address among the multiple data addresses; The multiple data to be written carried by the multiple write requests are written into the address space corresponding to the multiple target addresses.

9. The device according to claim 8, characterized in that The at least three types of data management include the multiple data blocks, the multiple data slices and the multiple data addresses, each data block includes multiple data slices, each data slice includes multiple data addresses, and the controller is specifically used to: Generate a target data block and a first-level address according to the size of the data, the size of the data block and the occupancy of the multiple data blocks; Generate a target data slice and a second-level address according to the occupancy status of multiple data slices included in the target data block; A third-level address is generated according to the occupation status of multiple data addresses included in the target data slice, thereby generating a target address.

10. The device according to claim 8, characterized in that The at least three types of data management include the multiple data blocks, the multiple data slices, the multiple data rows and the multiple data addresses, each data block includes multiple data slices, each data slice includes multiple data rows, each data row includes multiple data addresses, and the controller is specifically used to: Generate a target data block and a first-level address according to the size of the data, the size of the data block and the occupancy of the multiple data blocks; Generate a target data slice and a second-level address according to the occupancy status of multiple data slices included in the target data block; Generate a target data row and a third-level address according to the occupancy status of multiple data rows included in the target data slice; A fourth-level address is generated according to the occupation status of multiple data addresses included in the target data row, thereby generating a target address.

11. The device according to any one of claims 8 to 10, characterized in that: The controller is also used for: The multiple data stored in the multiple data addresses are deleted, and the use lock permissions of the multiple data addresses are released.

12. The device according to any one of claims 8 to 11, characterized in that: The multiple write requests come from multiple buses respectively, and the width of the bus is the product of the size of the data block and the number of the data blocks.

13. The device according to claim 12, characterized in that The number of the multiple data rows included in any one data slice is greater than or equal to the number of the buses.

14. The device according to any one of claims 8 to 13, characterized in that: The number of the multiple data addresses included in any one data row is equal to the size of the data row.

15. An electronic device, characterized in that: The electronic device comprises a processor and a storage device, the storage device comprises the storage device according to any one of claims 8 to 14, and the processor is used for processing data stored in the storage device.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes computer instructions, and when the computer instructions are executed on the storage device, the storage device executes the data storage method according to any one of claims 1 to 7.

17. A computer program product comprising instructions, characterized in that When the computer program product is executed on a computer device, the computer device is caused to execute the data storage method according to any one of claims 1 to 7.

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