Memory system, operating method thereof, and electronic device

Abstract

The embodiment of the invention provides a memory system, an operation method thereof and electronic equipment. The memory system includes: a memory device configured to store data; a controller coupled to the memory device; the controller is configured to: perform a first training operation of a data sampling delay value based on first training data, determine a first delay value range for the memory device to correctly read and write the first training data; performing a second training operation of a data sampling delay value based on the second training data, and determining a second delay value range in which the memory device correctly reads and writes the second training data; wherein data values of any two adjacent transmission periods in the first training data are opposite, data values of any two adjacent transmission periods in the second training data are opposite, and the first training data are different from the second training data; an actual data sampling delay value is determined based on the first range of delay values and the second range of delay values.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of memory, and in particular, to a memory system and an operating method thereof, and an electronic device. Background Art

[0002] Memories are often used to meet data exchange and storage requirements at different levels. As the operating frequency of the processor increases, the frequency of the memory interface is also required to be higher. Higher frequencies and signal quality issues of signal lines can easily lead to a decrease in the stability of memory access. Therefore, in order to improve the stability of memory access, the memory can be trained to continuously adjust the clock delay value for read and write operations to obtain the optimal clock delay value. However, existing memory training methods still have problems such as poor accuracy and long time consumption. Summary of the invention

[0003] In view of this, embodiments of the present application provide a memory system and an operating method thereof, and an electronic device.

[0004] On the one hand, an embodiment of the present application provides a memory system, including:

[0005] a memory device configured to store data;

[0006] A controller coupled to the memory device; the controller is configured to:

[0007] Performing a first training operation on data sampling delay values ​​based on first training data to determine a first delay value range that enables the memory device to correctly read and write the first training data;

[0008] Performing a second training operation on the data sampling delay value based on the second training data to determine a second delay value range that enables the memory device to correctly read and write the second training data;

[0009] The data values ​​of any two adjacent transmission periods in the first training data are opposite, the data values ​​of any two adjacent transmission periods in the second training data are opposite, and the first training data is different from the second training data;

[0010] An actual data sampling delay value is determined based on the first delay value range and the second delay value range.

[0011] In some embodiments, each bit value corresponding to the first training data and the second training data is opposite.

[0012] In some embodiments, the controller is specifically configured to:

[0013] Based on different data sampling delay values, training data is written into the memory device, and corresponding data is read from the memory device, and a delay value range of the data sampling delay value that makes the read data the same as the training data is determined; wherein the training data includes the first training data, and the delay value range includes the first delay value range; or, the training data includes the second training data, and the delay value range includes the second delay value range.

[0014] In some embodiments, the controller is specifically configured to:

[0015] Based on a plurality of data sampling delay values ​​that increase in sequence, the training data is written into the memory device, and corresponding data is read from the memory device; a first data sampling delay value that makes the read data identical to the training data is determined as a first boundary value of the delay value range; a first data sampling delay value that makes the read data different from the training data and greater than the first boundary value is determined as a second boundary value of the delay value range;

[0016] or,

[0017] Based on a plurality of data sampling delay values ​​that decrease in sequence, the training data is written into the memory device, and the corresponding data is read from the memory device; the first data sampling delay value that makes the read data identical to the training data is determined to be the second boundary value; and the first data sampling delay value that makes the read data different from the training data and smaller than the second boundary value is determined to be the first boundary value.

[0018] In some embodiments, determining the actual data sampling delay value based on the first delay value range and the second delay value range includes:

[0019] determining an intersection of the first delay value range and the second delay range;

[0020] The actual data sampling delay value is determined based on the intersection.

[0021] In some embodiments, determining the actual data sampling delay value based on the intersection includes:

[0022] One of a plurality of quartiles of the intersection is determined as the actual data sampling delay value.

[0023] In some embodiments, the controller is coupled to the memory device via N data lines, where N is a positive integer; the first training data corresponds to N bits of data in each transmission cycle and is transmitted respectively via the N data lines, and the second training data corresponds to N bits of data in each transmission cycle and is transmitted respectively via the N data lines.

[0024] On the other hand, an embodiment of the present application further provides an operating method of a memory system, the memory system comprising a memory device and a controller coupled to the memory device; the operating method comprising:

[0025] Performing a first training operation on data sampling delay values ​​based on first training data to determine a first delay value range that enables the memory device to correctly read and write the first training data;

[0026] Performing a second training operation on the data sampling delay value based on the second training data to determine a second delay value range that enables the memory device to correctly read and write the second training data;

[0027] The data values ​​of any two adjacent transmission periods in the first training data are opposite, the data values ​​of any two adjacent transmission periods in the second training data are opposite, and the first training data is different from the second training data;

[0028] An actual data sampling delay value is determined based on the first delay value range and the second delay value range.

[0029] In some embodiments, each bit value corresponding to the first training data and the second training data is opposite.

[0030] In some embodiments, the method specifically comprises:

[0031] Based on different data sampling delay values, training data is written into the memory device, and corresponding data is read from the memory device, and a delay value range of the data sampling delay value that makes the read data the same as the training data is determined; wherein the training data includes the first training data, and the delay value range includes the first delay value range; or, the training data includes the second training data, and the delay value range includes the second delay value range.

[0032] In some embodiments, the method specifically comprises:

[0033] Based on a plurality of data sampling delay values ​​that increase in sequence, the training data is written into the memory device, and corresponding data is read from the memory device; a first data sampling delay value that makes the read data identical to the training data is determined as a first boundary value of the delay value range; a first data sampling delay value that makes the read data different from the training data and greater than the first boundary value is determined as a second boundary value of the delay value range;

[0034] or,

[0035] Based on a plurality of data sampling delay values ​​that decrease in sequence, the training data is written into the memory device, and the corresponding data is read from the memory device; the first data sampling delay value that makes the read data identical to the training data is determined to be the second boundary value; and the first data sampling delay value that makes the read data different from the training data and smaller than the second boundary value is determined to be the first boundary value.

[0036] In some embodiments, determining the actual data sampling delay value based on the first delay value range and the second delay value range includes:

[0037] determining an intersection of the first delay value range and the second delay range;

[0038] The actual data sampling delay value is determined based on the intersection.

[0039] In some embodiments, determining the actual data sampling delay value based on the intersection includes:

[0040] One of a plurality of quartiles of the intersection is determined as the actual data sampling delay value.

[0041] In some embodiments, the controller is coupled to the memory device via N data lines, where N is a positive integer; the first training data corresponds to N bits of data in each transmission cycle and is transmitted respectively via the N data lines, and the second training data corresponds to N bits of data in each transmission cycle and is transmitted respectively via the N data lines.

[0042] On the other hand, an embodiment of the present application further provides an electronic device, comprising: the memory system according to any one of the above embodiments; and a processor coupled to the memory system.

[0043] In the embodiment of the present application, the data values ​​of any two adjacent transmission cycles in the first training data are opposite, the data values ​​of any two adjacent transmission cycles in the second training data are opposite, and the first training data is different from the second training data. In this way, on the one hand, the data values ​​of any two adjacent transmission cycles in each training data are opposite, ensuring that the transmission level on the data line is always alternating between 0 and 1 during the read and write operations, which is conducive to improving the accuracy of the data sampling delay value training results; on the other hand, the controller only uses two different training data to perform the data sampling delay value training operation, which is conducive to reducing the training time and improving the working efficiency of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of a memory system provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of a data line in a memory system provided in an embodiment of the present application;

[0046] Figure 3 A flowchart of a data sampling delay value training operation based on training data provided in an embodiment of the present application;

[0047] Figure 4 A schematic diagram of an intersection of a first delay value range and a second delay value range provided in an embodiment of the present application;

[0048] Figure 5 A flowchart of an intersection operation provided in an embodiment of the present application;

[0049] Figure 6 A flowchart of an operating method of a memory system provided in an embodiment of the present application;

[0050] Figure 7 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the embodiments of the present application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0053] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0055] In a memory system, data transmission between a memory device and a controller usually uses a data sampling (DataStrobe Signal, DQS) signal to sample a data signal (DQ) for read and write operations. In order to improve the stability of memory device access, the data sampling delay value of the data sampling signal can be trained, for example, read and write operations are performed under different data sampling delay values ​​to obtain the optimal actual data sampling delay value.

[0056] In some embodiments, multiple data sampling delay values ​​can be polled to read and write a fixed training data from the memory device through the bus at each data sampling delay value, and determine whether the written and read data are consistent, so as to find the actual data sampling delay value of the data sampling signal. Specifically, a fixed training data can be written and read based on multiple different data sampling delay values, and a data sampling delay value range that makes the written data the same as the read data can be determined; and then the actual data sampling delay value is determined based on the data sampling delay value range. However, since there may be signal quality issues on multiple data lines between the memory device and the controller, using only one fixed training data for training will result in inaccurate training results.

[0057] In other embodiments, multiple data sampling delay values ​​may be polled to read and write a large number of different training data from a memory device through a bus at each data sampling delay value, and determine whether the written and read data are consistent, thereby finding the actual data sampling delay value of the data sampling signal. Specifically, based on multiple different data sampling delay values, one training data may be written and read each time, and a data sampling delay value range that makes the written data the same as the read data may be determined; then, based on multiple data sampling delay value ranges corresponding to the multiple training data, the actual data sampling delay value may be determined. However, a large amount of training data may result in a long training time, and may not necessarily guarantee the validity of the actual data sampling delay value.

[0058] like Figure 1 As shown, an embodiment of the present application provides a memory system 100, including: a memory device 110, configured to store data; a controller 120, coupled to the memory device 110; the controller 120 is configured to: perform a first training operation of a data sampling delay value based on first training data, and determine a first delay value range that enables the memory device 110 to correctly read and write the first training data; perform a second training operation of a data sampling delay value based on second training data, and determine a second delay value range that enables the memory device 110 to correctly read and write the second training data; wherein, the data values ​​of any two adjacent transmission cycles in the first training data are opposite, the data values ​​of any two adjacent transmission cycles in the second training data are opposite, and the first training data is different from the second training data; and determine the actual data sampling delay value based on the first delay value range and the second delay value range.

[0059] In the embodiment of the present application, the memory system 100 includes at least one memory device 110 and a controller 120 coupled to the memory device 110 . The memory device 110 may be a volatile memory, including but not limited to a static random access memory (SRAM), a synchronous static random access memory (SSRAM), a pseudo static random access memory (PSRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) synchronous dynamic random access memory, an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM), a direct rambus random access memory (DRRAM), etc. The memory device 110 may also be a non-volatile memory, including but not limited to a read-only memory (ROM), a programmable read-only memory (PROM), a programmable read-only memory (PROM), etc. The memory device 110 may be an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electrically Erasable Programmable Read-Only Memory), a ferromagnetic random access memory (FRAM), a flash memory, etc. Here, the memory device 110 is described as a pseudo-static random access memory.

[0060] The controller 120 may be implemented by any suitable logic device, such as an application specific integrated circuit (ASIC), a DSP, a programmable logic device (PLD), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a general processor, a controller, a microcontroller (MCU), a microprocessor, etc. Here, the controller 120 is implemented by a part of the circuit in the microcontroller as an example for explanation.

[0061] The controller 120 uses the first training data and the second training data to perform a training operation of the data sampling delay value. Exemplarily, the controller 120 can perform a read and write operation of the training data under multiple data sampling delay values, respectively. The controller 120 can write and read the training data to the memory device 110 at a data sampling delay value each time. If the written and read data are correct, the data sampling delay value is added to the delay value range; in this way, the delay value range consisting of the data sampling delay value that enables the training data to be correctly read and written can be obtained; then, the controller 120 can determine the final actual data sampling delay value based on the first delay value range corresponding to the first training data and the second delay value range corresponding to the second training data. In other words, the controller 120 uses a polling method for both the first training data and the second training data to find out the delay value range corresponding to the memory device 110 to correctly write and read the training data. It should be noted that the multiple data sampling delay values ​​used in the training operation can be determined by a pre-experimental or empirical value. Multiple data sampling delay values ​​can be polled in an order from small to large, from large to small, etc., or they can be traversed in a completely random order.

[0062] The transmission of the first training data between the controller 120 and the memory device 110 may include multiple transmission cycles, and the data values ​​of any two adjacent transmission cycles in the first training data are opposite, where "opposite data values" refers to a pair of opposite binary values ​​of "1" and "0". Exemplarily, the first training data includes 8 bits of data corresponding to each transmission cycle. For example, the data corresponding to the i-th transmission cycle in the first training data is "00000000", i is an integer greater than 1, and the data corresponding to the i-1th transmission cycle and the i+1th transmission cycle in the first training data are both "11111111". That is, when the first training data is transmitted between the controller 120 and the memory device 110, the levels of any two adjacent transmission cycles are opposite, and sampling using the DQS signal at alternating levels can improve the accuracy of the training results. The second training data can be understood with reference to the above-mentioned example of the first training data, which will not be repeated here. However, it should be noted that the second training data is different from the first training data, so the actual data sampling delay value is determined by combining the first delay value range and the second delay value range to enhance the robustness of the training process and further improve the accuracy of the data sampling delay value training results.

[0063] In this way, on the one hand, the data values ​​of any two adjacent transmission cycles in each training data are opposite, ensuring that the transmission level on the data line always alternates between 0 and 1 during read and write operations, which is beneficial to improving the accuracy of the data sampling delay value training results; on the other hand, the controller only uses two different training data to perform data sampling delay value training operations, which is beneficial to reducing training time and improving the working efficiency of the memory system.

[0064] In some embodiments, the value of each bit corresponding to the first training data and the second training data is opposite.

[0065] In an embodiment of the present application, each bit corresponding to the first training data and the second training data has an opposite value, that is, each bit of the first training data is complementary to each other. For example, if the binary value of the first training data is "000000001111111100000000011111111", the binary value of the second training data is "111111110000000001111111100000000". It should be noted that the bit width of the first training data and the second training data is 32 bits as an example, but the bit width of the data in the present application is not limited to 32 bits. Through relevant tests, it can be found that whether the data "0" or the data "1" is transmitted first on the data line between the controller 120 and the memory device 110, the delay value range obtained by the final training is different. Therefore, by making each bit of the first training data complementary to that of the second training data, and then determining the actual data sampling delay value by combining the corresponding first delay value range and second delay value range (such as taking the intersection), the robustness of the data sampling delay value training can be further improved, making the training result more accurate. For example, the first training data can be 0x00FF00FF (hexadecimal value), and the second training data can be 0xFF00FF00.

[0066] In some embodiments, Figure 2 As shown, the controller 120 is coupled to the memory device 110 via N data lines, where N is a positive integer; the first training data corresponding to the N bits of data in each transmission cycle are transmitted respectively via the N data lines, and the second training data corresponding to the N bits of data in each transmission cycle are transmitted respectively via the N data lines.

[0067] In the embodiment of the present application, data is transmitted between the controller 120 and the memory device 110 via N data lines. Figure 2 The 8 data lines shown (corresponding to DQ0 to DQ7, respectively) are used as an example for explanation. The 8 data lines can transmit 8 bits of data at the same time, that is, the edge of a clock signal (such as a DQS signal) can transmit 1 byte of data. Since the signal quality of each data line in the memory system 100 is inconsistent, it is necessary to perform data sampling delay value training to obtain a suitable data sampling delay value so that the DQS signal can accurately sample the DQ signal.

[0068] The first training data corresponds to N bits of data in each transmission cycle and is transmitted through N data lines. For example, the 8-bit data corresponding to the i-th transmission cycle in the first training data is "00000000", and each bit in "00000000" is transmitted through a corresponding data line. The second training data can be understood with reference to the example of the first training data above, and will not be described in detail here.

[0069] In some embodiments, the controller 120 is specifically configured to: write training data into the memory device 110 based on different data sampling delay values, and read corresponding data from the memory device 110, and determine a delay value range of the data sampling delay value that makes the read data the same as the training data; wherein the training data includes first training data, and the delay value range includes a first delay value range; or, the training data includes second training data, and the delay value range includes a second delay value range.

[0070] In an embodiment of the present application, the controller 120 writes and reads the training data at a plurality of different data sampling delay values. For example, the controller 120 can write the training data to the memory device 110 at a data sampling delay value each time, and read the corresponding data. If the read data is the same as the written training data, the data sampling delay value is added to the delay value range. In this way, all data sampling delay values ​​that make the read data the same as the training data together constitute the delay value range corresponding to the training data. In other words, the controller 120 can determine whether the data sampling delay value enables the memory device 110 to correctly read and write the training data by comparing the read data and the training data. In some embodiments, the controller 120 can implement the above comparison process through a comparator hardware circuit or software.

[0071] In other embodiments, the memory system 100 may also determine whether the current data sampling delay value enables the memory device 110 to correctly read and write the training data in other ways. For example, the training data may be written into the memory device 110 in advance, the controller 120 reads the training data from the memory device 110, and then rewrites the read data into the memory device 110, and then the memory device 110 determines whether the rewritten data is the same as the original training data, so as to determine whether the current data sampling delay value enables the memory device 110 to correctly read and write the training data.

[0072] In some embodiments, the controller 120 is specifically configured to: write the training data to the memory device 110 based on a plurality of data sampling delay values ​​that increase in sequence, and read the corresponding data from the memory device 110; determine the first data sampling delay value that makes the read data the same as the training data as a first boundary value of the delay value range; determine the first data sampling delay value that makes the read data different from the training data and greater than the first boundary value as a second boundary value of the delay value range; or, based on a plurality of data sampling delay values ​​that decrease in sequence, write the training data to the memory device 110, and read the corresponding data from the memory device 110; determine the first data sampling delay value that makes the read data the same as the training data as a second boundary value; determine the first data sampling delay value that makes the read data different from the training data and less than the second boundary value as the first boundary value.

[0073] In an embodiment of the present application, the controller 120 may poll multiple data sampling delay values ​​in a training operation in an order from small to large or from large to small. Exemplarily, the controller 120 polls multiple data sampling delay values ​​in an order from small to large. At this time, the first data sampling delay value that makes the read data the same as the training data is the minimum boundary value of the delay value range, that is, the above-mentioned first boundary value; as the data sampling delay value gradually increases, the read data and the training data remain the same within a certain range. When the data sampling delay value continues to increase, the read data and the training data are different again. The data sampling delay value at this time can be determined as the maximum boundary value of the delay value range, that is, the above-mentioned second boundary value. The specific process of polling multiple data sampling delay values ​​in an order from large to small is opposite to the above-mentioned polling process from small to large, and will not be repeated here.

[0074] In some embodiments, the controller 120 is specifically configured to: write training data to the memory device 110 based on a first delay value; read corresponding data from the memory device 110; when the read data is different from the training data, increase the first delay value by a first preset step size, and write the training data to the memory device 110 based on the updated first delay value; when the read data is the same as the training data, determine the first delay value as a first boundary value; increase the first boundary value by a second preset step size as a second delay value, and write the training data to the memory device 110 based on the second delay value; read corresponding data from the memory device 110; when the read data is the same as the training data, increase the second delay value by a second preset step size, and write the training data to the memory device 110 based on the updated second delay value; when the read data is different from the training data, determine the second delay value as a second boundary value.

[0075] In the embodiments of the present application, Figure 3 The figure shows a flow chart of the steps of the controller performing data sampling delay value training based on any training data to determine the delay value range corresponding to the training data. It should be noted that Figure 3 Only the process of polling multiple data sampling delay values ​​in ascending order is shown.

[0076] Specifically, first, the controller writes the training data into the memory device based on the first delay value (step S101), where the initial first delay value can be the minimum value among multiple data sampling delay values, and the initial first delay value can be determined by experiments or experience values. Then the controller reads the corresponding data from the memory device (step S102), and determines whether the read data is the same as the training data (step S103). If the read data is different from the training data, the controller increases the first delay value by a first preset step size (step S104), and based on the updated first delay value, writes the training data into the memory device again for the next round of reading and judgment, and the first preset step size can be determined by experiments or experience values. If the read data is the same as the training data, the controller determines the current first delay value as the minimum boundary value of the delay value range, that is, the first boundary value (step S105).

[0077] After determining the first boundary value, the controller increases the first boundary value by a second preset step size as a second delay value (step S106), and writes the training data into the memory device based on the second delay value (step S107). The controller then reads the corresponding data from the memory device (step S108), and determines whether the read data is the same as the training data (step S109). If the read data is the same as the training data, the controller increases the second delay value by a second preset step size (step S106), and based on the updated second delay value, writes the training data into the memory device again for the next round of reading and judgment. The second preset step size can be determined by experiments or empirical values. If the read data is the same as the training data, the controller determines the current second delay value as the maximum boundary value of the delay value range, i.e., the second boundary value (step S110).

[0078] It should be noted that the first preset step size and the second preset step size can be set according to the actual performance requirements of the memory system. The smaller the preset step size, the more polling times, the longer the training time, but the more accurate the boundary value obtained by training. The larger the preset step size, the fewer polling times, the shorter the training time, but the accuracy of the boundary value obtained by training is reduced.

[0079] In some embodiments, Figure 4 and Figure 5 As shown, determining the actual data sampling delay value based on the first delay value range and the second delay value range includes: determining the intersection of the first delay value range and the second delay range; and determining the actual data sampling delay value based on the intersection.

[0080] In the examples of this application, refer to Figure 4 , the controller can take the intersection of the first delay value range and the second delay value range, and determine any value in the intersection as the actual data sampling delay value. Figure 5According to the steps shown, the controller can compare the first boundary value of the first delay value range and the second delay value range (step S201), and use the larger of the first boundary value left1 of the first delay value range and the first boundary value left2 of the second delay value range as the minimum boundary value left of the intersection (step S202 and step S203). Then, the controller can compare the second boundary value of the first delay value range and the second delay value range (step S204), and use the smaller of the second boundary value right1 of the first delay value range and the second boundary value right2 of the second delay value range as the maximum boundary value right of the intersection (step S205 and step S206). Finally, the controller determines the actual data sampling delay value based on the intersection (step S207). In some embodiments, the controller can implement the above comparison process through a comparator hardware circuit or software.

[0081] In some embodiments, determining the actual data sampling delay value based on the intersection includes: determining one of a plurality of quartiles of the intersection as the actual data sampling delay value.

[0082] In the embodiment of the present application, one of the first quartile, median (i.e., second quartile), and third quartile of the intersection can be determined as the actual data sampling delay value according to the design requirements of the memory system. It should be noted that the present application can also determine other values ​​in the intersection as the actual data sampling delay value, and no excessive restrictions are made here.

[0083] Based on the same inventive concept, an embodiment of the present application further provides an operating method of a memory system, wherein the memory system includes a memory device and a controller coupled to the memory device; Figure 6 As shown, the method includes:

[0084] Step S301, performing a first training operation of a data sampling delay value based on first training data, and determining a first delay value range that enables a memory device to correctly read and write the first training data;

[0085] Step S302, performing a second training operation of the data sampling delay value based on the second training data, and determining a second delay value range that enables the memory device to correctly read and write the second training data; wherein the data values ​​of any two adjacent transmission cycles in the first training data are opposite, the data values ​​of any two adjacent transmission cycles in the second training data are opposite, and the first training data is different from the second training data;

[0086] Step S303: determining an actual data sampling delay value based on the first delay value range and the second delay value range.

[0087] It should be understood that Figure 6The steps shown in the operations are not exclusive, and other steps may be performed before, after, or between any steps in the operations shown.

[0088] In this way, on the one hand, the data values ​​of any two adjacent transmission cycles in each training data are opposite, ensuring that the transmission level on the data line always alternates between 0 and 1 during read and write operations, which is beneficial to improving the accuracy of the data sampling delay value training results; on the other hand, the method only uses two different training data for data sampling delay value training operations, which is beneficial to reducing training time and improving the working efficiency of the memory system.

[0089] In some embodiments, the value of each bit corresponding to the first training data and the second training data is opposite.

[0090] In some embodiments, the operating method specifically includes: based on different data sampling delay values, writing training data into a memory device, and reading corresponding data from the memory device, and determining a delay value range of the data sampling delay value that makes the read data the same as the training data; wherein the training data includes first training data, and the delay value range includes a first delay value range; or, the training data includes second training data, and the delay value range includes a second delay value range.

[0091] In some embodiments, the operation method specifically includes: based on a plurality of data sampling delay values ​​that increase in sequence, writing training data to a memory device, and reading corresponding data from the memory device; determining that the first data sampling delay value that makes the read data the same as the training data is a first boundary value of a delay value range; determining that the first data sampling delay value that makes the read data different from the training data and greater than the first boundary value is a second boundary value of the delay value range; or, based on a plurality of data sampling delay values ​​that decrease in sequence, writing training data to a memory device, and reading corresponding data from the memory device; determining that the first data sampling delay value that makes the read data the same as the training data is a second boundary value; determining that the first data sampling delay value that makes the read data different from the training data and less than the second boundary value is a first boundary value.

[0092] In some embodiments, the operation method specifically includes: writing training data to a memory device based on a first delay value; reading corresponding data from the memory device; when the read data is different from the training data, increasing the first delay value by a first preset step size, and writing the training data to the memory device based on the updated first delay value; when the read data is the same as the training data, determining the first delay value as a first boundary value; increasing the first boundary value by a second preset step size as a second delay value, and writing the training data to the memory device based on the second delay value; reading corresponding data from the memory device; when the read data is the same as the training data, increasing the second delay value by a second preset step size, and writing the training data to the memory device based on the updated second delay value; when the read data is different from the training data, determining the second delay value as a second boundary value.

[0093] In some embodiments, determining the actual data sampling delay value based on the first delay value range and the second delay value range includes: determining an intersection of the first delay value range and the second delay range; and determining the actual data sampling delay value based on the intersection.

[0094] In some embodiments, determining the actual data sampling delay value based on the intersection includes: determining one of a plurality of quartiles of the intersection as the actual data sampling delay value.

[0095] In some embodiments, the controller is coupled to the memory device via N data lines, where N is a positive integer; the first training data corresponding to N bits of data in each transmission cycle are transmitted via the N data lines respectively, and the second training data corresponding to N bits of data in each transmission cycle are transmitted via the N data lines respectively.

[0096] Based on the same inventive concept, the present application also provides an electronic device, such as Figure 7 As shown, the electronic device 200 includes: a memory system 100 in any one of the above embodiments; a processor 210 coupled to the memory system 100. Exemplarily, the processor 210 may be a microprocessor, the memory device 110 in the memory system 100 may be a pseudo-static random access memory, and the controller 120 may be the processor 210 or may be implemented by at least a portion of the circuits in the processor 210 ( Figure 7 It is only shown for example that the controller 120 is implemented by a part of the circuit of the processor 210 ).

[0097] In the memory system, the operation method of the memory system, and the electronic device provided by the present application, on the one hand, the data values ​​of any two adjacent transmission cycles in each training data are opposite, ensuring that the transmission level on the data line always alternates between 0 and 1 during read and write operations, which is beneficial to improving the accuracy of the data sampling delay value training results; on the other hand, the method only uses two different training data to perform data sampling delay value training operations, which is beneficial to reducing the training time and improving the working efficiency of the memory system.

[0098] The various embodiments / implementations provided in this application can be combined with each other without causing any contradiction.

[0099] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memory system, characterized in that: The memory system comprises: a memory device configured to store data; A controller coupled to the memory device; the controller is configured to: Performing a first training operation on data sampling delay values ​​based on first training data to determine a first delay value range that enables the memory device to correctly read and write the first training data; Performing a second training operation on the data sampling delay value based on the second training data to determine a second delay value range that enables the memory device to correctly read and write the second training data; The data values ​​of any two adjacent transmission periods in the first training data are opposite, the data values ​​of any two adjacent transmission periods in the second training data are opposite, and the first training data is different from the second training data; An actual data sampling delay value is determined based on the first delay value range and the second delay value range.

2. The memory system according to claim 1, wherein: The value of each bit corresponding to the first training data and the second training data is opposite.

3. The memory system according to claim 1, wherein: The controller is specifically configured as follows: Based on different data sampling delay values, training data is written into the memory device, and corresponding data is read from the memory device, and a delay value range of the data sampling delay value that makes the read data the same as the training data is determined; wherein the training data includes the first training data, and the delay value range includes the first delay value range; or, the training data includes the second training data, and the delay value range includes the second delay value range.

4. The memory system according to claim 3, characterized in that: The controller is specifically configured as follows: Based on a plurality of data sampling delay values ​​that increase in sequence, the training data is written into the memory device, and corresponding data is read from the memory device; a first data sampling delay value that makes the read data identical to the training data is determined as a first boundary value of the delay value range; a first data sampling delay value that makes the read data different from the training data and greater than the first boundary value is determined as a second boundary value of the delay value range; or, Based on a plurality of data sampling delay values ​​that decrease in sequence, the training data is written into the memory device, and the corresponding data is read from the memory device; the first data sampling delay value that makes the read data identical to the training data is determined to be the second boundary value; and the first data sampling delay value that makes the read data different from the training data and smaller than the second boundary value is determined to be the first boundary value.

5. The memory system according to claim 1, wherein: The determining of the actual data sampling delay value based on the first delay value range and the second delay value range comprises: determining an intersection of the first delay value range and the second delay range; The actual data sampling delay value is determined based on the intersection.

6. The memory system according to claim 5, characterized in that: The determining the actual data sampling delay value based on the intersection includes: One of a plurality of quartiles of the intersection is determined as the actual data sampling delay value.

7. The memory system according to any one of claims 1 to 6, characterized in that: The controller is coupled to the memory device via N data lines, wherein N is a positive integer; the first training data corresponding to N bits of data in each transmission cycle are transmitted respectively via the N data lines, and the second training data corresponding to N bits of data in each transmission cycle are transmitted respectively via the N data lines.

8. A method for operating a memory system, characterized in that: The memory system includes a memory device and a controller coupled to the memory device; the operating method includes: Performing a first training operation on data sampling delay values ​​based on first training data to determine a first delay value range that enables the memory device to correctly read and write the first training data; Performing a second training operation on the data sampling delay value based on the second training data to determine a second delay value range that enables the memory device to correctly read and write the second training data; The data values ​​of any two adjacent transmission periods in the first training data are opposite, the data values ​​of any two adjacent transmission periods in the second training data are opposite, and the first training data is different from the second training data; An actual data sampling delay value is determined based on the first delay value range and the second delay value range.

9. The operating method according to claim 8, characterized in that: The value of each bit corresponding to the first training data and the second training data is opposite.

10. The operating method according to claim 8, characterized in that: The method specifically comprises: Based on different data sampling delay values, training data is written into the memory device, and corresponding data is read from the memory device, and a delay value range of the data sampling delay value that makes the read data the same as the training data is determined; wherein the training data includes the first training data, and the delay value range includes the first delay value range; or, the training data includes the second training data, and the delay value range includes the second delay value range.

11. The operating method according to claim 10, characterized in that: The method specifically comprises: Based on a plurality of data sampling delay values ​​that increase in sequence, the training data is written into the memory device, and corresponding data is read from the memory device; a first data sampling delay value that makes the read data identical to the training data is determined as a first boundary value of the delay value range; a first data sampling delay value that makes the read data different from the training data and greater than the first boundary value is determined as a second boundary value of the delay value range; or, Based on a plurality of data sampling delay values ​​that decrease in sequence, the training data is written into the memory device, and the corresponding data is read from the memory device; the first data sampling delay value that makes the read data identical to the training data is determined to be the second boundary value; and the first data sampling delay value that makes the read data different from the training data and smaller than the second boundary value is determined to be the first boundary value.

12. The operating method according to claim 8, characterized in that: The determining of the actual data sampling delay value based on the first delay value range and the second delay value range comprises: determining an intersection of the first delay value range and the second delay range; The actual data sampling delay value is determined based on the intersection.

13. The operating method according to claim 12, characterized in that: The determining the actual data sampling delay value based on the intersection includes: One of a plurality of quartiles of the intersection is determined as the actual data sampling delay value.

14. The operating method according to any one of claims 8 to 13, characterized in that: The controller is coupled to the memory device via N data lines, wherein N is a positive integer; the first training data corresponding to N bits of data in each transmission cycle are transmitted respectively via the N data lines, and the second training data corresponding to N bits of data in each transmission cycle are transmitted respectively via the N data lines.

15. An electronic device, characterized in that: include: The memory system as claimed in claims 1 to 7; A processor is coupled to the memory system.

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