Implementation method for 32-bit SSD master controller to process high-capacity solid state disk

Abstract

The invention provides an implementation method for processing a high-capacity solid state disk by a 32-bit SSD (Solid State Disk) master controller, which comprises the following steps of: processing a write command of a host: applying for a buffer area of a static random access memory when a memory management unit receives the write command, and coding a physical address of write command data to be written into an NAND flash memory into 32 bits by a hardware acceleration unit; and the memory management unit sends a write application to the front-end NVME module, write command data is transmitted from the host to a buffer area of the static random access memory in a direct memory access mode, and the SSD master controller drives the NAND controller to write the data into the NAND flash memory. According to the method, a large number of tasks needing to be processed by the CPU are completed by hardware, so that the complexity of software operation is reduced while the access efficiency is ensured, the number of needed CPUs is reduced, and the cost is saved.

Description

Technical Field

[0001] The present invention relates to the field of solid state disk storage, and more specifically to a method for implementing a 32-bit SSD master controller to process a large-capacity solid state disk. Background Art

[0002] With the rapid development of information technology, the amount of data of enterprises and individuals is growing, and the demand for large-capacity storage is becoming more and more urgent. Today, SSDs generally use L2P mapping tables to record the relationship between host logical block addresses and NAND physical block addresses. However, as the supported capacity increases, when the NAND physical block address information exceeds 32 bits, in the 32-bit CPU architecture, generally only the variables for storing data and the size of the L2P mapping table can be increased, but this will cause the logic and tasks that the CPU and software have to process to increase significantly. In order to ensure the access rate, only the number of CPUs can be increased or the CPU frequency can be increased, but this will increase the cost.

[0003] As the management complexity of the FTL algorithm increases, the number of transactions that the CPU needs to manage increases, and resource utilization and access efficiency become thorny issues. It is necessary to reduce the complexity of the software while ensuring access efficiency to reduce the number of CPUs in order to achieve the goal of reducing costs. Summary of the invention

[0004] The object of the present invention is to provide a method for realizing a 32-bit large-capacity solid-state hard disk by reducing software complexity to save resources of a CPU of an SSD host controller, thereby reducing costs.

[0005] According to one aspect of the present invention, a method for implementing a 32-bit SSD master controller to process a large-capacity solid-state hard disk is provided.

[0006] Processing host write commands:

[0007] When the memory management unit receives a write command, it applies for a buffer in the static random access memory.

[0008] The hardware acceleration unit encodes the physical address of the write command data to be written into the NAND flash memory into 32 bits.

[0009] The memory management unit sends a write request to the front-end NVME module, and transmits the write command data from the host to the buffer of the static random access memory by direct memory access, and the SSD master controller drives the NAND controller to write the data to the NAND flash memory;

[0010] Processing host's read command:

[0011] After receiving the read command, the hardware acceleration unit queries the L2P mapping table to obtain a 32-bit physical address corresponding to the logical address of the read command, and the hardware acceleration unit decodes the physical address.

[0012] The memory management unit requests a buffer for static random access memory.

[0013] The NAND controller reads the read command data from the NAND flash memory according to the physical address and transmits it to the buffer of the static random access memory.

[0014] The front-end NVME module transmits the read command data back to the host.

[0015] In some implementations, the front-end NVME module receives a write command or a read command.

[0016] In some implementations, after the hardware acceleration unit encodes the physical address of the write command data to be written into the flash memory into 32 bits, the L2P mapping table is updated.

[0017] In some implementations, the L2P mapping table is stored in a dynamic random access memory.

[0018] In some implementations, a P2L mapping table is stored in the NAND flash memory, and the hardware acceleration unit records the L2P mapping table during operation.

[0019] In some implementations, when garbage collection is started, the P2L mapping table of the block of the NAND flash memory that requires garbage collection is read to a specific location and then compared with the L2P mapping table stored in the dynamic random access memory.

[0020] The beneficial effects are as follows: the present invention reduces the storage resources for storing the L2P mapping table and simplifies the resources for processing data by the CPU and hardware. The present invention completes a large number of tasks that need to be processed by the CPU of the SSD master controller by hardware, thereby reducing the complexity of software operations while ensuring access efficiency, reducing the number of required CPUs, and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a system framework of a method for implementing a 32-bit large-capacity solid-state hard disk according to an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of a process of processing a write command in a method for implementing a 32-bit large-capacity solid-state hard disk according to an embodiment of the present invention;

[0023] Figure 3A schematic diagram of a flow chart of processing a read command in a method for implementing a 32-bit large-capacity solid-state hard disk according to an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of comparing an L2P mapping table and a P2L mapping table during garbage processing of a method for implementing a 32-bit large-capacity solid-state hard disk according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described below in conjunction with the accompanying drawings.

[0026] Figure 1 The system schematically shows a method for implementing a 32-bit large-capacity solid-state hard disk of the present invention. Figure 1 As shown, the system includes a memory management unit (BMU), a front-end NVME module, an SSD master controller, a NAND controller (NCTL) and a hardware acceleration unit (HW ACC). The memory management unit (BMU) is responsible for managing the memory buffer resources of the system. The front-end NVME module is responsible for communicating with the host. The SSD master controller CPU is responsible for software algorithms. The NAND controller NCTL is responsible for communicating with the flash memory (NAND). The hardware acceleration unit (HW ACC) is responsible for some hardware acceleration functions. The front-end NVME module receives commands (cmd) and data from the host. The memory management unit (BMU) automatically applies for memory buffer resources instead of the CPU. The hardware acceleration unit (HW ACC) replaces the SSD master controller CPU to make some settings, such as modifying the mapping table (L2P table) from the logical address to the physical address. After receiving the commands (cmd) and data received by the front-end NVME module, the SSD master controller drives the NAND controller (NTCL) to perform read and write operations. The NAND controller (NCTL) is responsible for communicating with the NAND.

[0027] Figure 2 and Figure 3 A method for implementing a 32-bit large-capacity solid-state hard disk of the present invention is schematically shown.

[0028] The physical address PBA of Nand flash memory is composed of the following parts, including block, page, chip (CE), flash channel, and fragment, which are combined into an integer value. The data variables that describe and store integer values ​​in current computer systems are generally 1 byte (8bit), 2 bytes (16bit), 4 bytes (32bit), 8 bytes (64bit), etc. The bit width for data calculation or transmission in computer systems is generally 4 bytes (32bit), 8 bytes (64bit), etc. When the capacity increases, the components of the physical address PBA of the above Nand flash memory are combined to exceed 32bit, resulting in the need to expand the L2P mapping table (table) storing PBA. The original 4-byte storage space needs to be expanded to 8-byte storage space for storage, and the SSD host controller and hardware acceleration unit (HW ACC) that processes PBA need to support 64-bit processing logic. When the SSD is operating the Nand flash memory, it needs to use information such as block, page, chip (CE), flash channel, fragment, etc. Without expanding the capacity and updating the SSD master controller, the physical address (PBA) recorded in the L2P mapping table can only record 32 bits. The present invention uses a custom encoding scheme and hardware conversion function to achieve the function of using 32 bits to describe a physical address (PBA) exceeding 32 bits, such as 33 or 34 bits.

[0029] Take an 8TB SSD implemented by a Nand flash memory as an example. The NAND flash memory has 363 blocks, 4176 pages, and 24 fragments, which requires 8 channels and 8 CEs. In the above solution, a block needs 9 bits to describe, a page needs 13 bits to describe, a CE channel needs 6 bits to describe, and a fragment needs 5 bits to describe. In total, 33 bits are needed to describe the physical address PBA. However, the values ​​of the block, page, and fragment do not use all the values ​​of the corresponding bit numbers. By re-encoding the block, page, and fragment data, the corresponding bits can be encoded. This encoding and conversion is automatically completed by the hardware acceleration module (HWACC), and the software can also call this function.

[0030] like Figure 2As shown, when the front-end NVME module receives a write command (write cmd) from the host, it sends the write command to the memory management unit (BMU), and the memory management unit (BMU) automatically applies for a buffer of the static random access memory (SRAM). The memory management unit sends a write application to the front-end NVME module, and the front-end NVME module transfers the data corresponding to the write command in the host to the applied static random access memory buffer (SRAM buffer) by direct memory access (DMA). The memory management unit (BMU) sends the write command to the SSD master controller CPU, which allocates an available NAND flash memory physical address and sends the write command to the nand controller, which writes the data to different blocks of the NAND flash memory. At the same time, the hardware acceleration unit (HW ACC) encodes the physical address (PBA) exceeding 32 bits in the NAND flash memory to which the write command data is to be written into 32 bits, and the hardware acceleration unit (HW ACC) updates the logical address to physical address mapping table (L2P table) information in the dynamic random access memory (DRAM). During the reading and writing process, the relationship between the host logic block address and the physical block address of the NAND flash memory is represented by the L2P mapping table. The L2P mapping table of the present invention will be fully recorded in the dynamic random access memory (DRAM) during operation.

[0031] like Figure 3As shown in the figure, when a read command (read cmd) is received from the host through the front-end NVMe module, the read command is sent to the memory management unit (BMU) and the hardware acceleration unit (HW ACC). The hardware acceleration unit (HW ACC) queries the L2P mapping table in the dynamic random access memory (DRAM) to obtain the 32-bit physical address (PBA) corresponding to the logical address (LBA) of the read command, and decodes it into the block, page, CE, channel, and fragment information required by the software. The above information is directly related to the physical address of the NAND flash memory where specific data is stored. The hardware acceleration unit (HW ACC) and the memory management unit (BMU) send all the information of the read command to the SSD master controller CPU, and the CPU of the SSD master controller sends the read command to the NAND controller. When the Nand controller completes the read command, the memory management unit (BMU) applies for the buffer (SRAM buffer) resources in the static random access memory. The NAND controller reads the data corresponding to the read command from the NAND flash memory according to the physical address information and transmits it to the buffer (SRAM buffer) in the static random access memory. The memory management unit sends the read request to the front-end NVME module, which then sends the data back to the host. The entire process is mostly completed by hardware, without the need for the FTL layer to participate too much.

[0032] When the physical address (PBA) information exceeds 32 bits, the above method will be used for mapping, converting the physical address (PBA) exceeding 32 bits into a 32-bit physical address (PBA), so as to achieve the purpose of using 32 bits to represent the physical address (PBA) information exceeding 32 bits. This reduces the storage resources for storing the L2P mapping table and simplifies the resources for CPU and hardware to process data.

[0033] In addition, considering the efficiency of garbage collection (GC), the present invention also uses a P2L mapping table to improve the efficiency of garbage collection GC. During the operation of the SSD, the host may repeatedly write the same logical address LBA. At this time, in order to increase the access speed, the SSD generally writes new data to a new NAND flash physical address PBA when writing repeatedly. Then the data written by the original NAND flash physical address PBA is invalid. During the garbage collection GC operation, we need to write the latest valid data to a new block. The existing SSD GC operation requires the CPU of the SSD master controller to query the L2P mapping table in sequence to find out which positions of the current garbage collection (GC) block are valid data. However, this requires the CPU of the SSD master controller to query the L2P table one by one, and also needs to record the changes of the L2P table in real time, which increases the access efficiency and software complexity. The present invention records L2P table information in the hardware acceleration unit (HW ACC) during operation, and records the P2L table information of the current block at a fixed position in the NAND flash memory, that is, the correspondence between the physical address PBA information of the NAND flash memory and the logical address LBA. When GC is started, the hardware reads the P2L mapping table of the block of the NAND flash memory that needs GC to a specific position and then compares it with the L2P mapping table information in the current DRAM. The PBA with the same information is a valid PBA. The hardware will automatically spit out the PBA that needs garbage collection GC, and then allocate it to the channel corresponding to the GC for GC processing.

[0034] like Figure 4 As shown, initially the L2P mapping table is LBA0 corresponding to PBA0, LBA1 corresponding to PBA1, LBA2 corresponding to PBA2, LBA3 corresponding to PBA3, and the P2L mapping table will also store the same correspondence, PBA0 corresponding to LBA0, PBA1 corresponding to LBA1, PBA2 corresponding to LBA2, and PBA3 corresponding to LBA3. The P2L mapping table is written to the NAND flash memory. After the P2L mapping table is written to the NAND flash memory, if the host writes LBA0 again, the new data of the host is directly written to other physical addresses PBA to update the L2P mapping table. Figure 4The new data is written to the physical address PBA marked as 0x1000. When the garbage collector GC reads the P2L mapping table and compares the L2P mapping table, it is found that LBA0 in the L2P mapping table no longer corresponds to PBA0. The location data of PBA0 is invalid. The GC can skip this 4K storage unit page without copying the invalid data in the PAB0 physical address to the new physical block. The hardware acceleration unit (HW ACC) compares the L2P mapping table and the P2L mapping table to obtain the corresponding 4K that needs GC garbage collection.

[0035] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A method for implementing a 32-bit SSD master controller to process a large-capacity solid-state hard disk, characterized in that: Processing host write commands: When the memory management unit receives a write command, it applies for a buffer in the static random access memory. The hardware acceleration unit encodes the physical address of the write command data to be written into the NAND flash memory into 32 bits. The memory management unit sends a write request to the front-end NVME module, and transmits the write command data from the host to the buffer of the static random access memory by direct memory access, and the SSD master controller drives the NAND controller to write the data to the NAND flash memory; Processing host's read command: After receiving the read command, the hardware acceleration unit queries the L2P mapping table to obtain a 32-bit physical address corresponding to the logical address of the read command, and the hardware acceleration unit decodes the physical address. The memory management unit requests a buffer for static random access memory. The NAND controller reads the read command data from the NAND flash memory according to the physical address and transmits it to the buffer of the static random access memory. The front-end NVME module transmits the read command data back to the host.

2. The method for implementing a 32-bit SSD master controller to process a large-capacity solid-state hard disk according to claim 1, characterized in that: The front-end NVME module receives a write command or a read command.

3. The method for implementing a 32-bit SSD master controller to process a large-capacity solid-state hard disk according to claim 1, characterized in that: After the hardware acceleration unit encodes the physical address of the write command data to be written into the flash memory into 32 bits, the L2P mapping table is updated.

4. The method for implementing a 32-bit SSD master controller to process a large-capacity solid-state hard disk according to claim 3, characterized in that: The L2P mapping table is stored in a dynamic random access memory.

5. The method for implementing a 32-bit SSD master controller to process a large-capacity solid-state hard disk according to claim 1, characterized in that: The NAND flash memory stores a P2L mapping table, and the hardware acceleration unit records the L2P mapping table during operation.

6. The method for implementing a 32-bit SSD master controller to process a large-capacity solid-state hard disk according to claim 5, characterized in that: When garbage collection is started, the P2L mapping table of the block of the NAND flash memory that needs garbage collection is read out and compared with the L2P mapping table stored in the dynamic random access memory.

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