Storage device and capacity detection control method, device and equipment of storage device

Abstract

The invention relates to storage equipment, and a capacity detection control method, device and equipment of the storage equipment. The storage device comprises a front end, a rear end and a first-class flash memory, the front end is connected with the rear end, the rear end is connected with the first-class flash memory through chip selection signals, and the rear end is used for scanning the chip selection signals through first-class firmware in the power-on process of the storage device so as to determine target chip selection signals connected with the first-class flash memory and obtain capacity parameters of the first-class flash memory. The capacity of the storage device is determined according to the capacity parameter and the target chip selection signal, the front end is used for issuing the second type of firmware to the rear end again after the rear end determines the capacity of the storage device, and the rear end is used for inputting and outputting data according to the capacity of the storage device through the second type of firmware. By adopting the method, the problem of memory occupation caused by adding a capacity detection function in the prior art can be solved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage device, a method, a device and a device for detecting and controlling the capacity of a storage device. Background Art

[0002] With the development of information technology, a large amount of data is generated all the time in all walks of life, and the storage of this large amount of data is becoming increasingly important. At the same time, solid-state drives are replacing mechanical hard drives with their faster read and write speeds, higher reliability, and lower energy consumption. In the field of storage devices, capacity is a key consideration. It not only determines how much data a device can store, but is also closely related to the performance and cost of the device.

[0003] At present, the capacity of storage devices is written in the firmware, and different capacities require different firmware, which makes the production process more complicated. When compiling the firmware package of the solid-state drive, multiple firmware packages need to be compiled, and the compilation time is several times longer than the normal compilation time, which greatly affects the efficiency of development; even if the compilation process is controlled by scripts and one-click compilation can be achieved, the compilation time cannot be shortened.

[0004] To solve this problem, the current general practice is to add a capacity detection function to the storage device to achieve the same set of firmware to adapt to a variety of different capacities. However, the operation of the capacity detection function requires a certain amount of IRAM (Internal Random Access Memory) or DRAM (Dynamic Random Access Memory). The solid-state drive controllers currently on the market have relatively little redundant space reserved during design, resulting in insufficient resources available for the firmware to work normally after adding the above function. Summary of the invention

[0005] Based on this, it is necessary to provide a storage device, a capacity detection control method, an apparatus and a device for a storage device that can solve the problem of memory occupancy during capacity detection in order to solve the above technical problems.

[0006] In a first aspect, a storage device is provided, the storage device comprising a front end, a back end and a first type of flash memory, the front end is connected to the back end, and the back end is connected to the first type of flash memory through a chip select signal, wherein:

[0007] The backend is used to scan the chip select signal through the first type firmware during the power-on process of the storage device to determine the target chip select signal connected to the first type flash memory, obtain the capacity parameter of the first type flash memory, and determine the capacity of the storage device according to the capacity parameter and the target chip select signal;

[0008] The front end is used to re-send the second type of firmware to the back end after the back end determines the capacity of the storage device;

[0009] The back end is used to input and output data according to the capacity of the storage device through the second type of firmware.

[0010] In one embodiment, the first type of flash memory is provided with a logic unit, the back end is connected to the logic unit through a chip select signal, the capacity parameter includes the number of logic units connected to the chip select signal and the size of the logic unit, the capacity includes physical capacity and user capacity, and the storage device is further provided with a second type of flash memory, wherein,

[0011] The back end is used to read the page parameters of the first type of flash memory connected to the target chip select signal, extract the number of logic units connected to the chip select signal and the size of the logic units from the page parameters, and determine the physical capacity of the storage device according to the number of logic units connected to the target chip select signal and the size of the logic units;

[0012] The backend is also used to obtain the daily whole disk write count pre-burned in the second type of flash memory, and determine the user capacity based on the daily whole disk write count and the physical capacity;

[0013] Among them, physical capacity is used to control the input and output of data, and user capacity is used for client queries.

[0014] In one of the embodiments, the backend is used to determine the reservation ratio according to the number of full disk writes per day, and determine the user capacity according to the reservation ratio and the physical capacity.

[0015] In one embodiment, the first type of flash memory is NAND flash memory, and the second type of flash memory is NOR flash memory.

[0016] In one embodiment, the back end is provided with at least one channel, the channel is provided with a channel controller, the channel controller is connected to at least one chip select signal, the chip select signal is connected to at least one first type flash memory, wherein,

[0017] The back end is used to run the first type of firmware through the channel controller during the power-on process of the storage device, so as to sequentially set each chip selection signal according to a preset sequence, and send a reset signal to the first type of flash memory connected to each chip selection signal;

[0018] The back end is also used to read the state of the first type flash memory connected to each chip select signal after a preset time, so as to scan the chip select signal, obtain the chip select signal of the connected first type flash memory in a reset state, and obtain the target chip select signal.

[0019] In one embodiment, the channel includes a plurality of channels, wherein:

[0020] The front end is also used to detect the number of logical units connected to each channel. When it is detected that the number of logical units connected to channels exceeding a preset number is less than the number of logical units connected to other channels, an abnormal log is recorded and the storage device is set to an abnormal state.

[0021] In a second aspect, a capacity detection control method for a storage device is provided. The storage device includes a front end, a back end, and a first type of flash memory. The front end is connected to the back end, and the back end is connected to the first type of flash memory through at least one chip select signal. The method is applied to the back end. The capacity detection control method for the storage device includes:

[0022] During the power-on process of the storage device, the chip select signal is scanned by the first type of firmware to determine the target chip select signal connected to the first type of flash memory;

[0023] Obtaining capacity parameters of the first type of flash memory, and determining the capacity of the storage device according to the capacity parameters and the target chip select signal;

[0024] The second type of firmware sent by the front end is received, and the second type of firmware is run to input and output data according to the capacity of the storage device.

[0025] In a third aspect, a capacity detection control device for a storage device is provided. The storage device includes a front end, a back end, and a first type of flash memory. The front end is connected to the back end. The back end and the first type of flash memory are connected via at least one chip select signal. The device is applied to the back end. The capacity detection control device for the storage device includes:

[0026] A scanning module, used for scanning the chip select signal through the first type of firmware during the power-on process of the storage device to determine the target chip select signal connected to the first type of flash memory;

[0027] An acquisition module, used for acquiring capacity parameters of the first type of flash memory, and determining the capacity of the storage device according to the capacity parameters and the target chip selection signal;

[0028] The running module is used to receive the second type of firmware sent by the front end, and run the second type of firmware to input and output data according to the capacity of the storage device.

[0029] In a fourth aspect, the present application provides a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the processor implements the steps of the storage device capacity detection control method provided in any one of the embodiments of the present application in the first aspect.

[0030] In a fifth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the storage device capacity detection control method provided in any embodiment of the present application in the first aspect.

[0031] The above-mentioned storage device, storage device capacity detection control method, device and equipment, by writing a first type of firmware specifically for scanning, this firmware is specifically responsible for completing the capacity scanning function, and can complete the scanning task under limited memory resources. When the scanning firmware completes the capacity scanning function, it re-sends the second type of firmware for normal operation to the back end. In this way, after completing the critical capacity scan, the back end can switch to the normal working mode, so that the input and output operations of the data can operate normally, avoiding functional confusion or malfunction due to insufficient memory. Therefore, the use of this application can solve the memory occupation problem caused by adding the capacity detection function in the traditional technology, and realize that when there is not much redundant space in the back end of the storage device, the flash memory capacity scan can still be completed and the storage device can perform data input and output normally, ensuring the stable operation of the storage device, and improving the flexibility and reliability of the storage device capacity identification and data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the internal structure of a storage device in some embodiments;

[0033] Figure 2 A schematic diagram of the internal structure of a storage device in some embodiments;

[0034] Figure 3 Schematic diagram of the flow of a capacity detection control method of a storage device in some other embodiments;

[0035] Figure 4 is a structural block diagram of a capacity detection control device for a storage device in some embodiments;

[0036] Figure 5 1 is a diagram of the internal structure of a computer device in some embodiments. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] In a first aspect, a storage device is provided, such as Figure 1 As shown, the storage device includes a front end, a back end and a first type of flash memory, the front end is connected to the back end, and the back end is connected to the first type of flash memory through a chip select signal, wherein,

[0039] The backend is used to scan the chip select signal through the first type firmware during the power-on process of the storage device to determine the target chip select signal connected to the first type flash memory, obtain the capacity parameter of the first type flash memory, and determine the capacity of the storage device according to the capacity parameter and the target chip select signal;

[0040] The front end is used to re-send the second type of firmware to the back end after the back end determines the capacity of the storage device;

[0041] The back end is used to input and output data according to the capacity of the storage device through the second type of firmware.

[0042] Among them, storage devices are devices used to store data information. It can include hard disks (such as mechanical hard disks and solid-state hard disks). In computer systems, storage devices are an important part of data storage. Storage arrays in servers are also a type of storage device that can provide a large amount of data storage services.

[0043] For a solid-state drive, the front end is a module that interacts with a server or PC (Personal Computer). It is mainly responsible for receiving data and instructions from external devices (such as servers and PCs), and at the same time feeding back the information processed inside the storage device to the external device.

[0044] The backend refers to the module that stores the data received by the frontend in the disk. It is responsible for communicating with the flash memory, managing and storing data, including reading and writing operations on the flash memory.

[0045] Type I flash memory refers to a non-volatile storage technology that can store data even after power failure. Type I flash memory has the characteristics of high storage density and can store a large amount of data in a small physical space, so it is often used in large-capacity data storage devices such as solid state drives (SSDs) and USB flash drives.

[0046] The chip enable (CE) signal is a signal between the back end and the first type of flash memory for selecting a specific flash memory chip (or flash memory unit). By scanning the chip enable signal, the back end can determine which flash memories are connected and their related information.

[0047] The capacity parameter is used to describe the storage capacity-related characteristics of the first type of flash memory and is an important basis for determining the overall capacity of the storage device.

[0048] The first type of firmware is the firmware stored in the storage device for scanning. During the power-on process of the storage device, it is called by the back end to scan the chip select signal and obtain the flash memory capacity parameters to determine the storage device capacity.

[0049] The second type of firmware is IO (Input / Output) firmware in the storage device, which is used to perform data input and output operations according to the capacity of the storage device.

[0050] Specifically, when the storage device starts to power on, the backend is initialized and is ready to start scanning chip select signal related operations. The backend starts the first type of firmware, which checks the chip select signal lines connected to the first type of flash memory in a certain order and rules through a preset scanning program. Each possible chip select signal line is checked one by one to determine which lines are in a valid connection state. These validly connected chip select signals are the target chip select signals. For example, if there are multiple chip select signal channels, the firmware will detect each channel one by one to determine whether the signal meets the characteristics of a valid flash memory connection.

[0051] Furthermore, for each first-class flash memory connected via the target chip select signal, the backend uses the first-class firmware to communicate with the flash memory. According to the communication protocol of the flash memory, the firmware sends a command to obtain capacity parameters to the flash memory. After receiving the command, the flash memory will feed back its own capacity parameter information to the backend.

[0052] Furthermore, after the backend collects the capacity parameters of the first type of flash memory corresponding to all target chip select signals, it performs calculations based on this information. According to a pre-set calculation rule, the total capacity of the storage device is calculated by combining the number of flash memories associated with the target chip select signals and the capacity parameters of each flash memory.

[0053] In this application, a special scanning firmware, i.e., the first type of firmware, is written for the scanning process to complete the capacity scanning function. After the above scanning function is completed, the normal working firmware, i.e., the second type of firmware, is re-issued to the back end to enable its IO to work normally.

[0054] In addition, the present application scans the chip select signal through the first type of firmware to determine the target chip select signal connected to the first type of flash memory, obtains the capacity parameters of the first type of flash memory, and determines the capacity of the storage device according to the capacity parameters and the target chip select signal, thereby achieving firmware unification. Specifically, in traditional technology, different firmware packages need to be burned for storage devices of different capacities (such as 2T / 4T / 8T / 16T, etc.). In the present application, when the storage device is powered on, the back end scans the chip select signal through the first type of firmware to determine the target chip select signal connected to the first type of flash memory, and then obtains the capacity parameters of the flash memory, and finally determines the capacity of the storage device. This step does not depend on pre-burned specific capacity firmware.

[0055] For example, whether it is a 2T or 4T storage device, its real capacity information can be obtained during this power-on scan process, rather than identifying it through firmware pre-burned for a specific capacity.

[0056] After the front end determines the capacity of the storage device at the back end, it re-sends the second type of firmware to the back end. The key here is that the second type of firmware is sent based on the determined capacity, and it can input and output data according to the actual determined capacity of the storage device.

[0057] This means that the second type of firmware can adapt to storage devices of different capacities. It does not burn different firmware for each capacity separately like traditional technology, but first determines the capacity, and then flexibly uses the same set of firmware for subsequent operations based on the capacity, thus achieving firmware unification and solving the problem of burning different firmware packages due to different capacities.

[0058] In one embodiment, a first type of flash memory is provided with a logic unit, and a back end is connected to the logic unit through a chip select signal, and the capacity parameters include the number of logic units connected to the chip select signal and the size of the logic units, and the capacity includes physical capacity and user capacity. The storage device is also provided with a second type of flash memory, wherein the back end is used to read the page parameters of the first type of flash memory connected to the target chip select signal, extract the number of logic units connected to the chip select signal and the size of the logic units from the page parameters, determine the physical capacity of the storage device according to the number of logic units connected to the target chip select signal and the size of the logic units, obtain the number of daily whole disk writes pre-burned in the second type of flash memory, and determine the user capacity according to the number of daily whole disk writes and the physical capacity, wherein the physical capacity is used to control the input and output of data, and the user capacity is used for client queries.

[0059] Among them, this application divides the capacity-related parameters in the original firmware into two parts:

[0060] 1. Information related to the first type of flash memory, including the number of target chip select signals connected to the first type of flash memory, the number of logic units connected to the chip select signals, and the size of the logic units, acquired by back-end scanning;

[0061] 2. DWPD (Drive Writes Per Day) information is irrelevant to the first type of firmware and is burned separately in the second type of flash memory for the firmware to obtain.

[0062] A logical unit (LUN) refers to the smallest unit in the first type of flash memory that can work independently and obtain status.

[0063] Physical capacity refers to the total amount of data that can actually be stored in the first-class flash memory in the storage device. It is determined by reading the page parameters of the first-class flash memory at the back end, extracting the number of logical units connected to the chip select signal and the size of the logical unit. This capacity reflects the actual storage capacity of the storage device at the hardware level, and is mainly used to control the data input and output operations within the storage device. For example, for a hard disk, its physical capacity is like the maximum space sum of all the storage platters inside the hard disk that can store data. This capacity determines how much data can be stored in the hard disk at the physical level.

[0064] User capacity refers to the storage capacity after considering some limiting factors (such as the number of full disk writes per day). It is determined based on the number of full disk writes per day pre-burned in the second-class flash memory and the calculated physical capacity. User capacity is usually less than or equal to the physical capacity, and it represents the amount of storage that can be effectively used by users when actually using the storage device. For example, because the storage device may reserve a portion of space for system maintenance, data backup, or limit the space available to users due to factors such as wear and tear, the capacity seen by the user (user capacity) will be different from the maximum capacity (physical capacity) that the device can actually physically store data.

[0065] In storage devices, page parameters are a set of parameters related to flash memory storage pages. For flash memory, data storage is organized in pages as the basic unit. Page parameters contain multiple information, such as the size of each storage page, which determines the amount of data at the page level for each data write or read operation. It also includes the format of data storage within the page, error correction code related information, etc. Error correction code information is used to detect and correct possible errors when reading data to ensure data accuracy. In addition, page parameters may also involve information such as the logical position of the page in the entire flash memory storage system. This information helps the back end of the storage device to accurately locate, read and write data, and is an important basis for storage devices to manage and operate data in flash memory.

[0066] Specifically, when the storage device is powered on, the back end starts the first type of firmware and prepares to perform subsequent operations. By running the first type of firmware to scan the chip select signal, the target chip select signal connected to the first type of flash memory is identified. The back end establishes a connection with the corresponding first type of flash memory through the target chip select signal and reads the page parameters of the flash memory. These page parameters contain information related to the logical unit. From the read page parameters, the number of logical units connected to the chip select signal and the size of each logical unit are extracted. This information is the key to determining the physical capacity. The back end calculates the physical capacity of the storage device according to a specific algorithm based on the number of logical units connected to the extracted target chip select signal and the size of the logical unit. For example, if the size of each logical unit is x bytes and there are n logical units in total, the physical capacity is nx bytes.

[0067] Furthermore, the backend obtains the data of the number of daily whole-disk writes from the information pre-burned in the second-type flash memory. Based on the obtained number of daily whole-disk writes and the calculated physical capacity, the user capacity is calculated through a specific formula or rule. The calculated physical capacity is used to control the input and output operations of data, while the user capacity is used for client queries to meet different usage requirements.

[0068] The beneficial effects of this embodiment are:

[0069] By reading the first type of flash memory page parameters to extract the number and size of logical units, and then determine the physical capacity, the storage device can accurately grasp its actual storage capacity, provide an accurate basis for data input and output control, and ensure efficient and stable data storage and transmission. For example, when writing large data files, the storage location can be reasonably allocated based on the precise physical capacity to avoid write failures caused by capacity estimation errors.

[0070] The user capacity is determined by combining the number of daily disk writes and physical capacity, taking into account the actual use and life of the device. The number of daily disk writes reflects the intensity of device usage, and the capacity available to users is adjusted accordingly, which not only ensures that users have reasonable storage space, but also prolongs the service life of storage devices by reserving part of the physical capacity for operations such as wear leveling.

[0071] In one of the embodiments, the backend is used to determine the reservation ratio according to the number of full disk writes per day, and determine the user capacity according to the reservation ratio and the physical capacity.

[0072] Among them, the reserved ratio refers to the ratio of the reserved space for wear leveling. The ratio of the reserved space for wear leveling refers to the ratio of the space reserved for wear leveling in the storage capacity of the solid-state drive (SSD) to the total physical capacity. Wear leveling is a technology used to extend the service life of solid-state drives. Since solid-state drives store data through flash memory chips, the write life of flash memory chips is limited. For example, when writing data, some storage units may be written frequently, which will exhaust their write life faster. To avoid this situation, a part of the space is reserved to balance the number of writes to each storage unit so that the data is written evenly to different storage units. The ratio of this reserved space to the physical capacity is the ratio of the reserved space for wear leveling. When the reserved ratio is high, the space available to users (user capacity) will be reduced relative to the physical capacity, but this will help extend the overall life and reliability of the solid-state drive.

[0073] Specifically, the present application can pre-set a loss coefficient k related to the number of writes, and calculate the loss leveling reserved space ratio p based on k, that is, p = k*n, where n is the number of writes to the entire disk per day. Further, the user capacity is calculated based on P. That is, user capacity = physical capacity*(1-ps), where s is the system occupied space ratio. The system occupied space ratio refers to the ratio of the space occupied by system files, system programs, and necessary data generated during system operation in the storage device to the physical capacity of the storage device.

[0074] The beneficial effect of this design is that the user capacity is determined by the reserved ratio and physical capacity, and can be flexibly allocated according to the actual usage of the storage device. If the number of daily whole disk writes is low, the reserved ratio is reduced accordingly, and users can use more space, improving the space utilization of the storage device; on the contrary, in the scenario of frequent writes, although the user's available space is reduced, the stability and reliability of storage are guaranteed.

[0075] In one embodiment, the first type of flash memory is NAND flash memory, and the second type of flash memory is NOR flash memory.

[0076] Among them, NAND flash memory is a non-volatile storage technology. Its data storage is organized in blocks and pages. This flash memory has the characteristics of high storage density and can store a large amount of data in a small physical space, so it is often used in large-capacity data storage devices, such as solid-state drives (SSDs) and USB flash drives.

[0077] NOR flash memory is also a non-volatile storage technology. Its data reading method is similar to that of ordinary random access memory, which can be read in bytes, which makes it have the advantage of fast random reading speed. NOR flash memory is mainly used to store program code. For example, some device firmware that needs to start quickly is usually stored in NOR flash memory. Because it can quickly provide instructions to the processor, it is convenient for the device to quickly start and run the program.

[0078] Therefore, the application uses NOR flash memory to store some critical information that needs to be accessed quickly, such as the number of daily full-disk writes pre-burned in it. These parameters are very important for the management and performance optimization of storage devices (such as determining user capacity). NOR flash memory can ensure that this information can be read quickly and accurately, thereby supporting the efficient operation of storage devices.

[0079] In one embodiment, if Figure 2 As shown, the back end is provided with at least one channel, the channel is provided with a channel controller (not shown), the channel controller is connected to at least one chip select signal, and the chip select signal is connected to at least one first type flash memory, wherein the back end is used to run the first type firmware through the channel controller during the power-on process of the storage device, so as to set each chip select signal in sequence according to a preset order, send a reset signal to the first type flash memory connected to each chip select signal, read the state of the first type flash memory connected to each chip select signal after a preset time, so as to scan the chip select signal, obtain the chip select signal of the connected first type flash memory in the reset state, and obtain the target chip select signal.

[0080] exist Figure 2In the invention, the storage device includes a front end, a flash memory conversion layer, and a back end. The connection between the back end and the first type of flash memory is divided into multiple channels. The channels are operated completely in parallel. A channel controller is provided in each channel. Each channel controller is connected to at least one chip select signal. Each chip select signal is connected to at least one first type of flash memory.

[0081] Among them, the Flash Translation Layer (FTL) is mainly responsible for the conversion of logical addresses to physical addresses. For operating systems and applications, they use logical addresses to access storage devices. FTL converts these logical addresses into physical addresses in the flash memory chip. For example, when the operating system wants to read a file, it sends out a logical address. FTL is like a translator, converting this logical address into the physical address of the file data actually stored in the flash memory, so that the data can be accurately obtained.

[0082] Specifically, the back end of the channel controller has a certain capability range and can support 4-16 CE signals, which are important signals for controlling and selecting the first type of flash memory chip.

[0083] The channel controller activates (sets) a CE signal each time in a specific order, and after activation, sends a reset command to the selected first-class flash memory. The purpose of this reset command is to return the first-class flash memory to an initial state and prepare for subsequent operations.

[0084] After the first type flash memory receives the reset command, it takes a certain amount of time (tRST) to complete the reset operation. After this time, the channel controller will try to read the status of the first type flash memory from the bus. This status information includes whether the first type flash memory responds normally and whether it is ready for subsequent operations.

[0085] Furthermore, if the channel controller can obtain the correct reset information from the bus, it means that the channel corresponding to the activated CE signal is connected to the first type of flash memory that is working normally. If the controller polls (checks one by one) all the maximum allowed times and cannot get the status information returned by the first type of flash memory, it means that the channel corresponding to the CE signal is either not connected to the first type of flash memory, or the connected first type of flash memory is not working properly. In this case, it is treated as not connected.

[0086] The beneficial effects of this embodiment are:

[0087] By sequentially setting the CE signal, sending a reset command, and reading the status information, it is possible to accurately detect whether the channel corresponding to each CE signal is connected to a normally functioning Class I flash memory. This method provides a reliable detection mechanism to ensure that the controller can clearly understand the actual physical connection status of the back-end storage module.

[0088] In addition, due to the addition of specific functions in the solid-state drive channel controller (such as the above-mentioned functions of scanning the chip select signal to determine the capacity, etc.), the operation of these functions requires the use of a portion of the internal random access memory (IRAM) or dynamic random access memory (DRAM). However, in the design of the back-end channel controller of the common solid-state drive controller on the market, there is not much memory space reserved for additional functions. Therefore, when these new functions are added, there will be a situation where the IRAM / DRAM memory required for the normal operation of the back-end channel controller is insufficient. However, this application solves the problem of insufficient memory by writing a special scanning firmware, and can complete the scanning task with limited memory resources.

[0089] When the scanning firmware completes the capacity scanning function, it will re-send the normal working firmware to the back-end channel controller. In this way, after completing the critical capacity scanning, the channel controller can switch to the normal working mode, so that the input / output (IO) operation can run normally, avoiding functional confusion or malfunction due to insufficient memory.

[0090] In one of the embodiments, the channels include multiple channels, wherein the front end is also used to detect the number of logical units connected to each channel. When it is detected that the number of logical units connected to channels exceeding a preset number is less than the number of logical units connected to other channels, an abnormal log is recorded and the storage device is set to an abnormal state.

[0091] In this application, the back end scans the number of logical units in each channel and passes the scan results to the back end. Generally speaking, for the channel controller that has been used, the number of CEs connected in each channel is the same. If there are different situations, they will be recorded in the configuration file in the second type of flash memory. After the back end scans the CE of each channel, the firmware will know the usage of CE. If the number of CEs of a channel is inconsistent and no special record is made in the second type of flash memory, it means that the welding of the first type of flash memory of a channel is abnormal. After reporting the above abnormal situation as an error, the subsequent initialization process is skipped and failure is returned.

[0092] It should be noted that when the number of CEs in a channel is inconsistent with the number of CEs in other channels, it is necessary to further determine whether the number of logical units in the channel is greater than the number of logical units in other channels. If so, no error is reported; if not, an error is reported.

[0093] The reason is that the present application may allow the number of logical units in one or two channels to be one or two more than the number of logical units in other channels. The purpose of such design is to increase the performance of the storage device by adding additional physical space on the disk.

[0094] However, if there are a small number of missing logical units, an error message will be displayed.

[0095] Specifically, the front end starts a detection program, and for each channel, obtains the number of logical units connected to the channel by interacting with the back end. This may involve sending a specific query instruction to the back end, and the back end returns the number of logical units of the corresponding channel based on the first type of flash memory information connected.

[0096] Furthermore, the number of logic units connected to each channel is compared. A preset number is set to count the number of channels with fewer connected logic units than other channels. For example, assuming there are 10 channels in total and the preset number is 3, when it is found that the number of logic units connected to 4 channels is significantly less than that of other channels, subsequent operations are triggered.

[0097] Once it is detected that the number of logical units connected to more than the preset number of channels is less than that of other channels, the front end records an abnormal log. The log content may include detailed information such as the detection time, the channel number involved, and the number of logical units in each channel. At the same time, the front end sets the storage device to an abnormal state, which may involve modifying the device status flag so that other parts of the system can recognize that the storage device is currently in an abnormal state.

[0098] The beneficial effects of this embodiment are:

[0099] It can timely detect possible hardware connection or configuration anomalies in storage devices. An abnormal number of logical units may indicate problems such as loose, damaged, or incorrectly configured first-class flash memory connections on some channels. By recording abnormal logs, detailed clues are provided for subsequent troubleshooting, which helps to quickly locate and solve problems and reduce device downtime.

[0100] Setting the storage device to an abnormal state can prevent the system from continuing to perform normal operations on the device that may have problems, avoid data loss or damage due to the use of abnormal channels, and ensure the security and integrity of the data.

[0101] Timely discovery and identification of abnormal conditions will help the system take appropriate protective measures, such as limiting read and write operations on the storage device or notifying the administrator to handle it. This helps maintain the stability of the entire storage system and prevent local problems from spreading and affecting the normal operation of other parts.

[0102] In a second aspect, a capacity detection control method for a storage device is provided. The storage device includes a front end, a back end, and a first type of flash memory. The front end is connected to the back end, and the back end is connected to the first type of flash memory through at least one chip select signal. The method is applied to the back end, and the method includes:

[0103] Step S31, during the power-on process of the storage device, the chip select signal is scanned by the first type firmware to determine the target chip select signal connected to the first type flash memory.

[0104] Step S32, obtaining the capacity parameters of the first type of flash memory, and determining the capacity of the storage device according to the capacity parameters and the target chip select signal.

[0105] Step S33, receiving the second type firmware sent by the front end, and running the second type firmware to input and output data according to the capacity of the storage device.

[0106] Specifically, after the storage device is powered on, the back end uses the first type of firmware to scan the chip select signal in a specific order and manner, and finds the first type of flash memory that is normally working corresponding to the target chip select signal by sending a reset signal and reading the status.

[0107] Furthermore, the back end reads relevant capacity parameters from the first type of flash memory connected to the target chip select signal, which may include the number of logical units of the flash memory, the size of the logical units, etc. Then, according to these parameters and the number of flash memories corresponding to the target chip select signal, the total capacity of the storage device is determined by a certain calculation method (such as adding the capacity of each flash memory). For example, if there are two flash memories corresponding to the target chip select signal, and the number and size of the logical units of each flash memory are known, the total capacity of the two flash memories can be calculated, that is, the capacity of the storage device.

[0108] Furthermore, after the front end learns the storage device capacity determined by the back end, it will issue the second type of firmware. The back end receives and runs the firmware, and it will reasonably arrange the data input and output operations according to the capacity of the storage device. For example, when writing data, it will determine whether there is enough space to store the data based on the capacity of the storage device, and how to allocate the data to different flash memory locations.

[0109] In this application, the first type of firmware is mainly used to scan the chip select signal during the power-on process of the storage device to determine the capacity of the flash memory. Its function focuses on identifying the capacity, rather than performing different data input / output operations for different capacities. This is equivalent to a universal "capacity detector". Regardless of the final capacity of the storage device, the capacity information can be obtained through this first type of firmware.

[0110] The second type of firmware works based on the determined capacity. After the backend determines the capacity of the storage device, the frontend re-issues the second type of firmware, which can input and output data based on the determined storage device capacity. Since it works based on the actual determined capacity, the second type of firmware can be applied to storage devices of different capacities.

[0111] For example, for storage devices with 2T and 4T capacities, although the capacities are different, after the capacity is identified by the first type of firmware, the second type of firmware can perform adaptive operations based on the identification result (2T or 4T), instead of burning different firmware for data input / output for 2T and 4T respectively as in traditional technology. Firmware unification is achieved at the core function level of data input / output.

[0112] In a third aspect, the present application provides a capacity detection control device for a storage device, such as Figure 4 As shown, the storage device includes a front end, a back end and a first type of flash memory, the front end is connected to the back end, the back end and the first type of flash memory are connected through at least one chip select signal, the device is applied to the back end, and the device includes:

[0113] A scanning module 41, used for scanning the chip select signal through the first type of firmware during the power-on process of the storage device to determine the target chip select signal connected to the first type of flash memory;

[0114] An acquisition module 42, used to acquire capacity parameters of the first type of flash memory, and determine the capacity of the storage device according to the capacity parameters and the target chip selection signal;

[0115] The running module 43 is used to receive the second type of firmware sent by the front end, and run the second type of firmware to input and output data according to the capacity of the storage device.

[0116] In a fourth aspect, the present application provides a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the storage device capacity detection control method provided in any one of the embodiments of the present application in the first aspect.

[0117] In one embodiment, the computer device may be a server, and its internal structure diagram may be as follows: Figure 5As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the capacity detection control method of the storage device is implemented.

[0118] In a fifth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the storage device capacity detection control method provided in any embodiment of the present application in the first aspect.

[0119] The computer readable storage medium may be Figure 5 A computer-readable storage medium in the computer device shown.

[0120] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing related hardware through a computer program, and the above-mentioned computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0121] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A storage device, characterized in that: The storage device includes a front end, a back end and a first type of flash memory, the front end is connected to the back end, and the back end is connected to the first type of flash memory through a chip select signal, wherein: The backend is used to scan the chip select signal through the first type of firmware during the power-on process of the storage device to determine the target chip select signal connected to the first type of flash memory, obtain the capacity parameter of the first type of flash memory, and determine the capacity of the storage device according to the capacity parameter and the target chip select signal; The front end is used to re-send the second type of firmware to the back end after the back end determines the capacity of the storage device; The back end is used to input and output data according to the capacity of the storage device through the second type of firmware.

2. The storage device according to claim 1, characterized in that The first type of flash memory is provided with a logic unit, the back end is connected to the logic unit through the chip select signal, the capacity parameter includes the number of logic units connected to the chip select signal and the size of the logic unit, the capacity includes physical capacity and user capacity, and the storage device is further provided with a second type of flash memory, wherein, The back end is used to read the page parameters of the first type of flash memory connected to the target chip select signal, extract the number of logic units connected to the chip select signal and the size of the logic units from the page parameters, and determine the physical capacity of the storage device according to the number of logic units connected to the target chip select signal and the size of the logic units; The backend is further used to obtain the number of daily whole-disk writes pre-burned in the second-type flash memory, and determine the user capacity according to the number of daily whole-disk writes and the physical capacity; The physical capacity is used to control the input and output of data, and the user capacity is used for query by the client.

3. The storage device according to claim 2, characterized in that: The backend is used to determine the reserved ratio according to the number of full disk writes per day, and determine the user capacity according to the reserved ratio and the physical capacity.

4. The storage device according to claim 2, characterized in that: The first type of flash memory is NAND flash memory, and the second type of flash memory is NOR flash memory.

5. The storage device according to claim 1, characterized in that: The back end is provided with at least one channel, the channel is provided with a channel controller, the channel controller is connected to at least one chip select signal, the chip select signal is connected to at least one of the first type flash memories, wherein, The back end is used to run the first type of firmware through the channel controller during the power-on process of the storage device, so as to sequentially set each of the chip select signals according to a preset order, and send a reset signal to the first type of flash memory connected to each of the chip select signals; The back end is also used to read the state of the first type flash memory connected to each chip select signal after a preset time, so as to scan the chip select signal, obtain the chip select signal of the connected first type flash memory in a reset state, and obtain the target chip select signal.

6. The storage device according to claim 4, characterized in that: The channels include a plurality of channels, wherein: The front end is also used to detect the number of logical units connected to each of the channels. When it is detected that the number of logical units connected to channels exceeding a preset number is less than the number of logical units connected to other channels, an abnormal log is recorded and the storage device is set to an abnormal state.

7. A capacity detection and control method for a storage device, characterized in that: The storage device comprises a front end, a back end and a first type of flash memory, the front end is connected to the back end, the back end and the first type of flash memory are connected via at least one chip select signal, the method is applied to the back end, and the method comprises: During the power-on process of the storage device, the chip select signal is scanned by the first type of firmware to determine a target chip select signal connected to the first type of flash memory; Acquire a capacity parameter of the first type of flash memory, and determine the capacity of the storage device according to the capacity parameter and the target chip select signal; The second type of firmware sent by the front end is received, and the second type of firmware is run to input and output data according to the capacity of the storage device.

8. A capacity detection control device for a storage device, characterized in that: The storage device comprises a front end, a back end and a first type of flash memory, the front end is connected to the back end, the back end and the first type of flash memory are connected via at least one chip select signal, the device is applied to the back end, and the device comprises: A scanning module, used for scanning the chip select signal through the first type of firmware during the power-on process of the storage device to determine the target chip select signal connected to the first type of flash memory; An acquisition module, used for acquiring a capacity parameter of the first type of flash memory, and determining the capacity of the storage device according to the capacity parameter and the target chip select signal; The running module is used to receive the second type of firmware sent by the front end, and run the second type of firmware to input and output data according to the capacity of the storage device.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claim 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to claim 7 are implemented.

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