Data caching and sending method based on multistage FIFO

Abstract

The invention discloses a data caching and sending method based on multistage FIFO (First In First Out), which belongs to the technical field of data caching, and comprises the following steps: after data is written into a first-stage FIFO, the transmission speed of the data is reduced through a second-stage FIFO, and the read control logic of the second-stage FIFO divides the data into four parts with similar quantity according to a read-out sequence by taking a time sequence as a part of a control condition. The first copy of data is written into the first three-level FIFO, the first three-level FIFO reads the data into the four-level FIFO after receiving the data, the second copy of data is written into the second three-level FIFO, and the third copy of data is written into the first three-level FIFO until the first copy of data is completely written into the four-level FIFO. And after the first part of data is completely read out by the four-stage FIFO, subsequent data are sequentially written in according to the sequence. By means of cache control of the multi-stage FIFO, the space for deploying a plug-in storage chip is saved, and the complexity of a control system is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of data cache, and in particular relates to a data cache and sending method based on multi-level FIFO. Background Art

[0002] Field Programmable Gate Arrays (FPGA) are programmable signal processing devices with rich logic resources. Users can change configuration information to define functions according to design requirements. FIFO (First Input First Output) memory is one of the commonly used units in chip design. Due to its first-in, first-out function, it is widely used in data receiving, sending, processing and other system fields. Nowadays, FIFO is used as the most important standard storage module in more and more FPGA design projects.

[0003] With the continuous increase in engineering needs and the continuous expansion of the scale of engineering design, more and more digital chips need to be integrated in the control board. Especially in space-based platforms, space-based equipment often needs to complete the integration and wiring of multiple boards in a limited space, which often limits the number of chips. In the existing data caching technology, especially in the extreme case of fast clock domain crossing slow clock domain and parallel data signal conversion to serial data signal, a more reliable solution is to integrate DDR3 chips, realize data caching by calling large-capacity DDR3 chips, and finally design appropriate control logic to realize data transmission. However, usually more than one functional module of DDR3 chip needs to be called, and increasing the number of aerospace-grade DDR3 chips will bring additional space occupation and wiring pressure. Therefore, there is an urgent need for a technical route that fully utilizes the resources of digital chips themselves to realize data caching and transmission in extreme cases such as space limitation, so as to provide a new solution for the design of space-based equipment platforms. Summary of the invention

[0004] The present invention aims at the inadequacy of the existing data caching and sending methods in the space-based platform, and provides a data caching and sending method based on multi-level FIFO. The method takes advantage of the rich logic resources, high speed and high performance of FPGA, and fully utilizes the resources of FPGA chip itself to replace the use of additional storage chip, thereby achieving the effect of reducing the space occupation and wiring pressure in the space-based platform.

[0005] The technical solution adopted by the present invention is as follows: a method for data caching and sending based on multi-level FIFO, comprising:

[0006] Step 1: The first-level FIFO obtains data.

[0007] Step 2: The secondary FIFO reads data from the primary FIFO according to the empty state of the primary FIFO, and outputs the data at a reduced speed.

[0008] Step 3, the read control logic of the secondary FIFO divides the data into four parts of similar quantity, wherein the first part of the data is used to be written into the first-third level FIFO, and the second part of the data is used to be written into the second-third level FIFO, and in this process, the data output is reduced in speed; Step 4, after the first-third level FIFO writes the first part of the data, the write control logic of the fourth level FIFO writes the first part of the data therein by judging the empty state of the first-third level FIFO, in this process, the second-third level FIFO writes the second part of the data through the empty state of the secondary FIFO, and the first-third level FIFO writes the third part of the data according to the empty state of the secondary FIFO while reading out the first part of the data, until the third part of the data is completely written into the first-third level FIFO and the first part of the data is completely written into the fourth level FIFO.

[0009] Step 5: After the remote read control logic completely reads out the first data, the fourth-level FIFO writes the second data through the empty state of the second and third-level FIFOs. After the data is read out, the second and third-level FIFOs write the fourth data from the second-level FIFO through their own empty state.

[0010] Step 6: After the remote read control logic completely reads out the second copy of the data, the four-stage FIFO writes the third and fourth copies of the data in sequence through the empty state of the second and third stage FIFOs, and is read out by the remote control logic.

[0011] From now on, the data is cached and sent.

[0012] The advantages and beneficial effects of the present invention compared with the prior art are:

[0013] In the design of the present invention, the advantages of rich FPGA logic resources can be fully utilized in the limited space of the space-based platform, the use of storage chips can be reduced, the space occupation can be reduced, and the wiring pressure can be alleviated.

[0014] The design of the present invention realizes multi-level caching and transmission of data through multiple FIFOs, and the connection method is simple. The number of FIFOs used and the connection method can be flexibly adjusted according to actual conditions such as timing requirements or data volume, thereby expanding application scenarios.

[0015] The design of the present invention replaces the control module of DDR3 by the read and write control of the FIFO module, thereby reducing the complexity of the control logic.

[0016] The input and output interface designed by the present invention is a standard FIFO read-write interface, which is easy to operate.

[0017] In a multi-system integrated circuit environment, the present invention uses multi-level FIFO cache control, which saves space for deploying external storage chips, reduces the complexity of the control system, simplifies data flow, facilitates further expansion, and can be flexibly configured according to data volume and timing requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A structural block diagram of a method for data caching and sending based on multi-level FIFO of the present invention;

[0019] Figure 2 The present invention is a flowchart of a method for data caching and sending based on multi-level FIFO. DETAILED DESCRIPTION

[0020] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described below are only used to explain the present invention, but not to limit the present invention, and the various technical features involved in the embodiments can be used in combination as long as they do not conflict with each other.

[0021] According to an embodiment of the present invention, a method for data caching and sending based on a multi-level FIFO is provided, and its structural block diagram is as follows: Figure 1 As shown in the flow chart, Figure 2 As shown, in Figure 1 and Figure 2 In the figure, FIFO1 refers to the first level FIFO, FIFO2 refers to the second level FIFO, FIFO3.1 refers to the first level FIFO, FIFO3.2 refers to the second level FIFO, and FIFO4 refers to the fourth level FIFO. The first level, second level, third level, and fourth level refer to setting multiple levels of FIFO in the FIFO structure.

[0022] Step 1: The first-level FIFO obtains data, which in one example is 836,000 bytes in total, and is written through the proximal write control logic.

[0023] Step 2: The secondary FIFO reads data from the primary FIFO according to the empty state of the primary FIFO, and outputs the data at a reduced speed; Figure 1 In the output, the empty state is shown as empty1; in the reduced speed output, the secondary FIFO read speed is reduced to 64% of the write speed.

[0024] Step 3: The read control logic of the secondary FIFO divides the data into four parts of similar quantity, where the first part of the data is used to write the first three-level FIFO, and the second part of the data is used to write the second three-level FIFO. In this process, the data is output at a reduced speed; in the reduced speed output, the read speed of the three-level FIFO is reduced to 62.5% of the write speed; among the four parts of data, the part with the least data volume is 70.3% of the part with the largest data volume. In one example, the first two parts of the data are 100,000 each, the third part of the data is 90,000, and the fourth part of the data is 128,000. In fact, as long as it is within the data volume allowed in the FIFO itself, it can meet the temporary storage of the four parts of data and does not cause any FIFO to overflow. The specific data volume can be flexibly controlled.

[0025] Step 4: After the first data is written into the first and third level FIFOs, the write control logic of the fourth level FIFO determines the empty state of the first and third level FIFOs ( Figure 1 1) writes the first data from it. During this process, the second and third level FIFOs pass through the empty state of the secondary FIFO ( Figure 1 The first and third level FIFOs write the second copy of data (shown as empty2), and the first and third level FIFOs write the third copy of data according to the empty state of the second level FIFO while reading out the first copy of data, until the third copy of data is completely written into the first and third level FIFOs and the first data is completely written into the fourth level FIFO; writing by judging the empty state of the first and third level FIFOs means that after the empty state of the first and third level FIFOs is not empty, the write enable of the fourth level FIFO takes effect and starts to receive data from the first and third level FIFOs.

[0026] In step four, the four-level FIFO uses the first and third level FIFOs to write the first data, the second and third level FIFOs to write the second data, and reads the first data from the first and third level FIFOs simultaneously, thereby ensuring that the first and third level FIFOs will not be full when writing the third data.

[0027] The first data is cached in the fourth-level FIFO and read out through the remote read control logic. When the fourth-level FIFO has not completely read out the first data, the second data is cached in the second and third-level FIFOs, the third data is cached in the first and third-level FIFOs, and the fourth data is cached in the second-level FIFO.

[0028] Step 5: After the remote read control logic completely reads out the first data, the fourth-level FIFO writes the second data through the empty state of the second and third-level FIFOs. After the data is read out, the second and third-level FIFOs write the fourth data from the second-level FIFO through their own empty state.

[0029] Step 6: After the remote read control logic completely reads out the second copy of the data, the four-stage FIFO writes the third and fourth copies of the data in sequence through the empty state of the second and third stage FIFOs, and is read out by the remote control logic.

[0030] That is, when the second copy of data is completely written into the fourth-level FIFO, the second third-level FIFO writes the fourth copy of data from the second-level FIFO. After each copy of data is completely read out from the fourth-level FIFO, the next copy of data is written in sequence from the third-level FIFO, and so on, thus completing the data caching and sending.

[0031] The remote read control logic makes full use of the blanking time to read data out of the four-level FIFO in sequence. The remote read logic performs a read operation based on the empty state of the four-level FIFO.

[0032] The near end refers to the control logic close to the first level FIFO, and the far end refers to the control logic close to the fourth level FIFO.

[0033] like Figure 2 As shown, in this embodiment, data needs to cross from the fast clock domain to the slow clock domain and be converted from parallel signals to serial signals. First, the first-level FIFO is clocked at a frequency of 125 MHz ( Figure 2 wr_clk (125MHz)) writes 16-bit data signal ( Figure 2 The data (16 bits) is shown in the figure), with a clock frequency of 125MHz ( Figure 2 rd_clk (125MHz)) reads out a 32-bit data signal ( Figure 2 The data is shown as data (32 bits) in the figure. The secondary FIFO is used as a transition to implement some cross-clock domain functions. The data is input by a clock frequency of 125MHz ( Figure 2 wr_clk (125MHz)), output at a clock frequency of 80MHz ( Figure 2 16-bit data signal (shown as rd_clk (80MHz)) Figure 2 The second-level FIFO sends the 1st to 200000th bytes to the first third-level FIFO (FIFO3.1), as shown in Figure 2 As shown in 1-100000 and 200001-290000, the bytes 200001-400000 are sent to the second third level FIFO (3.2), as Figure 2 The first three-level FIFO (FIFO3.1) is input at a clock frequency of 80MHz ( Figure 2 wr_clk (80MHz)), output at a clock frequency of 50MHz ( Figure 216-bit data signal (shown as rd_clk (50MHz)) Figure 2 The fourth FIFO (FIFO4) is input at a clock frequency of 50MHz ( Figure 2 wr_clk(50MHz)), output at a clock frequency of 50MHz ( Figure 2 16-bit data signal (shown as rd_clk (50MHz)) Figure 2 All data output by the four-level FIFO (FIFO4) is processed by the remote read control logic. After the secondary FIFO sends the 400,000th byte to FIFO3.2, it continues to send the 400,001st to 580,000th bytes to FIFO3.1, and the last 256,000 bytes are temporarily cached in the secondary FIFO. When data is written to the four-level FIFO, the remote read control logic reads the data from the four-level FIFO and performs parallel-to-serial conversion. After the current 200,000 bytes are completely read out by the remote control logic, the four-level FIFO makes a logical judgment through the empty state of FIFO3.2, writes the 200,001st to 400,000th bytes, and continues to be read by the remote control logic. FIFO3.2 also uses its own empty state as a conditional judgment to read the last 256,000 bytes from the secondary FIFO. After the four-stage FIFO reads out a piece of data completely, it receives subsequent data from the three-stage FIFO in sequence, and is output by the remote read control and converted into parallel and serial data, and finally outputs a 1-bit data signal to the outside.

[0034] The above description is only an embodiment of the present application and is not intended to limit the present application. Practitioners in this field should clearly recognize that the present application may have various extensions and changes, and different implementations may be used within the scope of the present invention to implement the described functions according to actual application conditions, and these extensions, changes and other implementations are all within the scope of the present disclosure.

Claims

1. A method for data caching and sending based on multi-level FIFO, characterized in that: The method comprises the following steps: Step 1: The first-level FIFO obtains data; Step 2: The secondary FIFO reads data from the primary FIFO according to the empty state of the primary FIFO, and outputs the data at a reduced speed; Step 3: The read control logic of the secondary FIFO divides the data into four parts of similar quantity, wherein the first part of the data is used to write into the first and third level FIFOs, and the second part of the data is used to write into the second and third level FIFOs, and the data is output at a reduced speed in this process; Step 4, after the first data is written into the first-level FIFO, the write control logic of the fourth-level FIFO writes the first data therein by judging the empty state of the first-level FIFO. In this process, the second-level FIFO writes the second data through the empty state of the second-level FIFO. While the first-level FIFO reads out the first data, it writes the third data according to the empty state of the second-level FIFO until the third data is completely written into the first-level FIFO and the first data is completely written into the fourth-level FIFO. Step 5: After the remote read control logic completely reads out the first copy of data, the fourth-level FIFO writes the second copy of data through the empty state of the second and third-level FIFOs. After the data is read out, the second and third-level FIFOs write the fourth copy of data from the second-level FIFO through their own empty state; Step 6: After the remote read control logic completely reads out the second copy of data, the four-stage FIFO writes the third and fourth copies of data in sequence through the empty state of the second and third-stage FIFOs, and reads them out by the remote control logic; From now on, the data is cached and sent.

2. The method for data caching and sending based on multi-level FIFO according to claim 1, characterized in that: Step 1 includes: the first-level FIFO writes data through the near-end write control logic.

3. The method for data caching and sending based on multi-level FIFO according to claim 2, characterized in that: The near end refers to the one close to the first-level FIFO, and the far end refers to the one close to the fourth-level FIFO.

4. The method for data caching and sending based on multi-level FIFO according to claim 1, characterized in that: Step 2 includes: the speed reduction ratio is: the read speed of the secondary FIFO is reduced to 64% of the write speed.

5. The method for data caching and sending based on multi-level FIFO according to claim 1, characterized in that: In step 3, the copy with the least amount of data contains 70.3% of the data of the copy with the most data.

6. The method for data caching and sending based on multi-level FIFO according to claim 1, characterized in that: In step 4, the four-stage FIFO writes the first data into the first and third-stage FIFOs, writes the second data into the second and third-stage FIFOs, and reads the first data from the first and third-stage FIFOs simultaneously.

7. The method for data caching and sending based on multi-level FIFO according to claim 1, characterized in that: After step 4, the first copy of data is cached in the fourth-level FIFO and read out through the remote read control logic, the second copy of data is cached in the second-third-level FIFO, the third copy of data is cached in the first-third-level FIFO, and the fourth copy of data is cached in the second-level FIFO.

8. The method for data caching and sending based on multi-level FIFO according to claim 1, characterized in that: The remote read control logic uses the blanking time to read data out of the four-level FIFO in sequence.

9. The method for data caching and sending based on multi-level FIFO according to claim 1, characterized in that: In the processing of step 1 to step 6, data crosses from the fast clock domain to the slow clock domain.

10. The method for data caching and sending based on multi-level FIFO according to claim 9, characterized in that: The second-level FIFO has an input clock frequency of 125MHz and an output clock frequency of 80MHz, the first-level FIFO and the second-level FIFO have an input clock frequency of 80MHz and an output clock frequency of 50MHz, and the fourth-level FIFO has an input clock frequency of 50MHz and an output clock frequency of 50MHz.

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