A pipeline ECC verification system and pipeline ECC verification method

Abstract

The present application discloses a pipeline ECC verification system and a pipeline ECC verification method. The pipeline ECC verification system includes: a comprehensive feature engine, a BM algorithm engine, and a positioning and correction engine; wherein the comprehensive feature engine, the BM algorithm engine, and the positioning and correction engine can work simultaneously; when the comprehensive feature engine, the BM algorithm engine, and the positioning and correction engine work simultaneously, the comprehensive features, ECC settings, and critical equations obtained by the positioning and correction engine are the comprehensive features, ECC settings, and critical equations of the ECC frame processed by the BM algorithm engine; the comprehensive features and ECC settings obtained by the BM algorithm engine are the comprehensive features and ECC settings of the ECC frame processed by the comprehensive feature engine. The present application enables the comprehensive feature engine, the BM algorithm engine, and the positioning and correction engine to process different ECC frames simultaneously, solving the problem in the prior art where two parts are idle and only one part is working during continuous operation.

Description

Technical Field

[0001] The present application relates to the technical field of flash memory controllers, and in particular to a pipeline ECC verification system and a pipeline ECC verification method. Background Art

[0002] From a semiconductor perspective, flash memory is considered non-volatile storage, but it is also an unreliable medium. Because flash memory is electronically driven, it has inherent defects common to electronic components, such as aging, electron leakage, and decay.

[0003] These potentials may be erroneous due to electron leakage or decay, as well as process defects. NAND Flash manufacturing processes cannot guarantee the reliability of the NAND memory array throughout its lifecycle, resulting in bad blocks during NAND production and use. To ensure data reliability, systems using NAND typically employ an ECC data verification mechanism, using an ECC verification algorithm to append ECC information to data frames.

[0004] For flash memory storage, a corresponding ECC engine circuit needs to be designed in the main control chip to achieve high-speed ECC processing of data frames.

[0005] The defects of the existing ECC engine design method are:

[0006] Any ECC frame will occupy the entire ECC engine's processing time until it is corrected or detected as uncorrectable. For example, the ECC engine is divided into three parts: the comprehensive signature engine, the BM algorithm engine, and the error location and correction engine. During continuous operation, two parts are idle and only one is active. Summary of the Invention

[0007] The object of the present invention is to provide a pipeline ECC checking system to solve at least one of the above technical problems.

[0008] One aspect of the present invention provides a pipeline ECC check system, the pipeline ECC check system comprising:

[0009] a comprehensive feature engine configured to obtain an ECC frame and a corresponding ECC setting and generate a comprehensive feature based on the ECC frame and the corresponding ECC setting;

[0010] A BM algorithm engine, configured to obtain comprehensive features and ECC settings and generate a critical equation based on the comprehensive features;

[0011] A positioning and correction engine is used to obtain comprehensive features, ECC settings, and critical equations and perform error positioning and correction based on the comprehensive features, ECC settings, and critical equations; wherein,

[0012] The comprehensive feature engine, BM algorithm engine and positioning and correction engine can work simultaneously;

[0013] When the comprehensive feature engine, the BM algorithm engine, and the positioning and correction engine operate simultaneously, the comprehensive features, ECC settings, and critical equations obtained by the positioning and correction engine are the comprehensive features, ECC settings, and critical equations of the ECC frame processed by the BM algorithm engine;

[0014] The comprehensive features and ECC settings acquired by the BM algorithm engine are the comprehensive features and ECC settings of the ECC frame processed by the comprehensive feature engine.

[0015] Optionally, the ECC operation direction is a decoding direction.

[0016] Optionally, the comprehensive feature engine, BM algorithm engine and positioning and correction engine use separate clock sources respectively.

[0017] The present application also provides a pipeline ECC verification method, which includes:

[0018] The comprehensive feature engine obtains the first ECC frame and the ECC setting corresponding to the first ECC frame;

[0019] The comprehensive feature engine generates a first comprehensive feature based on the first ECC frame and the corresponding first ECC setting;

[0020] The synthetic signature engine sends the first ECC setting and the first synthetic signature to the BM algorithm engine in an idle state.

[0021] Optionally, after the comprehensive feature engine sends the first ECC setting and the first comprehensive feature to the BM algorithm engine, the pipeline ECC check method further includes:

[0022] When the comprehensive feature engine obtains a second ECC frame after processing the first ECC frame and obtains an ECC setting corresponding to the second ECC frame, the comprehensive feature engine generates a second comprehensive feature based on the second ECC frame and the corresponding second ECC setting;

[0023] The BM algorithm engine generates a first critical equation according to the acquired first ECC setting and the first comprehensive feature and sends the first critical equation and the first ECC setting to the positioning and correction engine.

[0024] Optionally, when the BM algorithm engine sends the first critical equation and the first ECC setting to the positioning and correction engine and is idle, the pipeline ECC checking method further includes:

[0025] The comprehensive feature engine sends the second ECC setting and the second comprehensive feature to the BM algorithm engine in the idle state;

[0026] The positioning and correction engine is used to obtain a first comprehensive feature, a first ECC setting, and a first critical equation.

[0027] Optionally, after the positioning and correction engine sends the second ECC setting and the second comprehensive feature to the BM algorithm engine in the idle state, the pipeline ECC verification method further includes:

[0028] The BM algorithm engine generates a second critical equation according to the acquired second ECC setting and the second comprehensive feature;

[0029] The location and correction engine performs error location and correction based on the first comprehensive feature, the first ECC setting, and the first critical equation;

[0030] When the comprehensive feature engine obtains a third ECC frame and an ECC setting corresponding to the third ECC frame after processing the second ECC frame, the comprehensive feature engine generates a third comprehensive feature according to the third ECC frame and the corresponding third ECC setting.

[0031] Optionally, after the location and correction engine completes error location and correction according to the first comprehensive feature, the first ECC setting, and the first critical equation and is in an idle state, the pipeline ECC checking method further includes:

[0032] The BM algorithm engine sends the second critical equation and the second ECC setting to the positioning and correction engine;

[0033] The comprehensive feature engine sends the third ECC setting and the third comprehensive feature to the BM algorithm engine in the idle state.

[0034] Beneficial effects:

[0035] The pipeline ECC verification system of the present application achieves loose coupling of the three components of the ECC engine (comprehensive feature engine, BM algorithm engine, and error location and correction engine) by dividing them into three independent clock domains, allowing the three to process different ECC frames simultaneously, thereby solving the problem in the prior art that when the three components are working continuously, two parts are idle and only one part is working. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 2 is a schematic diagram of a pipeline ECC check system according to an embodiment of the present application.

[0037] Figure 2 It is a processing flow diagram of a pipeline ECC checking method according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the implementation of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below in conjunction with the drawings in the embodiments of this application. In the drawings, the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The described embodiments are part of the embodiments of this application, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain this application, and should not be understood as limitations on this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The embodiments of this application are described in detail below in conjunction with the drawings.

[0039] like Figure 1 The pipeline ECC check system shown includes a comprehensive feature engine, a BM algorithm engine, and a positioning and correction engine, wherein:

[0040] The comprehensive feature engine is used to obtain the ECC frame and the corresponding ECC setting and generate a comprehensive feature based on the ECC frame and the corresponding ECC setting;

[0041] The BM algorithm engine is used to obtain comprehensive features and ECC settings and generate critical equations based on the comprehensive features;

[0042] The positioning and correction engine is used to obtain comprehensive features, ECC settings and critical equations and perform error positioning and correction based on the comprehensive features, ECC settings and critical equations; wherein,

[0043] The comprehensive feature engine, the BM algorithm engine and the positioning and correction engine can work simultaneously;

[0044] When the comprehensive feature engine, the BM algorithm engine, and the positioning and correction engine operate simultaneously, the comprehensive features, ECC settings, and critical equations obtained by the positioning and correction engine are the comprehensive features, ECC settings, and critical equations of the ECC frame processed by the BM algorithm engine;

[0045] The comprehensive features and ECC settings acquired by the BM algorithm engine are the comprehensive features and ECC settings of the ECC frame processed by the comprehensive feature engine.

[0046] In this embodiment, the ECC operation direction is a decoding direction.

[0047] In this embodiment, the comprehensive feature engine, BM algorithm engine, and positioning and correction engine each use a separate clock source.

[0048] This method divides the ECC engine into three loosely coupled parts (the integrated feature engine, the BM algorithm engine, and the error location and correction engine), fully utilizing all three processing components. When an ECC frame (frame A) leaves the integrated feature engine and is processed by the BM algorithm engine, the integrated feature engine is empty, and the ECC processing engine allows the next frame (frame B) to enter the integrated feature engine immediately instead of waiting for the ECC engine to complete processing of frame A. This maximizes the efficiency of the ECC engine and improves ECC processing performance.

[0049] For example, the integrated feature engine uses 200Mhz, the BM algorithm engine and the error location and correction engine use 400Mhz. The time it takes the integrated feature engine to process one ECC frame is the time it takes the BM algorithm engine and the error location and correction engine to decode and process two ECC frames of data. The time it takes the error location and correction engine to process data is shorter than that of the BM algorithm engine. Therefore, the data will flow from the integrated feature engine -> BM algorithm engine -> error location and correction engine in sequence, and the front-end engine data will not be processed while the back-end engine is still occupied. In actual applications, different clock cycles can also be used, but it is necessary to ensure that the clock frequency of the back-end BM algorithm engine and error location and correction engine processing engine is 1.5 to 2 times the clock frequency of the integrated feature engine.

[0050] See also Figure 2 , the present application also provides a pipeline ECC verification method, the pipeline ECC verification method comprising:

[0051] The comprehensive feature engine obtains the first ECC frame and the ECC setting corresponding to the first ECC frame;

[0052] The comprehensive feature engine generates a first comprehensive feature based on the first ECC frame and the corresponding first ECC setting;

[0053] The synthetic signature engine sends the first ECC setting and the first synthetic signature to the BM algorithm engine in an idle state.

[0054] In this embodiment, after the comprehensive feature engine sends the first ECC setting and the first comprehensive feature to the BM algorithm engine, the pipeline ECC check method further includes:

[0055] When the comprehensive feature engine obtains a second ECC frame after processing the first ECC frame and obtains an ECC setting corresponding to the second ECC frame, the comprehensive feature engine generates a second comprehensive feature based on the second ECC frame and the corresponding second ECC setting;

[0056] The BM algorithm engine generates a first critical equation according to the acquired first ECC setting and the first comprehensive feature and sends the first critical equation and the first ECC setting to the positioning and correction engine.

[0057] In this embodiment, when the BM algorithm engine sends the first critical equation and the first ECC setting to the positioning and correction engine and is idle, the pipeline ECC checking method further includes:

[0058] The comprehensive feature engine sends the second ECC setting and the second comprehensive feature to the BM algorithm engine in the idle state;

[0059] The positioning and correction engine is used to obtain a first comprehensive feature, a first ECC setting, and a first critical equation.

[0060] In this embodiment, after the positioning and correction engine sends the second ECC setting and the second comprehensive feature to the BM algorithm engine in the idle state, the pipeline ECC check method further includes:

[0061] The BM algorithm engine generates a second critical equation according to the acquired second ECC setting and the second comprehensive feature;

[0062] The location and correction engine performs error location and correction based on the first comprehensive feature, the first ECC setting, and the first critical equation;

[0063] When the comprehensive feature engine obtains a third ECC frame and an ECC setting corresponding to the third ECC frame after processing the second ECC frame, the comprehensive feature engine generates a third comprehensive feature according to the third ECC frame and the corresponding third ECC setting.

[0064] In this embodiment, after the location and correction engine completes error location and correction according to the first comprehensive feature, the first ECC setting, and the first critical equation and is in an idle state, the pipeline ECC check method further includes:

[0065] The BM algorithm engine sends the second critical equation and the second ECC setting to the positioning and correction engine;

[0066] The comprehensive feature engine sends the third ECC setting and the third comprehensive feature to the BM algorithm engine in the idle state

[0067] When the ECC operation direction is READ (decoding), each ECC frame flows through the ECC engine (the integrated signature engine, the BM algorithm engine, and the error location and correction engine). The settings for each ECC frame (such as ECC selection, mode selection, and data size) are all passed through the pipeline together. Each stage of the ECC engine pipeline should adjust its operating mode based on the settings accompanying the input ECC frame.

[0068] The present application is further described in detail below by way of examples. It should be understood that the examples do not constitute any limitation to the present application.

[0069] The ECC engine enters the receiving mode after receiving the initial frame signal;

[0070] The ECC engine receives ECC frame A and the corresponding ECC setting A and sends them to the comprehensive feature engine for processing. After the comprehensive feature engine completes the processing, it sends the processed comprehensive feature A and the corresponding ECC setting A to the BM algorithm engine. At this time, if a new initial frame is received, the received ECC frame B and the corresponding ECC setting B are sent to the comprehensive feature engine for processing;

[0071] The comprehensive feature A, the corresponding ECC setting A, and the critical equation A are sent from the BM algorithm engine to the error location and correction engine for error location and correction. At the same time, the processed comprehensive feature B and the corresponding ECC setting B are sent to the BM algorithm engine. At this time, if a new initial frame is received, the received ECC frame C and the corresponding ECC setting C are sent to the comprehensive feature engine for processing;

[0072] After the error location and correction engine completes error location and correction for ECC frame A, it sends out the correct data frame A, completing the ECC process.

[0073] In this embodiment, ECC frame A, ECC frame B, ECC frame C and the first ECC frame, second ECC frame, and third ECC frame described above all represent multiple consecutive adjacent ECC frames. For example, ECC frame A is the first frame, then ECC frame B is the second frame after ECC frame A, and ECC frame C is the second frame after ECC frame B, that is, the third frame after ECC frame A.

[0074] Although the present invention has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications and improvements may be made based on the present invention. Therefore, such modifications and improvements, which do not depart from the spirit of the present invention, are intended to be within the scope of protection claimed herein.

Claims

1. A pipeline ECC check system, characterized in that: The pipeline ECC checking system comprises: a comprehensive feature engine configured to obtain an ECC frame and a corresponding ECC setting and generate a comprehensive feature based on the ECC frame and the corresponding ECC setting; A BM algorithm engine, configured to obtain comprehensive features and ECC settings and generate a critical equation based on the comprehensive features; A positioning and correction engine is used to obtain comprehensive features, ECC settings, and critical equations and perform error positioning and correction based on the comprehensive features, ECC settings, and critical equations; wherein, The comprehensive feature engine, BM algorithm engine and positioning and correction engine can work simultaneously; When the comprehensive feature engine, the BM algorithm engine, and the positioning and correction engine operate simultaneously, the comprehensive features, ECC settings, and critical equations obtained by the positioning and correction engine are the comprehensive features, ECC settings, and critical equations of the ECC frame processed by the BM algorithm engine; The comprehensive features and ECC settings obtained by the BM algorithm engine are the comprehensive features and ECC settings of the ECC frame processed by the comprehensive feature engine; The comprehensive feature engine, BM algorithm engine and positioning and correction engine use separate clock sources respectively.

2. The pipeline ECC checking system according to claim 1, wherein: The ECC operation direction is the decoding direction.

3. A pipeline ECC verification method, using the pipeline ECC verification system according to any one of claims 1 to 2, characterized in that: The pipeline ECC checking method comprises: The comprehensive feature engine obtains the first ECC frame and the ECC setting corresponding to the first ECC frame; The comprehensive feature engine generates a first comprehensive feature based on the first ECC frame and the corresponding first ECC setting; The synthetic signature engine sends the first ECC setting and the first synthetic signature to the BM algorithm engine in an idle state.

4. The pipeline ECC checking method according to claim 3, wherein: After the synthetic feature engine sends the first ECC setting and the first synthetic feature to the BM algorithm engine, the pipeline ECC check method further includes: When the comprehensive feature engine obtains a second ECC frame after processing the first ECC frame and obtains an ECC setting corresponding to the second ECC frame, the comprehensive feature engine generates a second comprehensive feature based on the second ECC frame and the corresponding second ECC setting; The BM algorithm engine generates a first critical equation according to the acquired first ECC setting and the first comprehensive feature and sends the first critical equation and the first ECC setting to the positioning and correction engine.

5. The pipeline ECC checking method according to claim 4, wherein: When the BM algorithm engine sends the first critical equation and the first ECC setting to the positioning and correction engine and is idle, the pipeline ECC checking method further includes: The comprehensive feature engine sends the second ECC setting and the second comprehensive feature to the BM algorithm engine in the idle state; The positioning and correction engine is used to obtain a first comprehensive feature, a first ECC setting, and a first critical equation.

6. The pipeline ECC checking method according to claim 5, wherein: Positioning and correction engine, after the comprehensive feature engine sends the second ECC setting and the second comprehensive feature to the BM algorithm engine in the idle state, the pipeline ECC verification method further includes: The BM algorithm engine generates a second critical equation according to the acquired second ECC setting and the second comprehensive feature; The location and correction engine performs error location and correction based on the first comprehensive feature, the first ECC setting, and the first critical equation; When the comprehensive feature engine obtains a third ECC frame and an ECC setting corresponding to the third ECC frame after processing the second ECC frame, the comprehensive feature engine generates a third comprehensive feature according to the third ECC frame and the corresponding third ECC setting.

7. The pipeline ECC checking method according to claim 6, wherein: After the location and correction engine completes error location and correction according to the first comprehensive feature, the first ECC setting, and the first critical equation and is in an idle state, the pipeline ECC check method further includes: The BM algorithm engine sends the second critical equation and the second ECC setting to the positioning and correction engine; The comprehensive feature engine sends the third ECC setting and the third comprehensive feature to the BM algorithm engine in the idle state.

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