Method, device and equipment for controlling memory access based on CPU (Central Processing Unit) and storage medium
By integrating the DMA controller in the CPU processor and setting up a built-in self-testing algorithm for memory, high-speed functional testing of memory is achieved, solving the problems of low testing efficiency and incompatibility between tools in the existing technology.
Patent Information
- Application Number
- CN202411998899.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-06
AI Technical Summary
The prior art is less efficient when performing functional tests on memory, and the implementation of built-in self-testing algorithms for memory is highly dependent on specific EDA tools, resulting in incompatibility between different tools.
By obtaining the DMA controller and integrating it into the CPU processor, obtaining the configuration information of the memory to be accessed and classifying it, setting up a built-in self-testing algorithm in the CPU processor, and data reading, writing and data verification test are carried out in parallel through the DMA controller.
High-speed functional testing of memory is implemented, testing efficiency is improved, and the problem of incompatibility between tools is solved because it does not rely on specific EDA tools.
Smart Images
Figure CN119938429A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field, and in particular to a method, device, equipment and storage medium for controlling memory access based on a CPU. Background Art
[0002] At present, when performing functional tests on memory, most solutions rely on an external low-speed clock to control the read and write signals, and realize the reading, writing and verification of memory through a preset test mode. However, the test speed of this method is slow, which cannot meet the needs of high-speed access testing, and requires more input and output interfaces to control. There is a related method that inserts the EDA tool into the memory built-in self-test algorithm at the register transfer level, and then selects the group of the memory built-in self-test algorithm through the command tool of the operating system, and controls the startup of the memory built-in self-test algorithm and the reading of the test results. However, when this method is used for memory access testing, the implementation of the memory built-in self-test algorithm is highly dependent on a specific EDA tool, which may be incompatible between different tools. The implementation of the memory built-in self-test algorithm is highly dependent on a specific EDA tool, which may be incompatible between different tools, resulting in low efficiency when performing functional testing on memory.
[0003] In view of this, how to improve the efficiency of functional testing of memory is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The present invention provides a method, device, equipment and storage medium for controlling memory access based on a CPU, so as to solve the above-mentioned technical problem of low efficiency when performing functional testing on the memory.
[0005] In a first aspect, an embodiment of the present invention provides a method for controlling memory access based on a CPU, comprising:
[0006] Acquire a DMA controller, and integrate the DMA controller into a CPU processor;
[0007] Acquire configuration information of the memory to be accessed, and classify the memory to be accessed according to the acquired configuration information of the memory to be accessed;
[0008] A memory built-in self-test algorithm is set in a CPU processor integrated with a DMA controller, and a first input / output pin of the CPU processor is used to determine whether the state of the current memory to be accessed enters a memory built-in self-test state;
[0009] If the current memory to be accessed enters the memory built-in self-test state, the DMA controller performs data reading and writing and data verification tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor.
[0010] In some embodiments, obtaining a DMA controller and integrating the DMA controller into a CPU processor includes:
[0011] Define the register mapping of the DMA controller in the CPU address space and set up the driver for the DMA controller in the CPU processor.
[0012] In some embodiments, determining whether the state of the current memory to be accessed enters the memory built-in self-test state through the first input / output pin of the CPU processor includes:
[0013] If the first input / output pin of the CPU processor is at a high level, the state of the memory currently to be accessed enters the memory built-in self-test state;
[0014] If the first input / output pin of the CPU processor is at a low level, the state of the memory to be accessed currently has not entered the memory built-in self-test state.
[0015] In some embodiments, the acquiring configuration information of the memory to be accessed, and classifying the memory to be accessed according to the acquired configuration information of the memory to be accessed, includes:
[0016] The configuration information of the memory is obtained through the memory management module of the operating system, and the memory to be accessed is classified according to the type of the memory to be accessed.
[0017] In some embodiments, the DMA controller performs data read and write tests on the to-be-accessed memory with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor, including:
[0018] Initialize the DMA controller, and read and write data of the memory to be accessed in parallel through the DMA controller;
[0019] The data read and written to the memory to be accessed is transferred to the set buffer area, and it is determined whether the read and write data of the memory to be accessed in the buffer area is correct;
[0020] If the read and write data of the memory to be accessed in the cache area is correct, the read and write functions of the memory to be accessed are normal, and the second input and output pin of the CPU processor outputs a high level;
[0021] If the read and write data of the memory to be accessed in the cache area is wrong, the read and write functions of the memory to be accessed are abnormal, and the second input and output pin of the CPU processor outputs a low level.
[0022] In some embodiments, the DMA controller performs data verification tests on the to-be-accessed memory with the same current configuration information in parallel, and outputs the test results through the second input / output pin of the CPU processor, including:
[0023] Initialize the DMA controller, and read and write data in the memory to be accessed through the DMA controller;
[0024] The data of the memory to be accessed is transferred to the set buffer area, and it is determined whether the read and write data of the memory to be accessed in the buffer area are consistent;
[0025] If the read and write data of the memory to be accessed in the cache area are consistent, the data verification function of the memory to be accessed is normal, and the second input and output pin of the CPU processor outputs a high level;
[0026] If the read and write data of the memory to be accessed in the cache area are inconsistent, the data verification function of the memory to be accessed is abnormal, and the second input and output pin of the CPU processor outputs a low level.
[0027] In some embodiments, after the DMA controller performs parallel data reading and writing and data verification tests on the to-be-accessed memory with the same current configuration information and outputs the test results through the second input and output pin of the CPU processor, the method further includes:
[0028] If the second input / output pin of the CPU processor outputs a low level, the mismatch flag position in the DMA controller is set to 1.
[0029] In a second aspect, an embodiment of the present invention further provides a device for controlling memory access based on a CPU, the device comprising:
[0030] A first acquisition module is used to acquire a DMA controller and integrate the DMA controller into a CPU processor;
[0031] A second acquisition module is used to acquire configuration information of the memory to be accessed, and classify the memory to be accessed according to the acquired configuration information of the memory to be accessed;
[0032] A judgment module, used for setting a memory built-in self-test algorithm in a CPU processor integrated with a DMA controller, and judging whether the state of a current memory to be accessed enters a memory built-in self-test state through a first input / output pin of the CPU processor;
[0033] The test module, if the current state of the memory to be accessed enters the memory built-in self-test state, the DMA controller performs data reading and writing and data verification tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor.
[0034] In a third aspect, an embodiment of the present invention further provides a computer device, the device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;
[0035] Memory, which is used to store computer programs;
[0036] The processor is used to implement the steps of the method for controlling memory access based on the CPU as described in any one of the first aspects above when executing a program stored in the memory.
[0037] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method for controlling memory access based on a CPU as described in any one of the above-mentioned first aspects are implemented.
[0038] The present invention provides a method, device, equipment and storage medium based on CPU control of memory access, which obtains a DMA controller and integrates the DMA controller into a CPU processor; obtains configuration information of the memory to be accessed, and classifies the memory to be accessed according to the obtained configuration information of the memory to be accessed; sets a memory built-in self-test algorithm in the CPU processor integrated with the DMA controller, and determines whether the current state of the memory to be accessed enters the memory built-in self-test state through the first input and output pin of the CPU processor; if the current state of the memory to be accessed enters the memory built-in self-test state, the DMA controller performs data reading and writing and data verification tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor. The embodiment of the present invention controls memory access through the CPU, and can perform high-speed functional tests on the memory, effectively improving the efficiency of functional tests on the memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.
[0040] Figure 1 A flowchart of a method for controlling memory access based on a CPU provided by an embodiment of the present invention;
[0041] Figure 2 A schematic diagram of a process flow of step S31 provided in an embodiment of the present invention;
[0042] Figure 3 A schematic diagram of a process flow of step S32 provided in an embodiment of the present invention;
[0043] Figure 4 A schematic diagram of the structure of a device for controlling memory access based on a CPU provided by an embodiment of the present invention;
[0044] Figure 5 A schematic diagram of the structure of a computer device provided by an embodiment of the present invention;
[0045] Figure 6 The present invention is a schematic diagram of a computer-readable storage medium structure. DETAILED DESCRIPTION
[0046] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0047] In order to make the description of the content of the present invention more detailed and complete, the following is an illustrative description of the implementation method and specific examples of the present invention; however, this is not the only form of implementing or applying the specific embodiments of the present invention. The implementation method covers the features of multiple specific embodiments and the method steps and their sequence for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equal functions and step sequences. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0048] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.
[0049] In the description of the embodiments of the present invention, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present invention, “multiple” means two or more than two, and other quantifiers are similar. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention, and the embodiments of the present invention and the features in the embodiments may be combined with each other without conflict.
[0050] Please refer to Figure 1 , is a flow chart of a method for controlling memory access based on a CPU provided by an embodiment of the present invention. The method for controlling memory access based on a CPU can be executed by software and / or hardware devices. For example, please refer to Figure 1 As shown, the method for controlling memory access based on the CPU may include:
[0051] S10, obtaining a DMA controller, and integrating the DMA controller into a CPU processor. Specifically, in an embodiment of the present invention, the DMA controller can directly manage data transmission without frequent intervention of the CPU processor, thereby reducing the burden of the CPU processor. In addition, the DMA controller can achieve high-speed data transmission, especially when processing a large amount of data, which can significantly improve the overall performance of the system.
[0052] S20, obtaining configuration information of the memory to be accessed, and classifying the memory to be accessed according to the obtained configuration information of the memory to be accessed. Specifically, in the embodiment of the present invention, by classifying the memory to be accessed, overload of a certain memory area can be avoided, and the memory with the same configuration information can be processed in parallel, which can improve the response speed of the system.
[0053] S30, setting a memory built-in self-test algorithm in a CPU processor integrated with a DMA controller, and judging whether the state of the current memory to be accessed enters the memory built-in self-test state through the first input and output pin of the CPU processor. Specifically, in the embodiment of the present invention, through the memory built-in self-test algorithm, the health of the memory can be detected when the system is started or regularly running, and potential faults can be discovered in time. By monitoring the memory state in real time through the first input and output pin, abnormal situations can be discovered and handled in time.
[0054] S40, if the current state of the memory to be accessed enters the memory built-in self-test state, the DMA controller performs data reading and writing and data verification tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor. Specifically, in the embodiment of the present invention, the DMA controller can process multiple memories to be accessed with the same configuration information in parallel, greatly shortening the test time, and outputting the test results through the second input and output pin can realize real-time monitoring and feedback of the memory to be accessed.
[0055] It should be noted that the method for controlling memory access based on the CPU proposed in the present invention can be applied not only to machine testing but also to power-on testing, and has high portability.
[0056] In some embodiments, the obtaining of the DMA controller and integrating the DMA controller into the CPU processor includes: defining a register mapping of the DMA controller in the CPU address space and setting a driver for the DMA controller in the CPU processor. Specifically, in the embodiments of the present invention, setting a driver for the DMA controller in the CPU processor can provide a high-level API interface to facilitate calling and managing the DMA controller.
[0057] In some embodiments, the method of judging whether the state of the memory to be currently accessed has entered the memory built-in self-test state by the first input-output pin of the CPU processor includes: if the first input-output pin of the CPU processor is at a high level, the state of the memory to be currently accessed has entered the memory built-in self-test state. If the first input-output pin of the CPU processor is at a low level, the state of the memory to be currently accessed has not entered the memory built-in self-test state. Specifically, in an embodiment of the present invention, the state of the first input-output pin can be used to instantly judge whether the memory has entered the self-test state, and real-time monitoring information can be provided. The system can respond quickly according to the state of the first input-output pin, such as starting or stopping the self-test, to ensure the accuracy and timeliness of the memory state.
[0058] In some embodiments, the step of obtaining the configuration information of the memory to be accessed and classifying the memory to be accessed according to the obtained configuration information of the memory to be accessed includes: obtaining the configuration information of the memory through the memory management module of the operating system, and classifying the memory to be accessed according to the type of the memory to be accessed. Specifically, in the embodiments of the present invention, the memory can be classified according to the memory type, and different types of memory resources can be managed more accurately. The operating system can optimize the memory allocation and scheduling strategy according to the characteristics of different types of memory, thereby improving the efficiency and performance of memory use.
[0059] In some embodiments, step S30 includes: S31, the DMA controller performs data read and write tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor; S32, the DMA controller performs data verification tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor.
[0060] In some embodiments, the DMA controller performs data read and write tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor. Figure 2 , Figure 2 A flow chart of step S31 provided in an embodiment of the present invention includes:
[0061] S311, initialize the DMA controller, and read and write data of the memory to be accessed in parallel through the DMA controller. Specifically, in the embodiment of the present invention, before using the DMA controller to read and write the memory, it is necessary to initialize it, configure the source address and the target address, and set the length of the transmitted data. After completing the initialization of the DMA controller, the DMA controller can use the system bus to read and write the memory in parallel.
[0062] S312, transferring the read and written data of the memory to be accessed to the set buffer area, and determining whether the read and written data of the memory to be accessed in the buffer area is correct. Specifically, in the embodiment of the present invention, as the DMA controller reads and writes the memory, the read data will be transferred to the buffer area according to the target address set during initialization, and determining whether the read and written data of the memory to be accessed in the buffer area is correct.
[0063] S313: If the read and write data of the memory to be accessed in the cache area is correct, the read and write function of the memory to be accessed is normal, and the second input and output pin of the CPU processor outputs a high level. Specifically, in the embodiment of the present invention, the CPU processor outputs a high level signal to the outside through the second input and output pin, and the high level is set as a signal indicating that the read and write function of the memory is normal. Other devices or modules connected to the pin can detect the level state of the pin, and know that the read and write function of the memory is normal, so as to perform corresponding subsequent operations.
[0064] S314. If the read and write data of the memory to be accessed in the cache area is wrong, the read and write function of the memory to be accessed is abnormal, and the second input and output pin of the CPU processor outputs a low level. The CPU processor outputs a low level signal to the outside through the second input and output pin, and the low level is set to indicate that the memory read and write function is abnormal. After the external device or module detects this low level signal, it can be timely informed that there is a problem with the memory, and then trigger the corresponding processing mechanism, such as issuing an alarm to prompt the user, so as to locate and solve the memory failure as soon as possible.
[0065] In some embodiments, the DMA controller performs data verification tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor. Figure 3 , Figure 3 A flow chart of step S32 provided in an embodiment of the present invention includes:
[0066] S321, initialize the DMA controller, and read and write data of the memory to be accessed through the DMA controller. Specifically, in the embodiment of the present invention, before using the DMA controller to read and write the memory, it needs to be initialized. After the DMA controller is initialized, the DMA controller can use the system bus to perform read and write operations on the memory in parallel.
[0067] S322, the data of the memory to be accessed that is read and written is transferred to the set cache area, and it is judged whether the read and written data of the memory to be accessed in the cache area are consistent. Specifically, in the embodiment of the present invention, in order to verify whether the data verification function of the memory to be accessed is normal, it is necessary to perform consistency judgment on the data in the cache area. The present invention can judge whether the read and written data of the memory to be accessed in the cache area are consistent by comparing whether the data read from the memory is the same as the data previously written to the memory.
[0068] S323. If the read and write data of the memory to be accessed in the cache area are consistent, the data verification function of the memory to be accessed is normal, and the second input / output pin of the CPU processor outputs a high level. Specifically, in the embodiment of the present invention, the CPU processor outputs a high level signal to the outside through its second input / output pin, and the high level is set as a signal indicating that the memory verification function is normal.
[0069] S324: If the read and write data of the memory to be accessed in the cache area are inconsistent, the data verification function of the memory to be accessed is abnormal, and the second input / output pin of the CPU processor outputs a low level. Specifically, in the embodiment of the present invention, the CPU processor outputs a low level signal to the outside through its second input / output pin, and the low level is set as a signal indicating that the memory verification function is abnormal.
[0070] In some embodiments, after the DMA controller performs parallel data reading and writing and data verification tests on the memory to be accessed with the same current configuration information, and outputs the test results through the second input and output pin of the CPU processor, the method further includes: if the second input and output pin of the CPU processor outputs a low level, then the mismatch flag position in the DMA controller is set to 1. Specifically, in the embodiment of the present invention, by setting the mismatch flag position to 1, errors found in the data verification process can be clearly indicated, helping the system to quickly identify the problem.
[0071] On the other hand, the present invention also provides a device for controlling memory access based on a CPU, please refer to Figure 4 , is a schematic diagram of a structure of a device for controlling memory access based on a CPU provided by an embodiment of the present invention, the device comprising:
[0072] The first acquisition module 41 is used to acquire the DMA controller and integrate the DMA controller into the CPU processor; the second acquisition module 42 is used to acquire the configuration information of the memory to be accessed, and classify the memory to be accessed according to the acquired configuration information of the memory to be accessed; the judgment module 43 is used to set the memory built-in self-test algorithm in the CPU processor integrated with the DMA controller, and judge whether the current state of the memory to be accessed enters the memory built-in self-test state through the first input and output pin of the CPU processor; the test module 44, if the current state of the memory to be accessed enters the memory built-in self-test state, the DMA controller performs data reading and writing and data verification tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor.
[0073] The device 40 for controlling memory access based on CPU provided in an embodiment of the present invention can execute the technical solution of the method for controlling memory access based on CPU in any of the above-mentioned embodiments, and its implementation principle and beneficial effects are similar to the implementation principle and beneficial effects of the method for controlling memory access based on CPU. Please refer to the implementation principle and beneficial effects of the device for controlling memory access based on CPU, which will not be repeated here.
[0074] Please refer to Figure 5, is a structural diagram of a computer device provided in an embodiment of the present invention, wherein the device includes a processor 501, which can be implemented by a general central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solution provided in the embodiment of the present application; a memory 502, which can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 502 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 502, and the processor 501 calls to execute the image compression method of the embodiment of the present application; the input / output interface 503 is used to realize information input and output; the communication interface 504 is used to realize the communication interaction between this device and other devices, and communication can be realized through wired methods (such as USB, network cables, etc.) or wireless methods (such as mobile networks, WIFI, Bluetooth, etc.); the bus 505 transmits information between the various components of the device (such as the processor 501, the memory 502, the input / output interface 503 and the communication interface 504); wherein the processor 501, the memory 502, the input / output interface 503 and the communication interface 504 realize communication connection with each other within the device through the bus 505.
[0075] Please refer to Figure 6 , which is a schematic diagram of the structure of a computer-readable storage medium in an embodiment of the present invention. The storage medium 60 in an embodiment of the present invention stores program instructions 61 that can implement the above-mentioned method of controlling memory access based on CPU, wherein the program instructions 61 can be stored in the above-mentioned storage medium in the form of a software product, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks or optical disks, or terminal devices such as computers, servers, mobile phones, and tablets.
[0076] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0077] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional units. The above is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present invention.
[0078] The above are only preferred embodiments of the present invention, and are not intended to limit the present invention in any form. Although the present invention has been disclosed as above in the form of preferred embodiments, it is not intended to limit the present invention. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.
Claims
1. A method for controlling memory access based on a CPU, characterized in that: include: Acquire a DMA controller, and integrate the DMA controller into a CPU processor; Acquire configuration information of the memory to be accessed, and classify the memory to be accessed according to the acquired configuration information of the memory to be accessed; A memory built-in self-test algorithm is set in a CPU processor integrated with a DMA controller, and a first input / output pin of the CPU processor is used to determine whether the state of the current memory to be accessed enters a memory built-in self-test state; If the current memory to be accessed enters the memory built-in self-test state, the DMA controller performs data reading and writing and data verification tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor.
2. The method for controlling memory access based on CPU according to claim 1, characterized in that: The step of obtaining a DMA controller and integrating the DMA controller into a CPU processor includes: Define the register mapping of the DMA controller in the CPU address space and set up the driver for the DMA controller in the CPU processor.
3. The method for controlling memory access based on CPU according to claim 1, characterized in that: The method of judging whether the state of the memory to be accessed currently enters the memory built-in self-test state through the first input / output pin of the CPU processor comprises: If the first input / output pin of the CPU processor is at a high level, the state of the memory currently to be accessed enters the memory built-in self-test state; If the first input / output pin of the CPU processor is at a low level, the state of the memory to be accessed currently has not entered the memory built-in self-test state.
4. The method for controlling memory access based on CPU according to claim 1, characterized in that: The obtaining of configuration information of the memory to be accessed, and classifying the memory to be accessed according to the obtained configuration information of the memory to be accessed, includes: The configuration information of the memory is obtained through the memory management module of the operating system, and the memory to be accessed is classified according to the type of the memory to be accessed.
5. The method for controlling memory access based on CPU according to claim 1, characterized in that: The DMA controller performs data read and write tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor, including: Initialize the DMA controller, and read and write data of the memory to be accessed in parallel through the DMA controller; The data read and written to the memory to be accessed is transferred to the set buffer area, and it is determined whether the read and write data of the memory to be accessed in the buffer area is correct; If the read and write data of the memory to be accessed in the cache area is correct, the read and write functions of the memory to be accessed are normal, and the second input and output pin of the CPU processor outputs a high level; If the read and write data of the memory to be accessed in the cache area is wrong, the read and write functions of the memory to be accessed are abnormal, and the second input and output pin of the CPU processor outputs a low level.
6. The method for controlling memory access based on CPU according to claim 5, characterized in that: The DMA controller performs data verification test on the memory to be accessed with the same current configuration information in parallel, and outputs the test result through the second input and output pin of the CPU processor, including: Initialize the DMA controller, and read and write data in the memory to be accessed through the DMA controller; The data of the memory to be accessed is transferred to the set buffer area, and it is determined whether the read and write data of the memory to be accessed in the buffer area are consistent; If the read and write data of the memory to be accessed in the cache area are consistent, the data verification function of the memory to be accessed is normal, and the second input and output pin of the CPU processor outputs a high level; If the read and write data of the memory to be accessed in the cache area are inconsistent, the data verification function of the memory to be accessed is abnormal, and the second input and output pin of the CPU processor outputs a low level.
7. The method for controlling memory access based on CPU according to claim 6, characterized in that: After the DMA controller performs parallel data reading and writing and data verification tests on the to-be-accessed memory with the same current configuration information, and outputs the test results through the second input and output pin of the CPU processor, the method further includes: If the second input / output pin of the CPU processor outputs a low level, the mismatch flag position in the DMA controller is set to 1.
8. A device for controlling memory access based on a CPU, characterized in that: The device comprises: A first acquisition module is used to acquire a DMA controller and integrate the DMA controller into a CPU processor; A second acquisition module is used to acquire configuration information of the memory to be accessed, and classify the memory to be accessed according to the acquired configuration information of the memory to be accessed; A judgment module, used for setting a memory built-in self-test algorithm in a CPU processor integrated with a DMA controller, and judging whether the state of a current memory to be accessed enters a memory built-in self-test state through a first input / output pin of the CPU processor; The test module, if the current state of the memory to be accessed enters the memory built-in self-test state, the DMA controller performs data reading and writing and data verification tests on the memory to be accessed with the same current configuration information in parallel, and outputs the test results through the second input and output pin of the CPU processor.
9. A computer device, characterized in that: The device includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, which is used to store computer programs; A processor, for implementing the steps of the method for controlling memory access based on a CPU as described in any one of claims 1 to 7 when executing a program stored in a memory.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for controlling memory access based on a CPU as described in any one of claims 1 to 7 are implemented.