Logical mapping table updating method of storage device, controller, device and medium

Abstract

The present application discloses a method for updating a logical mapping table of a storage device, as well as a controller, device, and medium, and relates to the field of logical mapping table management technology. The method includes: storing the first logical mapping information of the written logical data one by one; when the first storage quantity of the accumulated first logical mapping information is equal to the storage quantity threshold, writing the accumulated first logical mapping information into the SLC block to obtain the second logical mapping information; when the second storage quantity of the accumulated second logical mapping information is equal to the preset threshold, or in response to a mapping table forced update instruction, reading the currently accumulated second logical mapping information, sorting the second logical mapping information according to the logical address, and updating the corresponding first logical mapping table according to the sorted second logical mapping information to obtain the second logical mapping table; it can reduce the switching frequency of the logical mapping table in random write scenarios, improve random write performance, and reduce the read and write loss of the storage device.

Description

Technical Field

[0001] The present application relates to the technical field of logical mapping table management, and in particular to a method for updating a logical mapping table of a storage device, a controller, a device, and a medium. Background Art

[0002] NAND storage devices contain a mapping table to record the mapping relationship between logical addresses and physical addresses. This logical-to-physical mapping table is called the L2P table. When reading data, the logical mapping table is used to find the physical location of the data in the flash memory, allowing the correct data to be read. The size of the logical mapping table is relatively large and increases linearly with the capacity of the storage device. For example, the mainstream FTL (flash memory management algorithm) uses 4K mapping. If each 4K data uses 4 bytes of space to maintain mapping information, a 32GB storage device will have a 32MB logical mapping table, and a 128GB storage device will have a 128MB logical mapping table. However, typical storage devices do not have enough memory to cache these logical mapping tables in full in memory. They can only cache a portion of the logical mapping table. During the read and write process, the logical mapping table that matches the address of the logical data accessed by the host is read into memory. Before switching the logical mapping table, the partially updated logical mapping table in memory must be written to the flash memory to free up free memory space.

[0003] Storage products such as eMMC, UFS, SD cards, and USB flash drives have very little internal RAM (Random Access Memory). Generally, only a portion of the logical mapping table is cached in memory. In random write scenarios, the logical mapping table update method used in related technologies includes: immediately updating the mapping information corresponding to the data in question to the logical mapping table L2P after writing the data. This solution is limited by memory space, and the switching frequency of the logical mapping table is very high during random writes. This results in more logical mapping table reads and writes, which affects the read and write performance of the logical data, reduces random write performance, and shortens the life of the storage device. Therefore, there is an urgent need to optimize the logical mapping table update method. Summary of the Invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for updating a logical mapping table of a storage device, as well as a controller, device, and medium. The method can update the logical mapping table using sorted logical mapping information based on an optimized logical mapping table update strategy, thereby reducing the switching frequency of the logical mapping table in random write scenarios, improving random write performance, and reducing the read and write loss of the storage device.

[0005] In a first aspect, an embodiment of the present application provides a method for updating a logical mapping table of a storage device, which is applied to a controller of the storage device, wherein the storage device further includes: a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit includes: a data block, wherein the data block includes a plurality of SLC blocks;

[0006] The method comprises:

[0007] storing first logical mapping information of the logical data written into the data block one by one in the memory unit; wherein the first logical mapping information includes a logical address of the logical data and a corresponding physical address;

[0008] When a first storage quantity of the first logical mapping information accumulated and stored in the memory unit is equal to a storage quantity threshold, writing the first storage quantity of the first logical mapping information accumulated and stored in the memory unit into an SLC block to obtain second logical mapping information;

[0009] When a second storage quantity of the second logical mapping information accumulated in the SLC block is equal to a preset threshold, or in response to a mapping table forced update instruction, the currently accumulated second logical mapping information is read from the SLC block and cached into a temporarily requested memory unit, and the second logical mapping information is sorted according to the logical address to obtain sorted second logical mapping information;

[0010] A table update process is performed according to the sorted second logical mapping information, and the corresponding first logical mapping table is updated to obtain a second logical mapping table; wherein the table update process is used to update multiple adjacent second logical mapping information that hit the same first logical mapping table to the corresponding first logical mapping table to obtain a second logical mapping table.

[0011] In a second aspect, an embodiment of the present application provides a controller comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the logical mapping table update method of the storage device as described in any one of the embodiments of the first aspect.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising the controller as described in the embodiment of the second aspect.

[0013] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the logical mapping table updating method of a storage device as described in any one of the embodiments of the first aspect.

[0014] The embodiments of the present application include:

[0015] The storage device includes: a memory unit and a flash memory unit; wherein the flash memory unit includes: a data block, and the data block includes a plurality of SLC blocks; when it is necessary to update the logical mapping table of the storage device, first, the first logical mapping information of the logical data written into the data block is stored one by one in the memory unit; wherein the first logical mapping information includes the logical address of the logical data and the corresponding physical address; then, when the first storage quantity of the first logical mapping information accumulated in the memory unit is equal to the storage quantity threshold, the first logical mapping information accumulated in the first storage quantity is written into the SLC block to obtain the second logical mapping information; then, when the second storage quantity of the second logical mapping information accumulated in the SLC block is equal to the preset threshold, or in response to a forced update instruction of the mapping table, the second logical mapping information is updated from the SLC block. The currently accumulated second logical mapping information is read from the block and cached into the temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain the sorted second logical mapping information; this is conducive to determining multiple adjacent second logical mapping information that hit the same first logical mapping table, and thus is conducive to reducing the switching frequency of the logical mapping table in the subsequent table update processing; finally, the table update processing is performed according to the sorted second logical mapping information, and the corresponding first logical mapping table is updated to obtain the second logical mapping table; wherein the table update processing is used to: update multiple adjacent second logical mapping information that hit the same first logical mapping table to the corresponding first logical mapping table to obtain the second logical mapping table; implement an optimized logical mapping table update strategy; and after reading the first logical mapping table once, the multiple adjacent second logical mapping information that hit the same first logical mapping table can be written into the first logical mapping table, thereby reducing the switching frequency of the logical mapping table in the scenario of random writing of logical data, improving random write performance, reducing the read and write loss of the storage device, and reducing the loss of the life of the storage device. That is to say, the embodiment of the present application can update the logical mapping table through sorted logical mapping information based on the optimized logical mapping table update strategy, reduce the switching frequency of the logical mapping table in random write scenarios, improve random write performance, and reduce the read and write loss of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of a system architecture of a storage device provided by one embodiment of the present application;

[0017] Figure 2 This is a flow chart of a method for updating a logical mapping table of a storage device provided by one embodiment of the present application;

[0018] Figure 3 This is a schematic diagram of the overall process of storing and processing accumulated logical mapping information provided by an embodiment of the present application;

[0019] Figure 4 This is a schematic diagram of the overall process of reading, processing and updating the accumulated second logical mapping information provided by an embodiment of the present application;

[0020] Figure 5 This is a schematic diagram of the overall process of reading and writing a logical mapping table provided by an embodiment of the present application;

[0021] Figure 6 This is a schematic diagram of the hardware structure of a controller provided in one embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of this application more clear, this application is further described in detail below with reference to the accompanying drawings and embodiments.

[0023] It should be understood that in the description of this application, descriptions of orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0024] It should be noted that although a logical order is shown in the flowchart in the description of this application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of this application, "several" means one or more, and "more" means two or more. The description of "first" and "second" is only used to distinguish technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0026] First, some terms used in this application are explained:

[0027] OOB (out-of-band) area: Each NAND flash page has an OOB area for storing hardware ECC checksums, bad block markers, and file system organization information. This area is primarily used for hardware error correction and bad block handling. A 512-byte NAND page typically allocates 16 bytes of OOB per page; a 2KB page allocates 64 bytes of OOB per page.

[0028] SLC BLOCK refers to a storage block of single-level cell (SLC) flash memory. SLC is a NAND flash memory technology in which each cell can only store one bit of data.

[0029] The present application discloses a method for updating a logical mapping table of a storage device, a controller, an electronic device, and a computer-readable storage medium, and relates to the field of logical mapping table management technology. The method includes: storing the first logical mapping information of the written logical data one by one; when the first storage quantity of the accumulated first logical mapping information is equal to the storage quantity threshold, writing the accumulated first logical mapping information into the SLC block to obtain the second logical mapping information; when the second storage quantity of the accumulated second logical mapping information is equal to the preset threshold, or in response to a mapping table forced update instruction, reading the currently accumulated second logical mapping information and caching it into a temporarily applied memory unit, sorting the second logical mapping information according to the logical address, and updating the corresponding first logical mapping table according to the sorted second logical mapping information to obtain the second logical mapping table; it can reduce the switching frequency of the logical mapping table in random write scenarios, improve random write performance, and reduce the read and write loss of the storage device.

[0030] The embodiments of the present application are further described below with reference to the accompanying drawings.

[0031] like Figure 1 As shown, the storage device includes: a controller, a memory unit electrically connected to the controller, and a flash memory unit; wherein the flash memory unit includes: a data block, the data block includes multiple SLC blocks, wherein each data block includes multiple data pages, and each data page also includes an OOB area.

[0032] A data block is a block that stores data. It includes SLC blocks and TLC blocks, and is a block in the NAND flash. An SLC block is a block that stores data in SLC mode.

[0033] The flash memory unit is used to store the logical mapping table, logical data, and second logical mapping information; the memory unit is used to store the accumulated first logical mapping information; and the temporarily applied memory unit is used to cache the logical mapping table and second logical mapping information to be updated. A controller is used to execute the logical mapping table update method of the storage device provided in the embodiments of the present application.

[0034] Specifically, the memory unit refers to RAM (Random Access Memory). It is understood that the memory unit stores accumulated logical mapping information, logical mapping tables, data, and other global variables, and different types of data (accumulated first logical mapping information, to-be-updated logical mapping tables, and second logical mapping information) are simply stored in different locations in the memory unit.

[0035] Those skilled in the art will understand that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0036] The system embodiment described above is merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0037] Those skilled in the art will understand that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will know that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0038] Based on the above system structure, various embodiments of the method for updating the logical mapping table of the storage device of the present application are proposed below.

[0039] First, as Figure 2 As shown, the logic mapping table updating method of the storage device can be applied to Figure 1 The controller of the storage device shown in the figure further includes: a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit includes: a data block, wherein the data block includes multiple SLC blocks. The logical mapping table update method of the storage device may include but is not limited to steps S110 to S140.

[0040] Step S110: storing first logical mapping information of the logical data written into the data block into the memory unit one by one; wherein the first logical mapping information includes the logical address of the logical data and the corresponding physical address.

[0041] Step S120: When the first storage quantity of the first logical mapping information accumulated in the memory unit is equal to the storage quantity threshold, the first storage quantity of the first logical mapping information accumulated is written into the SLC block to obtain second logical mapping information.

[0042] Step S130: When the second storage quantity of the second logical mapping information accumulated in the SLC block is equal to a preset threshold, or in response to a forced update instruction of the mapping table, the currently accumulated second logical mapping information is read from the SLC block and cached into a temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain the sorted second logical mapping information.

[0043] Step S140: Perform table update processing based on the sorted second logical mapping information, update the corresponding first logical mapping table, and obtain a second logical mapping table; wherein the table update processing is used to: update multiple adjacent second logical mapping information that hit the same first logical mapping table to the corresponding first logical mapping table to obtain a second logical mapping table.

[0044] It is understood that in step S110, due to limited memory space, only a small, fixed memory unit can be requested to store the first logical mapping information corresponding to the written logical data. The limited storage capacity of the memory unit defines a storage quantity threshold for the first logical mapping information. It is understood that the storage quantity threshold is determined by the storage capacity of the memory unit, and the present embodiment does not impose any specific restrictions on the value of the storage quantity threshold.

[0045] According to some embodiments of the present application, in step S120, before writing the first logical mapping information of the accumulated first storage quantity into the SLC block, the method also includes: when the first storage quantity is equal to the storage quantity threshold, recording the address range of the data block where the logical data corresponding to the accumulated first logical mapping information is located; and recording the physical storage address of the accumulated stored first logical mapping information.

[0046] The embodiment of the present application records the address range of the data block where the logical data corresponding to the first logical mapping information is located, so as to facilitate the reconstruction of the logical mapping information when the logical mapping information is erroneous; and records the physical storage address of the first logical mapping information, so as to facilitate the subsequent orderly reading of the second logical mapping information stored in the SLC block.

[0047] According to some embodiments of the present application, the first logical mapping information of the accumulated first storage quantity is written into the SLC block, including: writing the first logical mapping information into the SLC block, and when confirming that the first logical mapping information is successfully written into the SLC block, obtaining the second logical mapping information, and clearing the first logical mapping information accumulated in the memory unit; continuing to write the first logical mapping information of the logical data into the memory unit until the second logical mapping information is equal to a preset threshold.

[0048] It is understandable that since the memory unit is fixed and can only store a limited amount of first logical mapping information, whenever the accumulated first logical mapping information reaches the storage quantity threshold, the first logical mapping information cached in the memory unit needs to be written to the SLC block to implement phased storage of the first logical mapping information, rather than storing the logical mapping information once each time logical data is written, thereby reducing the frequency of reading and writing the first logical mapping information, which is conducive to reducing read and write losses.

[0049] The embodiment of the present application implements the processing flow of storing accumulated logical mapping information through steps S110 to S120. Figure 3 , describing the overall process of processing the stored accumulated logical mapping information provided by the embodiment of the present application.

[0050] Step S301: writing logical data into a data block.

[0051] Step S302: storing first logic mapping information corresponding to the written logic data into a memory unit.

[0052] Step S303: Determine whether the first storage quantity of the first logical mapping information is equal to the storage quantity threshold; if so, jump to execute steps after step S304; if not, repeat step S301 to step S302.

[0053] Step S304: Record the address range of the data block where the logical data corresponding to the accumulated first logical mapping information is located and the physical storage address of the accumulated first logical mapping information.

[0054] Step S305: Write the accumulated first logical mapping information into the SLC block to obtain second logical mapping information.

[0055] Step S306: clearing the first logic mapping information accumulated in the memory unit.

[0056] Step S307: determine whether the accumulated second logical mapping information is equal to a preset threshold; if so, end; if not, jump to step S301 and subsequent steps.

[0057] It is understood that two conditions are set in step S130 to trigger the update of the logical mapping table. The first is to set a preset threshold. When the second stored amount of the accumulated second logical mapping information equals the preset threshold, the subsequent logical mapping information reading and sorting process and the logical mapping table update process in step S140 are triggered. The second is to respond to a mapping table forced update instruction sent by the administrator when it is necessary to forcibly update the accumulated second logical mapping information to the logical mapping table in some scenarios, and to trigger the subsequent logical mapping information reading and sorting process and the logical mapping table update process in step S140.

[0058] It is understandable that the preset threshold can be configured according to actual needs. Therefore, the embodiment of the present application does not impose any specific restrictions on the value of the preset threshold.

[0059] It is understood that under the second trigger condition, the amount of second logical mapping information updated to the logical mapping table is less than or equal to the preset threshold. However, this application does not impose specific restrictions on the scenario where the accumulated second logical mapping information needs to be forcibly updated to the logical mapping table.

[0060] In steps S110 to S140, when it is necessary to update the logical mapping table of the storage device, first, the first logical mapping information of the logical data of the written data block is stored one by one in the memory unit; wherein the first logical mapping information includes the logical address of the logical data and the corresponding physical address; then, when the first storage quantity of the first logical mapping information accumulated in the memory unit is equal to the storage quantity threshold, the accumulated first storage quantity of the first logical mapping information is written into the SLC block to obtain the second logical mapping information; then, when the second storage quantity of the second logical mapping information accumulated in the SLC block is equal to the preset threshold, or in response to the mapping table forced update instruction, the second logical mapping information is written from the SLC block to the SLC block to obtain the second logical mapping information. The currently accumulated second logical mapping information is read from the block and cached into the temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain the sorted second logical mapping information; this is conducive to determining multiple adjacent second logical mapping information that hit the same first logical mapping table, and thus is conducive to reducing the switching frequency of the logical mapping table in the subsequent table update processing; finally, the table update processing is performed according to the sorted second logical mapping information, and the corresponding first logical mapping table is updated to obtain the second logical mapping table; wherein the table update processing is used to: update multiple adjacent second logical mapping information that hit the same first logical mapping table to the corresponding first logical mapping table to obtain the second logical mapping table; implement an optimized logical mapping table update strategy; and after reading the first logical mapping table once, the multiple adjacent second logical mapping information that hit the same first logical mapping table can be written into the first logical mapping table, thereby reducing the switching frequency of the logical mapping table in the scenario of random writing of logical data, improving random write performance, reducing the read and write loss of the storage device, and reducing the loss of the life of the storage device. That is to say, the embodiment of the present application can update the logical mapping table through sorted logical mapping information based on the optimized logical mapping table update strategy, reduce the switching frequency of the logical mapping table in random write scenarios, improve random write performance, and reduce the read and write loss of the storage device.

[0061] According to some embodiments of the present application, step S130 is further described, wherein the currently accumulated second logical mapping information is read from the SLC block and cached into a temporarily applied memory unit, and the second logical mapping information is sorted according to the logical address to obtain the sorted second logical mapping information, including but not limited to steps S131 to S133.

[0062] Step S131: Read the second logical mapping information stored in the SLC blocks one by one according to the writing order of the physical storage addresses.

[0063] Step S132: When it is determined that the read second logical mapping information is correct and the number of temporarily applied memory units is sufficient, the read second logical mapping information is stored in the temporarily applied memory units in a writing order.

[0064] Step S133: in the temporarily applied memory unit, sort the second logical mapping information according to the order of logical addresses from large to small, or sort the second logical mapping information according to the order of logical addresses from small to large, to obtain sorted second logical mapping information.

[0065] It can be understood that, through step S131 , the second logical mapping information can be read in an orderly manner to avoid errors and omissions, thereby ensuring the integrity of data reading.

[0066] It is understandable that the read second logical mapping information may be wrong. Updating the wrong second logical mapping information to the logical mapping table is not conducive to the subsequent correct reading of the logical data. Through step S132, the correctness of the second logical mapping information is ensured and then the second logical mapping information is stored in the temporarily applied memory unit, laying the foundation for subsequent updates to obtain the correct logical mapping table.

[0067] It should be noted that the amount of accumulated second logical mapping information to be read needs to be determined based on the number of temporarily applied memory cells currently available. When the number of available temporarily applied memory cells is sufficient, all accumulated second logical mapping information is read out and placed sequentially in the temporarily applied memory cells. When the number of available temporarily applied memory cells is insufficient, part of the second logical mapping information is read out and placed sequentially in the temporarily applied memory cells.

[0068] Further explaining step S133, when all or part of the accumulated logical mapping information has been read into the temporarily requested memory unit, in order to improve random write performance, reduce frequent switching of logical mapping tables, and reduce the loss of flash memory life caused by writing a large number of logical mapping tables to the flash memory, the logical mapping information cached in the data buffer can be sorted in order of logical address from small to large or from large to small. After the sorting is adjusted, in the subsequent process of updating the second logical mapping information to the logical mapping table, adjacent second logical mapping information that hits the same logical mapping table is read once, and the adjacent second logical mapping information that hits the same logical mapping table is updated to the logical mapping table one by one, thereby reducing the number of logical mapping table switching times. In other words, step S133 facilitates determining multiple adjacent second logical mapping information that hit the same first logical mapping table by sorting the second logical mapping information.

[0069] Through step S131 to step S133, it is helpful to determine multiple adjacent second logical mapping information that hit the same first logical mapping table, thereby helping to reduce the switching frequency of the logical mapping table in subsequent table update processing and improve the efficiency of updating the logical mapping table.

[0070] According to some embodiments of the present application, each data block includes multiple data pages, and each data page also includes an OOB area; step S131: after reading the second logical mapping information stored in the SLC block one by one, the method also includes but is not limited to steps S134 to S135.

[0071] Step S134: when it is determined that the read second logical mapping information is erroneous, all data pages within the address range of the data block where the logical data corresponding to the recorded first logical mapping information is located are read.

[0072] Step S135 : obtaining first logical mapping information corresponding to each written logical data and the writing sequence of each logical data from the OOB area of ​​the read data page, and reconstructing erroneous second logical mapping information.

[0073] Through steps S134 to S135, when the read second logical mapping information is erroneous, the erroneous second logical mapping information is quickly reconstructed based on the address range of the data block where the logical data corresponding to the previously recorded first logical mapping information is located, so as to facilitate the subsequent correct and rapid update of the logical mapping table.

[0074] The embodiment of the present application implements a partial processing flow of reading the accumulated second logical mapping information through steps S131 to S135. Figure 4 , further illustrating the overall process of processing the read and update accumulated second logical mapping information provided by the embodiment of the present application.

[0075] Step S401 : When the second storage quantity of the second logical mapping information accumulated in the SLC block is equal to a preset threshold, or in response to a mapping table forced update instruction.

[0076] Step S402: Read the second logical mapping information stored in the SLC blocks one by one according to the recorded writing order of the physical storage addresses of the corresponding first mapping logics.

[0077] Step S403: Determine whether the read second logical mapping information is wrong; if so, jump to step S404 and subsequent steps; if not, jump to step S405 and subsequent steps.

[0078] Step S404: Read all data pages within the address range according to the address range of the data block where the logical data corresponding to the recorded first mapping logic is located, obtain the first logical mapping information corresponding to each written logical data from the OOB area of ​​the read data page, and reconstruct the erroneous second logical mapping information.

[0079] Step S405: Determine whether the number of temporarily applied memory units is sufficient; if so, jump to step S409 to step S410; if not, jump to step S406 to step S408.

[0080] Step S406: Cache the read portion of the accumulated second logical mapping information into the temporarily allocated memory unit.

[0081] Step S407: updating the second logical mapping information of part of the temporarily applied memory unit into the logical mapping table.

[0082] Step S408: Clear the temporarily applied memory unit and jump to re-execute step S401 and subsequent steps.

[0083] Step S409: Determine whether all accumulated second logical mapping information has been stored in the temporarily applied memory unit. If so, execute step S410; if not, re-execute step S401 and subsequent steps.

[0084] Step S410: updating all the second logical mapping information accumulated in the temporarily applied memory units into the logical mapping table, and then ending.

[0085] According to some embodiments of the present application, step S140 is further described. Step S140: performing table update processing according to the sorted second logical mapping information, updating the corresponding first logical mapping table to obtain a second logical mapping table, including but not limited to steps S141 to S144.

[0086] Step S141: Acquire mapping numbers of all first logical mapping tables corresponding to the sorted second logical mapping information.

[0087] Step S142: In response to the read cache command, asynchronously read the first logical mapping table indicated by the mapping number from the flash memory unit and cache it in the temporarily requested memory unit.

[0088] Step S143: When a first logic mapping table is read successfully, in the temporarily applied memory unit, the currently hit first logic mapping table is updated according to multiple adjacent second logic mapping information that hit the same first logic mapping table to obtain a corresponding second logic mapping table.

[0089] Step S144: after the currently hit first logical mapping table is updated, the next first logical mapping table is updated in response to the next read cache command, until all second logical mapping information is updated to the corresponding first logical mapping tables, thereby obtaining all corresponding second logical mapping tables.

[0090] Through steps S141 to S144, multiple adjacent second logical mapping information that hit the same first logical mapping table can be updated one by one to the currently hit first logical mapping table, reducing the switching frequency of the logical mapping table, improving random write performance, and reducing the read and write loss of the storage device.

[0091] According to some embodiments of the present application, after obtaining the second logical mapping table, the method further includes: receiving a write cache command; and in response to the write cache command, writing the updated second logical mapping table in the temporarily requested memory unit to the flash memory unit each time a second logical mapping table is obtained, thereby completing the update of all logical mapping tables.

[0092] Further describing the update process for the accumulated second logical mapping information provided in an embodiment of the present application: When all or part of the accumulated second logical mapping information has been read into a temporarily requested memory unit, the second logical mapping information cached in the temporarily requested memory unit is sorted in ascending or descending order of logical addresses. After this sorting, during subsequent updates of the logical mapping information to the logical mapping table L2P, the logical mapping information is updated one by one according to the sorted logical mapping information. Adjacent logical mapping information that hits the same logical mapping table is updated into the logical mapping table until all second logical mapping information cached in the temporarily requested memory unit is updated. If only part of the accumulated second logical mapping information is cached in the temporarily requested memory unit, after the second logical mapping information of the currently temporarily requested memory unit is updated, the remaining accumulated second logical mapping information must be read from the SLC block again and placed into the temporarily requested memory unit. The above second logical mapping information update process is repeated until the second logical mapping information in the SLC block is completely updated.

[0093] Combine Figure 5 , further illustrating the overall process of reading and writing the logical mapping table provided by the embodiment of the present application.

[0094] The read and write process of the logical mapping table L2P is as follows: obtain the map no of all logical mapping tables L2P corresponding to the sorted logical mapping information, use the flash cache read command to asynchronously read the logical mapping table from the flash memory, until the data of a certain logical mapping table is confirmed to have been read successfully, update the logical mapping information that hits this logical mapping table one by one, until the logical mapping information that hits this logical mapping table is completely updated, send the next cache read command for the logical mapping table that has not sent the flash read command, and repeat the above process until the upper limit of the number of logical mapping tables cached in the memory is reached. After completing the update of the logical mapping information corresponding to all cached logical mapping tables in the memory, use the flash cache write command to write all the updated cached logical mapping tables to the flash memory. Repeat the above process until all sorted logical mapping information is updated to the logical mapping table.

[0095] Step S501: Acquire mapping numbers of all first logical mapping tables corresponding to the sorted second logical mapping information.

[0096] Step S502: determine whether all second logical mapping information has been updated; if so, end the process; if not, continue to execute step S503 and subsequent steps.

[0097] Step S503: Determine whether all logical mapping tables have sent read commands; if so, execute step S508 and subsequent steps; if not, execute step S504 and subsequent steps.

[0098] Step S504: Use the cache read command (ie, read cache command) of the flash memory to asynchronously read the logical mapping table.

[0099] Step S505: Determine whether there is a logic mapping table that has read back data. If so, execute step S506 and subsequent steps; if not, jump to execute step S507 and subsequent steps.

[0100] Step S506: Update all logical mapping information that hits this logical mapping table into the logical mapping table.

[0101] Step S507: determine whether the number of logical mapping tables read by the Cache read command reaches the upper limit of the number of logical mapping tables cached in the memory unit; if so, continue to execute step S508; if not, jump to execute step S503 and subsequent steps.

[0102] Step S508: Entering a synchronization state to ensure that the data of all logic mapping tables in the memory unit have been read back.

[0103] Step S509: All the logical mapping information that hits the logical mapping table in the memory unit is updated into the logical mapping table accordingly.

[0104] Step S510: Use the cache write command (write cache command) of the flash memory to write all updated logical mapping tables in the cache into the flash memory unit, and jump to step S502.

[0105] like Figure 6 As shown, the present invention also provides a controller, comprising:

[0106] The processor 601 may be implemented as a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, and is configured to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0107] The memory 602 can be implemented in the form of a read-only memory, a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 602 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 602, and the processor 601 calls and executes the logical mapping table update method of the memory device in the embodiments of this application;

[0108] Input / output interface 603, used to implement information input and output;

[0109] Communication interface 604, used to implement communication interaction between the apparatus and other devices, which can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, Wi-Fi, Bluetooth, etc.);

[0110] Bus 605 , which transmits information between various components of the device (e.g., processor 601 , memory 602 , input / output interface 603 , and communication interface 604 );

[0111] The processor 601 , the memory 602 , the input / output interface 603 and the communication interface 604 are connected to each other in communication within the device via a bus 605 .

[0112] An embodiment of the present application also provides an electronic device, including the controller as described above.

[0113] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the method for updating the logical mapping table of the above-mentioned storage device is implemented.

[0114] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory optionally includes a memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of the above-mentioned networks include but are not limited to the Internet, an intranet, a local area network, a mobile communication network and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are located in one place, or may be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0115] Those skilled in the art will appreciate that all or some of the steps and systems in the method disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include computer storage media (or non-transitory media) and communication media (or temporary media). As known to those skilled in the art, the term computer storage media is included in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data) and is volatile and non-volatile, removable, and non-removable. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory, or other memory technology, CD-ROM, digital versatile disks (DVD), or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage, or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0116] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the present application.

Claims

1. A method for updating a logical mapping table of a storage device, characterized in that: A controller applied to a storage device, the storage device further comprising: a memory unit and a flash memory unit electrically connected to the controller; wherein the flash memory unit comprises: a data block, the data block comprising a plurality of SLC blocks; The method comprises: storing first logical mapping information of the logical data written into the data block one by one in the memory unit; wherein the first logical mapping information includes a logical address of the logical data and a corresponding physical address; When a first storage quantity of the first logical mapping information accumulated and stored in the memory unit is equal to a storage quantity threshold, writing the first storage quantity of the first logical mapping information accumulated and stored in the memory unit into an SLC block to obtain second logical mapping information; When a second storage quantity of the second logical mapping information accumulated in the SLC block is equal to a preset threshold, or in response to a mapping table forced update instruction, the currently accumulated second logical mapping information is read from the SLC block and cached into a temporarily requested memory unit, and the second logical mapping information is sorted according to the logical address to obtain sorted second logical mapping information; A table update process is performed according to the sorted second logical mapping information, and the corresponding first logical mapping table is updated to obtain a second logical mapping table; wherein the table update process is used to update multiple adjacent second logical mapping information that hit the same first logical mapping table to the corresponding first logical mapping table to obtain a second logical mapping table.

2. The method for updating a logical mapping table of a storage device according to claim 1, wherein: Before writing the first logical mapping information of the accumulated first storage quantity into the SLC block, the method further includes: When the first storage quantity is equal to a storage quantity threshold, recording an address range of a data block where the logical data corresponding to the accumulated first logical mapping information is located; The physical storage address of the accumulated stored first logical mapping information is recorded.

3. The method for updating the logical mapping table of a storage device according to claim 2, wherein: Writing the accumulated first storage quantity of the first logical mapping information into an SLC block includes: writing the first logical mapping information into the SLC block, obtaining the second logical mapping information when confirming that the first logical mapping information is successfully written into the SLC block, and clearing the first logical mapping information accumulated in the memory unit; The first logical mapping information of the logical data continues to be written into the memory unit until the second logical mapping information is equal to a preset threshold.

4. The method for updating a logical mapping table of a storage device according to claim 2, wherein: The method further comprises: reading the currently accumulated second logical mapping information from the SLC block and caching it in a temporarily applied memory unit; sorting the second logical mapping information according to the logical address to obtain sorted second logical mapping information; and Reading the second logical mapping information stored in the SLC blocks one by one according to the writing order of the physical storage addresses; When it is determined that the read second logical mapping information is correct and the number of temporarily applied memory units is sufficient, the read second logical mapping information is stored in the temporarily applied memory units according to the writing order; In the temporarily applied memory unit, the second logical mapping information is sorted according to the order of the logical addresses from large to small, or the second logical mapping information is sorted according to the order of the logical addresses from small to large to obtain the sorted second logical mapping information.

5. The method for updating the logical mapping table of a storage device according to claim 4, wherein: Each data block includes a plurality of data pages, and each of the data pages also includes an OOB area; After reading the second logical mapping information stored in the SLC blocks one by one, the method further includes: When it is determined that the read second logical mapping information is erroneous, reading all data pages within the address range of the data block where the logical data corresponding to the recorded first logical mapping information is located; The first logical mapping information corresponding to each written logical data and the writing sequence of each logical data are obtained from the OOB area of ​​the read data page, and the erroneous second logical mapping information is reconstructed.

6. The method for updating a logical mapping table of a storage device according to claim 3, wherein: The performing table updating processing according to the sorted second logical mapping information to update the corresponding first logical mapping table to obtain the second logical mapping table includes: Obtaining mapping numbers of all first logical mapping tables corresponding to the sorted second logical mapping information; In response to a read cache command, asynchronously read the first logical mapping table indicated by the mapping number from the flash memory unit and cache it in a temporarily applied memory unit; When a first logical mapping table is read successfully, in the temporarily applied memory unit, the first logical mapping table currently hit is updated according to multiple adjacent second logical mapping information that hit the same first logical mapping table to obtain a corresponding second logical mapping table; After the currently hit first logical mapping table is updated, the next first logical mapping table is updated in response to the next read cache command until all the second logical mapping information is updated to the corresponding first logical mapping tables, thereby obtaining all the corresponding second logical mapping tables.

7. The method for updating a logical mapping table of a storage device according to claim 6, wherein: After obtaining the second logical mapping table, the method further includes: Receive a write cache command; In response to the write cache command, each time a second logical mapping table is obtained, the second logical mapping table updated in the temporarily applied memory unit is written into the flash memory unit.

8. A controller, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the logical mapping table updating method of the storage device according to any one of claims 1 to 7.

9. An electronic device, characterized in that: Comprising the controller as claimed in claim 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for updating a logical mapping table of a storage device according to any one of claims 1 to 7.

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