A memory access system based on vertically extended networking

Abstract

The present invention relates to the field of computer technology, and in particular to a memory access system based on vertical expansion networking, including an address register group, a switch, M chips {A1, A2,.., A m ,..., A M}, M adapters {B1, B2,.., B m ,..., B M}, M network cards {C1, C2,..., C m ,..., C M}, where the switch includes M interfaces, A m is the mth chip, the value range of m is from 1 to M, M is the total number of chips, B m is the adapter corresponding to A m , C m is the network card corresponding to A m , A m , B m , C m are connected in sequence, each B m is connected to the address register group, and C m is connected to the mth interface of the switch. The present invention improves the memory access efficiency and flexibility based on vertical expansion networking, and enhances the system resource utilization rate.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to a memory access system based on vertical expansion networking. Background Art

[0002] In traditional network communication, data needs to go through multiple copies and protocol stack processing, which introduces significant latency and CPU (Central Processing Unit) overhead. In memory semantics-based interconnection systems, the current solutions mainly include two methods: Method 1, a method of scale-out remote direct memory access (RDMA) networking; Method 2, a method of optimizing with a software stack. Using RDMA technology, data can be directly transferred from the application buffer of one node to the application buffer of another node without the intervention of the operating system kernel or CPU, greatly reducing latency and improving bandwidth efficiency. However, for scale-up networking, the disadvantages of Method 1 are: the RDMA protocol is highly complex and difficult to implement. It not only requires the implementation of complex hardware designs for the RDMA protocol but also incurs additional software development and integration debugging work, greatly increasing the project's time cost and resource consumption. The disadvantages of Method 2 are: there are additional requirements for software and the system side, the complexity of the software and the system side is high, latency is increased, and it has an adverse impact on the overall system performance, which is more obvious especially in application scenarios with high bandwidth and low latency requirements. Therefore, how to improve the memory access efficiency and flexibility based on vertical expansion networking and enhance the system resource utilization has become a technical problem to be solved urgently. Summary of the Invention

[0003] The purpose of the present invention is to provide a memory access system based on vertical expansion networking, which improves the memory access efficiency and flexibility based on vertical expansion networking and enhances the system resource utilization.

[0004] The present invention provides a memory access system based on vertical expansion networking, including an address register group, a switch, M chips {A1, A2,.., A m ,..., A M}, M adapters {B1, B2,.., B m ,..., B M}, and M network cards {C1, C2,..., C m ,..., C M}, where the switch includes M interfaces, A m is the m-th chip, the value range of m is from 1 to M, M is the total number of chips, B m is the adapter corresponding to A m , C m is Am The corresponding network card, A m , B m , C m are connected in sequence. Each B m is connected to the address register group. C m is connected to the m-th interface of the switch;

[0005] The address register group is used to pre-configure the mapping relationship between the C m corresponding to each A m and the MAC address D m ;

[0006] The first A m is used to send a target access request to the first B m . The target access request includes the address of the first A m , the address of the second A m and the access data;

[0007] The first B m is used to determine the first D m corresponding to the address of the first A m and the second D m corresponding to the address of the second A m based on the mapping relationship between each A m in the address register group and D m . Then add the first D m to the source MAC frame, add the second D m to the target MAC frame, generate the first MAC packet set based on the source MAC frame, the target MAC frame and the access data, and send the first MAC packet set to the switch through the first C m ;

[0008] The switch is used to send the first MAC packet set to the second B m through the second C m ;

[0009] The second B m is used to parse the first MAC packet set, obtain the first D m , the second D m and the access data, determine the address of the first A m corresponding to the first D m and the address of the second A m corresponding to the corresponding second D m based on the mapping relationship between each A m in the address register group and D m , and send the address of the first A m , the address of the second A m and the access data to the second A m for memory access.

[0010] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, a memory access system based on vertical expansion networking provided by the present invention can achieve quite remarkable technological progressiveness and practicality, and has wide industrial utilization value. It has at least the following beneficial effects:

[0011] In the system of the present invention, the configuration of the address mapping relationship in the address register group is only implemented based on software, and the rest are implemented based on hardware, which reduces latency and improves system performance. In addition, the system of the present invention can achieve the addressing of the switch only through a simple protocol, without the need to implement complex protocols and software scheduling, with shorter access time and faster switching. The system of the present invention improves the memory access efficiency and flexibility based on vertical expansion networking, and improves the utilization rate of system resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0013] Figure 1 Schematic diagram of a memory access system based on vertical expansion networking provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0015] An embodiment of the present invention provides a memory access system based on vertical expansion networking, as Figure 1 shown, including an address register group, a switch, M chips {A1, A2,.., A m ,..., A M}, M adapters {B1, B2,.., B m ,..., B M}, M network cards {C1, C2,..., C m ,..., C M}, where the switch includes M interfaces, A m is the mth chip, the value range of m is from 1 to M, M is the total number of chips, B mFor A m The corresponding adapter, C m For A m The corresponding network card, A m , B m , C m Connect in sequence. Each B m is connected to the address register bank. C m is connected to the m-th interface of the switch. It should be noted that each chip is provided with a corresponding adapter and a corresponding network card, and the switch can recognize the MAC (Media Access Control Address) address of each network card.

[0016] As an embodiment, A1, A2,.., A m ,..., A M are set in the data bus layer, B1, B2,.., B m ,..., B M and the address register bank are set in the adapter layer. Each B m can access the address register bank. A m and B m are interconnected through a preset data bus.

[0017] The address register bank is used to pre-configure the mapping relationship of the MAC address D m corresponding to each A m . Each adapter obtains the mapping relationship of the MAC address D m corresponding to each A m by accessing the address register bank. m The mapping relationship of the MAC address D m .

[0018] The first A m is used to send a target access request to the first B m . The target access request includes the address of the first A m , the address of the second A m and the access data. It should be noted that the first A m is the source A m . The B m corresponding to the first A m is the first B m . The C m corresponding to the first A m is the first C m . The D m corresponding to the first A m is the first D m . The second A m is the target A m . The B m corresponding to the second Am For the second B m , Second A m Corresponding C m For the second C m , Second A m The corresponding D m For the second D m .

[0019] First B m For each A in the address register group m With D m The mapping relationship determines the first A m The first D corresponding to the address m and the second A m The second D corresponding to the address m , and the first D m Add the source MAC frame and add the second D m Add the target MAC frame. It should be noted that the source MAC frame and the target MAC frame are pre-specified MAC frames, and the source MAC frame and the source MAC frame can be located at the corresponding position of the sideband signal of the preset data bus. They can also be located at other unused specified positions of the preset data bus. The preset data bus can specifically be an AMBA (Advanced Microcontroller Bus Architecture) bus. More specifically, it can also be an AXI (Advanced eXtensible Interface) bus in the AMBA bus.

[0020] First B m Generate a first MAC group packet based on the source MAC frame, the target MAC frame and the access data, and pass it through the first C m The first MAC group packet is sent to the switch.

[0021] The switch is used to transmit the first MAC group packet through the second C m Send to Second B m The switch can directly identify the MAC addresses of all network cards. Since the first MAC group packet contains the source MAC frame and the target MAC frame, the switch can quickly and accurately address the first MAC group packet through the second C m Send to Second B m .

[0022] Second B m Used to parse the first MAC group packet and obtain the first D m , Second D m and access data based on each A in the address register set m With D mThe mapping relationship determines the first D m The corresponding first A m Address and the corresponding second D m The second A m Address, send the first A m Address, the second A m Address and the access data to the second A m For memory access.

[0023] It should be noted that the first A m Specifically, it can be a proximal chip, and the second A m Specifically, it can be a distal chip. The system of the present invention realizes a memory semantic addressing mechanism for multi-card vertical expansion networking of a switch, can simply access the address of the distal chip, and realizes direct access to the memory of the distal chip without implementing complex protocols. Compared with the traditional RDMA solution, the present invention does not need to implement complex protocol processes, has shorter required latency, faster address switching, and the access process is similar to accessing the local chip, significantly improving the utilization rate of system resources and communication efficiency.

[0024] The system of the present invention only configures the address mapping relationship in the address register group based on software, and the rest are implemented based on hardware, reducing latency and improving system performance. In addition, the system of the present invention can realize the addressing of the switch only through a simple protocol, without implementing complex protocols and software scheduling, with shorter access time and faster switching. The system of the present invention improves the memory access efficiency and flexibility based on vertical expansion networking, and improves the utilization rate of system resources.

[0025] When the second A m Completes the memory access, it can also send a reply message to the first A m Based on the system of the present invention. As an embodiment, the second B m Is also used to store the mapping result of the first D m And the first A m Address and the mapping result of the second D m And the second A m In the second B m By storing the mapping result of the first D m And the first A m Address and the mapping result of the second D m And the second A m In the second B m It is convenient for the second A m To send a reply message to the first A m For use.

[0026] The second A mFor generating a reply message to be sent to the second B after completing a memory access m ; The second B m For adding the first D m to the destination MAC frame, adding the second D m to the source MAC frame, generating a second MAC packet based on the source MAC frame, the destination MAC frame, and the reply message, and sending the second MAC packet to the switch through the second C m ; Deleting the mapping results of the first D m and the first A m addresses, and the mapping results of the second D m and the second A m from the second B m . The switch is used to send the second MAC packet to the first B m through the first C m . The first B m is used to parse the second MAC packet, obtain the first D m , the second D m , and the reply message, determine the first A m address corresponding to the first D m and the second A m address corresponding to the corresponding second D m based on the mapping relationship between each A m in the address register group and the D m , and send the first A m address, the second A m address, and the reply message to the first A m .

[0027] As an embodiment, the address register group includes {E1, E2,..., E m ,..., E M}, where E m is the mth group of registers for storing the mapping relationship between the corresponding A m and the corresponding D m . Each E m includes at least one register. That is, each register group stores a set of mapping relationships between an A m and the corresponding D m , achieving unified addressing of M chips. It should be noted that the number of address registers in each E m is set based on the bit width of the address register and the bit width of the MAC address. For example, if the bit width of the address register is 32bit and the bit width of the MAC address is 48bit, then each E mIt includes two address registers. The configuration process of the address register group can be specifically executed in the system stage or in the quasi-static stage. The quasi-static stage refers to the stage when the system is in the running stage, but none of the M chips are communicating with each other.

[0028] As an embodiment, A m and B m The preset data bus between them includes N data channels {F1, F2,..., F n ,..., F N}. Taking the AXI bus as an example, N = 5. F n is the nth data channel, where n ranges from 1 to N, and N is the number of data channels included in the preset data bus. A m sends a target access request G n to B m through F n . It should be noted that the N data channels are independent of each other. The first A m can send an access request to each F n The first B m . The access requests sent by different F n corresponding to the second B m may be the same or different. However, the first B m can only process one second B m possible access request at a time.

[0029] As an embodiment, the first B m selects an access request of one channel as the target access request for sending according to the priorities of the N data channels. In this example, it is necessary to preset the priorities of the N data channels, and the priorities of the N data channels are set according to specific application requirements.

[0030] As an embodiment, the first B m selects an access request of one channel as the target access request for sending by polling the N data channels. In this example, the described method can make the resource utilization of the N data channels as balanced as possible.

[0031] As an embodiment, the first B m obtains the second A m address corresponding to each data channel, and selects an access request corresponding to one second A m as the target access request for sending according to the priority corresponding to the second A m . In this example, the priority corresponding to the second A m is set according to specific application requirements.

[0032] As an embodiment, the first B m employs A m to select a second A m corresponding access request in a polling manner as the target access request for sending. It should be noted that a balanced polling manner can be specifically adopted to select a second A m corresponding access request as the target access request, or different ratios can be set for polling according to specific application requirements to achieve flexible configuration. In this example, there may be multiple selected access requests sent by different data channels. If there are multiple target access requests, the access data corresponding to the multiple target access requests is packetized. Since the destination A m is the same, the packetized data can be sent to the corresponding second A m together after packetization. m .

[0033] In view of the limitations existing in memory conversion in existing multi-card networking, the present invention proposes a memory semantic addressing mechanism for vertical expansion networking of multi-cards in a switch. By adding an address register group, using an expansion strategy for sideband signals, and combining a bus sideband signal access mechanism, efficient and flexible access to the memory of a remote chip is achieved. This mechanism can be compatible with the AMBA protocol specification, significantly expands and enhances the system bus, and reduces the implementation complexity by minimizing the system modification requirements. The system of the present invention can also utilize sideband signals. Compared with the traditional RDMA-based solution, it does not need to implement complex protocols and software scheduling, has a shorter access time, faster switching, and an access process similar to accessing the memory of the local chip, greatly improving the flexibility and efficiency of inter-system communication and promoting the optimal configuration and efficient utilization of system resources.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0035] The above are only the preferred embodiments of the present invention and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to form equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as the content does not depart from the technical solution of the present invention, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A memory access system based on vertically extended networking, characterized in that including an address register bank, a switch, M chips {A1, A2,.., A m ,..., A M}, M adapters {B1, B2,.., B m ,..., B M}, M network cards {C1, C2,..., C m ,..., C M}, where , the switch includes M interfaces, A m is the m-th chip, where m ranges from 1 to M, and M is the total number of chips, B m is the adapter corresponding to A m , C m is the network card corresponding to A m , A m , B m , C m are connected in sequence, and each B m is connected to the address register group, and C m is connected to the m-th interface of the switch; The address register group is used to pre-configure each A m corresponding C m MAC address D m mapping relationship; First A m For sending a target access request to the first B m The target access request includes the first A m address, the second A m address and access data; First B m For each A in the address register group m and D m to determine the first A based on the mapping relationship m The first D corresponding to the address m and the second A m The second D corresponding to the address m , add the first D m to the source MAC frame, add the second D m to the destination MAC frame, generate a first MAC packet group based on the source MAC frame, the destination MAC frame, and the access data, and send the first MAC packet group to the switch through the first C m ; The switch is used to send the first MAC packet group through the second C m to the second B m ; Second B m Used to parse the first MAC group packet and obtain the first D m , Second D m and access data based on each A in the address register set m With D m The mapping relationship determines the first D m The corresponding first A m Address and corresponding second D m Second A m Address, the first A m Address, Second A m The address and access data are sent to the second A m Perform memory access.

2. The system according to claim 1, characterized in that The second B m is also used to map the first D m and the first A m and store the mapping results of the addresses, as well as the second D m and the second A m in the second B m ; Second A m For generating a reply message to be sent to Second B after completing a memory access m ; The second B m For adding the first D m to the destination MAC frame, adding the second D m to the source MAC frame, generating a second MAC packet assembly based on the source MAC frame, the destination MAC frame and the reply information, and sending the second MAC packet assembly to the switch through the second C m deleting the mapping result of the first D m and the first A m and the mapping result of the second D m and the second A m from the second B m ; The switch is used for the second MAC packet assembly to pass through the first C m and send it to the first B m ; First B m For parsing the second MAC packet to obtain the first D m , the second D m and the reply information, based on each A in the address register group m and D m to determine the first D m corresponding first A m address and the corresponding second D m second A m address, and send the first A m address, the second A m address and the reply information to the first A m .

3. The system according to claim 1, characterized in that A1, A2,.., A m ,..., A M are set in the data bus layer, B1, B2,.., B m ,..., B M and the address register group is set in the adaptation layer, and each B m can access the address register group.

4. The system according to claim 1, characterized in that The address register group includes {E1, E2,..., E m ,..., E M}, where Em m is the m-th group of registers for storing the mapping relationship between the corresponding A m and the corresponding D m . Each Em m includes at least one register.

5. The system according to claim 1, characterized in that A m and B m are interconnected through a preset data bus, and the source MAC frame and the source MAC frame are located at corresponding positions of the sideband signals of the preset data bus.

6. The system according to claim 5, characterized in that The preset data bus is an AMBA bus.

7. The system according to claim 1, characterized in that A m and B m The preset data bus includes N data channels {F1, F2, ..., F n ,...,F N },F n is the nth data channel, the value range of n is 1 to N, N is the number of data channels contained in the preset data bus, A m By F n To B m Send target access request G n .

8. The system according to claim 7, characterized in that The first B m Select an access request of one channel as the target access request for transmission according to the priorities of N data channels or in a polling manner for the N data channels.

9. The system according to claim 7, characterized in that The first B m Obtain the second A corresponding to each data channel m address, and according to the second A m corresponding priority or use A m in a polling manner to select a second A m corresponding access request as the target access request for sending.

10. The system according to claim 9, characterized in that If there are multiple target access requests, the access data corresponding to the multiple target access requests is packetized.

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