Data transmission method and device based on DMA controller, equipment and medium

Abstract

The invention discloses a data transmission method, device and equipment based on a DMA controller and a medium, relates to the technical field of computer hardware and is applied to the DMA controller comprising a first host and a second host, and the first host and the second host are connected with a first AXI bus and a second AXI bus respectively. The method comprises the following steps: receiving configuration information issued by a processor, and generating a bus control request corresponding to the configuration information; the bus control request is sent to the processor, so that the processor distributes the control right of the first AXI bus and the control right of the second AXI bus to the first host and the second host respectively; and controlling the first host to read data in a data source end to the local through the first AXI bus, and controlling the second host to write the local data into a target end through the second AXI bus. According to the scheme, the data transmission performance of the DMA controller is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of computer hardware, and in particular to a data transmission method, device, equipment and medium based on a DMA controller. Background Art

[0002] DMA (Direct Memory Access Control) controller is a hardware circuit used to realize large-scale data transmission between two devices in the system. It is a data exchange mode that directly accesses data from the memory without going through the CPU (Central Processing Unit). In normal mode, the data exchange work will be completed by the CPU. During the data transmission process, the CPU cannot handle other tasks. Therefore, in order to improve the CPU work efficiency, the DMA controller is used to replace the CPU to complete the data exchange work. In DMA mode, the CPU only needs to issue instructions to the DMA controller and let the DMA controller handle the data transmission, which greatly reduces the CPU resource occupancy rate, greatly saves system resources, and improves the efficiency of data transmission.

[0003] With the development of VLSI design technology, DMA controller, as an important component of SoC system (System on Chip, a microchip that integrates all necessary components of a computer or other electronic system into a single chip), has become more and more integrated. It is particularly important to improve the data transmission performance of DMA controller.

[0004] From the above, it can be seen that how to improve the data transmission performance of the DMA controller is a problem to be solved in the art. Summary of the invention

[0005] In view of this, the object of the present invention is to provide a data transmission method, device, equipment and medium based on a DMA controller to improve the data transmission performance of the DMA controller. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses a data transmission method based on a DMA controller, which is applied to a DMA controller including a first host and a second host, wherein the first host and the second host are respectively connected to a first AXI bus and a second AXI bus; wherein the method comprises:

[0007] receiving configuration information sent by the processor, and generating a bus control request corresponding to the configuration information;

[0008] Sending the bus control request to the processor so that the processor allocates control rights of the first AXI bus and the second AXI bus to the first host and the second host respectively;

[0009] The first host is controlled to read data from the data source end to the local end through the first AXI bus, and the second host is controlled to write the local data to the target end through the second AXI bus.

[0010] Optionally, the DMA controller includes first-in-first-out cache queues;

[0011] The controlling the first host to read the data from the data source to the local through the first AXI bus includes:

[0012] Control the first host to read target read data corresponding to the current transaction to be read from the data source end through the first AXI bus, and save the target read data to a first target cache queue corresponding to the first identification information of the current transaction to be read, so as to complete the current transaction to be read;

[0013] Correspondingly, controlling the second host to write local data to the target end through the second AXI bus includes:

[0014] Determine from each of the cache queues a second target cache queue corresponding to the second identification information of the current transaction to be written, and control the second host to write the target write data of the second target cache queue to the target end through the second AXI bus to complete the current transaction to be written; wherein the first identification information is the same as or different from the second identification information.

[0015] Optionally, the DMA controller includes an interrupt controller;

[0016] The data transmission method based on the DMA controller also includes:

[0017] If it is detected that there is a first target data transmission transaction that meets a preset successful execution condition among the data transmission transactions of the DMA controller, the interrupt controller is triggered to generate a successful transmission interrupt signal, and the successful transmission interrupt signal is sent to the processor, so that the processor releases the control right of the first AXI bus and / or the second AXI bus;

[0018] If it is detected that there is a second target data transmission transaction that meets the preset error execution condition among the data transmission transactions of the DMA controller, the interrupt controller is triggered to generate a transmission failure interrupt signal, and the transmission failure interrupt signal is sent to the processor so that the processor can process the second target data transmission transaction.

[0019] Optionally, the DMA controller includes a request manager;

[0020] Before receiving the configuration information sent by the processor, the method further includes:

[0021] Receiving a transmission request corresponding to a current data transmission transaction sent by the data source end and the target end;

[0022] Accordingly, the data transmission method based on the DMA controller further includes:

[0023] If the data source and the target are external devices, when the first host and the second host respond to the transmission request, the request manager is controlled to send a request clear signal corresponding to the transmission request to the data source and the target;

[0024] If the data source and the target are not external devices, the request manager is controlled to set the transmission request to a high level until the first host and the second host complete the current data transmission transaction corresponding to the current transmission request.

[0025] Optionally, the DMA controller includes a handshake manager;

[0026] After controlling the request manager to send a request clear signal corresponding to the transmission request to the data source end and the target end, the method further includes:

[0027] Control the handshake manager to send a request confirmation signal to the data source and the target end, so that the data source and the target end determine whether to clear the transmission request based on the request confirmation signal, and if the transmission request has been cleared, generate a clear success signal;

[0028] Receive clear success signals sent by the data source and the target end, and when the current data transmission transaction meets the preset successful execution condition, jump to the step of triggering the interrupt controller to generate a transmission success interrupt signal.

[0029] Optionally, the DMA controller includes an arbitrator, the first host includes various read channels, and the second host includes various write channels;

[0030] The controlling the first host to read the data from the data source end to the local end through the first AXI bus, and controlling the second host to write the local data to the target end through the second AXI bus, comprises:

[0031] Determine a target read channel and a target write channel by using the arbitrator based on the priorities of the read channels and the priorities of the write channels, and send the address of the target read channel and the address of the target write channel to the first host and the second host respectively;

[0032] The first host is controlled to read the data in the data source end to the local end through the target read channel and the first AXI bus based on the address of the target read channel, and the second host is controlled to write the local data to the target end through the target write channel and the second AXI bus based on the address of the target write channel.

[0033] Optionally, the DMA controller includes a slave component;

[0034] The receiving processor sends the configuration information, including:

[0035] The configuration information sent by the processor is received through the slave component, and the configuration information is saved in the register module; wherein the register module includes a data source address register, a target address register, an interrupt register, and a transmission transaction register.

[0036] In a second aspect, the present application discloses a data transmission device based on a DMA controller, which is applied to a DMA controller including a first host and a second host, wherein the first host and the second host are connected to a first AXI bus and a second AXI bus respectively; wherein the device includes:

[0037] A request generation module, used to receive configuration information sent by the processor and generate a bus control request corresponding to the configuration information;

[0038] a control right acquisition module, used for sending the bus control request to the processor, so that the processor allocates the control rights of the first AXI bus and the second AXI bus to the first host and the second host respectively;

[0039] The data transmission module is used to control the first host to read the data in the data source end to the local end through the first AXI bus, and control the second host to write the local data to the target end through the second AXI bus.

[0040] In a third aspect, the present application discloses an electronic device, comprising:

[0041] Memory, used to store computer programs;

[0042] The processor is used to execute the computer program to implement the steps of the aforementioned disclosed data transmission method based on the DMA controller.

[0043] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned disclosed data transmission method based on a DMA controller are implemented.

[0044] The beneficial effects of the present application are as follows: the present application is applied to a DMA controller including a first host and a second host, wherein the first host and the second host are respectively connected to a first AXI bus and a second AXI bus; wherein the method comprises: receiving configuration information sent by a processor, and generating a bus control request corresponding to the configuration information; sending the bus control request to the processor so that the processor allocates control rights of the first AXI bus and the second AXI bus to the first host and the second host respectively; controlling the first host to read data from a data source end to a local end through the first AXI bus, and controlling the second host to write local data to a target end through the second AXI bus. It can be seen that the DMA controller of the present application includes a first host and a second host, and the first host is connected to the first AXI bus, and the second host is connected to the second AXI bus, that is, the present application is a multi-layer AXI host structure. In this way, when the first host and the second host of the DMA controller respectively obtain control of the first AXI bus and the second AXI bus, the first host is controlled to read the data in the data source end to the local through the first AXI bus, and the second host is controlled to write the local data to the target end through the second AXI bus. The pipeline operation of the multi-layer AXI host allows data to be executed continuously, fully utilizing system resources and improving the parallelism and performance of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0046] Figure 1 A flow chart of a data transmission method based on a DMA controller disclosed in this application;

[0047] Figure 2 A specific DMA controller schematic diagram disclosed in this application;

[0048] Figure 3 This is a structural schematic diagram of a data transmission device based on a DMA controller disclosed in this application;

[0049] Figure 4 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0051] DMA controller is a hardware circuit used to realize large-scale data transmission between two devices in the system. It is a data exchange mode that directly accesses data from the memory without going through the CPU. In normal mode, the data exchange work will be completed by the CPU. During the completion of this data transmission process, the CPU cannot handle other tasks. Therefore, in order to improve the CPU work efficiency, the DMA controller is used to replace the CPU to complete the data exchange work. In DMA mode, the CPU only needs to issue instructions to the DMA controller and let the DMA controller handle the data transmission, which greatly reduces the CPU resource occupancy rate, greatly saves system resources, and improves the efficiency of data transmission.

[0052] With the development of VLSI design technology, DMA controller, as an important component of SoC system, has become more and more integrated. It is particularly important to improve the data transmission performance of DMA controller.

[0053] To this end, the present application accordingly provides a data transmission solution based on a DMA controller to improve the data transmission performance of the DMA controller.

[0054] See also Figure 1 As shown, an embodiment of the present application discloses a data transmission method based on a DMA controller, which is applied to a DMA controller including a first host and a second host, wherein the first host and the second host are respectively connected to a first AXI bus and a second AXI bus; wherein the method includes:

[0055] Step S11: receiving configuration information sent by the processor, and generating a bus control request corresponding to the configuration information.

[0056] In this embodiment, the DMA controller includes a request manager; before receiving the configuration information sent by the processor, it also includes: receiving a transfer request corresponding to the current data transfer transaction sent by the data source and the target. The DMA controller includes a request manager, which can be used to receive a transfer request corresponding to the current data transfer transaction sent by the data source and the target. The current data transfer transaction includes a data read transaction that needs to be completed by the first host and a data write transaction that needs to be completed by the second host. The data read transaction means that the first host needs to complete reading data from the data source, and the data write transaction means that the second host needs to complete reading data from the locally stored data and writing the data to the target. The transfer request can trigger the DMA controller to start executing the current data transfer transaction.

[0057] In this embodiment, the DMA controller includes a slave component; the receiving configuration information sent by the processor includes: receiving the configuration information sent by the processor through the slave component, and saving the configuration information in the register module; wherein the register module includes a data source address register, a target address register, an interrupt register, and a transfer transaction register. When the DMA controller performs data transmission, it needs to complete the relevant configuration. When the relevant configuration is completed, the DMA controller acts as a slave, that is, the DMA controller acts as a slave to receive the configuration information from the processor through the slave interface. The processor may be a CPU (Central Processing Unit). Before the data starts to be transmitted, preprocessing is performed, and the information configured by the CPU to the DMA controller is addressed to the relevant configuration registers inside the DMA module through the address bus of the AXI bus, and then this information is configured to the register block in the DMA controller through the slave interface. The register module includes the data source address register, the target address register, the interrupt register, the transmission transaction register, and can also include the control register. The register module includes multiple important data registers to assist the DMA controller in completing the entire data transmission task, from the DMA controller as a slave to receive the configuration information from the CPU through the slave interface, to the DMA controller as a host, reading the relevant data of the source and target transmission tasks. The register group stores a lot of configuration information needed by the DMA controller.

[0058] After receiving the configuration information sent by the processor, a bus control request corresponding to the configuration information is generated, where the bus control request is used to indicate that the first host and the second host need to obtain the control right of the first AXI bus and the second AXI bus.

[0059] Step S12: Sending the bus control request to the processor so that the processor allocates the control rights of the first AXI bus and the second AXI bus to the first host and the second host respectively.

[0060] A bus control request is sent to the processor, and the processor distributes the control rights of the first AXI (Advanced eXtensible Interface) bus and the second AXI bus to the first host and the second host respectively. In this way, the first host and the second host can take over the first AXI bus and the second AXI bus respectively, that is, data is transmitted through the first AXI bus and the second AXI bus.

[0061] Step S13: Control the first host to read the data in the data source end to the local end through the first AXI bus, and control the second host to write the local data to the target end through the second AXI bus.

[0062] It should be noted that data transfer transactions are divided into transactions to be read and transactions to be written, and the identification information of the transactions to be read and the transactions to be written under the same data transfer transaction is the same, that is, the identification information of the transactions to be read and the transactions to be written under the same data transfer transaction is the same as the identification information of the data transfer transaction to which they belong. The first host and the second host can read and write data respectively at the same time, that is, in the process of controlling the first host to read data from the data source end to the local end through the first AXI bus, the second host can also be controlled to write local data to the target end through the second AXI bus.

[0063] In this embodiment, the DMA controller includes first-in-first-out cache queues; the control of the first host to read the data in the data source end to the local through the first AXI bus includes: controlling the first host to read the target read data corresponding to the current transaction to be read in the data source end through the first AXI bus, and saving the target read data to the first target cache queue corresponding to the first identification information of the current transaction to be read, so as to complete the current transaction to be read.

[0064] The cache queue is a temporary data storage unit. During the source-end transmission phase of data, the source-end control module writes the data read from the source device into the cache queue through the first AXI bus. That is to say, the first host is controlled to read the target read data corresponding to the current transaction to be read from the data source through the first AXI bus, and saves the target read data into the first target cache queue corresponding to the first identification information of the current transaction to be read, so as to complete the current transaction to be read.

[0065] In this embodiment, controlling the second host to write local data to the target end through the second AXI bus includes: determining the second target cache queue corresponding to the second identification information of the current transaction to be written from each of the cache queues, and controlling the second host to write the target write data of the second target cache queue to the target end through the second AXI bus to complete the current transaction to be written; wherein the first identification information is the same as or different from the second identification information.

[0066] A second target cache queue corresponding to the second identification information of the current transaction to be written is determined from each of the cache queues, wherein the current transaction to be written can be determined according to the situation of each transaction to be written, such as the size of each transaction, and then the corresponding second target cache queue is determined according to the second identification information of the current transaction to be written, and the second host is controlled to read the target write data from the second target cache queue and write it to the target end through the second AXI bus, thereby completing the current transaction to be written.

[0067] It should be noted that, in the present embodiment, the first host and the second host are used for reading data and writing data, respectively, that is, data reading and data writing are separated, and the FIFO buffer enables the DMA controller to separate the read and write operations, effectively handle the data transmission problems between different clock domains, and improve the overall data transmission efficiency, and the AXI bus supports out-of-order transmission, therefore, the current transaction to be read and the current transaction to be written of the first host may not belong to the same data transmission transaction, that is, the first identification information may be the same as or different from the second identification information.

[0068] In this embodiment, the DMA controller includes an interrupt controller; this embodiment also includes: if it is detected that there is a first target data transmission transaction that meets a preset successful execution condition among the data transmission transactions of the DMA controller, the interrupt controller is triggered to generate a transmission success interrupt signal, and the transmission success interrupt signal is sent to the processor, so that the processor releases the control of the first AXI bus and / or the second AXI bus; if it is detected that there is a second target data transmission transaction that meets a preset error execution condition among the data transmission transactions of the DMA controller, the interrupt controller is triggered to generate a transmission failure interrupt signal, and the transmission failure interrupt signal is sent to the processor, so that the processor processes the second target data transmission transaction. The DMA controller includes an interrupt controller, which is a module for generating a corresponding interrupt signal. The interrupt controller generates an interrupt signal by judging the current transmission state and sends it to the CPU. The CPU performs the next operation according to the state of the DMA controller, thereby improving the overall performance of the system. The interrupt controller generates a register configuration error signal, a transmission error interrupt and a transmission completion interrupt signal according to the configuration process of the DMA controller. That is, the interrupt controller can detect whether the data transmission transaction is successful. If it is detected that there is a first target data transmission transaction that meets the preset successful execution condition in each data transmission transaction of the DMA controller, the interrupt controller is triggered to generate a transmission success interrupt signal, and the transmission success interrupt signal is sent to the processor, so that the processor releases the control right of the first AXI bus and / or the second AXI bus, that is, when there is a data transmission transaction with successful transmission, the transmission success interrupt signal is sent to the processor; if it is detected that there is a second target data transmission transaction that meets the preset error execution condition in each data transmission transaction of the DMA controller, the interrupt controller is triggered to generate a transmission failure interrupt signal, and the transmission failure interrupt signal is sent to the processor, so that the processor processes the second target data transmission transaction, that is, when there is a data transmission transaction with failed transmission, the transmission failure interrupt signal is sent to the processor.

[0069] In this embodiment, it also includes: if the data source and the target are external devices, when the first host and the second host respond to the transfer request, the request manager is controlled to send a request clear signal corresponding to the transfer request to the data source and the target; if the data source and the target are not external devices, the request manager is controlled to set the transfer request to a high level until the first host and the second host complete the current data transfer transaction corresponding to the current transfer request. It can be understood that the data source and the target can be external devices or not. When the data source and the target are external devices, when the first host and the second host respond to the transfer request, the request manager is controlled to send a request clear signal corresponding to the transfer request to the data source and the target, that is, the corresponding transfer request is cleared to avoid the first host and the second host from responding to the same transfer request multiple times; if the data source and the target are not external devices, for example, the data source and the target are memories, the request manager is controlled to set the transfer request to a high level until the first host and the second host complete the current data transfer transaction corresponding to the current transfer request, that is, the signal corresponding to the transfer request is directly set to 1, and the data source and the target always send DMA transfer requests by default.

[0070] In this embodiment, the DMA controller includes a handshake manager; after controlling the request manager to send a request clear signal corresponding to the transfer request to the data source and the target end, it also includes: controlling the handshake manager to send a request confirmation signal to the data source and the target end, so that the data source and the target end determine whether to clear the transfer request based on the request confirmation signal, and if the transfer request has been cleared, a clear success signal is generated; receiving the clear success signal sent by the data source and the target end, and when the current data transmission transaction meets the preset successful execution condition, jumping to the step of triggering the interrupt controller to generate a transfer success interrupt signal. In order to ensure that the data source and the target end clear the corresponding transfer request after receiving the request clear signal, the DMA controller also includes a handshake manager. After sending the request clear signal, the handshake manager is controlled to send a request confirmation signal to the data source and the target end, so that the data source and the target end can determine whether to clear the transfer request based on the request confirmation signal, that is, if the data source and the target end have cleared the transfer request, a clear success signal is generated, the clear success signal sent by the data source and the target end is received, and when the current data transmission transaction meets the preset successful execution conditions, the step of triggering the interrupt controller to generate a transfer success interrupt signal is jumped to. It can be understood that if the data source and the target end have not cleared the transfer request, a clear failure signal is generated, and the request manager is triggered to send a request clear signal corresponding to the transfer request to the data source and the target end.

[0071] In this embodiment, the DMA controller includes an arbitrator, the first host includes each read channel, and the second host includes each write channel; the controlling the first host to read the data in the data source end to the local end through the first AXI bus, and controlling the second host to write the local data to the target end through the second AXI bus, includes: using the arbitrator to determine the target read channel and the target write channel based on the priority of each read channel and the priority of each write channel, and sending the address of the target read channel and the address of the target write channel to the first host and the second host respectively; controlling the first host to read the data in the data source end to the local end through the target read channel and the first AXI bus based on the address of the target read channel, and controlling the second host to write the local data to the target end through the target write channel and the second AXI bus based on the address of the target write channel. Since the DMA controller only allows one channel to perform data transmission at a time, a priority arbitration algorithm is adopted, and channel 0 is set to the highest priority and channel n is the lowest priority (n>1). When a channel is allowed, the arbitrator outputs the address and control information of the channel. If there are multiple channels performing data transmission at the same time, the arbitrator will give priority to allowing the high-priority channel to transmit data. Specifically, the first host includes various read channels, and the second host includes various write channels; in the process of reading and writing data, it is necessary to use an arbitrator to determine the target read channel and the target write channel based on the priority of each read channel and the priority of each write channel, and send the address of the target read channel and the address of the target write channel to the first host and the second host respectively; control the first host to read the data in the data source end to the local through the target read channel and the first AXI bus based on the address of the target read channel, and control the second host to write the local data to the target end through the target write channel and the second AXI bus based on the address of the target write channel.

[0072] The beneficial effects of the present application are as follows: the present application is applied to a DMA controller including a first host and a second host, wherein the first host and the second host are respectively connected to a first AXI bus and a second AXI bus; wherein the method comprises: receiving configuration information sent by a processor, and generating a bus control request corresponding to the configuration information; sending the bus control request to the processor so that the processor allocates control rights of the first AXI bus and the second AXI bus to the first host and the second host respectively; controlling the first host to read data from a data source end to a local end through the first AXI bus, and controlling the second host to write local data to a target end through the second AXI bus. It can be seen that the DMA controller of the present application includes a first host and a second host, and the first host is connected to the first AXI bus, and the second host is connected to the second AXI bus, that is, the present application is a multi-layer AXI host structure. In this way, when the first host and the second host of the DMA controller respectively obtain control of the first AXI bus and the second AXI bus, the first host is controlled to read the data in the data source end to the local through the first AXI bus, and the second host is controlled to write the local data to the target end through the second AXI bus. The pipeline operation of the multi-layer AXI host allows data to be executed continuously, fully utilizing system resources and improving the parallelism and performance of data transmission.

[0073] Below Figure 2 Taking a specific DMA controller schematic diagram as an example, the present application is described accordingly. The DMA controller consists of a host module, a slave module, a channel module, a handshake manager, an interrupt controller, an arbiter, a request manager, and a low-power module. The specific functions are as follows:

[0074] 1) Host module: The DMA controller includes a first host and a second host, and its interface is connected to the AXI bus interface. In the basic embodiment, two AXI hosts are embedded to build a double-layer AXI bus structure. When the DMA controller transmits data, the corresponding address and control information are output to the bus through the host interface of the host to complete the bus data transmission. The parallel function of data transmission is realized in combination with pipeline operation, and the independence of read and write operations is increased in conjunction with the multi-channel mode to avoid mutual exclusion. At the same time, the host also has an arbitration function to realize multi-channel transmission application arbitration to avoid data transmission conflicts.

[0075] 2) Slave module (i.e. slave component): transmits the data information of the CPU to configure the DMA task, pre-processes the data before starting to transmit, addresses the information configured by the CPU to the DMA controller to the relevant configuration registers inside the DMA module through the address bus of the AXI bus, and then configures this information to the register block in the DMA controller through the slave interface.

[0076] 3) Channel module: realizes the control function of DMA data transmission between devices. In this embodiment, the DMA controller supports multiple channels. Each channel has the same function and can independently cooperate with the slave module, host module, request manager, handshake manager, etc. to complete the data transmission work. According to the functional requirements of the channel module, it is divided into source control module, target control module, FIFO module, and register group module.

[0077] 4) The main function of the source control module is to control the DMA controller to read data from the data source device. When the module is working, the DMA controller acts as the AXI host and reads data from the data source device through the first AXI bus and stores it in the FIFO module in the channel module.

[0078] 5) The main function of the target control module is to control the DMA controller to write data to the target device. In this stage, the DMA controller still acts as the AXI host, reads the stored data from the FIFO module, and transfers the data to the target device through the AXI bus.

[0079] 6) The first-in-first-out cache queue is a temporary data storage unit. During the data transmission stage at the source end, the source end control module writes the data read from the source device into the FIFO buffer through the first AXI bus. During the data transmission stage at the target end, the target end control module transfers the data in the FIFO buffer to the target address through the second AXI bus. The FIFO buffer enables the DMA controller to separate read and write operations, effectively handle data transmission problems between different clock domains, and improve the overall data transmission efficiency.

[0080] 7) The register group module (i.e., register module) is an important data register that assists the DMA controller in completing the entire data transmission task, from when the DMA controller acts as a slave to receive configuration information from the CPU through the slave interface, to when the DMA controller acts as a host to read relevant data during the source and target transmission tasks. The register group stores a lot of configuration information that the DMA controller needs to use. The register group is divided into several registers with different functions, including source address registers, target address registers, interrupt registers, transmission transaction registers, and control registers. These registers constitute the register group of the DMA controller in this embodiment, providing necessary configuration information for the DMA controller's transmission.

[0081] 8) Interrupt controller (i.e. interrupt module): The module that generates the corresponding interrupt signal of the DMA controller. This module generates an interrupt signal and sends it to the CPU by judging the current transmission status. The CPU performs the next operation based on the status of the DMA controller, thereby improving the overall performance of the system. The interrupt module will generate a register configuration error signal, a transmission error interrupt, and a transmission completion interrupt signal according to the configuration process of the DMA controller.

[0082] 9) Request manager (i.e. request module): The request signal module sends an application to the host module to apply for bus control for each channel. The request signal module has two request signals, namely source request and destination signal request. When the source / destination device is a peripheral, it determines which peripheral issued the DMA request based on the information of the source peripheral and destination peripheral configured in the channel configuration register, and sends the request clear signal to the corresponding peripheral; when the source / destination device is a memory, the request module directly sets the transfer request signal to 1, and the default memory always issues DMA transfer requests.

[0083] 10) Handshake manager (i.e. handshake module): The external device requests the DMA controller to perform data transmission, and the handshake between the peripheral and the DMA controller is completed through the handshake manager, thereby realizing the data transmission function between the peripheral and the DMA. Since the DMA controller and the peripheral that issues the DMA transfer request signal may not be in the same clock domain, in order to ensure that the request clear signal issued by the DMA controller can be correctly received by the peripherals in different clock domains after a burst transfer, the handshake manager is used to handshake the request signal with the request clear signal to ensure that the request signal can be effectively cleared.

[0084] 11) Arbitrator (i.e. arbitration module): Since DMA only allows one channel to transmit data at a time, a fixed-priority arbitration algorithm is used, with channel 0 set to the highest priority and channel n to the lowest priority (n>1). When a channel is allowed, the arbitrator outputs the address and control information of the channel. If there are multiple channels transmitting data at the same time, the arbitrator will give priority to allowing high-priority channels to transmit data.

[0085] 12) Low-power module (i.e., low-power component): a module used to reduce the power consumption of the DMA controller. The power consumption of the DMA controller is reduced through the low-power module. In this embodiment, the low-power module achieves power consumption reduction by designing a gated clock module. When the CPU configures the DMA controller register, the clock of the main interface is turned off to avoid additional power consumption of other idle modules. Specifically, after receiving the configuration information sent by the processor, the registers of the DMA controller are configured accordingly based on the configuration information, and the low-power component is controlled to turn off the clock of the main interface of the gated clock. In addition, for some signals that change very frequently, Gray code encoding is performed to reduce the change frequency, thereby further reducing power consumption.

[0086] See also Figure 3 As shown, the embodiment of the present application discloses a data transmission device based on a DMA controller, which is applied to a DMA controller including a first host and a second host, wherein the first host and the second host are respectively connected to a first AXI bus and a second AXI bus; wherein the device includes:

[0087] The request generation module 11 is used to receive the configuration information sent by the processor and generate a bus control request corresponding to the configuration information;

[0088] A control right acquisition module 12, used for sending the bus control request to the processor, so that the processor allocates the control rights of the first AXI bus and the second AXI bus to the first host and the second host respectively;

[0089] The data transmission module 13 is used to control the first host to read the data in the data source end to the local end through the first AXI bus, and control the second host to write the local data to the target end through the second AXI bus.

[0090] The beneficial effects of the present application are as follows: the present application is applied to a DMA controller including a first host and a second host, wherein the first host and the second host are respectively connected to a first AXI bus and a second AXI bus; wherein the method comprises: receiving configuration information sent by a processor, and generating a bus control request corresponding to the configuration information; sending the bus control request to the processor so that the processor allocates control rights of the first AXI bus and the second AXI bus to the first host and the second host respectively; controlling the first host to read data from a data source end to a local end through the first AXI bus, and controlling the second host to write local data to a target end through the second AXI bus. It can be seen that the DMA controller of the present application includes a first host and a second host, and the first host is connected to the first AXI bus, and the second host is connected to the second AXI bus, that is, the present application is a multi-layer AXI host structure. In this way, when the first host and the second host of the DMA controller respectively obtain control of the first AXI bus and the second AXI bus, the first host is controlled to read the data in the data source end to the local through the first AXI bus, and the second host is controlled to write the local data to the target end through the second AXI bus. The pipeline operation of the multi-layer AXI host allows data to be executed continuously, fully utilizing system resources and improving the parallelism and performance of data transmission.

[0091] Furthermore, an embodiment of the present application also provides an electronic device. Figure 4 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0092] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data transmission method based on the DMA controller performed by the electronic device disclosed in any of the aforementioned embodiments.

[0093] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0094] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0095] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0096] Among them, the operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device to realize the operation and processing of the processor 21 on the massive data 223 in the memory 22, which can be Windows, Unix, Linux, etc. In addition to including a computer program that can be used to complete the data transmission method based on the DMA controller performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can also further include a computer program that can be used to complete other specific tasks. In addition to data transmitted from an external device received by the electronic device, the data 223 can also include data collected by its own input and output interface 25, etc.

[0097] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned disclosed data transmission method based on a DMA controller. The specific steps of the method can refer to the corresponding contents disclosed in the aforementioned embodiments, and will not be described in detail here.

[0098] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0099] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly with hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable EPROM (Erasable Programmable Read Only Memory), electrically erasable programmable EEPROM (Electrically Erasable Programmable read only memory), register, hard disk, removable disk, CD-ROM (Compact Disc Read-Only Memory), or any other form of storage medium known in the technical field.

[0100] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0101] The above is a detailed introduction to a data transmission method, device, equipment and medium based on a DMA controller provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data transmission method based on a DMA controller, characterized in that: A DMA controller is applied to a first host and a second host, wherein the first host and the second host are connected to a first AXI bus and a second AXI bus respectively; wherein the method comprises: receiving configuration information sent by the processor, and generating a bus control request corresponding to the configuration information; Sending the bus control request to the processor so that the processor allocates control rights of the first AXI bus and the second AXI bus to the first host and the second host respectively; The first host is controlled to read data from the data source end to the local end through the first AXI bus, and the second host is controlled to write the local data to the target end through the second AXI bus.

2. The data transmission method based on DMA controller according to claim 1, characterized in that: The DMA controller includes first-in-first-out cache queues; The controlling the first host to read the data from the data source to the local through the first AXI bus includes: Control the first host to read target read data corresponding to the current transaction to be read from the data source end through the first AXI bus, and save the target read data to a first target cache queue corresponding to the first identification information of the current transaction to be read, so as to complete the current transaction to be read; Correspondingly, controlling the second host to write local data to the target end through the second AXI bus includes: Determine from each of the cache queues a second target cache queue corresponding to the second identification information of the current transaction to be written, and control the second host to write the target write data of the second target cache queue to the target end through the second AXI bus to complete the current transaction to be written; wherein the first identification information is the same as or different from the second identification information.

3. The data transmission method based on DMA controller according to claim 2, characterized in that: The DMA controller includes an interrupt controller; The data transmission method based on the DMA controller also includes: If it is detected that there is a first target data transmission transaction that meets a preset successful execution condition among the data transmission transactions of the DMA controller, the interrupt controller is triggered to generate a successful transmission interrupt signal, and the successful transmission interrupt signal is sent to the processor, so that the processor releases the control right of the first AXI bus and / or the second AXI bus; If it is detected that there is a second target data transmission transaction that meets the preset error execution condition among the data transmission transactions of the DMA controller, the interrupt controller is triggered to generate a transmission failure interrupt signal, and the transmission failure interrupt signal is sent to the processor so that the processor can process the second target data transmission transaction.

4. The data transmission method based on DMA controller according to claim 3, characterized in that: The DMA controller includes a request manager; Before receiving the configuration information sent by the processor, the method further includes: Receiving a transmission request corresponding to a current data transmission transaction sent by the data source end and the target end; Accordingly, the data transmission method based on the DMA controller further includes: If the data source and the target are external devices, when the first host and the second host respond to the transmission request, the request manager is controlled to send a request clear signal corresponding to the transmission request to the data source and the target; If the data source and the target are not external devices, the request manager is controlled to set the transmission request to a high level until the first host and the second host complete the current data transmission transaction corresponding to the current transmission request.

5. The data transmission method based on DMA controller according to claim 4, characterized in that: The DMA controller includes a handshake manager; After controlling the request manager to send a request clear signal corresponding to the transmission request to the data source end and the target end, the method further includes: Control the handshake manager to send a request confirmation signal to the data source and the target end, so that the data source and the target end determine whether to clear the transmission request based on the request confirmation signal, and if the transmission request has been cleared, generate a clear success signal; Receive clear success signals sent by the data source and the target end, and when the current data transmission transaction meets the preset successful execution condition, jump to the step of triggering the interrupt controller to generate a transmission success interrupt signal.

6. The data transmission method based on DMA controller according to claim 1, characterized in that: The DMA controller includes an arbitrator, the first host includes various read channels, and the second host includes various write channels; The controlling the first host to read the data from the data source end to the local end through the first AXI bus, and controlling the second host to write the local data to the target end through the second AXI bus, comprises: Determine a target read channel and a target write channel by using the arbitrator based on the priorities of the read channels and the priorities of the write channels, and send the address of the target read channel and the address of the target write channel to the first host and the second host respectively; The first host is controlled to read the data in the data source end to the local end through the target read channel and the first AXI bus based on the address of the target read channel, and the second host is controlled to write the local data to the target end through the target write channel and the second AXI bus based on the address of the target write channel.

7. The data transmission method based on DMA controller according to any one of claims 1 to 6, characterized in that: The DMA controller includes a slave component; The receiving processor sends the configuration information, including: The configuration information sent by the processor is received through the slave component, and the configuration information is saved in the register module; wherein the register module includes a data source address register, a target address register, an interrupt register, and a transmission transaction register.

8. A data transmission device based on a DMA controller, characterized in that: A DMA controller applied to a first host and a second host, wherein the first host and the second host are connected to a first AXI bus and a second AXI bus respectively; wherein the device comprises: A request generation module, used to receive configuration information sent by the processor and generate a bus control request corresponding to the configuration information; a control right acquisition module, used for sending the bus control request to the processor, so that the processor allocates the control rights of the first AXI bus and the second AXI bus to the first host and the second host respectively; The data transmission module is used to control the first host to read the data in the data source end to the local end through the first AXI bus, and control the second host to write the local data to the target end through the second AXI bus.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the data transmission method based on a DMA controller as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the data transmission method based on a DMA controller as described in any one of claims 1 to 7 are implemented.

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