APB bus-based communication management methods, apparatus, devices, and storage media

Abstract

This application relates to a communication management method, apparatus, computer device, and storage medium based on the APB bus. The method includes: receiving an address signal sent by the microcontroller through the APB master interface and determining whether the address signal is valid; in response to the valid address signal, segmenting the address signal using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller; and in response to a control command from the microcontroller, performing read / write operations on the target register through the target APB slave interface. This method enables the selection of the APB slave interface through APB handshake signals and address segmentation, reducing APB bus wiring congestion, lowering the latency of the MCU accessing the APB slave interface, and avoiding access conflicts between multiple APB slave interfaces.

Description

Technical Field

[0001] This application relates to the field of bus interface technology, and in particular to a communication management method, apparatus, computer device, and storage medium based on the APB bus. Background Technology

[0002] The APB bus is a low-power, simple, and flexible bus architecture primarily used for communication between the processor and peripherals. In many embedded systems, the MCU acts as the master device, and peripheral modules act as slave devices, communicating via the APB bus. Since peripheral modules have multiple APB bus slave interfaces that require MCU control, current technologies typically use bus interconnects to connect multiple functional blocks, processors, memory, and peripheral components. Specifically, the MCU and the bus interconnect are connected through a set of APB bus interfaces. The bus interconnect uses a distributed switching structure to interconnect with each peripheral module, thereby enabling the MCU to control multiple APB slave interfaces through a single APB master interface.

[0003] However, the bus interconnect of the distributed switching architecture still has some problems in practical applications. For example, too many APB buses connected to the interconnect bus increase power consumption and area, and can lead to wiring congestion during chip design. In addition, when multiple APBs request access from the interface at the same time, access conflicts are likely to occur, increasing bus latency and thus affecting the overall system performance. Summary of the Invention

[0004] Therefore, it is necessary to provide an APB bus-based communication management method, apparatus, computer device, and storage medium that can automatically identify the selected APB slave interface in order to address the aforementioned technical problems.

[0005] On one hand, a communication management method based on the APB bus is provided. The APB bus is used to connect a microcontroller and a peripheral module. The microcontroller includes an APB master interface, and the peripheral module includes multiple APB slave interfaces. The APB slave interfaces are connected to at least one set of registers. The method includes:

[0006] Receive the address signal sent by the microcontroller through the APB main interface, and determine whether the address signal is valid;

[0007] In response to the address signal being valid, the address signal is segmented and judged using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, and a connection is established between the target APB slave interface and the microcontroller.

[0008] In response to the control command of the microcontroller, read and write operations are performed on the target register through the target APB slave interface.

[0009] In one embodiment, the method further includes:

[0010] Establish a mapping relationship between the APB slave interface and the address segments of the address signal;

[0011] An address mapping table is constructed based on the mapping relationship, so that the microcontroller generates the address signals corresponding to the target APB slave interface and the target register according to the address mapping table.

[0012] In one embodiment, receiving the address signal sent by the microcontroller through the APB main interface and determining whether the address signal is valid includes:

[0013] Detect the selection signal sent by the microcontroller;

[0014] In response to detecting that the selection signal is pulled high, the microcontroller receives an address signal, the address signal including the address of the target register;

[0015] Match the address signal with the address mapping table;

[0016] In response to the address signal existing in the address mapping table and the address of the target register being valid, the address signal is determined to be valid.

[0017] In one embodiment, the step of responding to the address signal being valid by segmenting the address signal using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal includes:

[0018] In response to the address signal being valid, a first address range and a second address range of the address signal are obtained, wherein the first address range is the high-order address and the second address range is the low-order address;

[0019] The first address range is segmented and judged according to the address mapping table to determine the target APB slave interface corresponding to the first address range, and the target register corresponding to the target APB slave interface is determined through the second address range.

[0020] In one embodiment, the step of segmenting the first address range according to the address mapping table to determine the target APB slave interface corresponding to the first address range, and determining the target register corresponding to the target APB slave interface through the second address range, includes:

[0021] Based on the mapping relationship between the APB slave interface and the address segments of the address signal in the address mapping table, the first address interval is divided into multiple address segments;

[0022] Detect the most significant bit in the first address range;

[0023] In response to the most significant bit being low, the first APB slave interface range is determined according to the address mapping table;

[0024] Detect the level of each position of the first address segment in the first address interval, and determine the target APB slave interface from the first APB slave interface range based on the level of each position of the first address segment;

[0025] In response to the most significant bit being high, the second APB slave interface range is determined according to the address mapping table;

[0026] Detect the level of each position of the second address segment in the first address interval, and determine the target APB slave interface from the range of the second APB slave interface based on the level of each position of the second address segment;

[0027] After determining the target APB slave interface, the selection signal of the target APB slave interface is pulled high, so that the target APB slave interface determines the target register according to the second address range.

[0028] In one embodiment, the method further includes: in response to the existence of target registers with the same address in the plurality of APB slave interfaces, storing the mapping relationship between the broadcast modes of the plurality of APB slave interfaces and the address segments of the address signal in the address mapping table; in response to determining that the broadcast mode is enabled for the plurality of APB slave interfaces according to the address signal and the address mapping table, establishing a connection between the plurality of APB slave interfaces and the microcontroller; and in response to a control command from the microcontroller, simultaneously performing read and write operations on the target registers with the same address in the plurality of APB slave interfaces through the broadcast mode.

[0029] In one embodiment, the step of performing a read / write operation on the target register through the target APB slave interface in response to a control command from the microcontroller includes: after determining the target APB slave interface, pulling up the selection signal of the APB slave interface to allow the microcontroller to send a control command through the APB bus; and performing a read / write operation on the target register according to the control command.

[0030] On the other hand, a communication management device based on the APB bus is provided. The APB bus is used to connect a microcontroller and a peripheral module. The microcontroller includes an APB master interface, and the peripheral module includes multiple APB slave interfaces. The APB slave interfaces are connected to at least one set of registers. The device includes:

[0031] The receiving module is used to receive the address signal sent by the microcontroller through the APB main interface and determine whether the address signal is valid.

[0032] The determination module is used to respond to the address signal being valid by segmenting the address signal through a preset address mapping table, determining the target APB slave interface and target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller.

[0033] The response module is used to perform read and write operations on the target register through the target APB slave interface in response to the control commands of the microcontroller.

[0034] In another aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0035] Receive the address signal sent by the microcontroller through the APB main interface, and determine whether the address signal is valid;

[0036] In response to the address signal being valid, the address signal is segmented and judged using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, and a connection is established between the target APB slave interface and the microcontroller.

[0037] In response to the control command of the microcontroller, read and write operations are performed on the target register through the target APB slave interface.

[0038] In another aspect, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0039] Receive the address signal sent by the microcontroller through the APB main interface, and determine whether the address signal is valid;

[0040] In response to the address signal being valid, the address signal is segmented and judged using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, and a connection is established between the target APB slave interface and the microcontroller.

[0041] In response to the control command of the microcontroller, read and write operations are performed on the target register through the target APB slave interface.

[0042] The aforementioned communication management method, device, computer equipment, and storage medium based on the APB bus manage all APB slave interfaces that require microcontroller control through APB handshake signals and address segmentation. By using an address mapping table to determine the target APB slave interface and target register corresponding to the address signal sent by the MCU, multiple APB slave interfaces connected to the interconnect bus are reduced to one, thereby reducing the bandwidth bottleneck, latency, power consumption, and physical layout complexity of the interconnect bus. Attached Figure Description

[0043] Figure 1 This is a block diagram of the structure of an SSD controller chip in the prior art;

[0044] Figure 2 This is a flowchart illustrating a communication management method based on the APB bus in one embodiment;

[0045] Figure 3 This is a block diagram of the SSD controller chip in one embodiment;

[0046] Figure 4 This is a schematic diagram of the APB bus connection of a PCIE subsystem in one embodiment;

[0047] Figure 5 This is a schematic diagram of the APB bus connection in broadcast mode in one embodiment;

[0048] Figure 6 This is a structural block diagram of a communication management device based on the APB bus in one embodiment;

[0049] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] like Figure 1As shown, taking the architecture of an SSD (Solid State Drive) controller chip as an example, it includes an MCU, NIC400, a PCIe subsystem, and a DDR subsystem, with each part connected via an APB bus. The controller chip is responsible for managing and controlling the operation and data transmission of the entire SSD, acting as the "brain" of the SSD, coordinating, controlling, and managing storage chips, data caching, and data transmission. With the increasing popularity of SSDs in the storage market, the performance and stability requirements for SSD controller chips are also rising. PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) is widely used for data transmission between SSD controller chips and the host. Compared to traditional SATA interface SSDs, PCIe interface SSDs offer higher speeds and performance as well as lower latency.

[0052] The APB (Advanced Peripheral Bus) is a low-power, simple, and flexible bus architecture primarily used for communication between the processor and peripherals. In the PCIe subsystem, PCIe functionality is mainly divided into two parts: the controller and the physical sublayer. The PCIe controller and physical sublayer contain multiple sets of registers that need to be controlled by the MCU (Microcontroller Unit) in the SSD host chip. During design, the PCIe registers use the APB bus to communicate with the MCU. The MCU acts as the master device, and the PCIe subsystem as the slave device. Because the PCIe subsystem has multiple APB bus interfaces that require MCU control, current technology uses the NIC400 for bus interconnection. The MCU interconnects with both the PCIe subsystem and the DDR subsystem through the NIC400. The NIC400 connects various functional blocks, processors, memory, and peripherals for communication. Using a distributed switching structure avoids bottlenecks and conflicts during bus interconnection, but it can lead to wiring congestion during chip design.

[0053] In one embodiment, such as Figure 2-4 As shown, a communication management method based on the APB bus is provided, wherein the APB bus is used to connect a microcontroller and a peripheral module, the microcontroller includes an APB master interface, and the peripheral module includes multiple APB slave interfaces. The method includes the following steps:

[0054] Step S1: Receive the address signal sent by the microcontroller through the APB main interface, and determine whether the address signal is valid.

[0055] In one embodiment, the method further includes: establishing a mapping relationship between the APB slave interface and the address segments of the address signal; constructing an address mapping table according to the mapping relationship, so that the microcontroller generates the address signal corresponding to the target APB slave interface and the target register according to the address mapping table.

[0056] like Figure 3 As shown, taking the SSD controller chip as an example, the MCU communicates with the PCIe subsystem. The PCIe subsystem design uses two PCIe controllers and two PCIe physical sublayers. The PCIe controllers and PCIe physical layers are interconnected through the PIPE interface. During the PCIe initialization phase, the registers of the PCIe controllers and PCIe physical sublayers need to be configured. In order to facilitate the MCU's control of each register of the PCIe controllers and PCIe physical sublayers, the design uniformly uses the APB bus to communicate with the MCU. Each PCIe controller has one APB slave interface, such as APB0 and APB3, and each PCIe physical layer has two APB slave interfaces, such as APB1, APB2, APB4, and APB5. All APB slave interfaces are uniformly managed and controlled by the APB management module.

[0057] In the APB management module, by specifying the address mapping table corresponding to the APB slave interface, a unique mapping relationship between multiple APB slave interfaces and the high bits of the address bus is defined in the mapping table. The MCU will send the address signal corresponding to the target APB slave interface according to the address mapping table, thereby accessing the target APB slave interface. Table 1 is an example of an address mapping table, as shown below.

[0058] Table 1 Address Mapping Table

[0059]

[0060] As shown in Table 1, in the PCIe subsystem, the number of registers controlled by different APB buses varies, resulting in different bit widths of the APB bus addresses allocated to the registers. However, the registers controlled by all APB slave interfaces will not exceed the address space of 0 to 20 bits. For example, APB2 and APB5 control more registers, so they use the APB bus address signal bits [17:0] during address allocation, while other APB slave interfaces only use the APB bus address signal bits [11:0].

[0061] It is understood that in this embodiment, since the PCIE subsystem of the SSD controller chip includes a total of 6 APB slave interfaces, the bus address is assigned to each APB slave interface through the address mapping table shown in Table 1, and the address width is allocated according to the number of registers. In actual applications, the address mapping table can be designed according to the number of registers to be configured and the number of APB slave interfaces used.

[0062] Based on the above steps, multiple APB slave interfaces can be effectively managed by using the APB management module. An address mapping table is designed based on the mapping relationship between the APB slave interfaces and address segments. The selection of the APB slave interface is achieved by segmenting the address signal, which simplifies the design of the APB management module, thereby reducing the physical layout complexity, power consumption and area of ​​the interconnect bus, and improving the overall performance and reliability of the system.

[0063] In another embodiment, when the microcontroller connects to multiple external devices via the APB bus, the logic resources of the field-programmable gate array (FPGA) can be used to implement the APB extended bus interface. The APB extended bus interface includes multiple bus connectors, each connecting to a corresponding external device and including an external device controller and at least one set of registers. The external device address space is segmented according to the address depth of the registers of the connected bus connectors, and a mapping relationship is formed between the address segments and the register addresses. A peripheral address mapping table is constructed based on the mapping relationship, so that the peripheral address signals sent by the microcontroller via the APB bus are mapped to the corresponding register address signals of the bus connectors according to the address mapping table, and further sent to the bus connectors. In response to control commands sent by the microcontroller, the external device controller performs read and write operations on the registers according to the register address signals.

[0064] In one embodiment, receiving the address signal sent by the microcontroller through the APB main interface and determining whether the address signal is valid includes: detecting a selection signal sent by the microcontroller; receiving the address signal sent by the microcontroller, the address signal including the address of the target register, in response to detecting that the selection signal is pulled high; matching the address signal with the address mapping table; and determining that the address signal is valid in response to the address mapping table containing the address signal and the address of the target register being valid.

[0065] For example, consider an MCU accessing a register of the APB4 slave interface in the PCIe subsystem. The address of this register is represented by 12'bx. When the APB management module detects that the MCU's select signal is pulled high, it determines that the MCU wants to access the APB slave interface in the PCIe subsystem. At this time, the MCU will send address 21'b100000011x through the APB master interface according to the address mapping table. Since the data width is 32 bits, the address sent by the MCU each time is a 4-byte aligned address.

[0066] Based on the above steps, the validity of the address signal is ensured in this way, and the timing of when the MCU is allowed to access the APB from the interface is determined by detecting the high or low level of the selection signal, thereby improving the accuracy and efficiency of the system's register access.

[0067] Step S2: In response to the address signal being valid, the address signal is segmented and judged using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, and a connection is established between the target APB slave interface and the microcontroller.

[0068] In one embodiment, the step of determining the target APB slave interface and target register corresponding to the address signal by segmenting the address signal according to a preset address mapping table in response to the address signal being valid includes: obtaining a first address range and a second address range of the address signal in response to the address signal being valid, wherein the first address range is the high-order address and the second address range is the low-order address; segmenting the first address range according to the address mapping table to determine the target APB slave interface corresponding to the first address range, and determining the target register corresponding to the target APB slave interface through the second address range.

[0069] The first address range is the address range corresponding to the APB slave interface, used to distinguish different APB slave interfaces. The second address range is used to determine the specific register address. The bit width of the APB bus address allocated to the register varies depending on the number of registers controlled by each APB slave interface. However, the registers controlled by all APB slave interfaces will not exceed the address space of 0 to 20 bits.

[0070] In one embodiment, the step of segmenting the first address interval according to the address mapping table, determining the target APB slave interface corresponding to the first address interval, and determining the target register corresponding to the target APB slave interface through the second address interval includes: dividing the first address interval into multiple address segments according to the mapping relationship between the APB slave interface and the address segments of the address signal in the address mapping table; detecting the most significant bit in the first address interval; determining the first APB slave interface range according to the address mapping table in response to the most significant bit being low; detecting the first... The system detects the level of each position in the address segment and determines the target APB slave interface from the first APB slave interface range based on the level of each position in the first address segment; in response to the most significant bit being high, it determines the second APB slave interface range based on the address mapping table; it detects the level of each position in the second address segment in the first address range and determines the target APB slave interface from the second APB slave interface range based on the level of each position in the second address segment; after determining the target APB slave interface, it pulls the selection signal of the target APB slave interface high, so that the target APB slave interface determines the target register based on the second address range.

[0071] Specifically, the address segmentation judgment method based on the address mapping table in Table 1 is as follows: First, the level of address signal

[20] bit is detected. When address signal

[20] bit is detected as 0, the possible APB slave interface range includes APB2 and APB5. Then, address signal

[18] bit is detected to determine the specific APB slave interface. When address signal

[20] bit is detected as 1, the possible APB slave interface range includes APB0, APB1, APB3, and APB4. Then, address signal [13:12] bits are detected to determine which APB slave interface is being accessed.

[0072] For example, when the MCU wants to access the APB4 slave interface, it checks the 20th bit of the address signal sent by the MCU. At this time, the 20th bit is 1, and it enters the APB0, APB3, APB1, APB4 branch judgment. Then it obtains the [13:12]th bits of the address signal. At this time, the [13:12]th bits of the address signal are 2'b11. The selection signal of the APB4 slave interface in the PCIe subsystem is pulled high, indicating that the APB4 slave interface is selected. The APB4 slave interface finds the register corresponding to the address according to the [11:0]th bits of the address signal, and reads and writes the register according to the instructions sent by the MCU.

[0073] It should be noted that in existing technologies, when an MCU accesses an APB slave interface, it also selects the APB slave interface based on the APB bus address signal. However, a relatively large address width is generally used for logical judgment, such as using the address signals [20:12] in Table 1 for APB slave interface selection. However, a large address width can lead to wiring congestion and timing difficulties during chip design. In this embodiment, the selection of the APB slave interface is achieved by using address segmentation judgment based on the APB handshake signal and address segmentation. This simplifies the design of the APB management module, reduces wiring congestion, reduces the latency of the MCU accessing the APB slave interface, avoids conflicts between multiple APB slave interfaces, reduces bus waiting time, and reduces the number of interfaces connected to the interconnect bus. This reduces the physical layout complexity, power consumption, and area of ​​the interconnect bus, thereby improving the performance of the interconnect bus.

[0074] In one embodiment, the method further includes: in response to the existence of target registers with the same address in the plurality of APB slave interfaces, storing the mapping relationship between the broadcast modes of the plurality of APB slave interfaces and the address segments of the address signal in the address mapping table; in response to determining that the broadcast mode is enabled for the plurality of APB slave interfaces according to the address signal and the address mapping table, establishing a connection between the plurality of APB slave interfaces and the microcontroller; and in response to a control command from the microcontroller, simultaneously performing read and write operations on the target registers with the same address in the plurality of APB slave interfaces through the broadcast mode.

[0075] like Figure 5 As shown, when the MCU wants to configure registers at the same address to multiple APB slave interfaces at the same time, such as simultaneously writing to registers at the same address in APB2 and APB5, a set of address mapping relationships can be added to the address mapping table of the APB management module to achieve the broadcast function. The new address mapping table is as follows: Figure 2 As shown.

[0076] Table 2 Address Mapping Table with Broadcast Mode

[0077]

[0078] As shown in Table 2, when the APB management module detects that [20:18] in the address signal is 010, it confirms that the broadcast mode is enabled for the APB2 and APB5 slave interfaces, so that the MCU can simultaneously control the APB2 and APB5 slave interfaces to perform register read and write operations.

[0079] Based on the above steps, when the MCU expects to configure registers with the same address to multiple APBs at the same time, by adding a broadcast mode mapping relationship to the address mapping table, the MCU can control multiple registers with the same address simultaneously, reducing the MCU configuration process and improving the performance of the interconnect bus.

[0080] Step S3: In response to the control command of the microcontroller, perform read and write operations on the target register through the target APB slave interface.

[0081] In one embodiment, the step of performing read / write operations on the target register through the target APB slave interface in response to the control command of the microcontroller includes: after determining the target APB slave interface, pulling up the selection signal of the APB slave interface to allow the microcontroller to send control commands through the APB bus; and performing read / write operations on the target register according to the control command.

[0082] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0083] In one embodiment, such as Figure 6 As shown, a communication management device based on the APB bus is provided, including: a receiving module, a determining module, and a responding module, wherein:

[0084] The receiving module is used to receive the address signal sent by the microcontroller through the APB main interface and determine whether the address signal is valid.

[0085] The determination module is used to respond to the address signal being valid by segmenting the address signal through a preset address mapping table, determining the target APB slave interface and target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller.

[0086] The response module is used to perform read and write operations on the target register through the target APB slave interface in response to the control commands of the microcontroller.

[0087] In one embodiment, the device further includes a mapping module, which is used to establish a mapping relationship between the APB slave interface and the address segments of the address signal; and to construct an address mapping table according to the mapping relationship, so that the microcontroller generates the address signal corresponding to the target APB slave interface and the target register according to the address mapping table.

[0088] In one embodiment, the receiving module is further configured to detect a selection signal sent by the microcontroller; in response to detecting that the selection signal is pulled high, receive an address signal sent by the microcontroller, the address signal including the address of the target register; match the address signal with the address mapping table; and in response to the address signal existing in the address mapping table and the address of the target register being valid, determine that the address signal is valid.

[0089] In one embodiment, the determining module is further configured to, in response to the address signal being valid, obtain a first address range and a second address range of the address signal, wherein the first address range is the high-order address and the second address range is the low-order address; perform segmentation judgment on the first address range according to the address mapping table, determine the target APB slave interface corresponding to the first address range, and determine the target register corresponding to the target APB slave interface through the second address range.

[0090] In one embodiment, the determining module is further configured to: divide the first address interval into multiple address segments according to the mapping relationship between the APB slave interface and the address segments of the address signal in the address mapping table; detect the most significant bit in the first address interval; determine a first APB slave interface range according to the address mapping table in response to the most significant bit being low; detect the position level of each position of the first address segment in the first address interval, and determine a target APB slave interface from the first APB slave interface range according to the position level of each position of the first address segment; determine a second APB slave interface range according to the address mapping table in response to the most significant bit being high; detect the position level of each position of the second address segment in the first address interval, and determine a target APB slave interface from the second APB slave interface range according to the position level of each position of the second address segment; and after determining the target APB slave interface, pull up the selection signal of the target APB slave interface, so that the target APB slave interface determines the target register according to the second address interval.

[0091] In one embodiment, the apparatus further includes a broadcast module, which is configured to, in response to the existence of target registers with the same address in multiple APB slave interfaces, store the mapping relationship between the broadcast modes of the multiple APB slave interfaces and the address segments of the address signal in the address mapping table; establish a connection between the multiple APB slave interfaces and the microcontroller in response to determining that the broadcast mode is enabled for the multiple APB slave interfaces based on the address signal and the address mapping table; and, in response to a control command from the microcontroller, simultaneously perform read and write operations on the target registers with the same address in the multiple APB slave interfaces through the broadcast mode.

[0092] In one embodiment, the response module is further configured to, after determining the target APB slave interface, pull up the selection signal of the APB slave interface, allowing the microcontroller to send control commands through the APB bus; and perform read / write operations on the target register according to the control commands.

[0093] Specific limitations regarding the APB bus-based communication management device can be found in the above description of the limitations of the APB bus-based communication management method, and will not be repeated here. Each module in the aforementioned APB bus-based communication management device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the corresponding operations of each module.

[0094] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 7 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores address mapping table data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements a communication management method based on the APB bus.

[0095] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0096] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0097] Receive the address signal sent by the microcontroller through the APB main interface, and determine whether the address signal is valid;

[0098] In response to the address signal being valid, the address signal is segmented and judged using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, and a connection is established between the target APB slave interface and the microcontroller.

[0099] In response to the control command of the microcontroller, read and write operations are performed on the target register through the target APB slave interface.

[0100] In one embodiment, when the processor executes the computer program, it further performs the following steps: establishing a mapping relationship between the APB slave interface and the address segments of the address signal; constructing an address mapping table according to the mapping relationship, so that the microcontroller generates the address signal corresponding to the target APB slave interface and the target register according to the address mapping table.

[0101] In one embodiment, when the processor executes a computer program, it further performs the following steps: detecting a selection signal sent by the microcontroller; in response to detecting that the selection signal is pulled high, receiving an address signal sent by the microcontroller, the address signal including the address of the target register; matching the address signal with the address mapping table; and in response to the address signal existing in the address mapping table and the address of the target register being valid, determining that the address signal is valid.

[0102] In one embodiment, when the processor executes a computer program, it further performs the following steps: in response to the address signal being valid, it obtains a first address range and a second address range of the address signal, wherein the first address range is a high-order address and the second address range is a low-order address; it performs segmentation judgment on the first address range according to the address mapping table, determines the target APB slave interface corresponding to the first address range, and determines the target register corresponding to the target APB slave interface through the second address range.

[0103] In one embodiment, when the processor executes a computer program, it further performs the following steps: dividing the first address interval into multiple address segments according to the mapping relationship between the APB slave interface and the address segments of the address signal in the address mapping table; detecting the most significant bit in the first address interval; determining a first APB slave interface range according to the address mapping table in response to the most significant bit being low; detecting the position level of each position of the first address segment in the first address interval, and determining a target APB slave interface from the first APB slave interface range according to the position level of each position of the first address segment; determining a second APB slave interface range according to the address mapping table in response to the most significant bit being high; detecting the position level of each position of the second address segment in the first address interval, and determining a target APB slave interface from the second APB slave interface range according to the position level of each position of the second address segment; after determining the target APB slave interface, pulling up the selection signal of the target APB slave interface, so that the target APB slave interface determines the target register according to the second address interval.

[0104] In one embodiment, when the processor executes the computer program, it further performs the following steps: in response to the existence of target registers with the same address in multiple APB slave interfaces, it stores the mapping relationship between the broadcast mode of the multiple APB slave interfaces and the address segments of the address signal in the address mapping table; in response to determining that the broadcast mode is enabled for the multiple APB slave interfaces according to the address signal and the address mapping table, it establishes a connection between the multiple APB slave interfaces and the microcontroller; in response to the control command of the microcontroller, it simultaneously performs read and write operations on the target registers with the same address in the multiple APB slave interfaces through the broadcast mode.

[0105] In one embodiment, when the processor executes the computer program, it further performs the following steps: after determining the target APB slave interface, it pulls the select signal of the APB slave interface high, allowing the microcontroller to send control commands through the APB bus; and performs read and write operations on the target register according to the control commands.

[0106] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0107] Receive the address signal sent by the microcontroller through the APB main interface, and determine whether the address signal is valid;

[0108] In response to the address signal being valid, the address signal is segmented and judged using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, and a connection is established between the target APB slave interface and the microcontroller.

[0109] In response to the control command of the microcontroller, read and write operations are performed on the target register through the target APB slave interface.

[0110] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: establishing a mapping relationship between the APB slave interface and the address segments of the address signal; constructing an address mapping table according to the mapping relationship, so that the microcontroller generates the address signal corresponding to the target APB slave interface and the target register according to the address mapping table.

[0111] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: detecting a selection signal sent by the microcontroller; in response to detecting that the selection signal is pulled high, receiving an address signal sent by the microcontroller, the address signal including the address of the target register; matching the address signal with the address mapping table; and in response to the address signal existing in the address mapping table and the address of the target register being valid, determining that the address signal is valid.

[0112] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: in response to the address signal being valid, obtaining a first address range and a second address range of the address signal, wherein the first address range is the high-order address and the second address range is the low-order address; performing segmentation judgment on the first address range according to the address mapping table, determining the target APB slave interface corresponding to the first address range, and determining the target register corresponding to the target APB slave interface through the second address range.

[0113] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: dividing the first address interval into multiple address segments according to the mapping relationship between the APB slave interface and the address segments of the address signal in the address mapping table; detecting the most significant bit in the first address interval; determining a first APB slave interface range according to the address mapping table in response to the most significant bit being low; detecting the position level of each position of the first address segment in the first address interval, and determining a target APB slave interface from the first APB slave interface range according to the position level of each position of the first address segment; determining a second APB slave interface range according to the address mapping table in response to the most significant bit being high; detecting the position level of each position of the second address segment in the first address interval, and determining a target APB slave interface from the second APB slave interface range according to the position level of each position of the second address segment; after determining the target APB slave interface, pulling up the selection signal of the target APB slave interface, so that the target APB slave interface determines the target register according to the second address interval.

[0114] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: in response to the existence of target registers with the same address in the plurality of APB slave interfaces, storing the mapping relationship between the broadcast modes of the plurality of APB slave interfaces and the address segments of the address signal in the address mapping table; in response to determining that the broadcast mode is enabled for the plurality of APB slave interfaces according to the address signal and the address mapping table, establishing a connection between the plurality of APB slave interfaces and the microcontroller; in response to the control command of the microcontroller, simultaneously performing read and write operations on the target registers with the same address in the plurality of APB slave interfaces through the broadcast mode.

[0115] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: after determining the target APB slave interface, it pulls the select signal of the APB slave interface high, allowing the microcontroller to send control commands through the APB bus; and performs read and write operations on the target register according to the control commands.

[0116] In one embodiment, a computer product is provided that stores a computer program, which, when executed by a processor, performs the following steps:

[0117] Receive the address signal sent by the microcontroller through the APB main interface, and determine whether the address signal is valid;

[0118] In response to the address signal being valid, the address signal is segmented and judged using a preset address mapping table to determine the target APB slave interface and target register corresponding to the address signal, and a connection is established between the target APB slave interface and the microcontroller.

[0119] In response to the control command of the microcontroller, read and write operations are performed on the target register through the target APB slave interface.

[0120] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: establishing a mapping relationship between the APB slave interface and the address segments of the address signal; constructing an address mapping table according to the mapping relationship, so that the microcontroller generates the address signal corresponding to the target APB slave interface and the target register according to the address mapping table.

[0121] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: detecting a selection signal sent by the microcontroller; in response to detecting that the selection signal is pulled high, receiving an address signal sent by the microcontroller, the address signal including the address of the target register; matching the address signal with the address mapping table; and in response to the address signal existing in the address mapping table and the address of the target register being valid, determining that the address signal is valid.

[0122] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: in response to the address signal being valid, obtaining a first address range and a second address range of the address signal, wherein the first address range is the high-order address and the second address range is the low-order address; performing segmentation judgment on the first address range according to the address mapping table, determining the target APB slave interface corresponding to the first address range, and determining the target register corresponding to the target APB slave interface through the second address range.

[0123] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: dividing the first address interval into multiple address segments according to the mapping relationship between the APB slave interface and the address segments of the address signal in the address mapping table; detecting the most significant bit in the first address interval; determining a first APB slave interface range according to the address mapping table in response to the most significant bit being low; detecting the position level of each position of the first address segment in the first address interval, and determining a target APB slave interface from the first APB slave interface range according to the position level of each position of the first address segment; determining a second APB slave interface range according to the address mapping table in response to the most significant bit being high; detecting the position level of each position of the second address segment in the first address interval, and determining a target APB slave interface from the second APB slave interface range according to the position level of each position of the second address segment; after determining the target APB slave interface, pulling up the selection signal of the target APB slave interface, so that the target APB slave interface determines the target register according to the second address interval.

[0124] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: in response to the existence of target registers with the same address in the plurality of APB slave interfaces, storing the mapping relationship between the broadcast modes of the plurality of APB slave interfaces and the address segments of the address signal in the address mapping table; in response to determining that the broadcast mode is enabled for the plurality of APB slave interfaces according to the address signal and the address mapping table, establishing a connection between the plurality of APB slave interfaces and the microcontroller; in response to the control command of the microcontroller, simultaneously performing read and write operations on the target registers with the same address in the plurality of APB slave interfaces through the broadcast mode.

[0125] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: after determining the target APB slave interface, it pulls the select signal of the APB slave interface high, allowing the microcontroller to send control commands through the APB bus; and performs read and write operations on the target register according to the control commands.

[0126] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0127] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A communication management method based on the APB bus, characterized in that, The APB bus is used to connect a microcontroller and a peripheral module. The microcontroller includes an APB master interface, and the peripheral module includes multiple APB slave interfaces. Each APB slave interface is connected to at least one set of registers. The method includes: Establish a mapping relationship between the APB slave interface and the address segments of the address signal; construct an address mapping table according to the mapping relationship, so that the microcontroller generates the address signal corresponding to the target APB slave interface and the target register according to the address mapping table, wherein the mapping relationship includes multiple unique mapping relationships between the APB slave interface and the high-order bits of the address bus; Receiving the address signal sent by the microcontroller through the APB main interface and determining whether the address signal is valid includes: detecting a selection signal sent by the microcontroller; in response to detecting that the selection signal is pulled high, receiving the address signal sent by the microcontroller, the address signal including the address of the target register; matching the address signal with the address mapping table; and in response to the address signal existing in the address mapping table and the address of the target register being valid, determining that the address signal is valid. In response to the address signal being valid, the address signal is segmented and judged using a preset address mapping table to determine the target APB slave interface and the target register corresponding to the address signal, and a connection is established between the target APB slave interface and the microcontroller. This includes: in response to the address signal being valid, obtaining a first address range and a second address range of the address signal, where the first address range is the high-order address and the second address range is the low-order address; segmenting and judging the first address range according to the address mapping table to determine the target APB slave interface corresponding to the first address range, and determining the target register corresponding to the target APB slave interface through the second address range; In response to the control command of the microcontroller, read and write operations are performed on the target register through the target APB slave interface.

2. The communication management method based on the APB bus according to claim 1, characterized in that, The step of segmenting the first address range according to the address mapping table, determining the target APB slave interface corresponding to the first address range, and determining the target register corresponding to the target APB slave interface through the second address range includes: Based on the mapping relationship between the APB slave interface and the address segments of the address signal in the address mapping table, the first address interval is divided into multiple address segments; Detect the most significant bit in the first address range; In response to the most significant bit being low, the first APB slave interface range is determined according to the address mapping table; Detect the level of each position of the first address segment in the first address interval, and determine the target APB slave interface from the first APB slave interface range based on the level of each position of the first address segment; In response to the most significant bit being high, the second APB slave interface range is determined according to the address mapping table; Detect the level of each position of the second address segment in the first address interval, and determine the target APB slave interface from the range of the second APB slave interface based on the level of each position of the second address segment; After determining the target APB slave interface, the selection signal of the target APB slave interface is pulled high, so that the target APB slave interface determines the target register according to the second address range.

3. The communication management method based on the APB bus according to claim 1, characterized in that, The method further includes: In response to the existence of target registers with the same address in multiple APB slave interfaces, the mapping relationship between the broadcast modes of the multiple APB slave interfaces and the address segments of the address signal is stored in the address mapping table; In response to determining, based on the address signal and the address mapping table, to enable broadcast mode for the plurality of APB slave interfaces, a connection is established between the plurality of APB slave interfaces and the microcontroller; In response to the control command of the microcontroller, read and write operations are performed simultaneously on the target registers at the same address in the multiple APB slave interfaces through the broadcast mode.

4. The communication management method based on the APB bus according to claim 1, characterized in that, The step of responding to the control command of the microcontroller by performing read / write operations on the target register through the target APB slave interface includes: After determining the target APB slave interface, the select signal of the APB slave interface is pulled high, allowing the microcontroller to send control commands through the APB bus; The target register is read and written according to the control command.

5. A communication management device based on the APB bus, characterized in that, For implementing the method of any one of claims 1-4, the APB bus is used to connect a microcontroller and a peripheral module, the microcontroller includes an APB master interface, the peripheral module includes a plurality of APB slave interfaces, the APB slave interfaces are connected to at least one set of registers, and the device comprises: The receiving module is used to receive the address signal sent by the microcontroller through the APB main interface and determine whether the address signal is valid. The determination module is used to respond to the address signal being valid by segmenting the address signal through a preset address mapping table, determining the target APB slave interface and target register corresponding to the address signal, and establishing a connection between the target APB slave interface and the microcontroller. The response module is used to perform read and write operations on the target register through the target APB slave interface in response to the control commands of the microcontroller.

6. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

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