Data processing method and device, chip and storage medium

Abstract

According to the data processing method and device, the chip and the storage medium provided by the invention, a first processor is connected with a second processor through an SPI interface and an MIPI interface, the first data acquired by a sensor is acquired in response, and the first data is processed in a first processing mode to obtain second data; inquiring whether the second processor is in an idle state or not through the SPI interface; in response to the fact that the second processor is in the idle state, the second data is transmitted to the second processor through the MIPI interface so that the second processor can process the second data in the second processing mode, reliable data communication and transmission between the double chips can be achieved, and the computing power can be improved compared with a single-chip design.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular, relates to a data processing method, device, chip and storage medium. Background Art

[0002] In current electronic device design, with the continuous increase in functions and the improvement of performance requirements, a single chip is often difficult to meet all requirements. Therefore, the use of multi-chip collaborative solutions has become a common practice. In a multi-chip system, how to reliably and efficiently realize data communication and transmission between chips is an urgent problem to be solved. Summary of the invention

[0003] In response to the above-mentioned problems, the embodiments of the present application provide a data processing method, device, chip and storage medium, which can realize reliable data communication and transmission between dual chips and improve computing power compared to single-chip design.

[0004] In a first aspect, an embodiment of the present application provides a data processing method, wherein the first processor is connected to the second processor via a serial peripheral interface SPI interface and a mobile industry processor interface MIPI interface, including:

[0005] In response to obtaining first data collected by the sensor, processing the first data in a first processing manner to obtain second data;

[0006] querying whether the second processor is in an idle state through the SPI interface;

[0007] In response to the second processor being in an idle state, transmitting the second data to the second processor through the MIPI interface, so that the second processor processes the second data in a second processing manner.

[0008] In some embodiments, the method further comprises:

[0009] In response to the first processor being powered on, querying a state of the second processor through the SPI interface;

[0010] In response to the state of the second processor being an initialization completion state, sending configuration information to the second processor based on the SPI interface, so that the second processor is configured based on the configuration information, wherein the second processor can process the second data in the second processing mode when the configuration is completed.

[0011] In some embodiments, the method further comprises:

[0012] In response to obtaining an interrupt notification sent by the second processor through the SPI interface, obtaining reverse data sent by the second processor through the SPI interface, wherein the reverse data includes: a processing result of the second data;

[0013] The first processing method is adjusted based on the processing result.

[0014] In some embodiments, the method further comprises:

[0015] In response to the second processor being in a non-idle state, the second data is discarded, or, according to the prompt of the reverse data, the second data is stored, and when it is found that the second processor is in an idle state, the second data is sent to the second processor through the MIPI interface.

[0016] In a second aspect, an embodiment of the present application provides a data processing method, which is applied to a second processor, wherein the second processor is connected to the first processor through an SPI interface and a MIPI interface, including:

[0017] In response to obtaining a query sent by the first processor through the SPI interface about whether the second processor is in an idle state, sending state information to the first processor through the SPI interface;

[0018] In response to obtaining second data sent by the first processor through the MIPI interface, the second data is processed in a second processing mode, wherein the first processor sends the second data to the second processor through the MIPI interface when determining that the second processor is in an idle state, and the first processor processes the first data in a first processing mode to obtain the second data when obtaining first data collected by the sensor.

[0019] In some embodiments, the method further comprises:

[0020] In response to obtaining configuration information sent by the first processor through the SPI interface, configuration is performed based on the configuration information, wherein the first processor sends the configuration information through the SPI interface in response to the state of the second processor being an initialization completion state.

[0021] In some embodiments, the method further comprises:

[0022] In response to completing the processing of the second data in the second processing mode, an interrupt message is sent to the first processor through the SPI interface, and reverse data is sent to the first processor through the SPI interface, wherein the reverse data includes: the processing result of the second data, and the first processor adjusts the first processing mode based on the processing result.

[0023] In some embodiments, the method further comprises:

[0024] In response to the second data processing being completed, the processed second data is output.

[0025] In a third aspect, an embodiment of the present application provides a data processing device, which is applied to a first processor, wherein the first processor is connected to a second processor via a serial peripheral interface SPI interface and a mobile industry processor interface MIPI interface, including:

[0026] A first processing module, configured to, in response to acquiring first data sent by the sensor, process the first data in a first processing manner to obtain second data;

[0027] A query module, used for querying whether the second processor is in an idle state through an SPI interface;

[0028] a first sending module, configured to transmit the second data to the second processor through the MIPI interface in response to the second processor being in an idle state, so that the second processor processes the second data in a second processing manner;

[0029] A receiving module is used to receive reverse data transmitted by the second processor through the SPI interface.

[0030] In a fourth aspect, an embodiment of the present application provides a data processing device, which is applied to a second processor, wherein the second processor is connected to the first processor through an SPI interface and a MIPI interface, including:

[0031] A second sending module, configured to send status information to the first processor through the SPI interface in response to obtaining a query sent by the first processor through the SPI interface as to whether the second processor is in an idle state;

[0032] A second processing module is used for processing the second data in a second processing mode in response to obtaining the second data sent by the first processor through the MIPI interface, wherein the first processor sends the second data to the second processor through the MIPI interface when determining that the second processor is in an idle state, and the first processor processes the first data in a first processing mode to obtain the second data when obtaining the first data sent by the sensor.

[0033] A third sending module is used to provide reverse data to the first processor through the SPI interface.

[0034] In a fifth aspect, an embodiment of the present application provides a first processor, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method provided in the first aspect when executing the computer program.

[0035] In a sixth aspect, an embodiment of the present application provides a second processor, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method provided in the second aspect when executing the computer program.

[0036] In a seventh aspect, an embodiment of the present application provides a chip, comprising: the first processor provided in the fifth aspect and the second processor provided in the sixth aspect, wherein the first processor is connected to the second processor via an SPI interface and a MIPI interface.

[0037] In some embodiments, the MIPI interface uses 4 pairs of differential lines, and the SPI interface uses 4 parallel data lines.

[0038] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the method provided in the first or second aspect above is implemented.

[0039] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0040] In the data processing method provided in the embodiment of the present application, the first processor is connected to the second processor through the SPI interface and the MIPI interface, and in response to obtaining the first data collected by the sensor, the first data is processed in a first processing manner to obtain the second data; the second processor is queried through the SPI interface whether it is in an idle state; in response to the second processor being in an idle state, the second data is transmitted to the second processor through the MIPI interface, so that the second processor processes the second data in the second processing manner, which can realize reliable data communication and transmission between the two chips and can improve the computing power compared with the single-chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0042] Figure 1 A schematic diagram of the structure of a data processing system provided in an embodiment of the present application;

[0043] Figure 2 A flowchart of a data processing method provided by the present application;

[0044] Figure 3 A schematic diagram of an implementation flow of a data processing method provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of an implementation flow of a data processing method provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of the structure of the first processor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0049] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0050] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0051] As used in the specification of this application and the appended claims, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrases "if it is determined" or "if it is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce detected" or "in response to detecting" depending on the context.

[0052] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0053] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways.

[0054] Based on the technical problems of the related art, an embodiment of the present application provides a data processing method, which can be applied to a first processor, the first processor is connected to a second processor through a serial peripheral interface (SPI, Serial Peripheral Interface) line and a mobile industry processor interface (MIPI, Mobile Industry Processor Interface) line, Figure 1 A structural diagram of a data processing system provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the first processor is provided with an SPI interface and a MIPI interface, the second processor is provided with an SPI interface and a MIPI interface, the SPI interface on the first processor is connected to the SPI interface on the second processor via an SPI line, and the MIPI interface on the first processor is connected to the MIPI interface on the second processor via a MIPI line. The first processor and the second processor can communicate bidirectionally via the SPI interface, and the first processor can transmit data to the second processor via the MIPI interface, and the MIPI interface is usually a one-way communication.

[0055] In the embodiment of the present application, SPI is a high-speed, full-duplex synchronous communication bus with a simple hardware interface and a flexible communication protocol. It is suitable for short-distance, low-speed data communication, while MIPI is an interface standard designed specifically for mobile devices. It supports high-speed, low-power data transmission, and is particularly suitable for the transmission of large amounts of data such as images and videos.

[0056] In the embodiment of the present application, the first processor can be considered as the main processor, the second processor can be considered as the slave processor, the first processor can be connected to at least one sensor, the second processor can also be connected to the sensor, the second processor is connected to the host and transmits the processing result to the host, and the sensor can be an image sensor. The connection between the sensor and the first processor is connected via the MIPI interface, and the connection between the sensor and the second processor is connected via the MIPI interface. The best embodiment of the present application is that the first processor and the second processor are integrated in the same chip to realize the interconnection of the two chips on the chip.

[0057] The present application embodiment provides a data processing method. Figure 2 The present application provides a flowchart of a data processing method, such as Figure 2 As shown, the method includes:

[0058] Step S101, in response to obtaining first data collected by a sensor, the first data is processed in a first processing manner to obtain second data.

[0059] In the embodiment of the present application, the first data may be image data or a physical quantity detected by a sensor. The first data is raw data directly collected and output by the sensor. The first processing method may be an algorithm for performing preliminary processing, and the first processing method may include one or more processing of filtering, calibration, data format conversion, resolution adjustment, etc.

[0060] In the embodiment of the present application, compared with the first data, the second data may be more accurate, clear, and more suitable for subsequent analysis or processing.

[0061] Step S102: query via the SPI interface whether the second processor is in an idle state.

[0062] In the embodiment of the present application, the first processor can send a query instruction to the second processor through the SPI interface to check whether the second processor is in an idle state. The second processor can send a response signal to the first processor through the SPI interface according to the current working state to indicate whether it is idle.

[0063] Step S103, in response to the second processor being in an idle state, transmitting the second data to the second processor through the MIPI interface, so that the second processor processes the second data in a second processing manner.

[0064] In the embodiment of the present application, when the second processor is in an idle state, the main chip transmits the second data to the second processor via the MIPI interface. The high speed and low power consumption characteristics of the MIPI interface ensure efficient and reliable transmission of the second data.

[0065] In the embodiment of the present application, the second processing method may be to perform in-depth analysis and decision-making on the second data. The in-depth analysis may be: identifying targets in the second data, and the decision may be: formulating relevant strategies based on the second data.

[0066] Step S104: receiving reverse data transmitted by the second processor through the SPI interface.

[0067] The data processing method provided in the embodiment of the present application is as follows: the first processor is connected to the second processor through the SPI interface and the MIPI interface; in response to obtaining the first data collected by the sensor, the first data is processed in a first processing manner to obtain the second data; the second processor is queried through the SPI interface whether it is in an idle state; in response to the second processor being in an idle state, the second data is transmitted to the second processor through the MIPI interface, so that the second processor processes the second data in the second processing manner; the reverse data transmitted by the second processor is received through the SPI interface, thereby realizing reliable data communication and transmission between the two chips, and improving the computing power compared to the single-chip design.

[0068] In some embodiments, before step S101, the method further includes:

[0069] Step S1011, in response to the first processor being powered on, querying the status of the second processor through the SPI interface.

[0070] In the embodiment of the present application, if the first processor is in the electronic device, when the electronic device is powered on, the first processor is powered on, and the second processor is also powered on at the same time. After the first processor is powered on and completes its basic initialization, the current state of the connected second processor is queried through the SPI interface. The first processor sends a state query instruction to the second processor through the SPI interface and waits for a response from the second processor.

[0071] Step S1012, in response to the state of the second processor being the initialization completion state, sending configuration information to the second processor based on the SPI interface, so that the second processor is configured based on the configuration information, wherein the second processor can process the second data in the second processing mode when the configuration is completed.

[0072] In an embodiment of the present application, after receiving the status query instruction, the second processor will check its own initialization status. If the second processor has completed initialization (including hardware initialization, software loading, etc.), the second processor will send a response signal indicating "initialization completed" to the first processor through the SPI interface. The first processor confirms through the response signal that the second processor has been initialized, and sends configuration information to the second processor through the SPI interface. The configuration information may include one or more of the operating mode, processing parameters, communication protocol, data transmission format, data format, etc. of the second processor. The data transmission format can be the amount of data, size, etc. of each frame, and the data format is: data header + data address + data packet. In an embodiment of the present application, the sending of configuration information usually follows a specific format and protocol to ensure the accuracy and integrity of the data.

[0073] Exemplarily, the data header head includes: frame count (frame count) + size (size), the data address (dataaddr) includes: sensor data 0 offset (sensor_data0_offset), sensor data 1 offset (sensor_data1_offset), NPU0 output offset (npu0_output_offset), NPU1 output offset (npu1_output_offset), sensor data 0 size (sensor_data0_size), sensor data 1 size (sensor_data1_size), NPU0 output size (npu0_output_size), NPU1 output size (pu1_output_sizedata).

[0074] In the embodiment of the present application, after receiving the configuration information, the second processor adjusts its internal settings and parameters according to the information. The configuration process may include steps such as setting registers and loading firmware. Once the second processor is configured, it has the ability to process the second data.

[0075] In some embodiments, step S104 includes:

[0076] In response to obtaining an interrupt notification sent by the second processor through the SPI interface, reverse data sent by the second processor is obtained through the SPI interface, wherein the reverse data includes: a processing result of the second data.

[0077] In an embodiment of the present application, when the second processor has processed the second data, an interrupt notification is sent to the first processor through the SPI interface. The interrupt notification is a signal used to inform the first processor that the second processor has completed the processing of the second data. After receiving the interrupt notification, the first processor will know that the second processor is ready to send reverse data. The first processor reads reverse data from the second processor through the SPI interface. These reverse data include the processing results of the second processor on the second data, status information, error information or other related data.

[0078] In some embodiments, after step S104, the method further includes:

[0079] Step S105: adjusting the first processing method based on the processing result.

[0080] After obtaining the processing result of the second processor, the first processor may adjust the first processing method according to the processing result. Adjusting the first processing method may include changing the data processing algorithm, adjusting parameter settings, optimizing the workflow, etc. The adjustment is to improve the accuracy, efficiency or adaptability of data processing to meet the functional requirements of the first processor or optimize performance.

[0081] Exemplarily, when the processing result indicates that the image recognition effect is poor, the first processor may improve the resolution of the image through an algorithm.

[0082] According to the method provided in the embodiment of the present application, after the second processor completes processing, the second processor uses the SPI interface to send reverse data or other necessary information to the first processor device, thereby forming a complete data closed loop and realizing collaborative work between the two chips.

[0083] In some embodiments, after step S102, the method further includes:

[0084] Step S106, in response to the second processor being in a non-idle state, discarding the second data, or storing the second data, and sending the second data to the second processor through the MIPI interface when it is found that the second processor is in an idle state.

[0085] In an embodiment of the present application, the second processor being in a non-idle state may be the second processor being in a busy state, and the second processor may be processing other data. At this time, the second data can be directly discarded, and the complexity and processing delay of the system can be reduced by discarding the second data. In some embodiments, the second data can be stored in the internal memory of the first processor. Storing data can ensure the integrity of the data and transmit it when the second processor becomes idle. This method requires the first processor to have sufficient storage space to temporarily store data, and a mechanism for managing storage and retrieval of data is required. After storing the second data, the first processor needs to query the status of the second processor regularly or asynchronously through the SPI interface. When it is detected that the second processor becomes idle, the first processor can prepare to send the previously stored data. The first processor sends the previously stored second data to the second processor via the MIPI interface.

[0086] In another embodiment, in step S106, the first processor responds to the second processor being in a non-idle state and stores the second data according to the prompt of the reverse data, and when it is found that the second processor is in an idle state, the stored second data is preferentially sent to the second processor through the MIPI interface. For example, when the first processor is an ISP processor, the second processor is an AI processor, and the first data is the initial image data sent by the image sensor, then the second data is the image data processed by the ISP processor, and the reverse data includes the ROI detection result of the AI ​​processor, so when the reverse data indicates abnormal information such as detecting a moving target, after receiving the reverse data, even if the second processor is found to be busy, the first processor will not discard the second data, but store it in a separately configured memory, and when the second processor is detected to be in an idle state next time, the stored second data is preferentially sent to the second processor for processing, until the reverse data indicates that the abnormal information is lost, the frame loss processing will continue, this method can not only reduce the storage space and the amount of data processing, but also reduce the complexity and processing delay of the system, and improve the data processing efficiency.

[0087] Based on the foregoing embodiments, an embodiment of the present application provides a data processing method that can be applied to a second processor, wherein an SPI interface and a MIPI interface are provided on the first processor, and an SPI interface and a MIPI interface are provided on the second processor, the SPI interface on the first processor is connected to the SPI interface on the second processor via an SPI line, and the MIPI interface on the first processor is connected to the MIPI interface on the second processor via a MIPI line, Figure 3 A schematic diagram of the implementation flow of a data processing method provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, including:

[0088] Step S301, in response to obtaining a query from the first processor via the SPI interface about whether the second processor is in an idle state, status information is sent to the first processor via the SPI interface.

[0089] In an embodiment of the present application, after processing the first data, the first processor can send a query request to the second processor through the SPI interface to check whether the second processor is in an idle state. After receiving the query request, the second processor will evaluate its current state and send status information to the first processor through the SPI interface. The status information may be a simple flag bit or a more complex status code to indicate whether the second processor is idle, busy, or in a specific operating mode.

[0090] Step S302, in response to obtaining the second data sent by the first processor through the MIPI interface, processing the second data in a second processing mode, wherein the first processor sends the second data to the second processor through the MIPI interface when determining that the second processor is in an idle state, and the first processor processes the first data in the first processing mode to obtain the second data when obtaining the first data collected by the sensor.

[0091] In the embodiment of the present application, after determining that the second processor is in an idle state, the first processor sends the second data to the second processor through the MIPI interface. After receiving the second data, the second processor processes the data according to a preset second processing method.

[0092] Step S303: providing reverse data to the first processor via the SPI interface.

[0093] The data processing method provided in the embodiment of the present application sends status information to the first processor through the SPI interface in response to obtaining a query from the first processor through the SPI interface as to whether the second processor is in an idle state; in response to obtaining second data sent by the first processor through the MIPI interface, the second data is processed in a second processing manner, thereby realizing reliable data communication and transmission between the two chips and improving computing power compared to a single-chip design.

[0094] In some embodiments, before step S301, the method further includes:

[0095] Step S3011, in response to obtaining configuration information sent by the first processor through the SPI interface, performing configuration based on the configuration information, wherein the first processor sends the configuration information through the SPI interface in response to the state of the second processor being an initialization completed state.

[0096] In the embodiment of the present application, after detecting that the second processor has entered the initialization completion state, the first processor will send configuration information to the second processor through the SPI interface. Before sending the configuration information, the first processor needs to query the state of the second processor through the SPI interface to ensure that it is in a state where it can receive the configuration information. After receiving the configuration information, the second processor will configure its own hardware and software according to the information.

[0097] In some embodiments, step S303 may be implemented by the following steps:

[0098] In response to completing the processing of the second data in the second processing mode, an interrupt message is sent to the first processor via the SPI interface, and reverse data is sent to the first processor via the SPI interface, wherein the reverse data includes: the processing result of the second data, and the first processor adjusts the first processing mode based on the processing result.

[0099] In an embodiment of the present application, the second processor will send an interrupt message to the first processor through the SPI interface. The interrupt message is a signal used to inform the first processor that the second processor has completed processing the second data and is ready to send the processing results. After sending the interrupt message, the second processor will then send reverse data to the first processor through the SPI interface. The reverse data includes the processing results of the second data. After receiving the reverse data, the first processor will parse the data to obtain the processing results of the second data. Based on the processing results, the first processor may adjust the first processing method. For example, when the reverse data prompts the second processor to detect ROI information, the first processor can perform window cropping on the received first data according to the position of the ROI information prompted in the reverse data, enlarge the resolution of the corresponding position, and perform other processing. In addition, the first processor can also adjust the configuration information of the second processor through the SPI interface based on the adjusted first data processing method, and the second processor adjusts the second processing method based on the adjusted configuration information.

[0100] In some embodiments, after step S303, the method further includes:

[0101] Step S304: in response to the second data processing being completed, output the processed second data.

[0102] In the embodiment of the present application, the processed second data can be output to the host. The output processed data can be used by the host.

[0103] Based on the foregoing embodiments, an embodiment of the present application further provides a data processing method, which is applied to a chip, the chip comprising: a first processor and a second processor, the first processor being connected to the second processor via an SPI interface and a MIPI interface, Figure 4 A schematic diagram of the implementation flow of a data processing method provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the method includes:

[0104] Step S401: power on the first processor and the second processor.

[0105] In the embodiment of the present application, the second processor exits the initialization state after being powered on successfully and initialized successfully.

[0106] Step S402: The first processor queries the initialization state of the second processor.

[0107] In the embodiment of the present application, when the first processor inquires that the second processor has been initialized, step S403 is executed.

[0108] Step S403: the first processor configures the second processor.

[0109] In the embodiment of the present application, the configuration content includes: MIPI data transmission format and data format, wherein the MIPI data transmission format specifies the amount and size of each frame of data; the data format can be: head+addr+data.

[0110] Step S404: the first processor completes processing of one frame of data.

[0111] Step S405: the first processor queries the state machine of the second processor.

[0112] In the embodiment of the present application, the state machine includes: an initialization state, a busy state, and an idle state. When it is found that the state of the second processor is the idle state, the data is sent to the second processor through the MIPI interface.

[0113] Step S406: the second processor starts data processing.

[0114] In the embodiment of the present application, the second processor starts to process data after receiving a signal from the Slave indicating that a frame of image data has started to be transmitted.

[0115] Step S407: the second processor sends an interrupt notification to the first processor.

[0116] Step S408: the first processor reads reverse data via SPI.

[0117] In the embodiment of the present application, the reverse data address needs to be agreed upon. Reverse data: data header and data packet, wherein the data header includes: defining the data packet size, data type, slave status, etc., and the data packet: customizing the protocol according to the application.

[0118] Step S409: the second processor outputs the processed data.

[0119] In the embodiment of the present application, the second processor can use ISP to debug the MIPI transmitter (TX) for data transmission. After step S409, continue to execute step S404.

[0120] In the method provided in the embodiment of the present application, the physical interface uses SPI as a data communication interface and MIPI as a data transmission interface; the first processor transmits the processed data and image data to the second processor via MIPI, and after the second processor completes the processing, it uses SPI to transfer the reverse data to the first processor, thereby completing the data closed loop between the dual chips and doubling the on-chip computing power and resources.

[0121] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0122] According to the aforementioned embodiments, the embodiments of the present application provide a data processing device, and the modules included in the device and the units included in the modules can be implemented by a processor in a computer device; of course, they can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU, Central Processing Unit), a microprocessor (MPU, Microprocessor Unit), a digital signal processor (DSP, Digital Signal Processing) or a field programmable gate array (FPGA, Field Programmable Gate Array), etc.

[0123] A data processing device provided in an embodiment of the present application is applied to a first processor, wherein the first processor is connected to a second processor via a serial peripheral interface SPI interface and a mobile industry processor interface MIPI interface. Figure 5 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the data processing device 500 includes:

[0124] A first processing module 501 is used for, in response to obtaining first data sent by the sensor, processing the first data in a first processing manner to obtain second data;

[0125] A first query module 502, used to query whether the second processor is in an idle state through the SPI interface;

[0126] A first sending module 503 is used for transmitting the second data to the second processor through the MIPI interface in response to the second processor being in an idle state, so that the second processor processes the second data in a second processing manner;

[0127] The first receiving module 504 is configured to receive reverse data transmitted by the second processor through the SPI interface.

[0128] In some embodiments, the data processing apparatus further includes:

[0129] A second query module, configured to query the state of the second processor via the SPI interface in response to the first processor being powered on;

[0130] The configuration sending module is used to send configuration information to the second processor based on the SPI interface in response to the state of the second processor being an initialization completion state, so that the second processor is configured based on the configuration information, wherein the second processor can process the second data in a second processing mode when the configuration is completed.

[0131] In some embodiments, the data processing apparatus further includes:

[0132] A receiving module, configured to obtain reverse data sent by the second processor through the SPI interface in response to obtaining an interrupt notification sent by the second processor through the SPI interface, wherein the reverse data includes: a processing result of the second data;

[0133] The adjustment module is used to adjust the first processing method based on the processing result.

[0134] In some embodiments, the data processing apparatus further includes:

[0135] The third processing module is used to discard the second data in response to the second processor being in a non-idle state, or, according to the prompt of the reverse data, store the second data, and send the second data to the second processor through the MIPI interface when it is found that the second processor is in an idle state.

[0136] Based on the above implementations, an embodiment of the present application further provides a data processing device, which is applied to a second processor, and the second processor is connected to the first processor through an SPI interface and a MIPI interface, including:

[0137] A second sending module, configured to send status information to the first processor through the SPI interface in response to obtaining a query sent by the first processor through the SPI interface as to whether the second processor is in an idle state;

[0138] A second processing module is configured to, in response to obtaining second data sent by the first processor through the MIPI interface, process the second data in a second processing manner, wherein the first processor sends the second data to the second processor through the MIPI interface when determining that the second processor is in an idle state, and the first processor processes the first data in the first processing manner to obtain the second data when obtaining the first data sent by the sensor;

[0139] A third sending module is used to provide reverse data to the first processor through the SPI interface.

[0140] In some embodiments, the data processing apparatus further includes:

[0141] The configuration module is used to perform configuration based on the configuration information in response to obtaining the configuration information sent by the first processor through the SPI interface, wherein the first processor sends the configuration information through the SPI interface in response to the state of the second processor being the initialization completion state.

[0142] In some embodiments, the data processing apparatus further includes:

[0143] The second sending module is used to send interrupt information to the first processor through the SPI interface in response to the completion of processing the second data in the second processing mode, and send reverse data to the first processor through the SPI interface, wherein the reverse data includes: the processing result of the second data, and the first processor adjusts the first processing mode based on the processing result.

[0144] In some embodiments, the data processing apparatus further includes:

[0145] The output module is used to output the processed second data in response to the completion of the second data processing.

[0146] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0147] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0148] Figure 6 This is a schematic diagram of the structure of the first processor provided in the embodiment of the present application. Figure 6 As shown, the first processor 3 of this embodiment may include: at least one processor 30 ( Figure 6 Only one processor 30 is shown in the figure), a memory 31, and a computer program 32 stored in the memory 31 and executable on at least one processor 30. When the processor 30 executes the computer program 32, the steps in any of the above-mentioned method embodiments are implemented; or, when the processor 30 executes the computer program 32, the functions of the modules / units in the above-mentioned device embodiments are implemented.

[0149] Exemplarily, the computer program 32 may be divided into one or more modules / units, one or more modules / units are stored in the memory 31, and are executed by the processor 30 to complete the present application. The one or more modules / units may be a series of computer program 32 instruction segments capable of completing a specific function, and the instruction segments are used to describe the execution process of the computer program 32 in the first processor 3.

[0150] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0151] An embodiment of the present application provides a computer program product. When the computer program product runs on a first processor, the first processor can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0152] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. According to this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program 32, and the computer program 32 can be stored in a computer-readable storage medium. When the computer program 32 is executed by the processor 30, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program 32 includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying the computer program code to the terminal, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, RandomAccess Memory), an electric carrier signal, a telecommunication signal and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0153] An embodiment of the present application further provides a second processor, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps in each method when executing the computer program.

[0154] Based on the foregoing embodiments, an embodiment of the present application provides a chip, including: a first processor and a second processor, wherein the first processor is connected to the second processor via an SPI interface and a MIPI interface.

[0155] In some embodiments, the MIPI interface uses 4 pairs of differential lines and the SPI interface uses 4 parallel data lines.

[0156] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0157] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0158] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0159] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0160] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

[0161] The relevant user personal information that may be involved in the various embodiments of this application is strictly in accordance with the requirements of laws and regulations, following the principles of legality, legitimacy and necessity, based on the reasonable purposes of business scenarios, to process the personal information that users actively provide during the use of products / services or generated due to the use of products / services, as well as the personal information obtained with the user's authorization.

[0162] The user personal information processed by the applicant will vary depending on the specific product / service scenario, and shall be based on the specific scenario in which the user uses the product / service, which may involve the user's account information, device information, driving information, vehicle information or other related information. The applicant will treat the user's personal information and its processing with a high degree of diligence.

[0163] The Applicant attaches great importance to the security of user personal information and has adopted reasonable and feasible security protection measures that comply with industry standards to protect user information and prevent personal information from being accessed, disclosed, used, modified, damaged or lost without authorization.

Claims

1. A data processing method, characterized in that: Applied to a first processor, the first processor is connected to a second processor via an SPI interface and a MIPI interface, the method comprising: In response to obtaining first data collected by the sensor, processing the first data in a first processing manner to obtain second data; querying whether the second processor is in an idle state through the SPI interface; In response to the second processor being in an idle state, transmitting the second data to the second processor through the MIPI interface, so that the second processor processes the second data in a second processing manner and provides reverse data; The reverse data transmitted by the second processor is received through the SPI interface.

2. The method according to claim 1, characterized in that The method further comprises: In response to the first processor being powered on, querying a state of the second processor through the SPI interface; In response to the state of the second processor being an initialization completion state, sending configuration information to the second processor based on the SPI interface, so that the second processor is configured based on the configuration information, wherein the second processor can process the second data in the second processing mode when the configuration is completed.

3. The method according to claim 1, characterized in that The receiving, through the SPI interface, reverse data transmitted by the second processor comprises: In response to obtaining an interrupt notification sent by the second processor through the SPI interface, obtaining reverse data sent by the second processor through the SPI interface, wherein the reverse data includes: a processing result of the second data; The method further comprises: The first processing method is adjusted based on the processing result.

4. The method according to claim 1, characterized in that: The method further comprises: In response to the second processor being in a non-idle state, the second data is discarded, or the second data is stored, and when it is found that the second processor is in an idle state, the second data is sent to the second processor through the MIPI interface.

5. The method according to claim 1, characterized in that The method further comprises: In response to the second processor being in a non-idle state and according to the prompt of the reverse data, the second data is stored, and when it is found that the second processor is in an idle state, the stored second data is preferentially sent to the second processor through the MIPI interface for processing.

6. The method according to claim 2, characterized in that The method further comprises: According to the prompt of the reverse data, the first processor adjusts the first processing mode, and adjusts the configuration information to the second processor through the SPI interface, so that the second processor adjusts the second processing mode accordingly based on the adjusted configuration information.

7. A data processing method, characterized in that: Applied to a second processor, the second processor is connected to the first processor via an SPI interface and a MIPI interface, comprising: In response to obtaining a query sent by the first processor through the SPI interface about whether the second processor is in an idle state, sending state information to the first processor through the SPI interface; In response to obtaining second data sent by the first processor through the MIPI interface, processing the second data in a second processing manner, wherein the first processor sends the second data to the second processor through the MIPI interface when determining that the second processor is in an idle state, and the first processor processes the first data in a first processing manner when obtaining first data collected by the sensor to obtain the second data; Reverse data is provided to the first processor via the SPI interface.

8. The method according to claim 7, characterized in that The method further comprises: In response to obtaining configuration information sent by the first processor through the SPI interface, configuration is performed based on the configuration information, wherein the first processor sends the configuration information through the SPI interface in response to the state of the second processor being an initialization completion state.

9. The method according to claim 7, characterized in that: Providing reverse data to the first processor through the SPI interface includes: In response to completing the processing of the second data in the second processing mode, an interrupt message is sent to the first processor through the SPI interface, and reverse data is sent to the first processor through the SPI interface, wherein the reverse data includes: the processing result of the second data, and the first processor adjusts the first processing mode based on the processing result.

10. The method according to claim 9, characterized in that The method further comprises: In response to the second data processing being completed, the processed second data is output.

11. The method according to claim 8, characterized in that The method further comprises: The configuration information adjusted by the first processor based on the reverse data is received through the SPI interface, and the second processing mode is adjusted accordingly.

12. A data processing device, characterized in that: Applied to a first processor, the first processor is connected to a second processor via an SPI interface and a MIPI interface, comprising: A first processing module, configured to, in response to acquiring first data sent by the sensor, process the first data in a first processing manner to obtain second data; A first query module, used for querying whether the second processor is in an idle state through an SPI interface; a first sending module, configured to transmit the second data to the second processor through the MIPI interface in response to the second processor being in an idle state, so that the second processor processes the second data in a second processing manner; The first receiving module is used to receive reverse data transmitted by the second processor through the SPI interface.

13. A data processing device, characterized in that: Applied to a second processor, the second processor is connected to the first processor via an SPI interface and a MIPI interface, comprising: A second sending module, configured to send status information to the first processor through the SPI interface in response to obtaining a query sent by the first processor through the SPI interface as to whether the second processor is in an idle state; A second processing module, configured to, in response to obtaining second data sent by the first processor through the MIPI interface, process the second data in a second processing manner, wherein the first processor sends the second data to the second processor through the MIPI interface when determining that the second processor is in an idle state, and the first processor processes the first data in a first processing manner when obtaining first data sent by the sensor to obtain the second data; A third sending module is used to provide reverse data to the first processor through the SPI interface.

14. A first processor, comprising: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 6 when executing the computer program.

15. A second processor, characterized in that: include: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 7 to 11 when executing the computer program.

16. A chip, characterized in that: include: The first processor of claim 14 and the second processor of claim 15, wherein the first processor is connected to the second processor via an SPI interface and a MIPI interface.

17. The chip according to claim 16, characterized in that: The MIPI interface is connected using 4 pairs of differential lines, and the SPI interface is connected using 4 parallel data lines.

18. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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