FPGA IP core system supporting parallel analysis of multiple protocols

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) IP (Intellectual Property) core system supporting parallel analysis of multiple protocols, which comprises a plurality of IP cores, and the plurality of IP cores are cascaded through an IP core connection bus to form an FPGA software system capable of simultaneously analyzing the multiple protocols in parallel. The method is used for analyzing data sent by satellite-borne equipment, rapidly adapting to various communication protocols, extracting specific information, rapidly constructing a test environment and improving interface test sufficiency.

Description

Technical Field

[0001] The present invention relates to the field of software evaluation, and in particular to an FPGA IP core system that supports parallel parsing of multiple protocols. The system can be used to construct an interface test environment in the development phase of satellite equipment, and to achieve deep customization of requirements and rapid progress delivery. Background Art

[0002] The communication protocols between satellite devices are generally private protocols, lacking unified standards across manufacturers and models. The traditional method is to develop customized software programs to parse the communication protocols negotiated by the communicating parties. This usually faces the following difficulties: (1) General parsing software is implemented using CPU software, and the protocol parsing speed is slow; (2) Customized parsing software has slow communication protocol negotiation and many iterative versions, and available parsing software cannot be obtained immediately.

[0003] During the development phase, satellite-borne equipment will be tested by the developer before being handed over to the satellite for overall integration. However, due to the development progress and customization, the construction of its test environment is very hasty and crude, making it difficult to build complex interface test scenarios. During the satellite integration phase, the interface environment when the equipment is working is quite different from the interface environment simulated by the test environment during the development phase, which is reflected in the change from exclusive work to full parallel work, and from focusing on some key data to focusing on all interface data. These changes are reflected in the result that untested parallel interface working scenarios and untested and confirmed interface data are prone to expose problems. The root cause is the insufficient capabilities of the interface test environment, which leads to insufficient interface testing.

[0004] With the rise of commercial spaceflight and the in-depth advancement of satellite industrialization, the development of satellite equipment faces the dual contradictions of deep customization and rapid delivery. In terms of quality and progress, it is required to be able to carry out sufficient and rapid testing during the equipment development stage. Therefore, the technology for rapid construction of the test environment is very urgent.

[0005] IP core means intellectual property core or intellectual property module, which plays a very important role in EDA technology development. The famous American Dataquest consulting company defines IP in the semiconductor industry as "pre-designed circuit function modules used in ASIC or FPGA". IP is mainly divided into soft IP, solid IP and hard IP. Soft IP is a functional block described in hardware description languages ​​such as Verilog / VHDL, but does not involve what specific circuit elements are used to implement these functions. Solid IP is a functional block that has completed the synthesis. Hard IP provides the final stage product of the design - the mask.

[0006] FPGA (Field-Programmable Gate Array) is a field-programmable gate array, which is a further development of programmable devices such as PAL, GAL, CPLD, etc. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices. Summary of the invention

[0007] In view of the problems existing in the prior art, the present invention provides an FPGA IP core system that supports parallel parsing of multiple protocols, which is used to parse data sent by satellite-borne equipment, quickly adapt to multiple communication protocols, extract specific information, quickly build a test environment, and improve the adequacy of interface testing.

[0008] The technical solution of the present invention is: an FPGA IP core system supporting parallel parsing of multiple protocols, including multiple IP cores, which are cascaded through an IP core connection bus to form an FPGA software system capable of simultaneously and parallelly parsing multiple protocols.

[0009] Furthermore, an instantiation interface is provided; the instantiation interface is used to determine the configuration of the maximum capability range of the IP during the FPGA software implementation process, and its configuration affects the physical resources occupied by the IP core;

[0010] Equipped with a register interface, the register interface is used to read and write registers inside the IP core;

[0011] Equipped with an input FIFO, the input data of the input FIFO is input through the data input interface, then read out through the reading control module, and then sent to the data analysis module and the bypass data output interface respectively after being read out; the depth and width of the FIFO can be configured through the instantiation interface;

[0012] Equipped with a frame FIFO, the frame FIFO is used to store a complete and valid frame of data, and its output is output through the valid data output interface; the depth and width of the cache can be configured through the instantiation interface, the depth of the frame FIFO is greater than or equal to the length of a frame of data, and the length of a frame of data = frame bit length / slice word length;

[0013] Equipped with registers, the contents of which can be changed at any time according to user needs during the software operation, and the scope of the configuration is subject to the instantiation configuration limit; each IP core contains at least 4 types of registers: the first type is frame description; the second type is sub-condition setting; the third type is sub-condition relationship; the fourth type is IP core description register; the frame description register describes the structure of the frame format through the configuration of the register; the sub-condition setting register is used to describe the trigger condition; the sub-condition relationship register is used to describe how multiple sub-conditions form the final trigger condition; the IP core description register can be read externally to obtain the maximum capability of the IP core, providing a basis for users to configure the IP core at runtime;

[0014] Equipped with a register read-write interface, the register read-write interface is used to read and write registers;

[0015] Equipped with a data input interface, the data input interface is used for data input FIFO interface signal;

[0016] Equipped with a trigger notification interface, the trigger notification includes (a) valid frame notification; (b) trigger success notification; (c) trigger sub-condition trigger notification, one sub-condition corresponds to one notification; (d) sub-condition trigger information, one sub-condition corresponds to one information;

[0017] Equipped with frame data output interface;

[0018] Equipped with bypass data output interface, bypass data will appear at the output end only when the input FIFO data is read out, and the output end interface signal is the standard FIFO interface signal;

[0019] It is equipped with a data analysis module, which analyzes the data output by the reading control module according to the instantiated interface configuration and register configuration. If a complete frame of data is obtained, the complete frame data is written into the frame FIFO and a valid frame notification is generated; if a sub-condition is met, the corresponding sub-condition trigger notification and sub-condition trigger information are output; if all sub-conditions are met and the sub-condition relationship meets the sub-condition connection relationship specified by the register configuration, a trigger success notification is output.

[0020] Furthermore, the instantiation configuration includes instantiation configuration parameters related to the verification algorithm, and supports data accumulation and verification, XOR verification and CRC verification.

[0021] The beneficial effect of the present invention is to provide an FPGA IP core system that supports parallel parsing of multiple protocols, and its innovation lies in:

[0022] 1. Use FPGA programming to implement multi-protocol analysis, which can achieve low-latency analysis compared to CPU software;

[0023] 2. Multi-protocol parsing can be achieved through instantiation configuration and register configuration without changing the code, which can support:

[0024] a) Support different data bit widths by configuring the FIFO width;

[0025] b) Support different data flows by configuring FIFO depth;

[0026] c) Support customizing different frame header identifiers;

[0027] d) Supports verification methods such as cumulative sum, cyclic redundancy check, and XOR check;

[0028] e) Support different frame data lengths;

[0029] 3. It has a bypass cascade interface, which can realize multi-protocol parallel analysis through cascading. Each level can use different instantiation configurations and register configurations.

[0030] 4. During operation, the supported protocols can be changed dynamically without modifying the code;

[0031] 5. The maximum capability of the IP core can be obtained through a unified description register. The driver software can obtain the number of instantiated IP cores and their respective capabilities through initialization scanning. There is no need to modify the driver software again based on the number of IP cores and instantiation configuration.

[0032] 6. Support single condition and multiple condition combination trigger notification, and display the trigger source information at the same time.

[0033] The present invention realizes an FPGA IP core system that supports parallel parsing of multiple protocols, reduces repeated development, supports rapid construction of a test environment, and improves interface test adequacy. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of the FPGA IP core system that supports parallel parsing of multiple protocols. DETAILED DESCRIPTION

[0035] The present invention will be further described below in conjunction with the accompanying drawings.

[0036] like Figure 1 In an actual system, the FPGA IP core system supporting parallel parsing of multiple protocols shown can instantiate multiple IP cores 1 and cascade them through the IP core connection bus 15.

[0037] The instantiation interface 2 is used to determine the configuration of the maximum capability range of the IP during the software implementation process, and its configuration affects the physical resources occupied by the IP core.

[0038] Register interface 3 is used to read and write registers inside the IP core.

[0039] The input data of the input FIFO 4 is input through the data input interface 10, and then read out through the reading control module 5, and then sent to the data analysis module 14 and the bypass data output interface 13. The depth and width of the FIFO can be configured by instantiating parameters.

[0040] The frame FIFO 5 is used to store a complete and valid frame of data, and its output is output through the valid data output interface 12. The depth and width of the cache can be configured by instantiation. The depth of the frame FIFO is greater than or equal to the length of a frame of data, and the length of a frame of data = frame bit length / slice word length. Table 1 shows the instantiation configuration of the FIFO.

[0041] Table 1

[0042] Serial number Parameter meaning significance Parameter Type A Input FIFO depth Input FIFO depth Unsigned integer B Frame FIFO depth Output FIFO depth Unsigned integer C FIFO width The width of the input FIFO and frame FIFO is the same Unsigned integer

[0043] It may include multiple instantiation configuration parameters 7, including at least register parameters. Table 2 shows the instantiation configuration parameters related to the verification algorithm.

[0044] Table 2

[0045] Serial number Parameter meaning significance Parameter Type A Support accumulation and verification The IP core supports the calculation of the cumulative sum of data, and the calculation parameters are configured through registers. Boolean B Support XOR check The IP core supports XOR calculation of data, and the calculation parameters are configured through registers. Boolean C Support CRC check The IP core supports CRC calculation for data. The calculation parameters are configured through registers. Boolean

[0046] The content of register 8 can be changed at any time according to user needs during the software operation process, and the scope of its configuration is limited by the instantiation configuration; the register configuration will not affect the physical resources occupied by the IP core. The register configuration determines the exact function of the IP core. The IP core of the present invention includes at least 4 types of registers: (1) frame description; (2) sub-condition setting; (3) sub-condition relationship; (4) IP core description register.

[0047] The frame description register shown in Table 3 mainly describes the structure of the frame format through the configuration of the register.

[0048] Table 3

[0049] Serial number Parameter meaning significance Parameter Type A Frame header feature value A fixed value that appears at the top of a frame. Unsigned integer B Frame header bit length Frame header data width Unsigned integer C Checksum offset The offset position of the check field Unsigned integer D Checksum bit length Check field length Unsigned integer E Verification algorithm Verification algorithm used Unsigned integer F Verify algorithm parameters 1 Verify algorithm parameters, such as initial values Unsigned integer G Verification algorithm parameters 2 Parameters of the verification algorithm, such as the generator polynomial of CRC Unsigned integer H Verification algorithm parameters 3 Verification algorithm parameters Unsigned integer K Check unit word length For example, the cumulative sum is accumulated by 8 bits or by 16 bits. Unsigned integer L Frame length The length of the entire frame in bits Unsigned integer M Slice word length The bit width of the data bit stream after serial-to-parallel conversion Unsigned integer

[0050] The sub-condition setting register shown in Table 4 is used to describe the trigger condition.

[0051] Table 4

[0052] Serial number Parameter meaning significance Parameter Type A Trigger value Reference value for data comparison Unsigned integer B Bit offset The bit offset relative to the start of the frame, starting at 0 Unsigned integer C Bit Length The starting value is 1, 0 is invalid Unsigned integer D Comparison equal, not equal, greater than, less than, greater than or equal to, less than or equal to Unsigned integer E Data Types Signed integer, unsigned integer Unsigned integer

[0053] The sub-condition relationship register shown in Table 5 is used to describe how multiple sub-conditions form the final trigger condition.

[0054] Table 5

[0055] Parameter meaning significance Parameter Type A Connection relationship 1 and, or Unsigned integer B Connection 2 and, or Unsigned integer C Connection 3 and, or Unsigned integer D ……

[0056] The IP core description registers shown in Table 6 can be read externally to obtain the maximum capability of the IP core and provide a basis for users to configure the IP core at runtime.

[0057] Table 6

[0058] Serial number Parameter meaning significance Parameter Type A Number of triggers supported Maximum number of triggers supported Unsigned integer B Input FIFO depth Input FIFO depth Unsigned integer C Output FIFO depth Output FIFO depth Unsigned integer D FIFO width The buffer width of the input FIFO is the same as that of the output FIFO. Unsigned integer E Supported algorithm types Which data verification algorithms are supported? Unsigned integer

[0059] The register read / write interface 9 is used to read and write the register 8. Table 7 shows the register read / write interface signals.

[0060] Table 7

[0061] Serial number Parameter meaning significance Parameter Type A Chip Select This IP core enables Unsigned integer B Offset Address The register offset address to be accessed Unsigned integer C Write Enable Write data is valid Unsigned integer D Read Enable Ready to read data valid Unsigned integer E Writing Data Data to be written Unsigned integer F Read Data Read data Unsigned integer

[0062] The data input interface 10 is used for data input FIFO interface signals. Table 8 shows the data input FIFO interface signals.

[0063] Table 8

[0064] Serial number Parameter meaning significance Parameter Type A Write Clock Input, accompanying clock for write operation Unsigned integer B Write Enable Input, write data valid Unsigned integer C Writing Data Input, data to be written Unsigned integer D This level FIFO is full Output, the input FIFO in this IP core is full Unsigned integer E The current FIFO is half full Output, the input FIFO in this IP core is about to be full Unsigned integer

[0065] 11 is the trigger notification interface. The trigger notification includes (1) valid frame notification; (2) trigger success notification; (3) trigger sub-condition trigger notification, one sub-condition corresponds to one notification; (4) sub-condition trigger information, one sub-condition corresponds to one information. See Table 9.

[0066] Table 9

[0067] Serial number Parameter meaning significance Parameter Type A Valid frame notification A valid frame is parsed and the data is stored in the frame FIFO. Unsigned integer B Trigger success notification A is satisfied, and all sub-conditions are triggered successfully, and all sub-conditions are connected through "sub-condition relations", the result is true Unsigned integer C Subcondition 1-n notification The condition of sub-condition X is satisfied Unsigned integer D Subcondition 1-n trigger information The comparison value corresponding to the trigger value of sub-condition X Unsigned integer

[0068] 12 is the frame data output interface. The frame data interface signal is shown in Table 10.

[0069] Table 10

[0070] Serial number Parameter meaning significance Parameter Type A Reading the clock Input, accompanying clock for read operation Unsigned integer B Read Enable Input, ready to read data valid Unsigned integer C Read Data Input, read data Unsigned integer D Frame FIFO empty Output: No data in the frame FIFO in the local IP core Unsigned integer E Frame FIFO half empty Output, the frame FIFO in the local IP core is about to be empty Unsigned integer

[0071] 13 is the bypass data output interface. Only when the input FIFO data is read out, the bypass data will appear at the output end. The output end interface signal is the standard FIFO interface signal. Table 11 shows the bypass data output interface signal.

[0072] Table 11

[0073] Serial number Parameter meaning significance Parameter Type A Write Clock Input, accompanying clock for write operation Unsigned integer B Write Enable Input, write data valid Unsigned integer C Writing Data Input, data to be written Unsigned integer D Post-stage FIFO full Output, the input FIFO in the next-stage IP core is full Unsigned integer E Post-stage FIFO is half full Output, the input FIFO in the next-stage IP core is about to be full Unsigned integer

[0074] 14 is a data analysis module, which analyzes the data output by the reading control module 5 according to the instantiation interface 2 configuration and the register configuration 3. If a complete frame of data is obtained, the complete frame data is written into the frame FIFO6 and a valid frame notification is generated; if a sub-condition is met, the corresponding sub-condition trigger notification and sub-condition trigger information are output; if all sub-conditions are met and the sub-condition relationship meets the sub-condition connection relationship specified by the register configuration 3, a trigger success notification is output.

[0075] 15 is an IP core connection bus, which is used to cascade multiple IP cores 1 to form FPGA software that can parse multiple protocols in parallel.

[0076] The present invention realizes an FPGA IP core system that supports parallel parsing of multiple protocols, reduces repeated development, supports rapid construction of a test environment, and improves interface test adequacy.

[0077] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An FPGA IP core system that supports parallel parsing of multiple protocols, characterized by: It comprises a plurality of IP cores (1), wherein the plurality of IP cores (1) are cascaded via an IP core connection bus (15) to form an FPGA software system capable of simultaneously and in parallel parsing a plurality of protocols.

2. The FPGA IP core system supporting parallel parsing of multiple protocols according to claim 1, characterized in that: An instantiation interface (2) is provided; the instantiation interface (2) is used to determine the configuration of the maximum capability range of the IP during the FPGA software implementation process, and the configuration affects the physical resources occupied by the IP core; A register interface (3) is provided, wherein the register interface (3) is used to read and write registers inside the IP core; An input FIFO (4) is provided, wherein input data of the input FIFO (4) is input through a data input interface (10), then read out through a reading control module (5), and after being read out, respectively sent to a data analysis module (14) and a bypass data output interface (13); the depth and width of the FIFO can be configured through an instantiation interface (2); A frame FIFO (6) is provided, wherein the frame FIFO (6) is used to store a complete and valid frame of data, and the output of the frame FIFO (6) is output through a valid data output interface (12); the depth and width of the cache can be configured through an instantiation interface (2), the depth of the frame FIFO is greater than or equal to the length of a frame of data, and the length of a frame of data = frame bit length / slice word length; A register (8) is provided, the content of which can be changed at any time according to user needs during the software operation process, and the scope of its configuration is subject to the instantiation configuration limit; each IP core contains at least four types of registers: the first type is frame description; the second type is sub-condition setting; the third type is sub-condition relationship; the fourth type is IP core description register; the frame description register describes the structure of the frame format through the configuration of the register; the sub-condition setting register is used to describe the trigger condition; the sub-condition relationship register is used to describe how multiple sub-conditions form the final trigger condition; The IP core description register can be read externally to obtain the maximum capability of the IP core, providing a basis for users to configure the IP core at runtime; A register read / write interface (9) is provided, wherein the register read / write interface (9) is used to read and write the register (8); A data input interface (10) is provided, wherein the data input interface (10) is used for data input FIFO interface signals; A trigger notification interface (11) is provided, wherein the trigger notification includes (a) a valid frame notification; (b) a trigger success notification; (c) a trigger sub-condition trigger notification, where one sub-condition corresponds to one notification; and (d) a sub-condition trigger message, where one sub-condition corresponds to one message. Equipped with a frame data output interface (12); Equipped with a bypass data output interface (13), the bypass data will appear at the output end only when the input FIFO data is read out, and the output end interface signal is a standard FIFO interface signal; A data analysis module (14) is provided. The data analysis module (14) analyzes the data output by the reading control module (5) according to the instantiation interface (2) configuration and the register configuration (3). If a complete frame of data is obtained, the complete frame data is written into the frame FIFO (6) and a valid frame notification is generated; if a certain sub-condition is satisfied, the corresponding sub-condition trigger notification and sub-condition trigger information are output; if all sub-conditions are satisfied and the sub-condition relationship satisfies the sub-condition connection relationship specified by the register configuration (3), a trigger success notification is output.

3. The FPGA IP core system supporting parallel parsing of multiple protocols according to claim 2, characterized in that: The instantiation configuration includes instantiation configuration parameters related to the verification algorithm, and supports data accumulation and verification, XOR verification and CRC verification.

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