Chip, electronic equipment and low-power-consumption control method

Abstract

The invention relates to a chip, electronic equipment and a low-power-consumption control method, the chip comprises a bus, a processor, at least one target module and at least one processor low-power-consumption control module in one-to-one correspondence with the target module, the processor is connected with the bus, and the processor is connected with the processor low-power-consumption control module. Sending a power-off instruction to the target low-power-consumption control module through the bus, wherein the power-off instruction is used for requesting to power off the target module; and the target low-power-consumption control module is respectively connected with the bus and the corresponding target module, controls the target module to be disconnected from the bus in response to the power-off instruction, and controls the target module to enter a low-power-consumption mode in response to a signal that the bus is disconnected from the target module. According to the embodiment of the invention, the problem that the bus is suspended when the target module in the chip enters the low-power-consumption mode can be reduced, and the influence on the normal operation of the chip is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a chip, an electronic device, and a low power consumption control method. Background Art

[0002] With the continuous development of integrated circuit technology, chip power consumption has become one of the important indicators to measure chip performance. Especially in the design of complex system on chip (SOC), low power design is particularly important. In order to reduce power consumption, the industry has proposed a variety of low power design methods, such as clock gating and multi-power domain design. However, these methods often face some challenges when applied to large-scale SOC design.

[0003] In large-scale SOC design, different modules often need to communicate through buses. Common buses include Advanced Microcontroller Bus Architecture (AMBA) and Network on Chip (NOC). These buses connect multiple modules and undertake important tasks of data transmission and control. Traditional low-power design methods, such as directly turning off the clock and power of the module, often ignore the processing of the bus connection status, which may cause the bus to hang, thus affecting the normal operation of the entire chip. Summary of the invention

[0004] The present disclosure proposes a technical solution for low power consumption control of a chip.

[0005] According to one aspect of the present disclosure, a chip is provided, the chip comprising: a bus, a processor, at least one target module, and a low power consumption control module corresponding to the target module one by one.

[0006] The processor is connected to the bus and sends a power-off instruction to the low-power control module through the bus, wherein the power-off instruction is used to request to power off the target module;

[0007] The low power control module is connected to the bus and the corresponding target module respectively, controls the target module to be disconnected from the bus in response to the power-off instruction, and controls the target module to enter a low power mode in response to a signal that the target module has been disconnected from the bus.

[0008] In a possible implementation, the low power consumption control module includes: a target control module and an interface interaction module;

[0009] The target control module, in response to the power-off instruction, sends a disconnection signal to the interface interaction module for requesting the target module to be disconnected from the bus; and, in response to the signal that the target module has been disconnected from the bus, controls the target module to enter a low power consumption mode;

[0010] The interface interaction module controls the target module to be disconnected from the bus in response to the disconnection signal, and returns a signal to the target control module indicating that the target module has been disconnected from the bus when it is determined that the target module is disconnected from the bus.

[0011] In a possible implementation, the bus includes: a low power consumption interface LPI;

[0012] The low power consumption interface LPI, in response to a disconnection request signal from the interface interaction module, performs power-off interaction with the interface interaction module, and after determining that the connection between the target module and the bus is disconnected, sends a connection disconnection status signal to the interface interaction module, wherein the connection disconnection status signal is used to indicate that the connection between the target module and the bus is disconnected.

[0013] In a possible implementation, the interface interaction module includes a first state machine, which is used to instruct the interface interaction exchange module to perform processing corresponding to the state of the first state machine;

[0014] The interface interaction module, in response to the disconnection signal, sends a disconnection request signal to the LPI in the bus, requesting to disconnect the target module from the bus; the first state machine enters a first waiting confirmation state, waiting for a response signal from the LPI in the bus;

[0015] The interface interaction module, after entering the first waiting confirmation state, triggers the counter counting. When the counter is full but no response signal from the LPI is received, the first state machine returns to the working indication state; when the counter is not full and a response signal from the LPI is received indicating that the disconnection request signal has been received, the first state machine enters the waiting low power consumption state to wait for a connection disconnection state signal indicating that the target module has successfully disconnected.

[0016] In a possible implementation, the interface interaction module triggers a counter to count after the first state machine enters the waiting low power consumption state. When the counter is full but the LPI disconnection state signal is not received, the first state machine enters a second waiting confirmation state and prepares to return to the working indication state. When the counter is not full and the LPI disconnection state signal is received, the first state machine enters a low power consumption indication state.

[0017] When receiving the disconnection status signal, the interface interaction module confirms that the connection between the target module and the bus has been disconnected, and returns a signal indicating successful disconnection to the target control module.

[0018] In a possible implementation, the target control module controls the target module to power on in response to the received power-on instruction, and after the power-on is completed, sends a connection signal to the interface interaction module for requesting to establish a connection between the target module and the bus;

[0019] The interface interaction module controls the target module to establish a connection with the bus in response to the connection signal.

[0020] In a possible implementation, the bus includes: a low power consumption interface LPI;

[0021] The low power interface LPI, in response to the connection request signal from the interface interaction module, performs power-on interaction with the interface interaction module, and after determining that the target module and the bus are successfully connected, returns a response signal indicating that the target module and the bus are successfully connected to the interface interaction module.

[0022] In a possible implementation, the interface interaction module, in response to the connection signal, sends a connection request signal to the low power interface LPI in the bus; the first state machine enters a second waiting confirmation state, waiting for a response signal from the LPI in the bus;

[0023] The LPI in the bus, in response to receiving the connection request signal, performs corresponding processing to reconnect the target module and the bus, and returns a response signal indicating that the target module and the bus are successfully connected to the interface interaction module when confirming that the target module and the bus have been successfully reconnected;

[0024] The interface interaction module returns a power-on success signal to the target control module in response to the received response signal indicating that the target module is successfully connected to the bus;

[0025] The target control module, in response to receiving the power-on success signal, determines that the target module is restored to be connected to the bus.

[0026] In a possible implementation, the chip further includes a processor control module;

[0027] The processor generates an idle signal WFI when detecting that all target modules in the chip have been powered off;

[0028] The processor control module sends a disconnection signal for requesting to disconnect the processor from the bus to the interface interaction module based on the idle signal;

[0029] The interface interaction module controls the processor to be disconnected from the bus in response to a disconnection signal sent by the processor control module, and returns a signal to the processor control module indicating that the processor has been disconnected from the bus when it is determined that the processor is disconnected from the bus;

[0030] The processor control module controls the processor to enter a low power consumption mode in response to a signal that the processor has disconnected from the bus, thereby powering off the entire chip.

[0031] In a possible implementation, the chip further includes a processor control module;

[0032] The processor, in response to the power-off configuration of the software end, sends a power-off instruction to the processor control module and the target control module through the bus;

[0033] The target control module powers off the target module in response to the power-off instruction;

[0034] The processor control module sends a disconnection signal for requesting the processor to be disconnected from the bus to the interface interaction module when detecting that all target modules in the chip have been powered off;

[0035] The interface interaction module controls the processor to be disconnected from the bus in response to a disconnection signal sent by the processor control module, and returns a signal to the processor control module indicating that the processor has been disconnected from the bus when it is determined that the processor is disconnected from the bus;

[0036] The processor control module controls the processor to enter a low power consumption mode in response to a signal that the processor has disconnected from the bus, thereby powering off the entire chip.

[0037] In a possible implementation, the chip further includes a processor control module;

[0038] The target control module and the processor control module, in response to an external power-on instruction when the chip is turned on, control the target module and the processor to power on, and after the power-on is completed, send a connection signal to the interface interaction module for requesting the target module and the processor to establish a connection with the bus;

[0039] The interface interaction module controls the target module and the processor to establish a connection with the bus in response to a connection signal for establishing a connection between the target module and the processor and the bus.

[0040] According to one aspect of the present disclosure, a low power consumption control method is provided, which is applied to the above chip, wherein the chip comprises: a bus, a processor, at least one target module, and a low power consumption control module corresponding to the target module one by one, and the method comprises:

[0041] The processor sends a power-off instruction to the low-power control module through the bus, wherein the power-off instruction is used to request to power off the target module;

[0042] The low power consumption control module controls the target module to be disconnected from the bus in response to the power-off instruction, and controls the target module to enter a low power consumption mode in response to a signal indicating that the target module has been disconnected from the bus.

[0043] In a possible implementation, the low power control module includes: a target control module and an interface interaction module; the low power control module controls the target module to be disconnected from the bus in response to the power-off instruction, and controls the target module to enter a low power mode in response to a signal that the target module has been disconnected from the bus, including:

[0044] The target control module, in response to the power-off instruction, sends a disconnection signal to the interface interaction module for requesting the target module to be disconnected from the bus; and, in response to the signal that the target module has been disconnected from the bus, controls the target module to enter a low power consumption mode;

[0045] The interface interaction module controls the target module to be disconnected from the bus in response to the disconnection signal, and returns a signal to the target control module indicating that the target module has been disconnected from the bus when it is determined that the target module is disconnected from the bus.

[0046] In a possible implementation, the bus includes: a low power consumption interface LPI; the low power consumption control module, in response to the power-off instruction, controls the target module to be disconnected from the bus, including:

[0047] The low power consumption interface LPI, in response to a disconnection request signal from the interface interaction module, performs power-off interaction with the interface interaction module, and after determining that the connection between the target module and the bus is disconnected, sends a connection disconnection status signal to the interface interaction module, wherein the connection disconnection status signal is used to indicate that the connection between the target module and the bus is disconnected.

[0048] In a possible implementation, the interface interaction module includes a first state machine, which is used to instruct the interface interaction exchange module to perform processing corresponding to the state of the first state machine; the low power interface LPI, in response to a disconnection request signal from the interface interaction module, performs power-off interaction with the interface interaction module, including:

[0049] The interface interaction module, in response to the disconnection signal, sends a disconnection request signal to the LPI in the bus, requesting to disconnect the target module from the bus; the first state machine enters a first waiting confirmation state, waiting for a response signal from the LPI in the bus;

[0050] The interface interaction module, after entering the first waiting confirmation state, triggers the counter counting. When the counter is full but no response signal from the LPI is received, the first state machine returns to the working indication state; when the counter is not full and a response signal from the LPI is received indicating that the disconnection request signal has been received, the first state machine enters the waiting low power consumption state to wait for a connection disconnection state signal indicating that the target module has successfully disconnected.

[0051] In a possible implementation, the low power consumption interface LPI, in response to a disconnection request signal from the interface interaction module, performs power-off interaction with the interface interaction module, including:

[0052] The interface interaction module triggers a counter to count after the first state machine enters the waiting state for low power consumption. When the counter is full but the LPI disconnection state signal is not received, the first state machine enters a second waiting confirmation state and prepares to return to the working indication state; when the counter is not full and the LPI disconnection state signal is received, the first state machine enters a low power consumption indication state;

[0053] When receiving the disconnection status signal, the interface interaction module confirms that the connection between the target module and the bus has been disconnected, and returns a signal indicating successful disconnection to the target control module.

[0054] In a possible implementation, the method further includes:

[0055] The target control module controls the target module to power on in response to the received power-on instruction, and after the power-on is completed, sends a connection signal to the interface interaction module for requesting the target module to establish a connection with the bus;

[0056] The interface interaction module controls the target module to establish a connection with the bus in response to the connection signal.

[0057] In a possible implementation, the bus includes: a low power consumption interface LPI; the method further includes:

[0058] The low power interface LPI, in response to the connection request signal from the interface interaction module, performs power-on interaction with the interface interaction module, and after determining that the target module and the bus are successfully connected, returns a response signal indicating that the target module and the bus are successfully connected to the interface interaction module.

[0059] In a possible implementation manner, the power-on interaction with the interface interaction module includes:

[0060] The interface interaction module, in response to the connection signal, sends a connection request signal to the low power interface LPI in the bus; the first state machine enters a second waiting confirmation state, waiting for a response signal from the LPI in the bus;

[0061] The LPI in the bus, in response to receiving the connection request signal, performs corresponding processing to reconnect the target module and the bus, and returns a response signal indicating that the target module and the bus are successfully connected to the interface interaction module when confirming that the target module and the bus have been successfully reconnected;

[0062] The interface interaction module returns a power-on success signal to the target control module in response to the received response signal indicating that the target module is successfully connected to the bus;

[0063] The target control module, in response to receiving the power-on success signal, determines that the target module is restored to be connected to the bus.

[0064] In a possible implementation, the chip further includes a processor control module; and the method further includes:

[0065] The processor generates an idle signal WFI when detecting that all target modules in the chip have been powered off;

[0066] The processor control module sends a disconnection signal for requesting to disconnect the processor from the bus to the interface interaction module based on the idle signal;

[0067] The interface interaction module controls the processor to be disconnected from the bus in response to a disconnection signal sent by the processor control module, and returns a signal to the processor control module indicating that the processor has been disconnected from the bus when it is determined that the processor is disconnected from the bus;

[0068] The processor control module controls the processor to enter a low power consumption mode in response to a signal that the processor has disconnected from the bus, thereby powering off the entire chip.

[0069] In a possible implementation, the chip further includes a processor control module; and the method further includes:

[0070] The processor, in response to the power-off configuration of the software end, sends a power-off instruction to the processor control module and the target control module through the bus;

[0071] The target control module powers off the target module in response to the power-off instruction;

[0072] The processor control module sends a disconnection signal for requesting the processor to be disconnected from the bus to the interface interaction module when detecting that all target modules in the chip have been powered off;

[0073] The interface interaction module controls the processor to be disconnected from the bus in response to a disconnection signal sent by the processor control module, and returns a signal to the processor control module indicating that the processor has been disconnected from the bus when it is determined that the processor is disconnected from the bus;

[0074] The processor control module controls the processor to enter a low power consumption mode in response to a signal that the processor has disconnected from the bus, thereby powering off the entire chip.

[0075] In a possible implementation, the chip further includes a processor control module; and the method further includes:

[0076] The target control module and the processor control module, in response to an external power-on instruction when the chip is turned on, control the target module and the processor to power on, and after the power-on is completed, send a connection signal to the interface interaction module for requesting the target module and the processor to establish a connection with the bus;

[0077] The interface interaction module controls the target module and the processor to establish a connection with the bus in response to a connection signal for establishing a connection between the target module and the processor and the bus.

[0078] According to one aspect of the present disclosure, an electronic device is provided, comprising the above circuit provided by the present disclosure.

[0079] In the embodiment of the present disclosure, the processor is connected to the bus, and sends a power-off instruction to the low-power control module through the bus, and the power-off instruction is used to request to power off the target module; the low-power control module is connected to the bus and the corresponding target module respectively, and controls the target module to disconnect from the bus in response to the power-off instruction, and controls the target module to enter a low-power mode in response to a signal that the target module has disconnected from the bus. Thus, when the target module needs to enter a low-power state, the processor sends a power-off instruction to the target control module through the bus, requesting to power off the target module, and the low-power control module first controls the target module to disconnect from the bus, and only controls the target module to enter a low-power mode when it is determined that the target module is disconnected from the bus, and does not force the target module to enter a low-power mode when the target module is connected to the bus, thereby reducing the problem of bus deadlock when entering a low-power mode, reducing the impact on the normal operation of the chip, and improving the operating efficiency of the chip.

[0080] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0082] Figure 1 A schematic diagram showing the structure of a chip according to an embodiment of the present disclosure is shown.

[0083] Figure 2 A schematic structural diagram of another chip according to an embodiment of the present disclosure is shown.

[0084] Figure 3 A schematic structural diagram of another chip according to an embodiment of the present disclosure is shown.

[0085] Figure 4 A state transition diagram of a first state machine according to an embodiment of the present disclosure is shown.

[0086] Figure 5 The timing waveform diagram of the chip according to the embodiment of the present disclosure is shown.

[0087] Figure 6 A schematic diagram of the structure of a chip based on the NOC bus according to an embodiment of the present disclosure is shown.

[0088] Figure 7 A flow chart of a low power consumption control method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0089] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0090] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0091] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0092] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0093] In a chip, if the target module is directly controlled to enter low-power mode, the module's clock and / or power supply will be turned off, so the module will stop working and stop consuming power, which can effectively reduce power consumption. However, if the module is still connected to other modules through the bus before or during shutdown, and these other modules are still active, then these other modules may still be waiting for the response or data of the shut down target module, which will cause other modules to be in a dead waiting state and unable to continue other work. And the communication protocol of the bus usually relies on the response and synchronization of all participants. If a module is shut down and other modules still try to communicate with it through the bus, the bus cannot correctly process the signals in the communication link, causing the bus to wait indefinitely for the signal or data of the shut down module and unable to provide communication for other modules that are working normally.

[0094] Based on this, the present disclosure provides a chip to solve the problem of bus jamming when the chip enters low power consumption.

[0095] Figure 1 A schematic diagram showing the structure of a chip according to an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the chip 100 includes: a bus 101, a processor 102, at least one target module 103, and a low power consumption control module 104 corresponding to the target module 103.

[0096] The processor 102 is connected to the bus 101 and sends a power-off instruction to the low-power control module 104 through the bus 101, wherein the power-off instruction is used to request to power off the target module 103;

[0097] The low power control module 104 is connected to the bus 101 and the corresponding target module 103, respectively, and controls the target module 103 to be disconnected from the bus 101 in response to the power-off instruction, and controls the target module 103 to enter a low power mode in response to a signal that the target module 103 has been disconnected from the bus.

[0098] The bus can be a set of signal lines connecting various modules in the chip, used to transmit data, addresses and control information between modules. The bus can be a transmission medium shared between modules, and multiple modules can interact based on the bus. The bus transmits data according to certain protocols or specifications to ensure the correctness and reliability of the data.

[0099] Exemplarily, the bus may be a NOC bus, which is a network structure implemented inside a chip and used to connect various modules or processor cores on the chip to achieve efficient communication between modules. In another example, the bus may also be an advanced microcontroller bus architecture AMBA, which is an on-chip bus standard for high-performance embedded systems and is often used in SoC chips of Advanced RISC Machine (ARM). In the AMBA architecture, each module is connected to the AXI port of AMBA through an Advanced eXtensible Interface (AXI).

[0100] The target module is a functional unit or component that is controlled by low power consumption during the chip low power consumption control process. The target module can be any module on the chip that needs to be controlled to enter low power consumption, such as processor core, memory module, input / output interface, etc. During the low power consumption control process, these modules can be controlled to enter low power consumption state individually as needed, or all of them can be controlled to enter low power consumption state to put the entire chip into low power consumption state.

[0101] Exemplarily, the target module may be a processor, such as a CPU core, a GPU core, etc. In addition, the target module may also be a target module, such as a digital signal processor in a chip, various types of memories, and various types of input / output interfaces.

[0102] The low power control module is used to generate and control power-related signals to achieve low power management of the target module. The low power control module generates a control signal to shut down or adjust the power supply of the module by monitoring the status of the chip or module and receiving instructions from software or hardware, thereby controlling the power consumption of the module. In addition, the low power control module may also include a state machine to achieve low power control based on the different states of the state machine in the low power control process. For details, please refer to the possible implementation methods provided in the present disclosure, which will not be repeated here.

[0103] When the target module needs to enter a low-power state, the processor generates a power-off instruction for controlling the low-power module to trigger the subsequent logic of entering low power. Exemplarily, the processor can determine that the target module needs to enter a low-power state based on software instructions. In another example, the processor can also determine that the target module needs to enter a low-power state based on hardware status monitoring. The processor can monitor the status of the chip or the target module and generate a power-off instruction through internal logic when certain conditions are met (such as when the target module is detected to be idle).

[0104] In response to the power-off instruction, the low-power control module controls the target module to disconnect from the bus according to the preset interface protocol or specification. After determining that the connection has been disconnected, the target module is controlled to enter the low-power mode. This ensures that the connection with the bus is safely disconnected before the target module enters the low-power state, preventing problems such as bus hanging or data loss.

[0105] After receiving the signal that the target module has disconnected the bus, the low power control module controls the target module to enter the low power mode. Exemplarily, the low power control module will execute operations such as shutting down the clock and power supply of the target module according to the preset control logic to control the target module to enter the low power mode.

[0106] In the embodiment of the present disclosure, considering that multiple modules inside the chip communicate through the bus, when the target module is turned off, if the connection between the target module and the bus is not disconnected normally, other modules and buses are still trying to communicate with the target module. At this time, since the feedback signal of the target module cannot be received, other modules or buses may be in a state of continuous waiting, which may cause bus communication congestion, and then cause the bus of the entire chip system to hang, affecting the performance of the chip. Based on this, in the embodiment of the present disclosure, the processor sends a power-off instruction to the low-power control module through the bus, and the power-off instruction is used to request to power off the target module; the low-power control module is connected to the bus and the corresponding target module respectively, and controls the target module to disconnect from the bus in response to the power-off instruction, and controls the target module to enter a low-power mode in response to a signal that the target module has disconnected the bus. Therefore, when the target module needs to enter a low-power state, the processor will send a power-off instruction to the target control module through the bus, requesting to power off the target module. The low-power control module will first control the target module to disconnect from the bus. Only when it is determined that the target module is disconnected from the bus will it control the target module to enter the low-power mode. The target module will not be forcibly controlled to enter the low-power mode when the target module is connected to the bus, which reduces the problem of bus hanging when entering the low-power mode, reduces the impact on the normal operation of the chip, and improves the operation efficiency of the chip.

[0107] The above chip can be implemented as a variety of technical solutions based on different application scenarios. The possible implementation methods of the chip provided by the present disclosure are described in detail below.

[0108] Figure 2 FIG. 2 is a schematic diagram showing the structure of another chip according to an embodiment of the present disclosure. Figure 2 As shown, the low power control module 104 includes: a target control module 1042 and an interface interaction module 1041; the target control module 1042, in response to the power-off instruction, sends a disconnect signal to the interface interaction module 1041 for requesting that the target module be disconnected from the bus; and, in response to the signal that the target module has been disconnected from the bus, controls the target module to enter a low power mode; the interface interaction module 1041, in response to the disconnect signal, controls the target module to be disconnected from the bus, and when it is determined that the target module is disconnected from the bus, returns a signal that the target module has been disconnected from the bus to the target control module.

[0109] The target control module can receive instructions from the processor and control the interface interaction module to interact with the bus to control the target module to disconnect or establish a connection with the bus. In addition, the target control module can also send power-on or power-off instructions to the target control module to control the target module to power on or off.

[0110] The interface interaction module establishes the connection between the target control module and the bus. It is a bridge for interaction between the target control module and the bus. It is used to transmit the control signal of the target control module and return the connection status information of the target module to achieve interaction in the low-power control process. The interface interaction module communicates with the bus through a predefined interface. The interface interaction module converts the control signal of the target control module into instructions or signals that can be understood by the target module or bus to control operations such as disconnection of the target module from the bus.

[0111] In the disclosed embodiment, through the coordinated work of the target control module and the interface interaction module, the low power control module can accurately control the power state of the target module. The target control module is responsible for receiving the power-off instruction and triggering the interface interaction module to perform the disconnection operation with the bus, thereby ensuring that the target module is safely disconnected from the bus before entering the low power mode, reducing bus deadlock or other potential problems.

[0112] Figure 3 FIG. 2 is a schematic diagram showing the structure of another chip according to an embodiment of the present disclosure. Figure 3As shown, the bus 103 includes: a low power consumption interface 1031; the low power consumption interface LPI, in response to a disconnection request signal from the interface interaction module, performs power-off interaction with the interface interaction module, and after determining that the connection between the target module and the bus is disconnected, sends a connection disconnection status signal to the interface interaction module, and the connection disconnection status signal is used to characterize that the connection between the target module and the bus is disconnected.

[0113] The low power interface LPI is an interface on the bus, which is used to handle the interaction related to the low power state of the target module. Each target module can correspond to a low power interface LPI.

[0114] When the target module needs to enter low power mode, the interface interaction module will send a disconnect request signal to the LPI to start the power-off interaction process. In response to the disconnect request signal from the interface interaction module, the LPI disconnects the physical or logical connection between the target module and the bus, and ensures that any ongoing data transmission or communication is safely terminated. After determining that the connection between the target module and the bus has been successfully disconnected, the LPI sends a disconnection status signal to the interface interaction module.

[0115] The disconnected status signal indicates that the target module is now disconnected from the bus and is ready to enter a low power mode.

[0116] In the disclosed embodiment, power-off interaction is used to ensure that the connection between the target module and the bus can be safely disconnected and restored when entering a low-power state, thereby avoiding problems such as bus hanging due to improper handling and improving the reliability and stability of low-power control.

[0117] In addition, the target control module and the interface exchange module in the embodiment of the present disclosure can both be hardware modules. Correspondingly, in this implementation, the bus and the low power interface LPI are also hardware modules. Then, the entire low power control process is automatically completed by hardware, reducing the need for software participation, improving the efficiency and automation of power consumption management, and reducing the complexity and cost of software development.

[0118] The target control module performs power-off interaction through the interface interaction module and the LPI in the bus, realizing low-power control, simplifying the connection and communication methods between modules, and reducing the complexity and design difficulty of the circuit.

[0119] In a possible implementation, the interface interaction module includes a first state machine, which is used to instruct the interface interaction exchange module to perform processing corresponding to the state of the first state machine; the interface interaction module, in response to the disconnection signal, sends a disconnection request signal to the LPI in the bus, requesting to disconnect the target module from the bus; the first state machine enters a first waiting confirmation state, waiting for a response signal from the LPI in the bus; the interface interaction module, after entering the first waiting confirmation state, triggers a counter to count, and when the counter is full but no response signal from the LPI is received, the first state machine returns to a working indication state; when the counter is not full and a response signal from the LPI is received indicating that the disconnection request signal has been received, the first state machine enters a waiting low power consumption state, waiting for a connection disconnection state signal indicating that the target module has successfully entered a low power consumption state.

[0120] In a possible implementation, the interface interaction module triggers a counter to count after the first state machine enters the waiting low power state. When the counter is full but the LPI connection disconnection state signal is not received, the first state machine enters a second waiting confirmation state and prepares to return to the working indication state. When the counter is not full and the LPI connection disconnection state signal is received, the first state machine enters a low power indication state. When the interface interaction module receives the connection disconnection state signal, it confirms that the connection between the target module and the bus has been disconnected, and returns a signal of successful disconnection to the target control module. The first state machine enters a low power indication state, indicating that the target module has entered a low power state.

[0121] When the target control module determines that it needs to enter a low power state, a power-off instruction can be triggered. For example, the lpi_go_idle signal used to characterize the power-off instruction can be set to 1 to trigger the power-off instruction. After the interface interaction module detects the signal, a disconnection request signal can be sent to the LPI in the bus. For example, the lpi_req signal used to characterize the disconnection request signal can be set to 1 to trigger the disconnection request signal to request that the target module be placed in a low power state.

[0122] It should be noted that the disconnect request signal and the connection request signal in the embodiment of the present disclosure may be implemented by two different signals. When the signal is set to 1, it is deemed that the corresponding signal is triggered; alternatively, the disconnect request signal and the connection request signal may also be implemented by the high and low bits of the same signal (referred to as the first request signal lpi_req for ease of description). For example, when the value of the first request signal lpi_req is 1 (high bit), the disconnect request signal is triggered; and when the value of the first request signal lpi_req is 0 (low bit), the connection request signal is triggered.

[0123] The interface interaction module may include a state machine, which is referred to as the first state machine for ease of description. The state jump of the first state machine is triggered by different events. For specific state jumps, please refer to the possible implementation methods provided in the present disclosure. The state of the first state machine is used to instruct the network interaction module to perform corresponding operations in the corresponding state.

[0124] After sending the disconnect request signal, the first state machine enters the first waiting confirmation state WaitAck1, so that the interface interaction module waits for the response signal of the LPI in the bus. The response signal indicates that the LPI has received the disconnect request signal and is processing it accordingly. This ensures that the disconnect request signal is correctly received and processed to prevent inconsistent states caused by signal transmission problems.

[0125] After receiving the disconnect request signal from the interface interaction module, the LPI in the bus executes the corresponding processing of controlling the target module to enter the low power consumption state, such as disconnecting the connection between the NOC bus and the target module. After the processing is completed, the LPI in the NOC sends a response signal to the interface interaction module to confirm that the disconnect request signal has been successfully processed. For example, the lpi_idle signal used to indicate whether the processing is successful can be set to 1 to confirm that the disconnect request signal has been successfully processed.

[0126] When the interface interaction module receives the disconnection status signal of the target module (for example, the lpi_idle signal is 1), it indicates that the target module has successfully entered the low power state and the connection with the NOC bus has been disconnected. At this time, the interface interaction module can confirm that the low power interaction process is completed, and the first state machine enters the low power indication state. In the low power indication state, the interface interaction module will continue to monitor related signals so as to restore the normal working state of the target module when necessary.

[0127] In the embodiment of the present disclosure, the first state machine is used to instruct the network interaction module to perform corresponding operations in the corresponding state, and through strict interaction protocols and state management of the interface interaction module, the accurate sending and successful processing of the disconnect request signal are ensured, thereby improving the reliability and stability of the low-power control process, and being able to avoid problems such as inconsistent states or system freezes caused by signal transmission problems to a certain extent.

[0128] The first waiting confirmation state is the state that the interface interaction module first enters after sending a disconnect request signal. This state indicates that the interface interaction module has sent a disconnect request signal to the target module, but has not received any response or confirmation.

[0129] After the first state machine enters the first waiting confirmation state, the interface interaction module can start an internal counter to start timing. The counter is used to limit the waiting time for a response to prevent the interface interaction module from waiting for a response signal indefinitely, thereby avoiding potential deadlock or resource exhaustion problems.

[0130] If the counter reaches the preset threshold (i.e., "full"), and the interface interaction module still does not receive a response signal, the interface interaction module will consider that the request may not be successfully sent or received for some reason, and the first state machine will return to the work indication state (WORK state), allowing the interface interaction module to continue to perform other tasks or resend the disconnect request signal.

[0131] If the interface interaction module receives a response signal before the counter is full, indicating that the LPI has successfully received the disconnect request signal, the interface interaction module will not wait for the counter to be full, but directly control the first state machine to enter the waiting low power state. In the waiting low power state, the interface interaction module will wait for the connection disconnection state signal, and the connection disconnection state signal indicates that the target module has successfully entered the low power state.

[0132] In the disclosed embodiment, after the first state machine of the interface interaction module enters the first waiting confirmation state, by introducing a counter mechanism, the interface interaction module can avoid waiting for a long time for confirmation of the first disconnection request signal, thereby improving the responsiveness and reliability of the chip. When the request is not successfully sent or received, the first state machine returns to the working indication state in time, allowing the interface interaction module to reallocate its resources for other tasks, thereby optimizing the resource utilization in the chip low power management process, and can avoid the interface interaction module from hanging, improving the stability and reliability of the chip.

[0133] When the interface interaction module receives a power-off instruction (lpi_go_idle) from the target control module, if the power-off instruction has been received and processed by the LPI interface of the bus, the first state machine will enter the waiting low power consumption state. This state indicates that the interface interaction module is waiting for the connection disconnection state signal sent by the LPI interface, and the connection disconnection state signal indicates that the target module has successfully entered the low power consumption state.

[0134] In the waiting state for low power consumption, in order to prevent the interface interaction module from hanging due to signal transmission delay, error or other abnormal conditions, the interface interaction module will trigger a counter to start counting to implement a timeout protection mechanism. If the interface interaction module does not receive the disconnection status signal of the LPI interface before the counter is full (for example, the lpi_idle signal is always 0, indicating that the target module has not successfully entered the low power consumption state), it is considered that there may be a problem in the power-off process. At this time, the first state machine will enter the second waiting confirmation state and prepare to return to the working indication state to prevent chip instability caused by long-term hanging.

[0135] If the interface interaction module receives the disconnection status signal of the LPI interface before the counter is full (for example, the lpi_idle signal is always 1), it means that the target module has successfully entered the low power state and the connection with the bus has been disconnected. At this time, the first state machine enters the low power indication state. This state indicates that the connection between the target module and the bus has been disconnected, and the target module can now enter the low power state.

[0136] In the embodiment of the present disclosure, after the first state machine enters the waiting low power state, by introducing a counter mechanism, the first state machine can return to the previous state in time when the request is not successfully processed, thereby optimizing the resource utilization in the chip low power management process, avoiding the interface interaction module from hanging, and improving the stability and reliability of the chip.

[0137] In addition, the full count value of the counter in the embodiment of the present disclosure can be configured by software, and the circuit designer or user can adjust the timeout period according to specific needs to adapt to different application scenarios and power consumption requirements.

[0138] In one possible implementation, the target control module controls the target module to power on in response to a received power-on instruction, and after the power-on is completed, sends a connection signal to the interface interaction module requesting that the target module be connected to the bus; the interface interaction module controls the target module to establish a connection with the bus in response to the connection signal.

[0139] In this implementation, a control flow for the target module to exit the low power state is further provided. When the target module needs to resume normal operation, the target control module can initiate the processing logic for exiting low power. The target control module will first control the target module to power on. The target control module will perform operations such as enabling the clock of the target module, restoring power supply, and resetting according to the preset control logic; then instruct the interface interaction module to control the restoration of the connection between the target module and the bus, and restore the normal working state of the target module.

[0140] When the target control module detects that the target module needs to exit the low power state, it will generate a connection signal for the control interface interaction module to trigger the subsequent logic of exiting low power. Exemplarily, the target module needs to exit the low power state, which can be determined by the processor based on software instructions or based on hardware events (such as power on). For details, please refer to the possible implementation methods provided in the present disclosure, which will not be described here.

[0141] In response to the connection signal of the target control module, the interface interaction module sends a connection request signal to the target module or bus according to the preset interface protocol or specification, instructing the target module to establish a connection with the bus. Then, the connection status between the target module and the bus is monitored, and after determining that the connection has been established, a signal is returned to the target control module indicating that the target module has been connected to the bus.

[0142] In the disclosed embodiment, when the target module exits the low power consumption state, it can safely restore the connection with the bus, thereby ensuring the normal operation of the target module and improving the stability of the chip.

[0143] In one possible implementation, the bus includes: a low power consumption interface LPI; the low power consumption interface LPI, in response to a connection request signal from the interface interaction module, performs power-on interaction with the interface interaction module, and after determining that the target module and the bus are successfully connected, determines that the target module and the bus are restored to a connection state.

[0144] As mentioned above, the low power interface LPI is a part of the bus used to handle connection requests in the low power state associated with the target module. Each target module can correspond to a low power interface LPI for effective interaction.

[0145] When the target module needs to recover from low power mode and re-establish the connection with the bus, the interface interaction module sends a connection request signal to the LPI to start the power-on interaction process. After receiving the connection request signal from the interface interaction module, the LPI performs a series of interactions with the interface interaction module to ensure that the physical or logical connection between the target module and the bus can be successfully established.

[0146] After determining that the target module is successfully connected to the bus, the low-power interface returns a response signal indicating that the target module is successfully connected to the bus to the interface interaction module.

[0147] In the disclosed embodiment, the power-on interaction process ensures that the target module can safely and reliably reconnect to the bus when it recovers from the low power mode. This approach avoids bus failure or communication interruption problems that may be caused by improper connection recovery, thereby improving the stability and reliability of low power control.

[0148] In addition, the target control module, interface interaction module, bus and low power interface LPI in this embodiment are all hardware modules. That is to say, the entire connection recovery process is automatically completed by hardware, reducing the intervention of software and improving the efficiency and automation level of power consumption management. At the same time, this also reduces the complexity and cost of software development.

[0149] The target control module performs power-on interaction through the interface interaction module and the low-power interface LPI in the bus, realizing a smooth transition of the target module from low-power mode to normal working mode. This process simplifies the connection and communication mode between modules, reduces the complexity and design difficulty of the circuit, and thus improves the performance and reliability of the entire system.

[0150] In a possible implementation, the interface interaction module, in response to the connection signal, sends a connection request signal to the low power interface LPI in the bus; the first state machine enters a second waiting confirmation state, waiting for a response signal from the LPI in the bus; the LPI in the bus, in response to receiving the connection request signal, performs corresponding processing to reconnect the target module and the bus, and returns a response signal indicating that the target module and the bus are successfully connected to the interface interaction module when it is confirmed that the target module and the bus have been successfully reconnected; the interface interaction module, in response to the received response signal indicating that the target module and the bus are successfully connected, returns a power-on success signal to the target control module; the target control module, in response to receiving the power-on success signal, determines that the target module is restored to the bus.

[0151] In this implementation, a control flow for the target module to exit the low power consumption state is further provided. When the target module needs to resume normal operation, the target control module can initiate a processing logic for exiting the low power consumption state and send a connection signal to the interface interaction module.

[0152] After receiving the connection signal, the interface interaction module may send a connection request signal to the LPI in the bus (for example, setting the first request signal lpi_req representing low power exit or entry to 0), requesting the LPI to perform an operation of re-establishing the connection between the target module and the bus.

[0153] After the interface interaction module sends the connection request signal, the first state machine enters the second waiting confirmation state (WaitAck0 state), and the interface interaction module waits for a response signal from the LPI to ensure that the LPI has received the request to exit low power consumption and starts to execute corresponding processing.

[0154] After receiving the connection request signal from the interface interaction module, the LPI performs the process of restoring the connection between the target module and the bus, and returns a response signal to the interface interaction module indicating that the connection request signal has been received. When confirming that the target module and the bus have been successfully reconnected, the LPI returns a response signal to the interface interaction module indicating that the target module and the bus have been successfully connected.

[0155] After sending a connection request signal to the low power interface LPI in the bus, the interface interaction module waits for a response signal (the lpi_ack signal is set to 0). If a response signal is received (the lpi_ack signal is set to 0), it indicates that the target module has successfully exited the low power state. At this time, the interface interaction module returns a signal to the target control module indicating that the connection is successfully disconnected (for example, the lpi_op_done signal is set to 1), notifying the target control module that the power supply and connection to the target module can be restored.

[0156] After receiving the signal of successful disconnection, the target control module confirms that the target module has been restored to the bus and enters the normal working mode.

[0157] In the disclosed embodiment, when the target module needs to recover from the low power state to the normal working mode, the data consistency and chip stability during the power state conversion process are ensured through a strict interaction protocol and state confirmation mechanism. When the target module exits the low power state, it can safely restore the connection with the bus, ensuring the normal operation of the target module and improving the stability of the chip.

[0158] Figure 4 A state transition diagram of a first state machine according to an embodiment of the present disclosure is shown. Figure 5 The timing waveform diagram of the chip of the embodiment of the present disclosure is shown. Among them, the top row of signals is the clock signal clk. The process of the clock signal rising edge 1-10 is the process of the target module entering the low power consumption state from the normal working state, that is, the power-off process. Figure 4 The state of the first state machine in Figure 5 The power-off process in the following section is described in detail:

[0159] When the rising edge of the clock signal is 2, the first state machine is in the working indication state WORK, the target control module sets the power-off instruction lpi_go_idle to 1, and sends it to the on-chip network interaction module. At this time, the state machine of the on-chip network interaction module is still in the working indication state;

[0160] When the rising edge of the clock signal is 3, the on-chip network interaction module sets the first request signal lpi_req to 1, triggers the disconnect request signal lpi_req, and sends it to the LPI to request that the target module be placed in a low-power state. At this time, the first state machine enters the first waiting confirmation state WaitAck1, waiting for the response signal lpi_ack of the LPI in the NOC to be set to 1. In the first waiting confirmation state, if lpi_ack is still 0 ( Figure 4 lpi_ack), and the counter is full (cnt==0), the first state machine returns to the working indication state.

[0161] When the rising edge of the clock signal is 5, after LPI receives the disconnect request signal, it sets the response signal lpi_ack to 1 and feeds it back to the on-chip network interaction module. At this time, the first state machine enters the waiting low-power state WaitIdle, and the on-chip network interaction module waits for LPI to return the connection disconnection state signal lpi_idle to 1 indicating that the target module has successfully entered the low-power state.

[0162] When the first state machine is in the waiting low power consumption state WaitIdle, if no disconnection state signal is received (i.e. lpi_idle is 0, Figure 4 lpi_idle) and the counter is full (cnt==0), the first state machine enters the second waiting for confirmation state (WaitAck0 state), and in the second waiting for confirmation state, if lpi_ack is still 0 ( Figure 4 lpi_ack), the first state machine returns to the work indication state WORK.

[0163] When the rising edge of the clock signal is 8, LPI disconnects the target module from the NOC, sets the lpi_idle signal to 1, and feeds back to the on-chip network interaction module.

[0164] When the rising edge of the clock signal is 9, after the on-chip network interaction module receives the disconnection status signal (lpi_idle is set to 1), the on-chip network interaction module returns a signal of successful disconnection to the target control module, sets lpi_op_done to 1, and the first state machine enters a low power indication state (Standby), indicating that the target module enters a low power state. When the on-chip network interaction module is in the low power indication state, the target module disconnection status signal noc_lpi_idle used to indicate that the target module is in an idle state can be set to 1.

[0165] At this point, the control of the target module entering a low power consumption state is achieved.

[0166] The process from the rising edge 11 to 20 of the clock signal is the process of the target module entering the normal working state from the low power consumption state, that is, the power-on process. Figure 4 The state of the first state machine in Figure 5 The power-off process in the following section is described in detail:

[0167] When the rising edge of the clock signal is 12, the target control module sets the connection signal lpi_exit_idle to 1 and sends it to the on-chip network interaction module. At this time, the first state machine is in a low power consumption indication state;

[0168] When the rising edge of the clock signal is 13, the on-chip network interaction module sets the first request signal lpi_req to 0, triggers the connection request signal, and sends it to the LPI to request that the target module be placed in a normal working state. At this time, the first state machine enters the second waiting confirmation state WaitAck0, and the on-chip network interaction module waits for the non-connection disconnection state signal from the LPI. And the target module connection disconnection state signal noc_lpi_idle is set to 0.

[0169] When the rising edge of the clock signal is 14, after receiving the connection request signal, the LPI returns a non-connection disconnection state signal (the lpi_idle signal is set to 0) to the on-chip network interaction module.

[0170] When the rising edge of the clock signal is 16, when LPI determines that the target module has exited the low power state, LPI returns a response signal indicating that the low power state has been exited to the on-chip network interaction module (set the lpi_ack signal to 0, Figure 4 lpi_ack) and fed back to the on-chip network interaction module.

[0171] When the rising edge of the clock signal is 17, the first state machine enters the work indication state WORK, and the on-chip network interaction module returns a signal indicating that the connection is successfully disconnected to the target control module, and sets lpi_op_done to 1.

[0172] At this point, the control of the target module exiting the low power consumption state is achieved.

[0173] After the target module is powered off, the processor can also be powered off. The processor can be a computing unit such as a CPU or a GPU, and the target module is a module other than the processor in the chip. The target module and the processor can establish a communication connection through a bus.

[0174] In the disclosed embodiment, the CPU can be in automatic power-off mode or software-controlled power-off mode. It should be noted that the automatic power-off mode can be configured by the user through software, that is, the user configures the power-off mode auto_pwr_en through software to select the automatic power-off mode or the software-controlled power-off mode. If the software-controlled power-off mode (auto_pwr_en=0) is selected, the instructions for entering and exiting low power consumption are all from the software configuration (pwr_off1, pwr_off2). If the hardware automatic power-off mode (auto_pwr_en=1) is selected, the instructions for entering and exiting low power consumption are all from the hardware logic.

[0175] When the target module no longer needs to communicate with other modules in the chip or perform tasks, it will request to enter a low-power state. The processor, as the computing core in the chip, is used to execute programs and control the operations of other modules. In the automatic power-off mode, when the processor enters the idle state, after determining that all target modules have successfully disconnected from the bus, the target control module can perform a power-off operation on the processor.

[0176] The logic of the automatic power-off mode is described in detail below. In a possible implementation, the chip also includes a processor control module; the processor generates an idle signal WFI when it detects that all target modules in the chip have been powered off; the processor control module sends a disconnect signal to the interface interaction module based on the idle signal to request that the processor be disconnected from the bus; the interface interaction module controls the processor to be disconnected from the bus in response to the disconnect signal sent by the processor control module, and returns a signal to the processor control module that the processor has been disconnected from the bus when it is determined that the processor is disconnected from the bus; the processor control module controls the processor to enter a low power consumption mode in response to the signal that the processor has been disconnected from the bus, and powers off the entire chip.

[0177] The processor control module is used to control the processor to power on or off. The processor control module can receive signals from the processor and control the power state of the processor based on these signals. The functions of the processor control module are similar to those of the target control module, both of which are used to receive instructions and control related modules to enter a low power state.

[0178] Each processor control module corresponds to an interface interaction module one by one. The interface interaction module is a bridge for interaction between the processor and the bus, and is responsible for transmitting control signals and status information to achieve low power consumption control of the processor.

[0179] The processor monitors the status of all target modules in the chip in real time. When it detects that all target modules are powered off, the processor is in an idle state, and the processor generates an idle signal (Wait For Interrupt, WFI). The processor control module receives this idle signal WFI and sends a disconnect signal to the interface interaction module based on the signal, requesting the interface interaction module to disconnect the processor from the bus.

[0180] After receiving the disconnect signal, the interface interaction module will interact with the low-power interface LPI on the bus, send a disconnect request signal to the LPI, and wait for the LPI to confirm that the connection has been disconnected. After confirming that the connection is disconnected, the interface interaction module will return a signal to the processor control module that the processor has disconnected the bus. After receiving the signal that the processor has disconnected the bus, the processor control module will control the processor to enter a low-power mode. For example, the processor clock is turned off, the power supply is cut off, etc., to achieve overall chip power consumption reduction.

[0181] In one example, after the processor generates an idle signal, the chip starts a counter to count. The preset value of the counter can be configured by software to ensure that the processor has stably entered the idle state and avoid low power control failure caused by instability in state transition.

[0182] When the counter reaches the preset value, the processor control module can determine that the processor has entered a stable idle state, send a power-off instruction to the corresponding interface interaction module, initiate the execution of the corresponding power-off interaction process, and the power of the processor will be cut off or the clock will be disabled to achieve the low power consumption target. For the specific power-off interaction process, please refer to the interaction process of the interface interaction module and LPI provided in the present disclosure, which will not be described here.

[0183] In the disclosed embodiments, by means of hardware automated control, the hardware automatically monitors the status of each target module and processor to achieve automatic power-off of the processor, thereby realizing automation of low-power control, reducing direct software involvement, improving chip flexibility and response speed, and effectively reducing chip power consumption.

[0184] In one possible implementation, the chip also includes a processor control module; the processor, in response to the power-off configuration of the software side, sends a power-off instruction to the processor control module and the target control module through the bus; the target control module, in response to the power-off instruction, powers off the target module; the processor control module, when detecting that all target modules in the chip have been powered off, sends a disconnect signal to the interface interaction module for requesting that the processor be disconnected from the bus; the interface interaction module, in response to the disconnect signal sent by the processor control module, controls the processor to be disconnected from the bus, and when determining that the processor is disconnected from the bus, returns a signal to the processor control module that the processor has been disconnected from the bus; the processor control module, in response to the signal that the processor has been disconnected from the bus, controls the processor to enter a low power consumption mode and powers off the entire chip.

[0185] In this implementation, the chip responds to the software power-off configuration to perform the power-off operation. When the software side configures the chip power-off instruction, the processor responds to the software configured power-off instruction, and then sends the power-off instruction to the processor control module and the target control module through the bus to request the target module and the processor in the chip to perform the power-off operation.

[0186] After receiving the power-off instruction from the processor, the target control module will perform a power-off operation on the target module. For the specific implementation of the power-off operation, please refer to the possible implementation methods provided in the present disclosure. The target control module will cut off the power supply of the target module or disable its clock to put the target module into a low power consumption mode.

[0187] The processor control module not only receives the power-off instruction from the processor, but also monitors the power-off status of the target modules in the chip. When the processor control module detects that all target modules have been powered off, it generates a disconnect signal and sends it to the corresponding interface interaction module, requesting the interface interaction module to disconnect the processor from the bus.

[0188] The interface interaction module is the bridge between the processor and the bus. After receiving the disconnect signal from the processor control module, it will interact with the LPI on the bus to ensure that the connection between the processor and the bus is safely disconnected. After determining that the connection is disconnected, the interface interaction module will return a signal to the processor control module indicating that the connection is successfully disconnected.

[0189] After receiving the signal from the interface interaction module indicating that the processor has disconnected the bus, the processor control module controls the processor to enter a low power consumption mode.

[0190] In the disclosed embodiment, after responding to the power-off configuration of the software end, the processor sends a power-off instruction to the processor control module and the target control module through the bus. The target control module performs the power-off operation on the target module, while the processor control module monitors the power-off state and controls the processor to enter the low power consumption mode. As a result, the problem of bus hanging when entering the low power consumption mode is reduced, the impact on the normal operation of the chip is reduced, and the operation efficiency of the chip is improved.

[0191] After all processors are powered off, the power control module in the trigger chip executes the chip power-off operation: the phase-locked loop enable output signal is set to a low level to turn off the phase-locked loop; the crystal oscillator enable output signal is set to a low level to turn off the crystal oscillator.

[0192] In this implementation, when the target modules and processors in the chip are all in a powered-off state, that is, when all the target modules and all the processors are powered-off, the power control module in the chip will perform a power-off operation on the chip.

[0193] When the chip is powered off, the enable signal of the phase-locked loop can be set to a low level to turn off the phase-locked loop (PLL), which is used to generate a stable clock signal. When the chip enters a low-power state, a high-frequency clock signal is no longer required, so turning off the PLL can significantly reduce power consumption.

[0194] Setting the PLL enable signal (such as PLLen_o) to a low level sends a shutdown signal to the PLL to stop it from working.

[0195] When the chip is powered off, the crystal oscillator (OSC) enable output signal can also be set to a low level to turn off the crystal oscillator, which is used to generate a reference clock signal. The clock frequency it generates is usually lower than the PLL. When the chip enters a low-power state, turning off the crystal oscillator can also reduce power consumption.

[0196] By setting the OSC enable signal (such as OSCen_o) to a low level, a shutdown signal is sent to OSC, which can shut down the crystal oscillator.

[0197] In the embodiment of the present disclosure, when it is determined that all target modules in the chip are in a power-off state, the power consumption of the chip in a standby or low-power state can be significantly reduced by turning off the PLL and the crystal oscillator.

[0198] The power control module can also receive the OSC32K signal (an oscillator signal with a frequency of 32.768kHz). When the chip enters low-power mode, the traditional system clock may be turned off or the frequency may be reduced to save energy. As a low-power oscillator, OSC32K can continue to run to provide the necessary time reference, allowing the chip to maintain basic time functions without significantly increasing power consumption.

[0199] In one possible implementation, the chip also includes a processor control module; the target control module and the processor control module, when the chip is turned on, respond to an external power-on instruction to control the target module and the processor to power on, and after the power-on is completed, send a connection signal to the interface interaction module to request that the target module and the processor be connected to the bus; the interface interaction module, in response to the connection signal for establishing a connection between the target module and the processor and the bus, controls the target module and the processor to establish a connection with the bus.

[0200] When the chip is turned on, a power-on command is sent to the chip from the outside, triggering the power management logic inside the chip. After receiving the power-on command, the processor control module will start the corresponding power management operation. For example: gradually increase the power supply voltage of the processor, enable the clock signal of the processor, and perform the reset operation of the processor. The reset operation is to ensure that the processor starts running from a known state to avoid abnormal behavior caused by unknown states.

[0201] The target control module will also respond to the power-on instruction and perform power-on operations on other target modules in the chip (such as memory, peripheral interfaces, etc.), for example: providing a stable power supply voltage for the target module, enabling the clock signal, and performing reset initialization and other operations.

[0202] After the power-on operation is completed, the processor control module and the target control module will send a connection signal to the corresponding interface interaction module, requesting the interface interaction module to establish the connection between the processor and the target module and the bus. The interface interaction module performs power-on interaction with the LPI on the bus to control the connection between the processor and the target module and the bus to ensure the safety and stability of the connection. For the specific power-on interaction process, please refer to the power-on interaction process between the interface interaction module and the LPI provided in the present disclosure, which will not be repeated here.

[0203] After the connection is successfully established, the processor and the target module can communicate and execute tasks through the bus. At this point, the chip has successfully recovered from a low-power state or a shutdown state to a normal working state. In addition, after all the target modules in the chip are powered on, the unnecessary modules can be powered off as needed. The specific power-off process can be referred to the possible implementation methods provided in the present disclosure, which will not be described here.

[0204] Figure 6 FIG. 2 is a schematic diagram showing the structure of a chip based on a NOC bus according to an embodiment of the present disclosure. Figure 6 As shown, the bus is a network on chip NOC bus, the target module and the CPU are connected to the NOC bus through an interface unit NIU for connecting each module, and the connection between the NOC and the NIU is an Advanced Extensible Interface (AXI); the chip also includes a low power interface LPI; the interface interaction module includes a network on chip interaction module noc_lpi. The target control module is also connected to the NIU in the NOC through AXI.

[0205] The on-chip network is an efficient bus interconnection structure implemented inside the chip, which is used to connect various modules in the chip. Specifically, the target module is connected to the NOC bus through the interface unit (NIU), which is used to realize the communication and data transmission between various modules and CPU and NOC bus. Various modules and CPU can interact through the NIU in the NOC bus.

[0206] In this implementation, the chip low-power control circuit also includes a low-power interface LPI for controlling the bus corresponding to the target module. The power control module is connected to the NOC through the LPI, and through power-off interaction with the LPI, it is determined that the connection between the target module and the NIU in the NOC is disconnected, and through power-on interaction with the LPI, it is determined that the connection between the target module and the NIU in the NOC is successful.

[0207] The power control module and the interface switching module in the embodiment of the present disclosure can both be hardware modules. Correspondingly, in this implementation, the NOC bus, the interface unit NIU and the low power interface LPI are also hardware modules. Then, the entire low power control process is automatically completed by hardware, reducing the need for software participation, improving the efficiency and automation of power management, and reducing the complexity and cost of software development. At the same time, the power control module can respond to the low power demand of the target module in a timely manner to achieve precise control of power consumption.

[0208] The target module and the CPU are controlled by the corresponding target control module and the processor control module respectively. The on-chip network interaction module noc_lpi includes a first state machine, and the on-chip network interaction module is connected to the low power interface LPI in the NOC. The circuit also includes a counter for performing counting operations in each process. The circuit also includes a data selector for selecting a power-off instruction corresponding to the automatic power-off mode from the software-triggered power-off instruction pwr_off2 and the power-off instruction in the automatic power-off mode according to the automatic power-off mode auto_pwr_en.

[0209] The CPU can send a power-off instruction to the NIU of the corresponding target control module through the NIU in the bus. The target control module receives the power-off instruction through the NIU in the NOC, and then sends a disconnection signal to noc_lpi for requesting to disconnect the target module from the NOC. In response to the disconnection signal, noc_lpi generates a disconnection request signal and sends it to the LPI. The LPI controls the target module and NIU to be disconnected through the NOC bus. After the NOC detects that the connection between the target module and the NIU is disconnected through the NIU, it sends a connection disconnection status signal to noc_lpi through the LPI; noc_lpi returns a signal to the target control module that the target module is disconnected successfully. In response to the signal, the target control module sends an instruction to turn off the power or the clock to the target module, thereby powering off the target module.

[0210] also, Figure 6 The pwr_off1 and pwr_off2 in the command are power-off instructions, and pwr_on1 and pwr_2 are power-on instructions. Figure 6 For descriptions of other modules and signals in the present invention, please refer to the possible implementation methods provided in the present invention, which will not be described in detail here.

[0211] According to one aspect of the present disclosure, an electronic device is provided, comprising the above chip provided by the present disclosure.

[0212] According to one aspect of the present disclosure, a low power consumption control method is provided, which is applied to the above chip. The chip includes: a bus, a processor, at least one target module, and a low power consumption control module corresponding to the target module one by one.

[0213] Figure 7 A flow chart of the low power consumption control method according to an embodiment of the present disclosure is shown. Figure 7 As shown, the method includes:

[0214] In step S701, the processor sends a power-off instruction to the low-power control module through the bus, where the power-off instruction is used to request to power off the target module;

[0215] In step S702, the low power control module controls the target module to be disconnected from the bus in response to the power-off instruction, and controls the target module to enter a low power mode in response to a signal indicating that the target module has been disconnected from the bus.

[0216] In a possible implementation, the low power control module includes: a target control module and an interface interaction module; the low power control module controls the target module to be disconnected from the bus in response to the power-off instruction, and controls the target module to enter a low power mode in response to a signal that the target module has been disconnected from the bus, including:

[0217] The target control module, in response to the power-off instruction, sends a disconnection signal to the interface interaction module for requesting the target module to be disconnected from the bus; and, in response to the signal that the target module has been disconnected from the bus, controls the target module to enter a low power consumption mode;

[0218] The interface interaction module controls the target module to be disconnected from the bus in response to the disconnection signal, and returns a signal to the target control module indicating that the target module has been disconnected from the bus when it is determined that the target module is disconnected from the bus.

[0219] In a possible implementation, the bus includes: a low power consumption interface LPI; the low power consumption control module, in response to the power-off instruction, controls the target module to be disconnected from the bus, including:

[0220] The low power consumption interface LPI, in response to a disconnection request signal from the interface interaction module, performs power-off interaction with the interface interaction module, and after determining that the connection between the target module and the bus is disconnected, sends a connection disconnection status signal to the interface interaction module, wherein the connection disconnection status signal is used to indicate that the connection between the target module and the bus is disconnected.

[0221] In a possible implementation, the interface interaction module includes a first state machine, which is used to instruct the interface interaction exchange module to perform processing corresponding to the state of the first state machine; the low power interface LPI, in response to a disconnection request signal from the interface interaction module, performs power-off interaction with the interface interaction module, including:

[0222] The interface interaction module, in response to the disconnection signal, sends a disconnection request signal to the LPI in the bus, requesting to disconnect the target module from the bus; the first state machine enters a first waiting confirmation state, waiting for a response signal from the LPI in the bus;

[0223] The interface interaction module, after entering the first waiting confirmation state, triggers the counter counting. When the counter is full but no response signal from the LPI is received, the first state machine returns to the working indication state; when the counter is not full and a response signal from the LPI is received indicating that the disconnection request signal has been received, the first state machine enters the waiting low power consumption state to wait for a connection disconnection state signal indicating that the target module has successfully disconnected.

[0224] In a possible implementation, the low power consumption interface LPI, in response to a disconnection request signal from the interface interaction module, performs power-off interaction with the interface interaction module, including:

[0225] The interface interaction module triggers a counter to count after the first state machine enters the waiting state for low power consumption. When the counter is full but the LPI disconnection state signal is not received, the first state machine enters a second waiting confirmation state and prepares to return to the working indication state; when the counter is not full and the LPI disconnection state signal is received, the first state machine enters a low power consumption indication state;

[0226] When receiving the disconnection status signal, the interface interaction module confirms that the connection between the target module and the bus has been disconnected, and returns a signal indicating successful disconnection to the target control module.

[0227] In a possible implementation, the method further includes:

[0228] The target control module controls the target module to power on in response to the received power-on instruction, and after the power-on is completed, sends a connection signal to the interface interaction module for requesting the target module to establish a connection with the bus;

[0229] The interface interaction module controls the target module to establish a connection with the bus in response to the connection signal.

[0230] In a possible implementation, the bus includes: a low power consumption interface LPI; the method further includes:

[0231] The low power interface LPI, in response to the connection request signal from the interface interaction module, performs power-on interaction with the interface interaction module, and after determining that the target module and the bus are successfully connected, returns a response signal indicating that the target module and the bus are successfully connected to the interface interaction module.

[0232] In a possible implementation manner, the power-on interaction with the interface interaction module includes:

[0233] The interface interaction module, in response to the connection signal, sends a connection request signal to the low power interface LPI in the bus; the first state machine enters a second waiting confirmation state, waiting for a response signal from the LPI in the bus;

[0234] The LPI in the bus, in response to receiving the connection request signal, performs corresponding processing to reconnect the target module and the bus, and returns a response signal indicating that the target module and the bus are successfully connected to the interface interaction module when confirming that the target module and the bus have been successfully reconnected;

[0235] The interface interaction module returns a power-on success signal to the target control module in response to the received response signal indicating that the target module is successfully connected to the bus;

[0236] The target control module, in response to receiving the power-on success signal, determines that the target module is restored to be connected to the bus.

[0237] In a possible implementation, the chip further includes a processor control module; and the method further includes:

[0238] The processor generates an idle signal WFI when detecting that all target modules in the chip have been powered off;

[0239] The processor control module sends a disconnection signal for requesting to disconnect the processor from the bus to the interface interaction module based on the idle signal;

[0240] The interface interaction module controls the processor to be disconnected from the bus in response to a disconnection signal sent by the processor control module, and returns a signal to the processor control module indicating that the processor has been disconnected from the bus when it is determined that the processor is disconnected from the bus;

[0241] The processor control module controls the processor to enter a low power consumption mode in response to a signal that the processor has disconnected from the bus, thereby powering off the entire chip.

[0242] In a possible implementation, the chip further includes a processor control module; and the method further includes:

[0243] The processor, in response to the power-off configuration of the software end, sends a power-off instruction to the processor control module and the target control module through the bus;

[0244] The target control module powers off the target module in response to the power-off instruction;

[0245] The processor control module sends a disconnection signal for requesting the processor to be disconnected from the bus to the interface interaction module when detecting that all target modules in the chip have been powered off;

[0246] The interface interaction module controls the processor to be disconnected from the bus in response to a disconnection signal sent by the processor control module, and returns a signal to the processor control module indicating that the processor has been disconnected from the bus when it is determined that the processor is disconnected from the bus;

[0247] The processor control module controls the processor to enter a low power consumption mode in response to a signal that the processor has disconnected from the bus, thereby powering off the entire chip.

[0248] In a possible implementation, the chip further includes a processor control module; and the method further includes:

[0249] The target control module and the processor control module, in response to an external power-on instruction when the chip is turned on, control the target module and the processor to power on, and after the power-on is completed, send a connection signal to the interface interaction module for requesting the target module and the processor to establish a connection with the bus;

[0250] The interface interaction module controls the target module and the processor to establish a connection with the bus in response to a connection signal for establishing a connection between the target module and the processor and the bus.

[0251] In a possible implementation, the low power consumption control method can be executed by the above chip, or by an electronic device such as a terminal device or a server. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The method can be implemented by a processor calling a computer-readable instruction stored in a memory. Alternatively, the method can be executed by a server.

[0252] In some embodiments, the method provided by the embodiments of the present disclosure can be used to implement the functions described in the above chip embodiments. Its specific implementation and technical effects can refer to the description of the above chip embodiments. For the sake of brevity, they will not be repeated here.

[0253] It can be understood that the above embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above methods of the specific implementation, the specific execution order of each step should be determined according to its function and possible internal logic.

[0254] Other components of the chip or electronic device in the above embodiment may adopt various technical solutions known to ordinary technicians in this field now and in the future, and will not be described in detail here.

[0255] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0256] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0257] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0258] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0259] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0260] The disclosure above provides many different embodiments or examples to realize different structures of the present disclosure. In order to simplify the disclosure of the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0261] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A chip, characterized in that: The chip includes: a bus, a processor, at least one target module, and a low power consumption control module corresponding to the target module. The processor is connected to the bus and sends a power-off instruction to the low-power control module through the bus, wherein the power-off instruction is used to request to power off the target module; The low power control module is connected to the bus and the corresponding target module respectively, controls the target module to be disconnected from the bus in response to the power-off instruction, and controls the target module to enter a low power mode in response to a signal that the target module has been disconnected from the bus.

2. The chip according to claim 1, characterized in that: The low power consumption control module includes: a target control module and an interface interaction module; The target control module, in response to the power-off instruction, sends a disconnection signal to the interface interaction module for requesting the target module to be disconnected from the bus; and, in response to the signal that the target module has been disconnected from the bus, controls the target module to enter a low power consumption mode; The interface interaction module controls the target module to be disconnected from the bus in response to the disconnection signal, and returns a signal to the target control module indicating that the target module has been disconnected from the bus when it is determined that the target module is disconnected from the bus.

3. The chip according to claim 2, characterized in that: The bus includes: a low power consumption interface LPI; The low power consumption interface LPI, in response to a disconnection request signal from the interface interaction module, performs power-off interaction with the interface interaction module, and after determining that the connection between the target module and the bus is disconnected, sends a connection disconnection status signal to the interface interaction module, wherein the connection disconnection status signal is used to indicate that the connection between the target module and the bus is disconnected.

4. The chip according to claim 3, characterized in that: The interface interaction module includes a first state machine for instructing the interface interaction exchange module to perform processing corresponding to the state of the first state machine; The interface interaction module, in response to the disconnection signal, sends a disconnection request signal to the LPI in the bus, requesting to disconnect the target module from the bus; The first state machine enters a first waiting confirmation state, waiting for a response signal from the LPI in the bus; The interface interaction module triggers a counter to count after entering the first waiting confirmation state. When the counter is full but no response signal from the LPI is received, the first state machine returns to the working indication state. When the counter is not full and a response signal from the LPI is received indicating that the disconnection request signal has been received, the first state machine enters a waiting low power consumption state to wait for a disconnection state signal indicating that the target module has been successfully disconnected.

5. The chip according to claim 4, characterized in that: The interface interaction module triggers a counter to count after the first state machine enters the waiting low power consumption state. When the counter is full but the LPI disconnection state signal is not received, the first state machine enters a second waiting confirmation state and prepares to return to the working indication state. When the counter is not full and a disconnection state signal of the LPI is received, the first state machine enters a low power consumption indication state; When receiving the disconnection status signal, the interface interaction module confirms that the connection between the target module and the bus has been disconnected, and returns a signal indicating successful disconnection to the target control module.

6. The chip according to claim 2, characterized in that: The target control module controls the target module to power on in response to the received power-on instruction, and after the power-on is completed, sends a connection signal to the interface interaction module for requesting the target module to establish a connection with the bus; The interface interaction module controls the target module to establish a connection with the bus in response to the connection signal.

7. The chip according to claim 6, characterized in that: The bus includes: a low power consumption interface LPI; The low power interface LPI, in response to the connection request signal from the interface interaction module, performs power-on interaction with the interface interaction module, and after determining that the target module and the bus are successfully connected, returns a response signal indicating that the target module and the bus are successfully connected to the interface interaction module.

8. The chip according to claim 7, characterized in that: The interface interaction module, in response to the connection signal, sends a connection request signal to the low power interface LPI in the bus; the first state machine enters a second waiting confirmation state, waiting for a response signal from the LPI in the bus; The LPI in the bus, in response to receiving the connection request signal, performs corresponding processing to reconnect the target module and the bus, and returns a response signal indicating that the target module and the bus are successfully connected to the interface interaction module when confirming that the target module and the bus have been successfully reconnected; The interface interaction module returns a power-on success signal to the target control module in response to the received response signal indicating that the target module is successfully connected to the bus; The target control module, in response to receiving the power-on success signal, determines that the target module is restored to be connected to the bus.

9. The chip according to claim 2, characterized in that: The chip also includes a processor control module; The processor generates an idle signal WFI when detecting that all target modules in the chip have been powered off; The processor control module sends a disconnection signal for requesting to disconnect the processor from the bus to the interface interaction module based on the idle signal; The interface interaction module controls the processor to be disconnected from the bus in response to a disconnection signal sent by the processor control module, and returns a signal to the processor control module indicating that the processor has been disconnected from the bus when it is determined that the processor is disconnected from the bus; The processor control module controls the processor to enter a low power consumption mode in response to a signal that the processor has disconnected from the bus, thereby powering off the entire chip.

10. The chip according to claim 2, characterized in that: The chip also includes a processor control module; The processor, in response to the power-off configuration of the software end, sends a power-off instruction to the processor control module and the target control module through the bus; The target control module powers off the target module in response to the power-off instruction; The processor control module sends a disconnection signal for requesting the processor to be disconnected from the bus to the interface interaction module when detecting that all target modules in the chip have been powered off; The interface interaction module controls the processor to be disconnected from the bus in response to a disconnection signal sent by the processor control module, and returns a signal to the processor control module indicating that the processor has been disconnected from the bus when it is determined that the processor is disconnected from the bus; The processor control module controls the processor to enter a low power consumption mode in response to a signal that the processor has disconnected from the bus, thereby powering off the entire chip.

11. The chip according to claim 2, characterized in that: The chip also includes a processor control module; The target control module and the processor control module, in response to an external power-on instruction when the chip is turned on, control the target module and the processor to power on, and after the power-on is completed, send a connection signal to the interface interaction module for requesting the target module and the processor to establish a connection with the bus; The interface interaction module controls the target module and the processor to establish a connection with the bus in response to a connection signal for establishing a connection between the target module and the processor and the bus.

12. A low power consumption control method, characterized in that: Applied to a chip as claimed in any one of claims 1 to 11, the chip comprising: a bus, a processor, at least one target module, and a low power consumption control module corresponding to the target module one by one, the method comprising: The processor sends a power-off instruction to the low-power control module through the bus, wherein the power-off instruction is used to request to power off the target module; The low power consumption control module controls the target module to be disconnected from the bus in response to the power-off instruction, and controls the target module to enter a low power consumption mode in response to a signal indicating that the target module has been disconnected from the bus.

13. An electronic device, characterized in that: Comprising a chip as described in any one of claims 1-11.

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