SOC system and method for determining IP cache capacity in system

Abstract

The invention belongs to the technical field of SOC system architecture design, and particularly discloses an SOC system and a method for determining IP cache capacity in the system. According to the method, the maximum write data delay and the minimum read data delay of the IP in the SOC system under the limit load are firstly counted, and then the write data cache capacity and the read data cache capacity of the IP are calculated according to the maximum write data delay and the minimum read data delay obtained through statistics. The method provided by the invention not only can reduce redundancy and waste of the cache capacity, but also can avoid data transmission errors caused by insufficient cache capacity. Besides, compared with other methods, the method provided by the invention is simple in implementation process and low in coupling degree with the SOC system, can be popularized and applied to different SOC systems, and has high compatibility and universality.

Description

Technical Field

[0001] The present application belongs to the technical field of SOC system architecture design, and specifically relates to a SOC system and a method for determining IP cache capacity in the system. Background Art

[0002] As chip integration and functional complexity continue to increase, a large number of IPs will be integrated into SOC chips. Since there is an uncertain delay when writing data in the IP to the public memory or reading it from the public memory, each IP will use a cache to cache data that cannot be processed in time. The cache is generally implemented by SRAM or register group. The capacity of each IP cache will affect the area and power consumption of the entire SOC system. Therefore, it is necessary to reduce the use of IP cache as much as possible during the chip design process.

[0003] The capacity of each IP buffer is determined by the delay of the IP in the SOC system. In the current chip product design process, the conventional technical solution is to estimate the buffer capacity based on experience. In order to ensure normal business operations under the worst delay, design engineers often deliberately increase the buffer capacity to increase the IP's ability to resist data overflow or data underflow. However, this technical solution not only causes redundancy and waste of the buffer, but also increases the area and power consumption of the SOC system. Moreover, due to the lack of experience of the design engineers, the reserved buffer capacity may be insufficient, resulting in the inability to correctly transmit data in certain application scenarios, which in turn makes some functions of the chip product unusable. Summary of the invention

[0004] In order to solve at least one of the problems mentioned in the above background technology, the present application proposes a SOC system and a method for determining IP cache capacity in the system.

[0005] According to a first aspect of the present application, a method for determining IP cache capacity in a SOC system is provided, the method comprising the following steps: Step S1, counting the maximum write data delay and the minimum read data delay of the IP in the SOC system under extreme load, the specific steps comprising:

[0006] First, a delay statistics module is constructed using a hardware description and verification language, and the constructed delay statistics module is mounted on the IP in the SOC system;

[0007] In a possible implementation, the SOC system uses an AXI bus as an on-chip interconnection protocol.

[0008] Then, the SOC system is operated so that the IP works under the extreme load; then, the delay statistics module calculates the minimum read data delay of the IP. Specifically, the minimum read data delay calculation formula is:

[0009]

[0010] Min Read =min{Read i |i=1,2,3...N}

[0011] Where i is the number of times the IP performs a read data operation, N is the total number of times the IP performs a read data operation, and t u is the start time of IP data reading under extreme load, t v Read is the IP data reading cutoff time under extreme load. i is the read data delay when the IP performs the read data operation for the ith time under extreme load, min is the minimum function, T p is the clock period, Min Read The minimum data read delay of the IP under extreme load;

[0012] Finally, the delay statistics module counts the maximum write data delay of the IP. Specifically, the maximum write data delay calculation formula is:

[0013]

[0014] Max Write =max{Write i |i=1,2,3...N}

[0015] Where i is the number of times the IP performs a write data operation, N is the total number of times the IP performs a write data operation, and t m is the start time of writing data to the IP under extreme load, t n Write is the cut-off time for the IP to write data under extreme load. i is the data write delay when the IP performs the data write operation for the ith time under extreme load, max is the maximum value function, T p is the clock period, Max Write It is the maximum data write delay of the IP under extreme load.

[0016] Step S2, calculating the write data cache capacity and the read data cache capacity of the IP according to the statistically obtained maximum data write delay and minimum data read delay of the IP.

[0017] The calculation formula for write data cache capacity is:

[0018]

[0019] In the formula, Mem Write The write data cache capacity of the IP, Max Writeis the maximum number of delay cycles for writing data to the IP under extreme load, Data_Num is the number of data that needs to be written, T Write The number of clock cycles used to write Data_Num data.

[0020] The calculation formula for the read data cache capacity is:

[0021]

[0022] In the formula, Mem Read The read data cache capacity of the IP, Min Read is the minimum number of delay cycles for reading data of the IP under extreme load, Data_Num is the number of data to be read, T Read The number of clock cycles used to read Data_Num data.

[0023] Conventional technical solutions estimate the cache capacity based on experience, but this easily leads to cache redundancy and waste, as well as increases the area and power consumption of the SOC system. In view of the shortcomings of conventional technical solutions, this application proposes to first count the maximum write data delay and minimum read data delay of the IP in the SOC system under extreme load, and then calculate the write data cache capacity and read data cache capacity of the IP based on the maximum write data delay and minimum read data delay obtained by statistics.

[0024] Step S3, determining the actual write data cache capacity and read data cache capacity of the IP according to the calculated write data cache capacity and read data cache capacity of the IP.

[0025] According to the second aspect of the present application, a SOC system is provided, which includes at least one IP module, and each IP module includes a read cache and a write cache. Specifically, the write data cache capacity and the read data cache capacity of the IP module are calculated according to the method in the first aspect of the present application and its various embodiments.

[0026] The beneficial effects of this application are:

[0027] The method proposed in this application can not only reduce the redundancy and waste of cache capacity, but also avoid data transmission errors caused by insufficient cache capacity. In addition, compared with other methods, the method proposed in this application is simple to implement, has a low degree of coupling with the SOC system, can be promoted and applied to different SOC systems, and has high compatibility and universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a flowchart of this application. DETAILED DESCRIPTION

[0029] The following will describe the schemes in the embodiments provided in this application in conjunction with the drawings in this application.

[0030] The terms "first", "second", etc. in the specification and claims of this application and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of this application.

[0031] Embodiment 1:

[0032] like Figure 1 As shown, the present application provides a method for determining IP cache capacity in a SOC system, comprising the steps of:

[0033] Step S1, counting the maximum data write delay and the minimum data read delay of the IP in the SOC system under extreme load, the implementation steps are as follows:

[0034] Step S101, constructing a delay statistics module by using a hardware description and verification language, and mounting the constructed delay statistics module on an IP in a SOC system.

[0035] Optionally, the SOC system uses an AXI bus as an on-chip interconnection protocol.

[0036] Optionally, the hardware description and verification language is SystemVerilog, and the module is mounted on the IP in the SOC system through an instantiation method.

[0037] Step S102, operating the SOC system so that the IP operates under extreme load.

[0038] In the specific implementation process, for write data operations, the extreme load means that the bandwidth usage that the IP in the SOC system can obtain reaches the minimum. At this time, for the IP, when performing write data operations, the cache capacity demand reaches the maximum value.

[0039] For read data operations, the extreme load means that the bandwidth usage that the IP in the SOC system can obtain reaches the maximum. At this time, for the IP, when performing read data operations, the cache capacity demand reaches the maximum value.

[0040] Step S103, the delay statistics module counts the minimum read data delay of the IP, specifically, the minimum read data delay calculation

[0041] The formula is:

[0042]

[0043] MinRead =min{Read i |i=1,2,3...N}

[0044] Where i is the number of times the IP performs a read data operation, N is the total number of times the IP performs a read data operation, and t u is the start time of IP data reading under extreme load, t v Read is the IP data reading cutoff time under extreme load. i is the read data delay when the IP performs the read data operation for the ith time under extreme load, min is the minimum function, T p is the clock period, Min Read The minimum data read delay of the IP under extreme load;

[0045] Step S104, the delay statistics module counts the maximum data write delay of the IP. Specifically, the maximum data write delay calculation formula is:

[0046]

[0047] Max Write =max{Write i |i=1,2,3...N}

[0048] Where i is the number of times the IP performs a write data operation, N is the total number of times the IP performs a write data operation, and t m is the start time of writing data to the IP under extreme load, t n Write is the cut-off time for the IP to write data under extreme load. i is the data write delay when the IP performs the data write operation for the ith time under extreme load, max is the maximum value function, T p is the clock period, Max Write It is the maximum data write delay of the IP under extreme load.

[0049] Step S2, calculating the write data cache capacity and the read data cache capacity of the IP according to the statistically obtained maximum data write delay and minimum data read delay of the IP.

[0050] The calculation formula for write data cache capacity is:

[0051]

[0052] In the formula, Mem Write The write data cache capacity of the IP, Max Write is the maximum number of delay cycles for writing data to the IP under extreme load, Data_Num is the number of data that needs to be written, TWrite The number of clock cycles used to write Data_Num data.

[0053] The calculation formula for the read data cache capacity is:

[0054]

[0055] In the formula, Mem Read The read data cache capacity of the IP, Min Read is the minimum number of delay cycles for reading data of the IP under extreme load, Data_Num is the number of data to be read, T Read The number of clock cycles used to read Data_Num data.

[0056] Step S3, determining the actual write data cache capacity and read data cache capacity of the IP according to the calculated write data cache capacity and read data cache capacity of the IP.

[0057] The present application also provides a SOC system, which includes at least one IP module, and each IP module includes a read cache and a write cache. Specifically, the write data cache capacity and the read data cache capacity of the IP module are calculated according to the method for determining the IP cache capacity in the SOC system described in this embodiment.

[0058] Embodiment 2:

[0059] First, according to step S1, the maximum data write delay and the minimum data read delay of the IP in the SOC system under extreme load are counted.

[0060] First, the write data cache capacity and the read data cache capacity of the IP are calculated based on the statistically obtained maximum write data delay and minimum read data delay of the IP.

[0061] In an optional implementation, assuming that the design requirement of IP1 is to write 10 data within 100 clock cycles, and assuming that the maximum write data delay of IP1 extreme load is 20, the cache capacity of IP1 write data is:

[0062]

[0063] According to the calculation results, in this embodiment, the write data cache capacity that needs to be supported under the extreme load of IP1 is the capacity of 5 data.

[0064] Embodiment 3:

[0065] First, according to step S1, the maximum data write delay and the minimum data read delay of the IP in the SOC system under extreme load are counted.

[0066] In an optional implementation, assuming that the design requirement of IP1 is to read 10 data within 200 clock cycles, and assuming that the minimum read data delay of IP1 extreme load is 10, the cache capacity of IP1 read data is:

[0067]

[0068] According to the calculation results, in this embodiment, under extreme load, the read data cache capacity that IP1 needs to support is the capacity of 10 data.

[0069] So far, the working process of this application has been implemented once according to the method disclosed in this application.

[0070] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

[0071] It should be noted that the serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments. And the terms "including", "comprising" or any other variants thereof herein are intended to cover non-exclusive inclusion, so that the process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, device, article or method including the element.

Claims

1. A method for determining IP cache capacity in a SOC system, characterized in that: Includes steps: Step S1, counting the maximum data write delay and the minimum data read delay of the IP in the SOC system under extreme load; Step S2, calculating the write data cache capacity and the read data cache capacity of the IP according to the statistically obtained maximum data write delay and minimum data read delay of the IP; Step S3, determining the actual write data cache capacity and read data cache capacity of the IP according to the calculated write data cache capacity and read data cache capacity of the IP.

2. The method for determining IP cache capacity in a SOC system according to claim 1, characterized in that: Step S1 includes the steps Step S101, constructing a delay statistics module by hardware description and verification language, and mounting the constructed delay statistics module on the IP in the SOC system; Step S102, operating the SOC system so that the IP operates under extreme load; Step S103, the delay statistics module counts the minimum read data delay of the IP; Step S104: The delay statistics module counts the maximum data write delay of the IP.

3. The method for determining IP cache capacity in a SOC system according to claim 2, characterized in that: The minimum data read delay of the IP in step S103 is calculated by the following formula: Min Read =min{Read i |i=1,2,3...N} Where i is the number of times the IP performs a read data operation, N is the total number of times the IP performs a read data operation, and t u is the start time of IP data reading under extreme load, t v Read is the IP data reading cutoff time under extreme load. i is the read data delay when the IP performs the read data operation for the ith time under extreme load, min is the minimum function, T p is the clock period, Min Read It is the minimum data read delay of the IP under extreme load.

4. The method for determining IP cache capacity in a SOC system according to claim 2, characterized in that: The maximum data write delay of the IP in step S104 is calculated by the following formula: Max Write =max{Write i |i=1,2,3...N} Where i is the number of times the IP performs a write data operation, N is the total number of times the IP performs a write data operation, and t m is the start time of writing data to the IP under extreme load, t n Write is the cut-off time for the IP to write data under extreme load. i is the data write delay when the IP performs the data write operation for the ith time under extreme load, max is the maximum value function, T p is the clock period, Max Write It is the maximum data write delay of the IP under extreme load.

5. The method for determining IP cache capacity in a SOC system according to claim 1, characterized in that: The calculation formula for calculating the write data cache capacity of the IP in step S2 is as follows: In the formula, Mem Write The write data cache capacity of the IP, Max Write is the maximum number of delay cycles for writing data to the IP under extreme load, Data_Num is the number of data that needs to be written, T Write The number of clock cycles used to write Data_Num data.

6. The method for determining IP cache capacity in a SOC system according to claim 1, characterized in that: The calculation formula for calculating the read data cache capacity of the IP in step S2 is as follows: In the formula, Mem Read The read data cache capacity of the IP, Min Read is the minimum number of delay cycles for reading data of the IP under extreme load, Data_Num is the number of data to be read, T Read The number of clock cycles used to read Data_Num data.

7. A SOC system, comprising at least one IP module, each IP module comprising a read cache and a write cache, characterized in that: The write data cache capacity and the read data cache capacity of the IP module are calculated according to the method for determining the IP cache capacity in the SOC system according to any one of claims 1 to 6.

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